Preparation method of semiconductor structure, semiconductor structure, device and equipment
By fabricating PN junctions in the flip-chip stacked transistor process, the problem of poor circuit design flexibility in the prior art is solved, and high-density transistor integration and circuit performance improvement are achieved.
Patent Information
- Application Number
- CN202411345982.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-01-24
AI Technical Summary
Existing technologies do not involve the fabrication of PN junctions in flip-chip stacked transistor processes, resulting in poor flexibility in semiconductor device circuit design.
An active structure, including a first active structure close to the substrate and a second active structure far from the substrate, is formed on a substrate by forming an active structure on a substrate. After ion implantation, a first PN junction structure is formed. The substrate is then removed by flipping the wafer to expose the first active structure, and a second PN junction structure is formed based on the first active structure, thus forming a PN junction.
It enhances the flexibility of circuit design in semiconductor devices and improves transistor integration density and circuit performance.
Smart Images
Figure CN119364842A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art
[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further improve the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size. In the preparation process of flip-chip stacked transistors, a method for preparing PN junctions is urgently needed. Summary of the invention
[0003] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus, which can prepare a PN junction of a semiconductor structure and enhance the flexibility of circuit design in a semiconductor device.
[0004] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising: forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the second active structure being farther away from the substrate than the first active structure; forming a first PN junction structure based on the second active structure; flipping the first PN junction structure and removing the substrate to expose the first active structure; forming a second PN junction structure based on the first active structure, the first PN junction structure and the second PN junction structure constituting a PN junction; wherein, before forming the first PN junction structure, ion implantation is performed on the first active structure and the second active structure.
[0005] In one possible embodiment, an active structure is formed on a substrate, including: providing a substrate; sequentially forming a first material layer and a second material layer on the substrate; performing ion implantation on the first material layer and the second material layer; and etching the implanted first material layer and the implanted second material layer to form an active structure, wherein the first active structure is the etched first material layer, and the second active structure is the etched second material layer.
[0006] In one possible implementation, a first PN junction structure is formed based on a second active structure, including: epitaxially growing a first epitaxial structure on the second active structure; depositing a dielectric material on the first epitaxial structure to form a first interlayer dielectric layer; etching a first portion of the first interlayer dielectric layer to expose the first epitaxial structure; and forming a first metal structure on the first epitaxial structure.
[0007] In one possible implementation, a second PN junction structure is formed based on the first active structure, including: epitaxially growing a second epitaxial structure on the first active structure; depositing a dielectric material on the second epitaxial structure to form a second interlayer dielectric layer; etching a first portion of the second interlayer dielectric layer to expose the second epitaxial structure; and forming a second metal structure on the second epitaxial structure.
[0008] In one possible implementation, before forming the first PN junction structure, ion implantation is performed on the first active structure and the second active structure, including: after forming the active structure, forming a shallow trench isolation structure on the substrate and exposing the second active structure; depositing a semiconductor material on the shallow trench isolation structure to form a dummy gate structure surrounding the second active structure; and using the dummy gate structure as a mask, performing ion implantation on the first active structure and the second active structure.
[0009] In one possible implementation, a first PN junction structure is formed based on the second active structure, including: etching a pseudo-gate structure to expose the second active structure; epitaxially growing a first epitaxial structure on the second active structure; depositing a dielectric material on the first epitaxial structure to form a first interlayer dielectric layer; etching a first portion of the first interlayer dielectric layer to expose the first epitaxial structure; and forming a first metal structure on the first epitaxial structure.
[0010] In one possible embodiment, before forming a second PN junction structure based on the first active structure, the method also includes: thinning the shallow trench isolation structure to a preset height to expose the second active structure; forming a second PN junction structure based on the first active structure, including: epitaxially growing a second epitaxial structure on the first active structure; depositing a dielectric material on the second epitaxial structure to form a second interlayer dielectric layer; etching a first portion of the second interlayer dielectric layer to expose the second epitaxial structure; and forming a second metal structure on the second epitaxial structure.
[0011] In a possible implementation, the ions implanted include P-type ions or N-type ions.
[0012] In the second aspect, an embodiment of the present application provides a semiconductor structure, which is made by the preparation method described in the first aspect and any one of the embodiments thereof, including: an active structure, which is ion implanted; a first PN junction structure and a second PN junction structure arranged back to back, and the first PN junction structure and the second PN junction structure constitute a PN junction.
[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: a semiconductor structure as described in the second aspect above.
[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.
[0015] The technical solution provided by this application may have the following beneficial effects:
[0016] In an embodiment of the present application, an active structure is formed on a substrate, the active structure includes a first active structure close to the substrate and a second active structure away from the substrate, and ion implantation is performed on the active structure; then a first PN junction structure is formed based on the second active structure; then the first PN junction structure is flipped and the substrate is removed to expose the first active structure, and a second PN junction structure is formed based on the first active structure, and the first PN junction structure and the second PN junction structure are connected through the active structure, so that a PN junction with two poles on both sides of the substrate can be formed, thereby enhancing the flexibility of circuit design in semiconductor devices.
[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0019] Figure 1 It is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;
[0020] Figure 2 This is a schematic top view of a first semiconductor structure in an embodiment of the present application;
[0021] Figures 3 to 9 A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;
[0022] Fig.10 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application;
[0023] Fig.11 This is a schematic diagram of a second structure of a semiconductor structure in an embodiment of the present application;
[0024] Fig.12 This is a schematic diagram of a third structure of a semiconductor structure in an embodiment of the present application;
[0025] Fig.13 is a schematic top view of a fourth semiconductor structure in an embodiment of the present application;
[0026] Fig.14 This is a schematic diagram of a fourth structure of a semiconductor structure in an embodiment of the present application;
[0027] Fig.15 This is a schematic top view of a fifth semiconductor structure in an embodiment of the present application;
[0028] Fig.16 This is a fifth structural schematic diagram of the semiconductor structure in the embodiment of the present application.
[0029] The above pictures:
[0030] 10. Flip-chip stacked transistor; 11. First transistor (front transistor); 111. Second fin structure; 112. First source-drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 115. First source-drain metal; 12. Second transistor (back transistor); 121. First fin structure; 122. Second source-drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 125. Second source-drain metal; 21. Substrate; 211. First material layer; 212. Second material layer; 22. Photoresist layer; 23. Fin structure for ion implantation ; 231. a first fin structure subjected to ion implantation; 232. a second fin structure subjected to ion implantation; 24. a fin structure not subjected to ion implantation; 25. a shallow trench isolation structure; 26. a first pseudo-gate structure; 27. a first spacer; 28. a first epitaxial structure; 29. a first metal structure; 30. a first insulating layer; 31. a first oxide layer; 32. a second oxide layer; 33. a third insulating layer; 34. a carrier wafer; 35. a second pseudo-gate structure; 36. a second spacer; 37. a second epitaxial structure; 38. a second metal structure; 39. a second insulating layer; 40. a third oxide layer. DETAILED DESCRIPTION
[0031] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.
[0032] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.
[0033] In one embodiment, there are two schemes for the manufacturing process of stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.
[0034] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using substrate bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.
[0035] The second solution is based on substrate bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the substrate on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to substrate bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonding substrate; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.
[0036] However, some solutions for preparing flip-chip stacked transistors do not involve a solution for making a PN junction in a flip-chip stacked transistor process.
[0037] Therefore, an embodiment of the present application provides a method for preparing a semiconductor structure, which can prepare a PN junction of the semiconductor structure and enhance the flexibility of circuit design in the semiconductor device.
[0038] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.
[0039] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application. Figure 1 As shown, the method for preparing a semiconductor structure includes the following steps.
[0040] Step S110: forming an active structure on a substrate.
[0041] The active structure includes a first active structure and a second active structure, and the second active structure is farther away from the substrate than the first active structure.
[0042] In a possible implementation, the implementation process of step S110 may be: providing a substrate; sequentially forming a first material layer and a second material layer on the substrate, and performing ion implantation on the first material layer and the second material layer; etching the implanted first material layer and the implanted second material layer to form an active structure, wherein the first active structure is the etched first material layer, and the second active structure is the etched second material layer.
[0043] That is, the present application may first perform ion implantation, and then etch the ion implanted material layer to form an active structure, and this solution is referred to as the first solution.
[0044] The substrate may be, for example, any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a silicon carbide substrate.
[0045] After providing the substrate, semiconductor materials can be stacked on the substrate in sequence to form a first material layer and a second material layer, and then ion implantation can be performed on the first material layer and the second material layer. That is, the area where the PN junction needs to be formed can be determined, and then the gaseous material doped with ions can be introduced into the arc chamber for discharge ionization to form an ion beam. The charged ions are implanted into the first material layer and the second material layer through electric field acceleration.
[0046] In some embodiments, the ions implanted may be P-type ions or N-type ions. The P-type ions may be any one of the following: boron (B), gallium (Ga), aluminum (Al). The N-type ions may be any one of the following: phosphorus (P), arsenic (As), antimony (Sb).
[0047] Through the ion implantation process, high-quality, highly controllable PN junctions can be easily formed on semiconductor materials, providing a basis for the preparation of various semiconductor devices.
[0048] The first material layer and the second material layer are used to form an active structure. For example, the doping of the first material layer and the second material layer may be the same or different.
[0049] After ion implantation of the first material layer and the second material layer, the implanted first material layer and the second material layer can be etched to form a plurality of first active structures and second active structures standing upright on the substrate. The first active structure is the etched first material layer, and the second active structure is the etched second material layer.
[0050] The etching process may be, for example, at least one of dry etching, wet etching, reactive ion etching, etc.
[0051] After forming the active structures (including the first active structure and the second active structure), an oxide material may be deposited on the substrate and the active structures to form a shallow trench isolation (STI) surrounding the first active structure.
[0052] It can be understood that an oxide material can be deposited on the substrate and the active structure, and the oxide material can be thinned until the upper surface of the active structure is exposed, thereby forming a shallow trench isolation structure whose upper surface is flush with the upper surface of the active structure, and then the shallow trench isolation structure is further back-etched to a certain depth, so that the shallow trench isolation structure wraps the first active structure and exposes the second active structure. In this way, the operation of forming the front structure of the PN junction based on the exposed second active structure in step S120 is performed subsequently. Among them, the oxide material forming the shallow trench isolation structure can be exemplarily any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc. The thinning process can be exemplarily a process such as chemical-mechanical planarization (CMP).
[0053] In another possible implementation, after the active structure is formed through step S110, a shallow trench isolation structure can be formed on the substrate to expose the second active structure; a semiconductor material is deposited on the shallow trench isolation structure to form a dummy gate structure surrounding the second active structure; and ion implantation is performed on the first active structure and the second active structure using the dummy gate structure as a mask.
[0054] That is, the present application can also first etch the material layer to form an active structure, and then perform ion implantation, and this solution is called the second solution.
[0055] It can be understood that the second solution is to first form an active structure, then form a shallow trench isolation structure that wraps the underlying active structure (the first active structure), and then deposit a semiconductor material on the shallow trench isolation structure to form a dummy gate structure, and then use the dummy gate as a mask to perform ion implantation on the first active structure and the second active structure. Since the dummy gate structure covers a portion of the active structure area, this portion of the area will not be implanted with ions, so there is a portion of the active structure that is not implanted with ions.
[0056] In one embodiment, the semiconductor material forming the dummy gate structure may be polysilicon, amorphous silicon, or the like.
[0057] Step S120: forming a first PN junction structure based on the second active structure.
[0058] In some embodiments, the implementation process of step S120 may be: epitaxially growing a first epitaxial structure on the second active structure; depositing a dielectric material on the first epitaxial structure to form a first interlayer dielectric layer; etching a first portion of the first interlayer dielectric layer to expose the first epitaxial structure; and forming a first metal structure on the first epitaxial structure.
[0059] It is understandable that a portion of the second active structure can be etched to form a groove, and epitaxial growth is performed at the groove to form a first epitaxial structure. After the first epitaxial structure is formed, an insulating material (such as silicon dioxide SiO2) can be deposited on the first epitaxial structure and the second active structure, and a planarization process is performed to form a first interlayer dielectric layer, and the first interlayer dielectric layer can cover the first epitaxial structure and the second active structure. Then, a certain area of the first interlayer dielectric layer is etched to expose the first epitaxial structure, and then a metal material is filled on the first epitaxial structure to form a first metal structure.
[0060] Exemplarily, strained materials such as silicon germanium or silicon carbide can be formed by selective epitaxial growth to fill the groove, and then a first epitaxial structure can be formed on the strained material by a heavy doping process. The first epitaxial structure can be a P-type structure or an N-type structure. When the doped ions are P-type ions, the first epitaxial structure is a P-type structure, and when the doped ions are N-type ions, the first epitaxial structure is an N-type structure.
[0061] For the second scheme, in some embodiments, the implementation process of step S120 may be: etching the dummy gate structure to expose the second active structure; epitaxially growing the first epitaxial structure on the second active structure; depositing a dielectric material on the first epitaxial structure to form a first interlayer dielectric layer; etching a first portion of the first interlayer dielectric layer to expose the first epitaxial structure; and forming a first metal structure on the first epitaxial structure.
[0062] It can be understood that since there is a dummy gate structure surrounding the second active structure in the second scheme, this scheme first etches the dummy gate structure to expose the second active structure, and then the first epitaxial structure, the first interlayer dielectric layer and the first metal structure can be formed in sequence in the same manner as the first scheme, so that the front structure of the PN junction can be obtained.
[0063] In some embodiments, after forming the front side structure of the PN junction, a first metal interconnection layer may be formed on the front side structure of the PN junction.
[0064] It is understandable that the first metal interconnection layer can be formed by performing back-end processes (such as dielectric deposition between interconnection lines, metal line formation, lead pad formation, etc.) on the front structure.
[0065] Step S130: flipping the first PN junction structure and removing the substrate to expose the first active structure.
[0066] It can be understood that after the front structure of the PN junction is prepared, the PN junction can be flipped over to prepare the back structure of the PN junction on the front structure.
[0067] In one embodiment, an insulating material (such as silicon oxide) may be deposited on the first metal interconnect layer to form an insulating layer, and the insulating layer may be bonded to the carrier wafer. The PN junction is then flipped over and the substrate is removed, so that the first active structure is exposed, so that the back structure of the PN junction can be prepared using the first active structure.
[0068] In one embodiment, after flipping the wafer, the substrate may be removed by polishing or chemical mechanical planarization.
[0069] In some embodiments, after the PN junction is flipped and the substrate is removed, the shallow trench isolation structure can be thinned to a preset height to expose the first active structure, and the thinned shallow trench isolation structure is used to isolate the front structure and the back structure of the PN junction.
[0070] It is understandable that after removing the substrate, the upper surface of the first active structure is flush with the upper surface of the shallow trench isolation structure, so the shallow trench isolation structure can be thinned to a preset height to expose the peripheral side of the first active structure, so that the back structure of the PN junction can be formed according to the first active structure exposed on the peripheral side. The preset height can be set according to actual needs, and the embodiment of the present application is not limited to this.
[0071] Step S140: forming a second PN junction structure based on the first active structure.
[0072] The first PN junction structure and the second PN junction structure constitute a PN junction.
[0073] In some embodiments, the implementation process of step S140 may be: epitaxially growing a second epitaxial structure on the first active structure; depositing a dielectric material on the second epitaxial structure to form a second interlayer dielectric layer; etching a first portion of the second interlayer dielectric layer to expose the second epitaxial structure; and forming a second metal structure on the second epitaxial structure.
[0074] Among them, the method of forming the second epitaxial structure, the second interlayer dielectric layer, and the second metal structure of the PN junction can refer to the method of forming the first epitaxial structure, the first interlayer dielectric layer, and the first metal structure of the PN junction in the above step S120, and will not be repeated here.
[0075] It should be noted that in the second scheme of using the dummy gate structure as a mask for ion implantation, since the dummy gate structure will cover a portion of the active structure, resulting in this portion of the active structure not being ion implanted, the PN junction finally formed is in the extension direction of the active structure, and the active structure that is ion implanted and the active structure that is not ion implanted are separated.
[0076] Since the second epitaxial structure is epitaxially grown based on the first active structure, the first epitaxial structure is epitaxially grown based on the second active structure, and the first active structure and the second active structure are self-aligned structures, the second epitaxial structure and the first epitaxial structure are self-aligned structures, which effectively improves the symmetry of the PN junction structure.
[0077] It should be noted that the type of the second epitaxial structure is different from the type of the first epitaxial structure. When the first epitaxial structure is a P-type structure, the second epitaxial structure is an N-type structure. When the first epitaxial structure is an N-type structure, the second epitaxial structure is a P-type structure.
[0078] After the back structure of the PN junction is prepared, a second metal interconnection layer may be formed on the back structure.
[0079] In an embodiment of the present application, an active structure is formed on a substrate, the active structure including a first active structure close to the substrate and a second active structure away from the substrate; then a first PN junction structure is formed based on the second active structure; then the first PN junction structure is flipped and the substrate is removed to expose the first active structure, and a second PN junction structure is formed based on the first active structure, so that a PN junction with two poles on both sides of the substrate can be formed, thereby enhancing the flexibility of circuit design in semiconductor devices.
[0080] The above two solutions are solutions for forming a PN junction separately. The present application can also prepare a PN junction while preparing a flip-chip stacked transistor. The substrate provided in this way may include a first region and a second region, a PN junction is made in the first region, and a flip-chip stacked transistor is made in the second region. The solution is described below.
[0081] In some embodiments, a first material layer and a second material layer can be formed on two regions of the substrate; a photoresist layer is covered on the second region, and ion implantation is performed on the first material layer and the second material layer using the photoresist layer as a mask; the photoresist layer is removed; and the first material layer and the second material layer of the two regions are etched to respectively form a first active structure and a second active structure in the first region, and a first active structure and a second active structure in the second region.
[0082] It can be understood that since the second region has a photoresist layer as a protective layer during ion implantation, the first material layer and the second material layer in the second region are not ion implanted, and thus the first active structure and the second active structure obtained after etching the first material layer and the second material layer in the second region are also not ion implanted.
[0083] In some embodiments, after forming an active structure (including a first active structure and a second active structure), operations can be performed simultaneously in two regions according to the process flow for preparing a flip-chip stacked transistor. First, a shallow trench isolation structure covering the second active structure is formed on the substrate; polysilicon material is deposited in the gate region to form a first pseudo-gate structure, and a first spacer is formed on the sidewall of the first pseudo-gate structure; a first source-drain structure is epitaxially grown on the second active structure, and an interlayer dielectric is deposited on the first source-drain structure to form a first interlayer dielectric layer; a first gate structure is formed, and the first gate structure includes a first gate dielectric layer and a first gate electrode layer coated on the second active structure; a first source-drain metal is formed on the first source-drain structure, so that the front transistor and the front structure of the PN junction can be prepared. After that, a back-end process can be performed to form a first metal interconnect layer. Among them, the first source-drain structure can be called a first epitaxial structure in the PN junction, and the first source-drain metal can be called a first metal structure in the PN junction.
[0084] It should be noted that after forming the first dummy gate structure, the first dummy gate structure in the region where the PN is located (the first region) can be removed by photolithography. Since the first dummy gate structure is used to define the first gate structure, the first dummy gate structure is removed when forming the first gate structure of the stacked flip-chip transistor, so that the first gate structure can be formed based on the region defined by the first dummy gate structure. As for the region where the PN junction is located, the first dummy gate structure has already been removed, and the interlayer dielectric or other materials formed thereafter will fill the region of the first dummy gate structure. Therefore, when forming the first gate structure, the first gate structure does not exist in the region where the PN junction is located.
[0085] In some embodiments, the first dummy gate structure formed above can be removed by an etching process to obtain a first gate groove, an insulating material can be deposited at the first gate groove to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute a first gate structure.
[0086] Exemplarily, the first gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.
[0087] Exemplarily, the first gate electrode layer may be composed of multiple layers of electrode materials, each layer of which includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).
[0088] In addition, in some embodiments, after the first gate structure is formed, the first gate structure can be etched to a preset height, and an insulating material can be deposited on the etched first gate structure to form an insulating layer to protect the first gate structure. In this way, when the first source and drain metal is formed by photolithography, if an offset occurs during photolithography drilling, it will also be punched on the insulating layer, preventing the gate metal from directly contacting the source and drain metal, thereby reducing the requirements for photolithography.
[0089] After the front structure of the front transistor and the PN junction is prepared, the process flow of preparing the flip-chip stacked transistor is still followed to operate synchronously in the two regions. After wafer bonding and flipping, the substrate is removed; the shallow trench isolation structure is thinned to a preset height to expose the first active structure; polysilicon material is deposited in the gate region of the stacked transistor to form a second pseudo-gate structure, and a second spacer is formed on the sidewall of the second pseudo-gate structure; a second source-drain structure is epitaxially grown on the second active structure, and an interlayer dielectric is deposited on the second source-drain structure to form a second interlayer dielectric layer; a second gate structure is formed, and the second gate structure includes a second gate dielectric layer and a second gate electrode layer coated on the first active structure; a second source-drain metal is formed on the second source-drain structure, so that the back transistor and the back structure of the PN junction can be prepared. After that, a back-end process can be performed to form a second metal interconnect layer. Among them, the second source-drain structure can be called a second epitaxial structure in the PN junction, and the second source-drain metal can be called a second metal structure in the PN junction.
[0090] It should be noted that after forming the second dummy gate structure, the second dummy gate structure in the PN region (first region) can be photolithographically removed. Since the second dummy gate structure is used to define the second gate structure, the second dummy gate structure is removed when forming the second gate structure of the stacked flip-chip transistor, so that the second gate structure can be formed based on the region defined by the second dummy gate structure. As for the region where the PN junction is located, the second dummy gate structure has already been removed, and the interlayer dielectric or other materials formed thereafter will fill the region of the second dummy gate structure. Therefore, when forming the second gate structure, the second gate structure does not exist in the region where the PN junction is located. Among them, the method for forming the second gate structure can refer to the above-mentioned method for forming the first gate structure, which will not be repeated here.
[0091] In addition, in some embodiments, after the second gate structure is formed, the second gate structure can be etched to a preset height, and an insulating material can be deposited on the etched second gate structure to form an insulating layer to protect the second gate structure. In this way, when the second source and drain metal is formed by photolithography, if an offset occurs during photolithography drilling, it will also be punched on the insulating layer, preventing the gate metal from directly contacting the source and drain metal, thereby reducing the requirements for photolithography.
[0092] The above is a solution in which ion implantation is performed first and then an active structure is formed when a flip-chip stacked transistor is prepared while a PN junction is prepared. Correspondingly, in the case of preparing a flip-chip stacked transistor while a PN junction is prepared, an active structure may be formed first and then ion implantation is performed. This solution is described below.
[0093] In some embodiments, a first material layer and a second material layer can be formed on both regions of the substrate; the first material layer and the second material layer of the two regions are etched to form a first active structure and a second active structure in the first region, and a first active structure and a second active structure in the second region, respectively; a shallow trench isolation structure covering the second active structure is formed on the substrate, and polysilicon material is deposited in the gate region to form a first pseudo-gate structure; ion implantation is performed using the first pseudo-gate structure as a mask, so that the first active structure and the second active structure that are implanted in the first region, and the first active structure and the second active structure that are not implanted in the second region can be formed. After that, the first pseudo-gate structure in the first region is removed, and then the flip-chip stacked transistor and the PN junction are simultaneously prepared according to the first scheme described above. In the first region, there are the first gate structure and the second gate structure of the flip-chip stacked transistor, and the first gate structure and the second gate structure are vertically opposite to the active structure that is not implanted.
[0094] In the embodiment of the present application, the PN junction region is defined by photolithography, ion implantation is performed in the region, and the transistor region is defined by photolithography on both the front and back sides, so as to avoid forming a pseudo gate structure in the PN junction region, thereby forming a PN junction with two poles on both sides of the substrate. Based on the self-aligned flip-chip transistor, the present application further proposes a solution for making a through PN junction that is compatible with its process, which saves process steps and enhances the flexibility of circuit design.
[0095] The following describes a method for preparing a semiconductor structure provided in an embodiment of the present application by taking a fin-shaped structure as an example in which the active structure in the semiconductor structure is an example. Figure 2 It is a schematic top view of the first semiconductor structure in the embodiment of the present application. Figure 2 (a) is a top view of a PN junction. Figure 2(b) is a top view schematic diagram of the flip-chip stacked transistor. For ease of understanding, the top view in (a) only shows the fin structure and PN junction area, and the top view in (b) only shows the fin structure, gate structure and source-drain structure. Among them, the AA' direction is the section direction of the PN junction along the PN junction area; the BB' direction is the section direction of the PN junction along the fin structure; the A1-A1' direction is the section direction of the flip-chip stacked transistor along the source-drain structure; the B1-B1' direction is the section direction of the flip-chip stacked transistor along the fin structure.
[0096] The first preparation process is first introduced below. Figures 3 to 9 is a schematic diagram of the first preparation process of the semiconductor structure in the embodiment of the present application, Figures 3 to 9 (a) is a schematic diagram of the structure of a PN junction in a semiconductor structure during the first preparation process. Figures 3 to 9 (b) is a schematic diagram of the structure of a flip-chip stack transistor in a semiconductor structure during the first preparation process. Fig.10 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application. Fig.10 (a) is a schematic diagram of the first structure of a PN junction in a semiconductor structure. Fig.10 (b) is a schematic diagram of the first structure of a flip-chip stacked transistor in a semiconductor structure.
[0097] In one example, a first process for preparing a semiconductor structure may include the following steps:
[0098] Step 1: Cover the second region of the substrate wafer 21 with a photoresist layer 22, and use the photoresist layer 22 as a mask to perform ion implantation to obtain Figure 3 The structure shown.
[0099] It can be understood that the first region of the substrate 21 is used to prepare a PN junction, and the second region is used to prepare a flip-chip stacked transistor. First, the first material layer 211 and the second material layer 212 can be sequentially formed in the two regions of the substrate 21, and then the second material layer 212 in the second region is covered with a photoresist to form a photoresist layer 22, and then the first material layer and the second material layer are ion-implanted using the photoresist layer as a mask. Since the second material layer in the first region is not covered with photoresist, the PN junction region (first region) can be graphically penetrated, and low-doped deep well ion implantation can be performed on the first material layer and the second material layer located in the penetrated PN junction region.
[0100] Step 2: remove the photoresist layer 22, then etch the first material layer and the second material layer using a standard process to form a fin structure 23 in which ions are implanted in the first region, and a fin structure 24 in which ions are not implanted in the second region, and deposit an oxide material on the substrate 21 to form a shallow trench isolation structure 25; deposit a semiconductor material on the shallow trench isolation structure 25 to form a first dummy gate structure 26, and etch the first dummy gate structure in the region where the PN junction is located; form a first spacer 27 on both sides of the first dummy gate structure and the first fin structure, and obtain the following: Figure 4 The structure shown.
[0101] It can be understood that, in the region where the flip-chip stacked transistor is located, the shallow trench isolation structure 25 wraps the portion of the fin structure close to the substrate 21, i.e., the first fin structure 121, and exposes the portion of the fin structure away from the substrate 21, i.e., the second fin structure 111. In the region where the PN junction is located, the shallow trench isolation structure 25 wraps the first fin structure 231 for ion implantation, and exposes the second fin structure 232 for ion implantation.
[0102] Step 3: Prepare the front transistor of the flip-chip stack transistor and the first epitaxial structure 28, the first interlayer dielectric layer 113, and the first metal structure 29 in the area where the PN region is located according to the standard process to obtain Figure 5 The structure shown.
[0103] It can be understood that the first fin structure in the source and drain region can be etched to a preset height to form a first source and drain groove in the source and drain region, a first source and drain structure 112 is formed at the first source and drain groove, an interlayer dielectric is deposited on the first source and drain structure 112 to form a first interlayer dielectric layer 113, and then the first pseudo-gate structure 23 is removed, a first gate structure 114 is formed in the gate region, and a first source and drain metal 115 is formed. Among them, the first source and drain structure in the region where the PN junction is located can also be called a first epitaxial structure, and the first source and drain metal can also be called a first metal structure. Here, a P-type device and a P-pole of a PN junction are made on the front side.
[0104] In addition, after forming the first gate structure, the first gate structure 114 may be selectively etched to a preset height, and an insulating material may be deposited on the etched first gate structure 114 to form a first insulating layer 30 , and then a first oxide layer 31 may be formed on the first insulating layer 30 .
[0105] It should be noted that when etching the first fin structure, the spacers on both sides of the first fin structure are also etched away. Figure 5There is no spacer in AA' and A1-A1' of (a). Moreover, since the first dummy gate structure in the region where the PN junction is located has been removed in the previous step, there is no first gate structure in the region where the PN junction is located in this step.
[0106] Step 4: Perform the back-end process and deposit SiO2 to form the second oxide layer 32, and deposit SiCN on the second oxide layer 32 to form the third insulating layer 33, so as to obtain Figure 6 The structure shown.
[0107] Figure 6 The first metal interconnection layer formed by the back-end process is not shown.
[0108] Step 5: Bond the carrier wafer 34 to the third insulating layer 33 above the third insulating layer 33, and then flip the wafer to obtain Figure 7 The structure shown.
[0109] Step 6: Remove the substrate 21 and thin the shallow trench isolation structure 25 to expose the second fin structure, and obtain Figure 8 The structure shown.
[0110] Step 7: depositing semiconductor material on the thinned shallow trench isolation structure 25 to form a second pseudo gate structure 35, and etching the second pseudo gate structure in the PN junction area; forming a second spacer 36 on both sides of the second pseudo gate structure and the second fin structure, and obtaining Fig. 9 The structure shown.
[0111] Step 8: Prepare the back transistor of the flip-chip stack transistor and the second epitaxial structure 37, the second interlayer dielectric layer 123, and the second metal structure 38 in the area where the PN region is located according to the standard process to obtain Fig.10 The structure shown.
[0112] It can be understood that the second fin structure in the source and drain region can be etched to a preset height to form a second source and drain groove in the source and drain region, a second source and drain structure 122 is formed at the second source and drain groove, an interlayer dielectric is deposited on the second source and drain structure 122 to form a second interlayer dielectric layer 123, and then the second pseudo-gate structure 35 is removed, a second gate structure 124 is formed in the gate region, and a second source and drain metal 125 is formed. Among them, the second source and drain structure in the region where the PN junction is located can also be called a second epitaxial structure, and the second source and drain metal can also be called a second metal structure. Here, an N-type device and an N-pole of a PN junction are made on the back. Therefore, based on the first preparation method, a PN junction with a P-type on the front and an N-type on the back can be prepared. See Fig.10 In B-B1' of (a), the active structure between the first epitaxial structure 28 and the second epitaxial structure 37 is entirely ion implanted.
[0113] In addition, after forming the second gate structure, the second gate structure 124 may be selectively etched to a preset height, and an insulating material may be deposited on the etched second gate structure 124 to form a second insulating layer 39 , and then a third oxide layer 40 may be formed on the second insulating layer 39 .
[0114] In addition, after forming the back-side transistor, a back-end process can be performed to form a second metal interconnection layer. Fig.10 The second metal interconnect layer is not shown.
[0115] It should be noted that when etching the second fin structure, the spacers on both sides of the second fin structure are also etched away. Fig.10 There is no spacer in AA' and A1-A1' of (a). Moreover, since the second dummy gate structure in the region where the PN junction is located has been removed in the previous step, there is no second gate structure in the region where the PN junction is located in this step.
[0116] Fig.11 This is a schematic diagram of the second structure of the semiconductor structure in the embodiment of the present application. Fig.11 (a) is a schematic diagram of the second structure of the PN junction in the semiconductor structure. Fig.11 (b) in the figure is a schematic diagram of the second structure of the flip-chip stacked transistor in the semiconductor structure. Referring to the first preparation method, the difference from the first preparation method is that the second preparation method is that the first step is to sequentially form a first material layer and a second material layer on two regions of the substrate wafer, and then use a standard process to etch the first material layer and the second material layer to form a fin structure without ion implantation in the two regions; a shallow trench isolation structure is formed on the substrate, and a semiconductor material is deposited on the shallow trench isolation structure to form a first dummy gate structure in the two regions, and then the first dummy gate structure is used as a mask to perform ion implantation on the fin structure, and the first dummy gate structure in the first region is removed, and a first spacer is formed on both sides of the first dummy gate structure and the first fin structure in the second region, and then the third to eighth steps in the first preparation method are performed. Since the first dummy gate structure is used as a mask for ion implantation in this scheme, the first dummy gate structure will cover a portion of the fin structure area, and this portion of the area will not be ion implanted, so if Fig.11 As shown in BB' of (a), the PN junction finally formed is spaced apart from the fin structure that has been ion-implanted and the fin structure that has not been ion-implanted in the extending direction of the fin structure.
[0117] Fig.12 This is a schematic diagram of the third structure of the semiconductor structure in the embodiment of the present application. Fig.12 (a) is a schematic diagram of the third structure of the PN junction in the semiconductor structure. Fig.12(b) in the figure is a schematic diagram of the third structure of the flip-chip stacked transistor in the semiconductor structure. Referring to the first preparation method, the third preparation method is different from the first preparation method in that the N-type device and the N-pole of the PN junction are first made on the front side, and then the P-type device and the P-pole of the PN junction are made on the back side. The starting doping type can be selected as P-type low-concentration doping or N-type low-concentration doping. Starting doping refers to the ion implantation type of the active structure connecting the P-pole and the N-pole of the PN junction.
[0118] Fig.13 It is a schematic top view of the fourth semiconductor structure in the embodiment of the present application. Fig.13 (a) is a top view of a PN junction. Fig.13 (b) is a top view schematic diagram of the flip-chip stacked transistor. For ease of understanding, the top view in (a) only shows the fin structure and PN junction area, and the top view in (b) only shows the fin structure, gate structure and source-drain structure. Among them, the AA' direction is the section direction of the PN junction along the PN junction area; the BB' direction is the section direction of the PN junction along the fin structure; the A1-A1' direction is the section direction of the flip-chip stacked transistor along the source-drain structure; the B1-B1' direction is the section direction of the flip-chip stacked transistor along the fin structure.
[0119] Fig.14 This is a schematic diagram of the fourth structure of the semiconductor structure in the embodiment of the present application. Fig.14 (a) is a schematic diagram of the fourth structure of the PN junction in the semiconductor structure. Fig.14 (b) is a schematic diagram of a fourth structure of a flip-chip stacked transistor in a semiconductor structure. Referring to the first preparation method, the preparation can be performed on a multi-fin device, so that a PN junction of the multi-fin device can be obtained.
[0120] Fig.15 It is a schematic top view of the fifth semiconductor structure in the embodiment of the present application. Fig.15 (a) is a top view schematic diagram of a flip-chip stacked transistor including a PN junction. Fig.15 (b) is a top view schematic diagram of a flip-chip stacked transistor without a PN junction. For ease of understanding, the top view in (a) only shows the fin structure, gate structure, source-drain structure (epitaxial structure) and PN junction region, and the top view in (b) only shows the fin structure, gate structure and source-drain structure. Among them, the AA' direction is the direction of the section along the PN junction region; the BB' direction is the direction of the section along the fin structure; the A1-A1' direction is the direction of the section along the source-drain structure; and the B1-B1' direction is the direction of the section along the fin structure.
[0121] Fig.16 This is a fifth structural schematic diagram of the semiconductor structure in the embodiment of the present application. Fig.16(a) is a fifth structural schematic diagram of a flip-chip stack transistor including a PN junction in a semiconductor structure. Fig.16 (b) is a schematic diagram of the fifth structure of a flip-chip stacked transistor that does not contain a PN junction in the semiconductor structure. Referring to the first preparation method, the difference from the first preparation method is that in the fifth preparation method, a fin structure and STI are first formed, and the area where the PN junction is located is not defined by photolithography. A pseudo-gate structure is directly formed on the front of all areas, and then ion implantation is performed using the pseudo-gate structure as a mask, and subsequent preparation is performed according to the standard process. It should be noted that since this method is to perform ion implantation using the pseudo-gate structure as a mask after the pseudo-gate structure is formed, the part of the fin structure covered by the pseudo-gate structure is not ion implanted.
[0122] The embodiment of the present application can further propose a solution for preparing a punch-through PN junction that is compatible with the process of the self-aligned flip-chip stacked transistor, thereby saving process steps and enhancing the flexibility of the FFET device circuit design.
[0123] It should be noted that the above is an introduction to the structure of the semiconductor structure provided by the present application by taking the fin field effect transistor as an example. The preparation method in the embodiment of the present application can also be applied to the stacking of transistors in various forms such as full-surround gate transistors, planar transistors, vertical field effect transistors, fork-shaped transistors, etc., which are not shown in the embodiment of the present application.
[0124] Furthermore, the flip-chip stacked transistor provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to detect the above semiconductor structure.
[0125] The present application provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can refer to the above semiconductor structure, which will not be described in detail here.
[0126] The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be referred to the above semiconductor structure, which will not be repeated here.
[0127] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.
[0128] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: forming an active structure on a substrate, wherein the active structure comprises a first active structure and a second active structure, wherein the second active structure is farther from the substrate than the first active structure; Based on the second active structure, forming a first PN junction structure; Flipping the first PN junction structure and removing the substrate to expose the first active structure; Based on the first active structure, a second PN junction structure is formed, wherein the first PN junction structure and the second PN junction structure constitute a PN junction; Wherein, before forming the first PN junction structure, ion implantation is performed on the first active structure and the second active structure.
2. The method according to claim 1, characterized in that The forming of an active structure on a substrate comprises: providing a substrate; forming a first material layer and a second material layer in sequence on the substrate; performing ion implantation on the first material layer and the second material layer; The injected first material layer and the injected second material layer are etched to form the active structure, wherein the first active structure is the etched first material layer, and the second active structure is the etched second material layer.
3. The method according to claim 1, characterized in that The forming of a first PN junction structure based on the second active structure comprises: epitaxially growing a first epitaxial structure on the second active structure; Depositing a dielectric material on the first epitaxial structure to form a first interlayer dielectric layer; Etching a first portion of the first interlayer dielectric layer to expose the first epitaxial structure; A first metal structure is formed on the first epitaxial structure.
4. The method according to claim 1, characterized in that: Based on the first active structure, a second PN junction structure is formed, including: epitaxially growing a second epitaxial structure on the first active structure; depositing a dielectric material on the second epitaxial structure to form a second interlayer dielectric layer; Etching a first portion of the second interlayer dielectric layer to expose the second epitaxial structure; A second metal structure is formed on the second epitaxial structure.
5. The method according to claim 1, characterized in that Before forming the first PN junction structure, the step of performing ion implantation on the first active structure and the second active structure includes: After forming the active structure, forming a shallow trench isolation structure on the substrate and exposing the second active structure; Depositing a semiconductor material on the shallow trench isolation structure to form a dummy gate structure surrounding the second active structure; Using the dummy gate structure as a mask, ion implantation is performed on the first active structure and the second active structure.
6. The method according to claim 5, characterized in that The forming of a first PN junction structure based on the second active structure comprises: etching the dummy gate structure to expose the second active structure; epitaxially growing a first epitaxial structure on the second active structure; Depositing a dielectric material on the first epitaxial structure to form a first interlayer dielectric layer; Etching a first portion of the first interlayer dielectric layer to expose the first epitaxial structure; A first metal structure is formed on the first epitaxial structure.
7. The method according to claim 5, characterized in that Before forming a second PN junction structure based on the first active structure, the method further includes: Thinning the shallow trench isolation structure to a predetermined height to expose the second active structure; The forming of a second PN junction structure based on the first active structure comprises: epitaxially growing a second epitaxial structure on the first active structure; depositing a dielectric material on the second epitaxial structure to form a second interlayer dielectric layer; Etching a first portion of the second interlayer dielectric layer to expose the second epitaxial structure; A second metal structure is formed on the second epitaxial structure.
8. A semiconductor structure, prepared using the preparation method according to any one of claims 1 to 7, characterized in that: include: An active structure, wherein the active structure is ion implanted; A first PN junction structure and a second PN junction structure are arranged opposite to each other, and the first PN junction structure and the second PN junction structure form a PN junction.
9. A semiconductor device, characterized in that: include: The semiconductor structure as claimed in claim 8.
10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.