Planar indium gallium arsenic avalanche photodiode and manufacturing method

Abstract

The invention relates to the field of infrared photoelectric devices, in particular to a planar indium gallium arsenic avalanche photodiode which comprises a diffusion layer, an avalanche layer, a charge layer, a component gradient layer, a light absorption layer, a buffer layer and a substrate. The diffusion layer includes a convex diffusion region and a step diffusion region. The convex diffusion region is located above the step diffusion region. The avalanche layer is located below the step diffusion region. And the charge layer, the component gradient layer, the light absorption layer, the buffer layer and the substrate are sequentially arranged below the avalanche layer. The invention also comprises a method. The double-step diffusion avalanche photodiode has the advantages that the doping morphology of a traditional double-step diffusion avalanche photodiode can be modulated, an electric field is in step distribution with a strong center and a weak edge, the generated electric field is converged forwards, an effective photosensitive surface is not greatly attenuated, a protection ring structure can be omitted, the edge breakdown probability is reduced, and the effective duty ratio of the photosensitive surface is improved. Meanwhile, the method is compatible with the prior art, production equipment does not need to be changed, and the method is suitable for manufacturing the planar indium gallium arsenic avalanche photodiode.

Description

Technical Field

[0001] The invention relates to the field of infrared photoelectric devices, in particular to a planar indium gallium arsenide avalanche photodiode and a manufacturing method thereof. Background Art

[0002] Avalanche photodiodes are widely used in optical communications and laser radars because of their high gain and strong single-photon weak signal detection capabilities. The light absorption layer uses indium gallium arsenide material. Indium gallium arsenide detectors are photodetectors with the best comprehensive performance in the short-wave infrared band. The materials will also be different depending on hole multiplication and electron multiplication. The basic structure of the device is mainly divided into two types: table type and planar type. It is mainly obtained by heteroepitaxial growth on an indium phosphide substrate. From the basic device structure, it is divided into two structures: table type and planar type.

[0003] For hole multiplication detectors, the SAGCM structure is mainly used, and the buffer layer, light absorption layer, gradient layer, charge layer and cap layer are grown on the indium phosphide substrate respectively. Compared with the exposed junction area of ​​the mesa type, the PN junction structure of the planar structure will be buried in the cap layer, and the P-type area will be formed by diffusion, which is more conducive to low dark count rate and suitable for single photon detection. However, compared with the mesa junction, the area formed by diffusion has a curvature effect, so that when the photosensitive source is large, the edge electric field is higher than the central electric field, which is not convenient for the detection of the light source. This phenomenon is especially obvious when the bias voltage is over, resulting in premature breakdown. In the field of single photon detection, this problem has received more and more attention.

[0004] In order to suppress the edge breakdown of planar InGaAs detectors, researchers in related fields have explored and proposed a series of methods, including avalanche photodiodes with composite guard ring structures and methods for making the same (invention patent application number: CN117913174A), and using an etching pit method to suppress the edge breakdown of planar InGaAs / InP Geiger mode APDs (Photonic Journal 47, 0523001 (2018)). And using a two-layer insulating dielectric passivation method to enhance voltage resistance through low- and high-power passivation to reduce the risk of edge breakdown (invention patent application number: CN202310376064.0). In addition, there are reports of using a multi-layer etching pit method to form an N-level coaxial symmetrical step structure that is gradually recessed from both sides to the middle (invention patent application number: CN202211144013.7). Most of these disclosed patents or implementation ideas only suppress existing diffusion morphologies. Due to the large diffusion aperture and the lateral diffusion of the diffusion source in the material, the electric field peak will always appear on the outside of the top. If the diffusion morphology is not guided, the electric field dispersion problem cannot be fundamentally solved. However, when the top diffusion space is reduced, due to the convergence of the forward diffusion morphology, even if the electric field peak is still at the edge, the electric field is still in a relatively central position for the entire multiplication zone. Therefore, the above measures can suppress the edge electric field to a certain extent, but they do not fundamentally guide the electric field to the forward convergence effect. Summary of the invention

[0005] The object of the present invention is to provide a planar InGaAs avalanche photodiode and a manufacturing method thereof, mainly to solve the problems existing in the above-mentioned prior art.

[0006] In order to achieve the above-mentioned purpose, the technical solution adopted by the present invention is to provide a planar InGaAs avalanche photodiode, characterized in that it comprises a diffusion layer, an avalanche layer, a charge layer, a composition gradient layer, a light absorption layer, a buffer layer and a substrate; the diffusion layer comprises a raised diffusion region and a step diffusion region; the raised diffusion region is located above the step diffusion region; the avalanche layer is located below the step diffusion region; below the avalanche layer are the charge layer, the composition gradient layer, the light absorption layer, the buffer layer and the substrate in sequence.

[0007] Further, the diffusion layer doping type is N-type, the diffusion type is P-type, and the thickness is preferably 4.8 microns; wherein the raised diffusion area is a ring hole structure, and the thickness is preferably 100 to 500 nanometers; the material of the step diffusion area is preferably Inp; the material of the raised diffusion area is preferably Inp or Inp. 0.52 A l 0.48 As.

[0008] Furthermore, the material of the charge layer is preferably Inp, the thickness is preferably 0.125 micrometers, and the doping type is N type.

[0009] Furthermore, the material of the composition gradient layer is preferably InGaAsP, the thickness is preferably 0.02 to 0.06 micrometers, and the doping type is N-type.

[0010] Furthermore, the material of the light absorbing layer is preferably In 0.53 Ga 0.47 As or InGaAsP, preferably with a thickness of 2.0 microns and an N-type doping type.

[0011] Furthermore, the material of the buffer layer is preferably InP, the thickness is preferably 1 micrometer, and the doping type is N-type; the material of the substrate is preferably InP, and the doping type is N-type.

[0012] The present invention also discloses a method for manufacturing the above-mentioned planar InGaAs avalanche photodiode, which is characterized by comprising the steps of:

[0013] Step S10, obtaining a pre-etched material; the pre-etched material comprises, from the bottom layer to the top layer, the buffer layer, the light absorption layer, the component gradient layer, the charge layer, and the diffusion layer in sequence; the top of the diffusion layer comprises a pre-etched layer;

[0014] Step S20, using a pattern mask ultraviolet lithography process to generate a raised diffusion region in the pre-etched layer;

[0015] Step S30, using an atomic diffusion process to perform a first diffusion in the raised diffusion area;

[0016] Step S40, using an atomic diffusion process to perform a second diffusion in the entire diffusion layer to form the step diffusion region;

[0017] Step S50, using ultraviolet lithography to generate electrode patterns corresponding to the positive and negative electrodes;

[0018] Step S60: using the sputtering coating process to form the positive and negative electrodes using the electrode pattern.

[0019] Furthermore, in step S20, the following steps are specifically included:

[0020] Step S21, using plasma enhanced chemical vapor deposition technology to produce a silicon nitride film;

[0021] Step S22, photolithography to generate a mask for the raised diffusion region on the silicon nitride film;

[0022] Step S23, using a plasma etching process to generate the raised diffusion region.

[0023] Furthermore, in step S30, the following steps are specifically included:

[0024] Step S31, using plasma enhanced chemical vapor deposition technology to produce a silicon nitride film;

[0025] Step S32, photolithography is performed on the silicon nitride film to generate a first diffusion mask; the size of the first diffusion mask is less than or equal to the size of the raised diffusion region;

[0026] Step S33, using a plasma etching process to generate a first diffusion region;

[0027] Step S34, completing the first atomic diffusion through the first diffusion zone.

[0028] Furthermore, in step S40, the following steps are specifically included:

[0029] Step S41, using plasma enhanced chemical vapor deposition technology to produce a silicon nitride film;

[0030] Step S42, photolithography to generate a second diffusion mask on the silicon nitride film; the size of the second diffusion mask is larger than the size of the raised diffusion area;

[0031] Step S43, using a plasma etching process to generate a second diffusion region;

[0032] Step S44, completing the second atomic diffusion through the second diffusion zone.

[0033] In view of the above technical features, the planar InGaAs avalanche photodiode and manufacturing method of the present invention have the following significant advantages over the prior art:

[0034] 1. The present invention improves and innovates the diffusion morphology of the planar InGaAs avalanche photodiode, effectively converges the electric field forward, and the effective photosensitive surface does not significantly attenuate. Figure 5 , showing the difference in electric field distribution between the prior art and the present invention on the same 10 micron effective photosensitive surface device. In the traditional structure generated by the prior art, the electric field distribution is strong at the edge and weak in the center. However, after modulation by the ring hole structure of the present invention, the electric field presents a step distribution with strong center and weak edge.

[0035] 2. The present invention solves the problem that the electric field at the edge of existing large diffusion aperture devices is large and the electric field is not concentrated. Figure 6, showing the IV curves of the conventional structure of the prior art and the ring hole structure of the present invention. Under the same pull-through voltage, the device performance of the planar InGaAs avalanche photodiode of the present invention is greatly improved, and the breakdown voltage value is pushed back.

[0036] 3. The manufacturing method of the planar InGaAs avalanche photodiode of the present invention is compatible with existing processes and does not require changes in production equipment. In addition, the process parameters of the ring hole structure of the raised diffusion area are controllable, and the material and thickness of the layer can be set through previous experience accumulation to achieve the regulation of the diffusion rate and modulate the final electric field distribution. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic side view of a preferred embodiment of a planar InGaAs avalanche photodiode of the present invention;

[0038] Figure 2 It is a schematic diagram of the side view structure of a pre-etched material used to produce a planar InGaAs avalanche photodiode in a preferred embodiment of the planar InGaAs avalanche photodiode of the present invention;

[0039] Figure 3 A preferred embodiment of the planar InGaAs avalanche photodiode of the present invention is a schematic diagram of a top view of the structure arranged in 2×2 units;

[0040] Figure 4 A comparison diagram of diffusion morphologies of the planar InGaAs avalanche photodiode of the present invention between different preferred embodiments;

[0041] Figure 5 A schematic diagram showing a comparison of the electric field strengths of the planar InGaAs avalanche photodiode of the present invention and the conventional double-step structure InGaAs avalanche photodiode;

[0042] Figure 6 It is a comparison diagram of IV curves of the planar InGaAs avalanche photodiode of the present invention and the conventional double-step structure InGaAs avalanche photodiode;

[0043] Figure 7 It is a method flow chart of a preferred embodiment of the method for manufacturing a planar InGaAs avalanche photodiode of the present invention.

[0044] In the figure:

[0045] 1-backlight, 2-raised diffusion region, 3-passivation film layer, 4-step diffusion region, 5-avalanche layer, 6-charge layer, 7-composition gradient layer, 8-light absorption layer, 9-buffer layer, 10-substrate, 11-P-type metal contact electrode, 12-N-type metal contact electrode, 13-pre-etching layer, 14-cap layer. DETAILED DESCRIPTION

[0046] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0047] See also Figures 1 to 4 The present invention discloses a planar InGaAs avalanche photodiode, a preferred embodiment of which comprises a passivation film layer 3, a diffusion layer, an avalanche layer 5, a charge layer 6, a composition gradient layer 7, a light absorption layer 8, a buffer layer 9 and a substrate 10.

[0048] The planar InGaAs avalanche photodiode is processed on the pre-etched material. The diffusion layer and the avalanche layer 5 are formed by processing the pre-etched layer 13 and the cap layer 14. The overall thickness of the diffusion layer is 4.8 microns, and its doping type is N-type, and the doping concentration is N-type 1.6×10 14 cm -3 , the diffusion type is P type. In the diffusion layer, there are two regions: the raised diffusion region 2 and the step diffusion region 4. The raised diffusion region 2 is formed on the pre-etched layer 13, and it is located directly above the step diffusion region 4. The material of the step diffusion region 4 is I np, and after the diffusion process, a P-type strong multiplication electric field region and a multiplication region are formed. The material of the passivation film layer 3 is silicon nitride, formed above the step diffusion region 4, and located on the same horizontal plane as the raised diffusion region 2.

[0049] The raised diffusion region 2 is a ring hole structure with an outer diameter of R, an inner diameter of r, and a certain height h. Specifically, in the diffusion process, the diffusion speed of the protruding part of the ring hole structure in the raised diffusion region 2 is lower than the diffusion speed in the ring hole structure. Therefore, by controlling the size of the raised diffusion region 2, the shape of the P-type diffusion in the step diffusion region 4 can be controlled. After diffusion, the raised diffusion region 2 forms a P-type as a whole, and the doping concentration is greater than or equal to 1×10 18 cm -3 . The height h of the raised diffusion zone 2 will directly affect the difference in diffusion rate between the protrusion and the ring hole. When h is too high, the rate difference will be too large and form redundant steps. When h is appropriate, the lateral diffusion at the hole will smoothly merge with the area where the protrusion structure diffuses downward, and no new steps will be generated. In this embodiment, the height h of the raised diffusion zone 2 is 500 nanometers. The size of the inner diameter r of the raised diffusion zone 2 determines the size of the final strong multiplication electric field region, and the size of the outer diameter R determines the size of the photosensitive surface of the device, that is, the size of the multiplication zone.

[0050] In the standard process, two atomic diffusions are required. The radius of the first diffusion is different in different embodiments and is selected between the inner radius r and the outer radius R, so as to modulate the electric field of the multiplication region of different shapes as required. Figure 4 In the first embodiment, the first diffusion radius is selected to be equal to the inner diameter r, while in the second embodiment, the first diffusion radius is selected to be equal to the outer diameter R. In both embodiments, the second diffusion radius is consistent and is greater than the outer diameter R. It can be seen that the step shape formed in the first embodiment is steeper.

[0051] In addition, the material of the raised diffusion region 2 can also affect the diffusion. 0.52 Al 0.48 As and In 0.53 Ga 0.47 As can also be used as a carrier for P diffusion. Therefore, in different embodiments, in addition to InP, the material of the pre-etching layer can also be InP. 0.52 Al 0.48 As or In 0.53 Ga 0.47 As, the raised diffusion region 2 and the stepped diffusion region 4 are made of different materials.

[0052] Below the step diffusion region 4 is the avalanche layer 5. Below the avalanche layer 5 is the charge layer 6. The charge layer 6 is made of I np, has a thickness of 0.125 microns, is doped with N type, and has a doping concentration of 2.0×10 17 cm -3 Below the charge layer 6 is the composition graded layer 7. The composition graded layer 7 is made of InGaAsP, has a thickness of 0.02 microns, is doped with N-type, and has a doping concentration of 2.0×10 16 cm -3 In other embodiments, the thickness of the composition gradient layer 7 can be selected from 0.02 micrometers to 0.06 micrometers. Below the composition gradient layer 7 is the light absorption layer 8. The material of the light absorption layer 8 is InGaAsP, the thickness is 2.0 micrometers, the doping type is N-type, and the doping concentration is 2.38×10 14 cm -3 In other embodiments, the material of the light absorbing layer 8 may also be selected to be In 0.53 Ga 0.47 As. Below the light absorption layer 8 is a buffer layer 9. The material of the buffer layer 9 is InP, the thickness is 1 micron, the doping type is N-type, and the doping concentration is 5.0×10 17 cm -3 The buffer layer 9 is located above the substrate 10. The material of the substrate 10 is InP, the doping type is N type, and the doping concentration is 3.0×10 18 cm-3 .

[0053] The positive and negative electrodes of the diode are respectively arranged on the raised diffusion region 2 and the substrate 10. A P-type metal contact electrode 11 is arranged on the raised diffusion region 2, and an N-type metal contact electrode 12 is arranged on the substrate 10. In application, the backlight 1 is incident from the direction of the substrate 10.

[0054] See also Figure 7 The present invention also discloses a method for manufacturing the above-mentioned planar InGaAs avalanche photodiode, a preferred embodiment of which comprises the steps of:

[0055] Step S100, obtaining a pre-etching material.

[0056] The pre-etching material includes multiple layers of material layers that have been formed, starting from the substrate upward, which are a buffer layer, a light absorption layer, a component gradient layer, a charge layer, a diffusion layer and a pre-etching layer.

[0057] The thickness of the pre-etched layer is 500 nanometers. In the subsequent process, a raised diffusion area is formed in the pre-etched layer, and its height is etched according to the product characteristics.

[0058] Step S201, generating a thin film layer.

[0059] A silicon nitride film is formed on the surface of the pre-etched layer by using plasma enhanced chemical vapor deposition technology.

[0060] Step S202: Photolithography to generate a mask.

[0061] On the silicon nitride film, a mask of a raised diffusion region is formed by photolithography. The mask is annular in shape, with an inner diameter r of 7.15 microns and an outer diameter R of 10.5 microns.

[0062] Step S203, generating a raised diffusion area.

[0063] The silicon nitride film in the area not covered by the mask and the pre-etched layer below are removed by plasma etching process, and the remaining part forms a ring hole structure with an inner diameter of r and an outer diameter of R, that is, a raised diffusion area.

[0064] Step S301, generating a thin film layer.

[0065] A silicon nitride film is formed on the surface of the pre-etched material by using plasma enhanced chemical vapor deposition technology.

[0066] Step S302: Photolithography to generate a first diffusion mask.

[0067] On the silicon nitride film, a first diffusion mask is generated by photolithography. The first diffusion mask is circular in shape, and its radius is smaller than the outer diameter of the ring hole structure of the raised diffusion region, and the radius is selected as 7.2 microns here.

[0068] In other embodiments, the radius of the first diffusion mask can be larger, for example, 8.5 microns, or even equal to the outer diameter of the ring hole structure of the raised diffusion region, that is, 10.5 microns. Different first diffusion mask radii correspond to different shapes of multiplication region electric fields.

[0069] Step S303: generating a first diffusion region.

[0070] The silicon nitride film in the area not covered by the first diffusion mask is removed by a plasma etching process, thereby forming a circular first diffusion area with a radius equal to the radius of the first diffusion mask.

[0071] Step S304, completing the first atomic diffusion

[0072] Zinc atoms are injected into the first diffusion zone at 530 degrees Celsius to complete the first atomic diffusion and form the shape after the first atomic diffusion in the diffusion layer.

[0073] Step S401, generating a thin film layer.

[0074] A silicon nitride film is formed on the surface of the pre-etched material by using plasma enhanced chemical vapor deposition technology.

[0075] Step S402: Photolithography to generate a second diffusion mask.

[0076] On the silicon nitride film, a second diffusion mask is generated by photolithography. The second diffusion mask is circular in shape, and its radius is larger than the outer diameter of the ring hole structure of the raised diffusion area. Here, the radius is selected to be 15 microns. The radius of the second diffusion mask corresponds to the final photosensitive area of ​​the diode.

[0077] Step S403: generating a second diffusion region.

[0078] The silicon nitride film in the area not covered by the second diffusion mask is removed by a plasma etching process, thereby forming a circular second diffusion area with a radius equal to the radius of the second diffusion mask.

[0079] Step S404, completing the second atomic diffusion

[0080] Using the second diffusion region, zinc atoms are injected and the second atomic diffusion is completed at 530 degrees Celsius. The shape of the second atomic diffusion is combined with the shape after the first atomic diffusion to form the final P-type step diffusion region. The N-type semiconductor region below the P-type step diffusion region and between the charge layer forms an avalanche layer.

[0081] Step S500, generating an electrode pattern.

[0082] On the front side of the pre-etched material, that is, the raised diffusion area, ultraviolet lithography is used to generate an electrode pattern corresponding to the electrode. On the substrate, ultraviolet lithography is used to generate an electrode pattern corresponding to the electrode.

[0083] Step S600, forming positive and negative electrodes.

[0084] Using the sputtering coating process, according to the direction depicted by the electrode pattern, positive and negative electrodes are deposited on the positive and negative sides of the diode, namely the P-type metal contact electrode connected to the raised diffusion area, and the N-type metal contact electrode connected to the substrate.

[0085] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A planar indium gallium arsenide avalanche photodiode, characterized in that: It comprises a diffusion layer, an avalanche layer, a charge layer, a composition gradient layer, a light absorption layer, a buffer layer and a substrate; the diffusion layer comprises a raised diffusion region and a step diffusion region; the raised diffusion region is located above the step diffusion region; the avalanche layer is located below the step diffusion region; below the avalanche layer are the charge layer, the composition gradient layer, the light absorption layer, the buffer layer and the substrate in sequence.

2. The planar InGaAs avalanche photodiode according to claim 1, characterized in that: The doping type of the diffusion layer is N-type, the diffusion type is P-type, and the thickness is preferably 4.8 microns; wherein the raised diffusion area is a ring hole structure, and the thickness is preferably 100 to 500 nanometers; the material of the step diffusion area is preferably Inp; the material of the raised diffusion area is preferably Inp or In 0.52 Al 0.48 As.

3. The planar InGaAs avalanche photodiode according to claim 1, characterized in that: The material of the charge layer is preferably Inp, the thickness is preferably 0.125 micrometers, and the doping type is N type.

4. The planar InGaAs avalanche photodiode according to claim 1, characterized in that: The material of the composition gradient layer is preferably InGaAsP, the thickness is preferably 0.02 to 0.06 micrometers, and the doping type is N-type.

5. The planar InGaAs avalanche photodiode according to claim 1, characterized in that: The material of the light absorbing layer is preferably In 0.53 Ga 0.47 As or InGaAsP, preferably with a thickness of 2.0 microns and an N-type doping type.

6. The planar InGaAs avalanche photodiode according to claim 1, characterized in that: The material of the buffer layer is preferably InP, the thickness is preferably 1 micron, and the doping type is N-type; the material of the substrate is preferably InP, and the doping type is N-type.

7. A method for manufacturing the planar InGaAs avalanche photodiode according to claim 1, characterized in that: Contains steps: Step S10, obtaining a pre-etched material; the pre-etched material comprises, from the bottom layer to the top layer, the buffer layer, the light absorption layer, the component gradient layer, the charge layer, and the diffusion layer in sequence; the top of the diffusion layer comprises a pre-etched layer; Step S20, using a pattern mask ultraviolet lithography process to generate a raised diffusion region in the pre-etched layer; Step S30, using an atomic diffusion process to perform a first diffusion in the raised diffusion area; Step S40, using an atomic diffusion process to perform a second diffusion in the entire diffusion layer to form the step diffusion region; Step S50, using ultraviolet lithography to generate electrode patterns corresponding to the positive and negative electrodes; Step S60: using the sputtering coating process to form the positive and negative electrodes using the electrode pattern.

8. The method for manufacturing a planar InGaAs avalanche photodiode according to claim 7, characterized in that: In step S20, the steps are specifically included: Step S21, using plasma enhanced chemical vapor deposition technology to produce a silicon nitride film; Step S22, photolithography to generate a mask for the raised diffusion region on the silicon nitride film; Step S23, using a plasma etching process to generate the raised diffusion region.

9. The method for manufacturing a planar InGaAs avalanche photodiode according to claim 7, characterized in that: In step S30, the steps are specifically included: Step S31, using plasma enhanced chemical vapor deposition technology to produce a silicon nitride film; Step S32, photolithography is performed on the silicon nitride film to generate a first diffusion mask; the size of the first diffusion mask is less than or equal to the size of the raised diffusion region; Step S33, using a plasma etching process to generate a first diffusion region; Step S34, completing the first atomic diffusion through the first diffusion zone.

10. The method for manufacturing a planar InGaAs avalanche photodiode according to claim 7, characterized in that: In step S40, the steps are specifically included: Step S41, using plasma enhanced chemical vapor deposition technology to produce a silicon nitride film; Step S42, photolithography to generate a second diffusion mask on the silicon nitride film; The size of the second diffusion mask is larger than the size of the raised diffusion area; Step S43, using a plasma etching process to generate a second diffusion region; Step S44, completing the second atomic diffusion through the second diffusion zone.

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