Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention discloses a solar cell and a preparation method thereof, and a photovoltaic module, and the solar cell comprises a silicon substrate, and the light receiving surface of the silicon substrate comprises a light receiving region and a gate region; the first tunneling oxide layer is positioned on one side of the light receiving surface of the silicon substrate; the first doped polycrystalline silicon layer is arranged on one side, far away from the silicon substrate, of the first tunneling oxide layer, and the orthographic projection of the first doped polycrystalline silicon layer on the silicon substrate is located in the gate region; the protection layer is located on the side, away from the first tunneling oxide layer, of the first doped polycrystalline silicon layer, the protection layer comprises silicon oxide, and the thickness of the protection layer ranges from 2 nm to 6 nm. Therefore, the passivation effect of the light receiving surface of the cell can be improved, the parasitic absorption of the first doped polycrystalline silicon layer to light is reduced, and the photoelectric conversion efficiency of the cell is improved.

Description

Technical Field

[0001] The present application relates to the photovoltaic field, and specifically, to solar cells and methods for preparing the same, and photovoltaic modules. Background Art

[0002] At present, the photovoltaic industry is in the transition stage from P-type to N-type. The preparation of N-type TOPcon (Tunnel Oxide Passivating Contact) cells is highly compatible with the preparation of PERC (Passivated Emitter and Rear Cell) cells. It only needs to add the preparation process of the tunnel oxide layer and the polysilicon layer, so that it can be upgraded based on the original PERC production line, which greatly reduces the production and manufacturing costs of the cells and is favored by many manufacturers. At present, the structure of the backlight side of the TOPcon cell can form a good passivation contact, but the passivation contact on the light-receiving side is still poor, which makes the photoelectric conversion efficiency of the cell low. Therefore, the current solar cells still have many deficiencies in the actual production and application process, which need to be further improved. Summary of the invention

[0003] In the first aspect of the present application, the present application proposes a solar cell, comprising: a silicon substrate, the light-receiving surface of the silicon substrate comprising a light-receiving region and a gate region; a first tunneling oxide layer, the first tunneling oxide layer being located on one side of the light-receiving surface of the silicon substrate; a first doped polysilicon layer, the first doped polysilicon layer and the first tunneling oxide layer being located on a side away from the silicon substrate, and the orthographic projection of the first doped polysilicon layer on the silicon substrate being located in the gate region; a protective layer, the protective layer being located on a side of the first doped polysilicon layer away from the first tunneling oxide layer, the protective layer comprising silicon oxide, and the thickness of the protective layer being 2nm-6nm. Thus, the passivation effect of the light-receiving surface of the cell can be improved, the parasitic absorption of light by the first doped polysilicon layer can be reduced, and the photoelectric conversion efficiency of the cell can be improved.

[0004] In some embodiments, the thickness of the first doped polysilicon layer is 40 nm-200 nm. Thus, the protective layer can protect the first doped polysilicon layer in the gate region, so that the first doped polysilicon layer in the gate region is retained after the alkaline etching process.

[0005] In some embodiments, the first tunneling oxide layer satisfies at least one of the following conditions: the first tunneling oxide layer comprises silicon-based oxide; the thickness of the first tunneling oxide layer is 1nm-2nm. Thus, the first tunneling oxide layer can be provided to achieve efficient carrier selective transmission and enhance current collection.

[0006] In some embodiments, a first passivation layer is further included, the first passivation layer is located on a side of the protective layer away from the first doped polysilicon layer, and on a side of the first tunneling oxide layer in the light receiving area away from the silicon substrate, and the first passivation layer includes at least one of aluminum-based oxide, silicon-based nitride, silicon-based oxide, and silicon-based oxynitride. Thus, the passivation effect of the gate region can be improved by the first passivation layer.

[0007] In some embodiments, the light-receiving surface of the silicon substrate is a textured surface; and / or the backlight surface of the silicon substrate is a polished surface. Thus, the photoelectric conversion efficiency of the battery can be further improved.

[0008] In some embodiments, the silicon substrate comprises an N-type silicon wafer, and the first doped polysilicon layer comprises a P-type polysilicon, thereby helping to exhibit a lower light-induced degradation effect under illumination and improve photoelectric conversion efficiency.

[0009] In the second aspect of the present application, the present application proposes a method for preparing the aforementioned solar cell, comprising: forming a first tunneling oxide layer and a preformed first doped polysilicon layer stacked on one side of the light-receiving surface of the silicon substrate; laser processing the preformed first doped polysilicon layer to form a protective layer; alkaline etching the preformed first doped polysilicon layer located in the light-receiving area to expose the first tunneling oxide layer located in the light-receiving area to form a first doped polysilicon layer; forming a first passivation layer on the side of the protective layer away from the first doped polysilicon layer and on the side of the first tunneling oxide layer located in the light-receiving area away from the silicon substrate. Thus, the aforementioned solar cell can be prepared by a simple method, which has the advantages of simple process and low cost.

[0010] In some embodiments, the wavelength of the laser treatment is 315 nm-390 nm; and / or the power of the laser treatment is 2 W-5 W. This helps to form a protective layer with a moderate thickness.

[0011] In some embodiments, the alkaline etching treatment satisfies at least one of the following conditions: the etching solution of the alkaline etching treatment includes at least one of an aqueous solution of NaOH and an aqueous solution of KOH; the mass fraction of the etching solution of the alkaline etching treatment is 5%-15%; the time of the alkaline etching treatment is 80s-120s; the temperature of the alkaline etching treatment is 35°C-50°C. This helps to completely remove the preformed first doped polysilicon layer in the light-receiving area.

[0012] In the third aspect of the present application, the present application proposes a photovoltaic module, comprising at least one battery string, wherein the battery string comprises at least two aforementioned solar cells, or a solar cell prepared by the aforementioned method. Thus, the photovoltaic module has all the features and advantages of the aforementioned solar cell and the method for preparing the solar cell, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0014] Figure 1 A schematic diagram of the structure of a solar cell according to an embodiment of the present application;

[0015] Figure 2 This is a schematic structural diagram of a solar cell according to another embodiment of the present application;

[0016] Figure 3 A schematic diagram of a process for preparing a solar cell according to an embodiment of the present application.

[0017] Description of reference numerals:

[0018] Silicon substrate 10; first tunneling oxide layer 21; second tunneling oxide layer 22; first doped polysilicon layer 31; second doped polysilicon layer 32; first passivation layer 41; second passivation layer 42; protective layer 43; first gate 51; second gate 52; light receiving area 100; gate area 200. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the drawings, but unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repeated descriptions of actually identical structures may be omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate understanding by those skilled in the art. In addition, the drawings and the following description are provided for those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0020] Unless otherwise defined, all technical and scientific terms used in this application have the same meanings as those commonly understood by technicians in the technical field to which this application belongs; the terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application; unless otherwise specified, the numerical values ​​of the parameters mentioned in this application can be measured using various measurement methods commonly used in the art (for example, they can be tested according to the methods given in the embodiments of this application).

[0021] The terms "including" and "having" in the specification and claims of the present application and any modifications thereof are open expressions, that is, including the contents specified in the present application but not excluding other contents.

[0022] In the description of this application, regardless of whether the words "about" or "approximately" are used, all the numbers disclosed herein are approximate values. The value of each number may differ by less than 10% or a reasonable difference considered by those skilled in the art, such as 1%, 2%, 3%, 4% or 5%.

[0023] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. "First feature" and "second feature" may include one or more of the features.

[0024] In the description of the present application, "A and / or B" may include the case of A alone, the case of B alone, or any of the cases of A and B, where A and B are only used for examples and may be any technical feature connected by "and / or" in the present application.

[0025] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0026] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0027] By forming a TOPcon (i.e. tunneling oxide layer and doped polysilicon layer) passivation structure on the light-receiving side of the battery, the passivation contact of the light-receiving side of the battery can be effectively improved. However, doped polysilicon will have a parasitic absorption effect on light, so that part of the incident light is not converted into useful electrical energy, but into heat energy, resulting in a decrease in the battery's utilization of light.

[0028] In the present application, a TOPcon structure is selectively set in the gate region on the light-receiving side of the silicon substrate. Since the gate structure itself will block the light from irradiating the silicon substrate, the TOPcon structure located on the light-receiving side of the silicon substrate can effectively improve the passivation contact of the light-receiving surface of the battery without additionally blocking the incident light, thereby effectively reducing the parasitic absorption problem of light by the doped polysilicon in the TOPcon structure.

[0029] For ease of understanding, the preparation process of the solar cell in the present application is briefly described below: after forming the TOPcon structure on the light-receiving surface of the silicon substrate 10 by conventional processes, the doped polysilicon layer in the gate region is laser treated, thereby forming a silicon oxide protective layer 43 in the gate region, and then the doped polysilicon layer in the light-receiving region 100 that is not covered by the silicon oxide protective layer can be removed by conventional alkaline etching, and the doped polysilicon layer in the gate region is retained due to the presence of the silicon oxide protective layer 43, thereby alleviating the disadvantage of strong parasitic absorption of the doped polysilicon layer in the light-receiving region 100. Furthermore, the first tunneling oxide layer of the TOPcon structure that has not been removed in the light-receiving region 100 is thinner, and there is almost no parasitic absorption, which has almost no effect on the photocurrent. Therefore, by omitting the removal step of the first tunneling oxide layer in the light-receiving region, the cost can be significantly reduced without affecting the battery performance. The TOPcon structure in the gate region can effectively passivate the contact, and the silicon oxide protective layer 43 formed by laser treatment can further improve the passivation effect.

[0030] In a first aspect of the present application, the present application proposes a solar cell, referring to Figure 1 , including: a silicon substrate 10, the light-receiving surface of the silicon substrate 10 including a light-receiving area 100 and a gate area 200; a first tunneling oxide layer 21, the first tunneling oxide layer 21 is located on one side of the light-receiving surface of the silicon substrate 10; a first doped polysilicon layer 31, the first doped polysilicon layer 31 is located on a side away from the silicon substrate 10, and the orthographic projection of the first doped polysilicon layer 31 on the silicon substrate 10 is located in the gate area 200; a protective layer 43, the protective layer 43 is located on a side away from the first doped polysilicon layer 31, the protective layer 43 includes silicon oxide, and the thickness of the protective layer 43 is 2nm-6nm. Therefore, the TOPcon structure located in the gate area can improve the passivation effect of the light-receiving surface of the battery, and because the first doped polysilicon layer 31 is not provided in the light-receiving area, the parasitic absorption of light by the first doped polysilicon layer 31 in the light-receiving area is effectively reduced, thereby improving the photoelectric conversion efficiency of the battery.

[0031] As an example, the thickness of the protective layer may be 2 nm, 3 nm, 4 nm, 5 nm or 6 nm.

[0032] In some embodiments, reference Figure 2 When the silicon substrate 10 is an N-type silicon wafer, the first doped polysilicon layer 31 located on the light-receiving side of the silicon substrate is P-type polysilicon (i.e. silicon doped with boron), and the second doped polysilicon layer 32 located on the backlight side of the silicon substrate is N-type polysilicon (i.e. silicon doped with phosphorus). This helps to show a lower light-induced degradation effect under illumination and improve the photoelectric conversion efficiency.

[0033] In some embodiments, the thickness of the first doped polysilicon layer 31 is 40 nm-200 nm. Thus, the protection layer 43 can protect the first doped polysilicon layer 31 in the gate region 200, so that the first doped polysilicon layer 31 in the gate region 200 is retained after the alkaline etching process.

[0034] As an example, the thickness of the first doped polysilicon layer may be 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm.

[0035] There may be a natural oxide layer with a thickness of about 1 nm on the surface of the first doped polysilicon layer away from the silicon substrate. When the thickness of the protective layer is within the aforementioned range, the protective layer can preserve the first doped polysilicon layer 31 in the gate region 200 after alkaline etching treatment, while having little effect on the characteristics of the first doped polysilicon layer itself.

[0036] In some embodiments, the first tunneling oxide layer 21 satisfies at least one of the following conditions: the first tunneling oxide layer 21 includes a silicon-based oxide (SiO x ); the thickness of the first tunnel oxide layer 21 is 1nm-2nm. Thus, the first tunnel oxide layer 21 can be provided to achieve efficient carrier selective transmission and enhance current collection.

[0037] As an example, the first tunnel oxide layer may include silicon oxide (SiO x ), thus, the passivation effect of the first tunnel oxide layer is the best and easy to mass produce.

[0038] As an example, the thickness of the first tunnel oxide layer may be 1 nm, 1.5 nm or 2 nm.

[0039] When the thickness of the first tunnel oxide layer is within the above range, the first tunnel oxide layer can reduce the recombination rate of carriers (electrons and holes), and the first tunnel oxide layer located in the light-receiving area has very little parasitic absorption of the incident light, and has little effect on the photoelectric conversion efficiency of the battery.

[0040] In some embodiments, reference Figure 1 , a first passivation layer 41, the first passivation layer 41 is located on a side of the protective layer 43 away from the first doped polysilicon layer 31, and on a side of the first tunneling oxide layer 21 in the light receiving area 100 away from the silicon substrate 10, and the first passivation layer 41 may include an aluminum-based oxide (AlO x ), silicon-based nitride (SiN x), silicon-based oxide (SiO x ), silicon-based oxynitride (SiON). Thus, the passivation effect of the gate region 200 can be improved by the first passivation layer 41.

[0041] In some embodiments, the light-receiving surface of the silicon substrate 10 is a textured surface; and / or the backlight surface of the silicon substrate 10 is a polished surface. Thus, the photoelectric conversion efficiency of the battery can be further improved.

[0042] The pn junction in the battery is located on the light-receiving surface of the silicon substrate. The shorter wavelength part of the incident light will produce a photovoltaic effect at the pn junction, and the longer wavelength part of the incident light will pass through the main body of the silicon substrate 10 to reach the backlight surface of the silicon substrate. When the backlight surface of the silicon substrate is a velvet surface, the longer wavelength part of the light will be reflected chaotically and cannot be effectively reflected to the pn junction of the light-receiving surface for use; when the back surface of the silicon substrate is a polished surface, the longer wavelength part of the light will be reflected more uniformly and can be effectively reflected to the light-receiving surface of the silicon substrate for use. In addition, when the backlight surface of the silicon substrate 10 is a polished surface, it is easier to coat the backlight surface and the passivation contact effect is better.

[0043] As an example, refer to Figure 1 and Figure 2 The light-receiving surface of the silicon substrate 10 is a textured surface. Therefore, the textured structure has a better light trapping effect and can improve the utilization rate of incident light.

[0044] As an example, refer to Figure 2 The backlight surface of the silicon substrate 10 is a polished surface. Therefore, the incident light is reflected on the polished surface for secondary use, and the polished surface is easier to passivate, and the separation efficiency of photogenerated carriers is higher.

[0045] In some embodiments, reference Figure 2 The backlight surface of the silicon substrate may include a second tunneling oxide layer 22, a second doped polysilicon layer 32 and a second passivation layer 42 stacked in sequence. A second gate 52 is also disposed on the side of the second passivation layer away from the silicon substrate.

[0046] As an example, the thickness of the second polysilicon layer 32 may be 20 nm-160 nm.

[0047] As an example, the thickness of the second tunnel oxide layer 21 may be 1 nm-2 nm.

[0048] In some embodiments, reference Figure 1 and Figure 2 The first gate 41 is electrically connected to the protection layer 43 through the through hole on the first passivation layer 41 , thereby being electrically connected to the first polysilicon layer 31 .

[0049] In the second aspect of the present application, the present application proposes a method for preparing the aforementioned solar cell, whereby the aforementioned solar cell can be prepared by a simple method, which has the advantages of simple process and low cost. Specifically, the method comprises:

[0050] S100: forming a first tunneling oxide layer and a preformed first doped polysilicon layer stacked on one side of the light-receiving surface of the silicon substrate

[0051] In some embodiments, reference Figure 3 In (a), a first tunneling oxide layer 21 and a preformed first doped polysilicon layer 31' are stacked on the light-receiving surface of the silicon substrate.

[0052] In some embodiments, reference Figure 3 In (a), there is no particular restriction on the preparation order of the first tunneling oxide layer 21 and the preformed first doped polysilicon layer 31' located on the light-receiving surface of the silicon substrate, and the second tunneling oxide layer 22 and the second doped polysilicon layer 32 located on the backlight side of the silicon substrate. For example, the first tunneling oxide layer 21 and the preformed first doped polysilicon layer 31' on the light-receiving surface of the silicon substrate may be prepared in sequence, and then the second tunneling oxide layer 22 and the second doped polysilicon layer 32 located on the backlight side of the silicon substrate may be prepared in sequence; or the first tunneling oxide layer 21 on the light-receiving surface of the silicon substrate and the second tunneling oxide layer 22 located on the backlight side of the silicon substrate may be prepared at the same time, and then the preformed first doped polysilicon layer 31' and the second doped polysilicon layer 32 may be prepared. Specifically, the tunneling oxide layer and the doped polysilicon layer may be prepared by low pressure chemical vapor deposition (LPCVD).

[0053] As an example, the silicon substrate may be an N-type silicon wafer.

[0054] As an example, boron diffusion may be performed on the preformed first doped polysilicon layer 31 ′, and phosphorus diffusion may be performed on the second doped polysilicon layer 32 .

[0055] In some embodiments, before forming the first tunneling oxide layer 21 and the pre-formed first doped polysilicon layer 31', the following may be included: cleaning and texturing the light-receiving surface of the original silicon wafer to make the light-receiving surface of the silicon substrate a texturing surface, and diffusing boron on the light-receiving surface of the cleaned and texturing silicon wafer, and performing oxidation treatment, and then alkaline polishing on the backlight surface to make the backlight surface of the silicon substrate a polishing surface, and finally removing the borosilicate glass on the light-receiving surface of the silicon wafer.

[0056] Boron diffusion can form a boron-doped silicon layer on the light-receiving surface of the N-type silicon substrate, thereby forming a pn junction on the light-receiving side of the substrate. Oxidation treatment can form a certain thickness of borosilicate glass on the light-receiving surface of the silicon substrate, thereby protecting the velvet structure of the light-receiving surface when the backlight surface of the silicon substrate is subsequently wet-polished with alkali. The oxide layer formed by the oxidation treatment can absorb some inactive impurity elements after boron diffusion and remove them in the subsequent wet process, thereby reducing carrier recombination.

[0057] In some embodiments, the borosilicate glass is a dead layer, has no carriers, and cannot produce a photovoltaic effect. In the alkali polishing process, the light-receiving surface of the silicon substrate is protected by borosilicate glass, and an alkaline solution can be used directly to polish the backlight surface, and then hydrogen fluoride can react with the borosilicate glass to remove the borosilicate glass on the light-receiving surface.

[0058] S200: Laser processing the preformed first doped polysilicon layer

[0059] In some embodiments, see Figure 3 In step (b), a laser with a specific power and wavelength is used to perform laser processing on the preformed first doped polysilicon layer 31 ′ in the area of ​​the light-receiving surface where the first gate is to be printed, so as to form a local silicon oxide protective layer, thereby forming a protective layer 43 .

[0060] In some embodiments, the wavelength of the laser treatment is 315nm-390nm.

[0061] As an example, the power wavelength of the laser treatment may be 315 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, 370 nm, 380 nm, or 390 nm.

[0062] In some embodiments, the power of the laser treatment is 2W-5W.

[0063] As an example, the power of the laser treatment may be 2W, 2.5W, 3W, 3.5W, 4W, 4.5W, or 5W.

[0064] When the power and wavelength of the laser processing are within the aforementioned range, the laser energy is moderate, and the laser can be well controlled to process only the preformed first doped polysilicon layer in the gate region to form a silicon oxide protective layer of moderate thickness. Compared with the technical solution of directly forming a patterned doped polysilicon layer using a mask, the cost of the mask is relatively high, and it can only be applied to a predetermined pattern, which is not convenient for structural improvement; compared with the technical solution of directly removing the doped polysilicon layer in the light-receiving area using laser processing, the doped polysilicon layer in the light-receiving area occupies a larger area, and an excessively large processing area will make the processing time too long, the consumption of the laser head is too large, and there is also the possibility of damaging the silicon substrate.

[0065] S300: performing alkaline etching on the preformed first doped polysilicon layer located in the light receiving area

[0066] In some embodiments, reference Figure 3 In (c), in this step, the preformed first doped polysilicon layer 31' in the light receiving area is removed by wet etching. During the wet etching process, the silicon oxide protection layer 43 can protect the TOPcon structure in the gate area from corrosion by the etching solution to expose the first tunneling oxide layer 21 located in the light receiving area 100 to form a first doped polysilicon layer 31.

[0067] In some embodiments, the etching solution for the alkaline etching treatment includes at least one of an aqueous solution of NaOH and an aqueous solution of KOH. For example, the mass fraction of the etching solution for the alkaline etching treatment is 5%-15%.

[0068] As an example, the etching solution may be a mixture of an aqueous solution of NaOH and an aqueous solution of KOH in a mass ratio of 1:5.

[0069] In some embodiments, the alkaline etching treatment lasts for 80s-120s, and the alkaline etching treatment temperature is 35° C.-50° C. This helps to completely remove the preformed first doped polysilicon layer 31 ′ in the light receiving area 100 .

[0070] S400: forming a first passivation layer 41 on a side of the protection layer 43 away from the first doped polysilicon layer 31 and on a side of the first tunneling oxide layer 21 in the light receiving area 100 away from the silicon substrate 10

[0071] In some embodiments, reference Figure 3 In (d), in this step, a first passivation layer and a second passivation layer are deposited on the light-receiving surface and the backlight surface of the silicon substrate respectively.

[0072] In some embodiments, preparing solar cells may further include: metallizing the silicon substrate by screen printing, sintering and light injection, so that the screen-printed silver paste or other conductive paste can be solidified by sintering. Light injection treatment refers to placing the finished battery under certain temperature and light conditions, adjusting the Fermi level change by temperature and light intensity, and controlling the total amount and valence of H to improve the passivation performance.

[0073] In the third aspect of the present application, the present application proposes a photovoltaic module, comprising at least one battery string, wherein the battery string comprises at least two aforementioned solar cells, or a solar cell prepared by the aforementioned method. Thus, the photovoltaic module has all the features and advantages of the aforementioned solar cell and the method for preparing the solar cell, which will not be described in detail here.

[0074] In some embodiments, the solar cells may be connected together by serial welding, so that the electric energy generated by the individual solar cells can be collected for subsequent transmission.

[0075] In some embodiments, the solar cells may be arranged at intervals or stacked together in a shingled form.

[0076] For example, the photovoltaic module further includes an encapsulation layer and a cover plate, wherein the encapsulation layer is used to cover the surface of the battery string, and the cover plate is used to cover the surface of the encapsulation layer away from the battery string.

[0077] In some embodiments, the photovoltaic system may include the photovoltaic assembly described above. Therefore, the photovoltaic system has all the features and advantages of the photovoltaic assembly described above, which will not be described in detail here.

[0078] Photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water power stations, etc., and can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is to say, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0079] The scheme of the present application is described below by specific examples. It should be noted that the following examples are only used to illustrate the present application and should not be considered as limiting the scope of the present application. If no specific technology or conditions are specified in the examples, the technology or conditions described in the literature in this area or the product instructions are used. The reagents or instruments used are not specified by the manufacturer, and are all conventional products that can be obtained commercially.

[0080] Example 1

[0081] Step S1) cleaning and texturing the N-type silicon wafer.

[0082] Step S2) Boron is diffused on the front side of the cleaned and textured N-type silicon wafer, and then oxidized to prepare a PN junction and a borosilicate glass layer.

[0083] Step S3) removes the borosilicate glass layer plated on the side and back sides, and performs alkali polishing on the back side of the silicon wafer.

[0084] Step S4) tunneling silicon oxide and intrinsic polysilicon are deposited simultaneously on the front and back sides using LPCVD.

[0085] Step S5) Phosphorus is diffused on the back side of the silicon wafer to form N-type polysilicon.

[0086] Step S6) Boron is diffused on the front side of the silicon wafer to form P-type polysilicon.

[0087] Step S7) Use a laser with a wavelength of 355 nm (processing power of 3.5 W) to process the front area to be printed with grid lines to form a local protective layer (silicon oxide film layer).

[0088] Step S8) using 40° C., 9% potassium hydroxide solution to treat the front side for 100 seconds to remove the P-type polysilicon in the non-gate line area.

[0089] Step S9) Deposit a passivation anti-reflection film on both the front and back sides of the silicon wafer. First, deposit AlO on the front side by ALD. x The film layer is 16nm, and then SiN is deposited by PECVD x The film layer is 75nm, and SiN is deposited on the back x The film layer is 75nm.

[0090] Step S10) metallization screen printing is performed on the silicon wafer, and sintering and light injection are performed to obtain a battery.

[0091] Example 2

[0092] Example 2 is consistent with Example 1, except that the power of the laser treatment used is 5W.

[0093] Example 3

[0094] Example 3 is consistent with Example 1, except that the power of the laser processing used is 2W.

[0095] Example 4

[0096] Example 4 is consistent with Example 1, except that the mass fraction of the potassium hydroxide solution used in S8 is 5%.

[0097] Example 5

[0098] Example 5 is consistent with Example 1, except that the mass fraction of the potassium hydroxide solution used in S8 is 15%.

[0099] Example 6

[0100] Example 6 is consistent with Example 1, except that the cleaning time of S8 alkaline solution is 80s.

[0101] Example 7

[0102] Example 7 is consistent with Example 1, except that the cleaning time of S8 alkaline solution is 120s.

[0103] Comparative Example 1

[0104] Comparative Example 1 is consistent with Example 1, except that no alkaline etching treatment is performed, and the first doped polysilicon layer located in the light receiving area is retained.

[0105] Comparative Example 2

[0106] Comparative Example 2 is consistent with Example 1, except that the light-receiving surface of the silicon substrate is not provided with the first doped polysilicon layer and the first tunneling oxide layer.

[0107] The performance of the solar cells prepared in the above examples and comparative examples was tested under standard test conditions (AM1.5, 25°C, 1000 W / m 2 ), using steady-state test on IV tester. Test parameters include photoelectric conversion efficiency (Eta / %), open circuit voltage (Uoc / V), short circuit current (Isc / A) and fill factor (FF / %). Test results are shown in Table 1:

[0108] Table 1

[0109] serial number Eta / % Isc / A Uoc / V FF / % Example 1 26.60 18.467 0.7309 86.90 Example 2 26.45 18.448 0.7285 86.79 Example 3 26.47 18.444 0.7288 86.83 Example 4 26.33 18.346 0.7294 86.77 Example 5 26.44 18.446 0.7287 86.74 Example 6 26.35 18.341 0.7299 86.79 Example 7 26.45 18.457 0.7291 86.68 Comparative Example 1 25.99 18.334 0.7229 86.47 Comparative Example 2 25.86 18.372 0.7186 86.39

[0110] The test results show that the conversion efficiency of the solar cell provided by the embodiments of the present application is better than that of comparative examples 1 to 2 in all aspects, among which embodiment 1 performs the best. The laser processing power of embodiments 2 to 3 varies compared with that of embodiment 1. The laser power of embodiment 2 is higher, which damages the deposited first doped polysilicon layer, resulting in a slight decrease in the opening voltage. The laser power of embodiment 3 is lower, and the prepared protective layer is thinner, and the protection ability of the first doped polysilicon layer below is weak, resulting in slight damage to the first doped polysilicon layer in the subsequent wet process; the wet processing ability of embodiments 4 and 6 is weak, resulting in the first doped polysilicon layer in the light-receiving area not being completely removed, resulting in front parasitic absorption, causing a slight decrease in short current; the wet processing ability of embodiments 5 and 7 is strong, resulting in damage to the first doped polysilicon layer in the gate line area, causing a slight decrease in the opening voltage.

[0111] It should be noted that the present application is not limited to the above-mentioned embodiments. The above-mentioned embodiments are only examples, and the embodiments having the same structure as the technical idea and exerting the same effect within the scope of the technical solution of the present application are all included in the technical scope of the present application. In addition, without departing from the scope of the main purpose of the present application, various modifications that can be thought of by those skilled in the art to the embodiments and other methods of combining some of the constituent elements in the embodiments are also included in the scope of the present application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, wherein the light-receiving surface of the silicon substrate includes a light-receiving region and a gate region; A first tunneling oxide layer, wherein the first tunneling oxide layer is located on a light-receiving surface side of the silicon substrate; A first doped polysilicon layer, wherein the first tunnel oxide layer of the first doped polysilicon layer is away from a side of the silicon substrate, and an orthographic projection of the first doped polysilicon layer on the silicon substrate is located in the gate region; A protective layer, wherein the protective layer is located on a side of the first doped polysilicon layer away from the first tunneling oxide layer, the protective layer comprises silicon oxide, and the thickness of the protective layer is 2nm-6nm.

2. The solar cell according to claim 1, characterized in that The thickness of the first doped polysilicon layer is 40nm-200nm.

3. The solar cell according to claim 1, characterized in that The first tunnel oxide layer satisfies at least one of the following conditions: The first tunneling oxide layer comprises a silicon-based oxide; The thickness of the first tunnel oxide layer is 1 nm-2 nm.

4. The solar cell according to any one of claims 1-3 further comprises a first passivation layer, wherein the first passivation layer is located on a side of the protective layer away from the first doped polysilicon layer, and on a side of the first tunneling oxide layer in the light receiving area away from the silicon substrate, and the first passivation layer comprises at least one of aluminum-based oxide, silicon-based nitride, silicon-based oxide, and silicon-based oxynitride.

5. The solar cell according to any one of claims 1 to 3, characterized in that: The light-receiving surface of the silicon substrate is a textured surface; and / or the light-receiving surface of the silicon substrate is a polished surface.

6. The solar cell according to any one of claims 1 to 3, characterized in that: The silicon substrate includes an N-type silicon wafer, and the first doped polysilicon layer includes P-type polysilicon.

7. A method for preparing the solar cell according to any one of claims 1 to 6, characterized in that: include: Forming a first tunneling oxide layer and a preformed first doped polysilicon layer in a stacked manner on one side of the light-receiving surface of the silicon substrate; performing laser processing on the preformed first doped polysilicon layer to form a protective layer; Performing alkaline etching on the preformed first doped polysilicon layer located in the light receiving area to expose the first tunneling oxide layer located in the light receiving area to form a first doped polysilicon layer; A first passivation layer is formed on a side of the protection layer away from the first doped polysilicon layer and a side of the first tunneling oxide layer in the light receiving area away from the silicon substrate.

8. The method according to claim 7, characterized in that The wavelength of the laser treatment is 315nm-390nm; and / or the power of the laser treatment is 2W-5W.

9. The method according to claim 7 or 8, characterized in that: The alkaline etching treatment satisfies at least one of the following conditions: The etching solution for the alkaline etching treatment includes at least one of an aqueous solution of NaOH and an aqueous solution of KOH; The mass fraction of the etching solution for alkaline etching treatment is 5%-15%; The alkaline etching treatment time is 80s-120s; The temperature of the alkaline etching treatment is 35°C-50°C.

10. A photovoltaic module, characterized in that: The invention comprises at least one battery string, wherein the battery string comprises at least two solar cells according to any one of claims 1 to 6, or a solar cell prepared by the method according to any one of claims 7 to 9.

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