Adjustable timing event monitoring window

Abstract

The microelectronic circuit may include at least one timing event detector circuit configured to generate a timing event observation signal in response to a change in a digital value at an input of an associated register circuit during a timing event monitoring window. The microelectronic circuit may also include a control input for adjusting at least a duration of the timed event monitoring window.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to microelectronic circuit technology that includes internal monitoring for detecting timing events.Some example embodiments relate to adjusting the duration or position of a timed event monitoring (TEM) window. Background Art

[0002] The processing path in the microelectronic circuit can be implemented with logic cells and register circuits, for example, so that the register circuit stores the output value of the previous logic cell at the rising edge, falling edge, or both the rising edge and the falling edge of the trigger signal (if the register circuit includes a flip-flop) or at the high level or low level of the trigger signal (if the register circuit includes a latch). The trigger edge of the trigger signal (such as a clock signal) or some other control event can define an allowed time limit before which the digital value should appear at the data input of the register circuit to be correctly stored. The allowed time limit is not necessarily the exact moment of the trigger edge, but is defined in some relationship to the trigger edge due to physical effects (such as the finite rate at which the voltage level can change). The amount of time required for the data input to be stable before the trigger edge can be called the setup time. On the other hand, in some applications, the data input should remain stable for a certain time after the trigger edge. The minimum amount of time required for the data input to be stable after the trigger edge can be called the hold time. The logic cell can also be referred to as a combinational logic block.

[0003] Monitor circuits can be used to detect timing events. Monitor circuits can include timing event detector circuits. Monitor circuits can include circuit elements or functions added to or associated with register circuits, and are configured to generate timing event observation (TEO) signals in response to detecting a timing event. Timing events can, for example, include changes in the digital value of data input that occurs during a setup time later than the allowed time limit. In addition to actual monitor circuits, microelectronic circuits can include OR-trees and / or other structures for collecting, processing, and analyzing TEO signals from monitor circuits. Monitor circuits can also be used as stand-alone devices for other applications, such as edge detectors in digital phase-locked loops.

[0004] Detection of a timing event may trigger compensatory action, for example involving changes in the value of other operating parameters of the circuit, such as the clock frequency, or temporarily changing the clock waveform. Summary of the invention

[0005] This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0006] Example embodiments of the present disclosure achieve optimization of timing event detection by providing a dynamically adjustable TEM window. This benefit and other benefits can be achieved by the features of the independent claims. Further example embodiments are provided in the dependent claims, the description and the drawings.

[0007] According to a first aspect, a microelectronic circuit comprises: at least one timing event detector circuit configured to generate a timing event observation signal in response to a change in a digital value at an input of an associated register circuit during a timing event monitoring window; and a control input for adjusting at least one duration of the timing event monitoring window.

[0008] According to an exemplary embodiment of the first aspect, the timing event monitoring windows are associated with respective edges of the clock signal.

[0009] According to an exemplary embodiment of the first aspect, the microelectronic circuit further comprises a timing event monitoring window clock generator circuit for generating a timing event monitoring window clock signal, the timing event monitoring window clock signal indicating a duration of the timing event monitoring window and a position of the timing event monitoring window relative to a corresponding edge of the clock signal.

[0010] According to an example embodiment of the first aspect, a timing event monitoring window clock generator circuit is configured to provide a timing event monitoring window clock signal to a single timing event detector circuit, a subset of the timing event detector circuits of a microelectronic circuit, or all the timing event detector circuits of a microelectronic circuit.

[0011] According to an exemplary embodiment of the first aspect, a timed event monitoring window clock generator circuit comprises a tapped delay line for delaying a clock signal.

[0012] According to an example embodiment of the first aspect, the timing event monitoring window clock generator circuit is configured to: delay a clock signal to obtain a delayed clock signal; and generate a timing event monitoring window clock signal based on a combination of the clock signal and the delayed clock signal.

[0013] According to an example embodiment of the first aspect, the microelectronic circuit is configured to adjust a delay of the delayed clock signal based on a control input so as to adjust a duration of a timing event monitoring window.

[0014] According to an example embodiment of the first aspect, the duration of the timed event monitoring window is configured to be adjusted by selecting one of a plurality of outputs of the tapped delay line corresponding to a desired delay.

[0015] According to an exemplary embodiment of the first aspect, the combination of the clock signal and the delayed clock signal comprises a NOR operation.

[0016] According to an example embodiment of the first aspect, a timing event monitoring window clock generator circuit is configured to delay a clock signal to obtain a delayed clock signal, wherein the delayed clock signal indicates a duration of the timing event monitoring window and a position of the timing event monitoring window relative to a corresponding edge of the clock signal.

[0017] According to an exemplary embodiment of the first aspect, the microelectronic circuit is configured to adjust a duty cycle of the delayed clock signal in order to adjust a duration of a timing event monitoring window.

[0018] According to an example embodiment of the first aspect, the microelectronic circuit is configured to adjust a delay of the delayed clock signal so as to adjust a position of a timing event monitoring window relative to a corresponding edge of the clock signal.

[0019] According to an example embodiment of the first aspect, a timing event monitoring window clock generator circuit includes a time-to-digital converter configured to convert multiple outputs of a tapped delay line into digital values ​​in response to enabling calibration of the timing event monitoring window clock generator circuit, and the timing event monitoring window clock generator circuit is further configured to: determine a current clock cycle length of a clock signal based on the digital value; and reselect one of the multiple outputs of the tapped delay line based on the current clock cycle length so as to substantially maintain a desired delay relative to the current clock cycle length of the clock signal.

[0020] According to an example embodiment of the first aspect, the time-to-digital converter includes a capture register configured to capture multiple outputs of a tapped delay line, and wherein a timing event monitoring window clock generator circuit is configured to determine a current clock cycle length of a clock signal based on the captured multiple outputs of the tapped delay line.

[0021] According to an exemplary embodiment of the first aspect, at least a portion of the timing event monitoring window precedes a corresponding edge of the clock signal.

[0022] According to an exemplary embodiment of the first aspect, the timed event monitoring window precedes a corresponding edge of the clock signal, and wherein the timed event monitoring window ends at the clock edge.

[0023] According to an exemplary embodiment of the first aspect, the second timing event monitoring window is located after an edge of the clock signal.

[0024] According to an exemplary embodiment of the first aspect, a portion of the timing event monitoring window is located after an edge of the clock signal.

[0025] According to an example embodiment of the first aspect, the microelectronic circuit further comprises: a plurality of processing paths comprising logic cells and register circuits, wherein the register circuits are configured to temporarily store output values ​​of the logic cells in synchronization with a clock signal; a replica path emulating the operation of a critical path of the plurality of processing paths, wherein the replica path comprises a one-bit counter having feedback via a delay line matched to the critical path, and wherein the associated register circuit comprises a one-bit counter.

[0026] According to a second aspect, a method for operating a microelectronic circuit comprises generating a timing event observation signal in response to detecting a change in a digital value at an input of an associated register circuit during a timing event monitoring window; and adjusting at least a duration of the timing event monitoring window.

[0027] According to an example embodiment of the second aspect, the timing event monitoring windows are associated with respective edges of the clock signal.

[0028] According to an exemplary embodiment of the second aspect, the method further comprises generating a timed event monitoring window clock signal indicating a duration of the timed event monitoring window and a position of the timed event monitoring window relative to a corresponding edge of the clock signal.

[0029] According to an example embodiment of the second aspect, the method further comprises providing a timing event monitoring window clock signal to a single timing event detector circuit, a subset of the timing event detector circuits of the microelectronic circuit, or all timing event detector circuits of the microelectronic circuit.

[0030] According to an example embodiment of the second aspect, the timing event monitoring window is generated based on a tapped delay line configured to delay a clock signal.

[0031] According to an example embodiment of the second aspect, the method further comprises: delaying the clock signal to obtain a delayed clock signal; and

[0032] A timed event monitoring window clock signal is generated based on a combination of the clock signal and the delayed clock signal.

[0033] According to an example embodiment of the second aspect, the method further comprises: adjusting a delay of the delayed clock signal based on a control input so as to adjust a duration of the timing event monitoring window.

[0034] According to an example embodiment of the second aspect, the duration of the timed event monitoring window is adjusted by selecting one of a plurality of outputs of the tapped delay line that corresponds to a desired delay.

[0035] According to an example embodiment of the second aspect, the combination of the clock signal and the delayed clock signal comprises a NOR operation.

[0036] According to an exemplary embodiment of the second aspect, the method further comprises: delaying the clock signal to obtain a delayed clock signal, wherein the delayed clock signal indicates a duration of the timing event monitoring window and a position of the timing event monitoring window relative to a corresponding edge of the clock signal.

[0037] According to an exemplary embodiment of the second aspect, the method further comprises: adjusting a duty cycle of the delayed clock signal so as to adjust a duration of the timing event monitoring window.

[0038] According to an exemplary embodiment of the second aspect, the method further comprises: adjusting a delay of the delayed clock signal so as to adjust a position of the timing event monitoring window relative to a corresponding edge of the clock signal.

[0039] According to an example embodiment of the second aspect, a timing event monitoring window clock signal is generated based on a time-to-digital converter, which is configured to convert multiple outputs of a tapped delay line into digital values ​​in response to enabling calibration of a timing event monitoring window clock generator circuit, and the method also includes: determining a current clock cycle length of the clock signal based on the digital value; and reselecting one of the multiple outputs of the tapped delay line based on the current clock cycle length so as to substantially maintain a desired delay relative to the current clock cycle length of the clock signal.

[0040] According to an example embodiment of the second aspect, the time-to-digital converter comprises a capture register configured to capture multiple outputs of the tapped delay line, and the method further comprises determining a current clock cycle length of the clock signal based on the captured multiple outputs of the tapped delay line.

[0041] According to an example embodiment of the second aspect, at least a portion of the timing event monitoring window precedes a corresponding edge of the clock signal.

[0042] According to an example embodiment of the second aspect, the timed event monitoring window precedes a corresponding edge of the clock signal, and wherein the timed event monitoring window ends at the clock edge.

[0043] According to an example embodiment of the second aspect, a second timing event monitoring window is provided after an edge of the clock signal.

[0044] According to an example embodiment of the second aspect, a portion of the timing event monitoring window is located after an edge of the clock signal.

[0045] According to an example embodiment of the second aspect, a microelectronic circuit comprises a plurality of processing paths, the plurality of processing paths comprising logic cells and register circuits, wherein the register circuits are configured to temporarily store output values ​​of the logic cells in synchronization with a clock signal, and the method further comprises: simulating the operation of a critical path of the plurality of processing paths by means of a replica path, wherein the replica path comprises a one-bit counter having feedback via a delay line matching the critical path, and wherein the associated register circuit comprises a one-bit counter.

[0046] Any of the above-described example embodiments may be combined with one or more of the other example embodiments.Many of the accompanying features will be more readily understood as they become better understood by reference to the following detailed description in relation to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are included to provide a further understanding of the present invention and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and together with the description help explain the principles of the present invention. In the drawings:

[0048] Figure 1 An example of a microelectronic circuit with timing event monitoring is shown;

[0049] Figure 2 An example of a timed event monitoring clock generator circuit is shown, the timed event monitoring clock generator circuit being configured to generate a timed event monitoring clock signal based on a combination of a clock signal and a delayed clock signal;

[0050] Figure 3 An example of a timing diagram illustrating signals associated with timing event monitoring clock signal generation based on a NOR operation between a clock signal and a delayed clock signal is shown;

[0051] Figure 4 An example of a timed event monitoring clock generator circuit is shown, the timed event monitoring clock generator circuit being configured to generate a timed event monitoring clock signal based on a delayed clock signal;

[0052] Figure 5 An example of a timing diagram illustrating signals associated with monitoring clock signal generation based on a delayed clock signal for a timing event;

[0053] Figure 6 An example of a timing event window monitoring clock generator circuit with calibration function is shown;

[0054] Figure 7An example of a microelectronic circuit is shown that includes a timing event monitoring circuit associated with a replica path that includes a one-bit counter; and

[0055] Figure 8 An example of a method of operating a microelectronic circuit is shown.

[0056] In the drawings, the same reference numerals are used to denote the same components. DETAILED DESCRIPTION

[0057] The following describes a microelectronic circuit and its design and operation method. The microelectronic circuit may include multiple processing paths, the processing paths including logic cells and register circuits. The processing paths may include a series of circuit elements through which digital data may be processed in the logic cells and temporarily stored in register circuits between consecutive logic cells on the processing path. The register circuits may be configured to temporarily store output values ​​of the logic cells in synchronization with a clock signal. Software executed by the microelectronic circuit may define which processing paths are used in what manner at any given time.

[0058] Figure 1 An example of a microelectronic circuit with timing event monitoring is shown. As described above, the microelectronic circuit 100 may include multiple processing paths. The microelectronic circuit 100 may include a register circuit 110, such as a latch or trigger of any suitable type, optionally in combination with (one or more) other components. The register circuit 110 may belong to one of the processing paths of the microelectronic circuit 100 or to a replica path associated with one or more of the processing paths. The register circuit 110 may have a data input for receiving a digital value of a data signal (D) and a clock signal input for receiving a clock signal (CLK). The clock signal may be configured as a trigger signal for the register circuit 110 to store a digital value (D) currently appearing at the data input (e.g., at the rising edge or falling edge of the clock signal). The clock signal CLK may also be referred to as a master clock signal or a data clock signal.

[0059] The replica path can be configured to simulate the operation of one or more of the processing paths, for example using known input data. If a timing event is detected at the replica path, it can be assumed with reasonable probability that the timing event also occurred at the (one or more) "real" processing paths under the same operating conditions, for example, under the influence of the same values ​​of operating parameters (such as operating voltage, clock frequency, etc.). The operating parameters can be adjusted to avoid or at least reduce the probability of timing events at the (one or more) processing paths. For example, the operating voltage can be increased or the clock frequency can be reduced, at least in the corresponding part of the microelectronic circuit.

[0060] The register circuit 110 may be associated with a timing event monitoring (TEM) circuit 120. The data input of the TEM circuit 120 may be connected to the data input of the register circuit 110. Thus, the TEM circuit 120 may receive as an input a copy of the data input into the register circuit 110. The TEM circuit 120 may be configured to generate a timing event observation (TEO) signal, e.g., in response to a change in a digital value at the data input (D) of the register circuit 110 that occurs during a TEM monitoring window associated with a corresponding edge of a clock signal (CLK), e.g., later than an allowed time limit before the edge of the clock signal (CLK). For example, the TEO signal may include a binary digital signal that is normally at a logic low level, but at the moment of detecting a timing event (e.g., a change in data value during the TEM window), the TEM circuit 120 may raise the TEO signal to a logic high level. The TEO signal may remain at a logic high level until the end of the clock cycle in which the timing event is observed, or optionally longer.

[0061] Each instance of the TEM window can be associated with a corresponding edge of a clock signal (CLK). Therefore, a specific instance of the TEM window can monitor a timing event associated with a corresponding clock edge. However, a TEM window independent of the clock edge can be arranged to monitor timing events that are not directly associated with the edge of the clock signal. The duration and position of the TEM window can be defined by a TEM window clock signal (TEM_CLK) received as another input at the TEM circuit 120. The TEM window can also be referred to as a timing event observation (TEO) window. The TEM circuit 120 can also be referred to as a timing event detector circuit.

[0062] The microelectronic circuit 100 may further include a TEM window clock generator circuit 130, which may also be referred to as a TEM clock generator. The TEM window clock generator circuit 130 may be configured to generate a TEM window clock signal (TEM_CLK), for example, based on a (master) clock signal (CLK), and provide the generated TEM_CLK to the TEM circuit 120. The TEM window clock signal may indicate a duration of the TEM window and a position of the TEM window relative to a corresponding clock edge. For example, a logic high level or a logic low level of the TEM_CLK may define a position and duration of the TEM window. Referring to Figure 2 and Figure 4 An example of the TEM window clock generator circuit 130 is described.

[0063] The TEM window clock generator circuit 130 can provide its output to one or more TEM circuits 120. In one example, TEM_CLK is provided to a single TEM circuit 120. This will enable a register circuit-specific configuration of the TEM window. Alternatively, TEM_CLK can be provided to a group of TEM circuits, such as a subset of the TEM circuits of the microelectronic circuit 100. For example, a subset can be defined by classifying the TEM circuits based on the likelihood that a timing event occurs in the register circuits they monitor. This likelihood can be estimated, for example, based on the length of the processing path before the corresponding TEM circuit in the absence of other TEM circuits. The same TEM_CLK signal can be provided to the TEM circuits within the same category. This enables the TEM overhead in terms of silicon area to be reduced while achieving a certain degree of TEM window optimization for different parts of the microelectronic circuit. TEM_CLK can also be provided to all register circuits of the microelectronic circuit 100. This makes the TEM overhead very low because the microelectronic circuit 100 can include a single TEM window clock signal generator 130.

[0064] The microelectronic circuit 100 may include a control input for adjusting at least one duration of the TEM window. Optionally, the position of the TEM window relative to the corresponding clock edge may also be adjusted. The duration and / or position of the TEM window may be adjusted dynamically (e.g., during the run time of the microelectronic circuit 100), for example based on various operating parameters (e.g., the current operating voltage or clock frequency, or the number of detected timing events).

[0065] In one example, the control input comprises a TEM window clock signal input of the TEM circuit 120. Alternatively, the control input may comprise a control input within the TEM window clock generator circuit 130, wherein the control input may be configured to modify the TEM window clock signal provided to the TEM circuit 120, such as by referring to, for example, Figure 2 As further described, the adjustable TEM window can optimize the monitoring of timing events at the microelectronic circuit 100. The monitoring of timing events by the TEM circuit 120 consumes power, so shortening the duration of the TEM window whenever possible can save power. Therefore, the energy consumption of the microelectronic circuit 100 can be reduced.

[0066] Figure 2An example of a TEM window clock generator circuit configured to generate a TEM clock signal based on a combination of a clock signal and a delayed clock signal is shown. As described above, the TEM window clock generator circuit (indicated by reference numeral 130-1 in this example) can receive a clock signal CLK (master clock) as an input. The TEM window clock generator circuit 130-1 may include a plurality of delay elements 131-1, 131-2, ..., 131-n, which are configured to delay the input clock signal. The delay elements may form a tapped delay line (TDL) 131 or be part of a tapped delay line 131. The outputs of the respective delay elements may be provided to a multiplexer (MUX) 132, for example, via an n-wide bus. The multiplexer 132 may be configured to select one of its inputs (i.e., the clock signal (CLK) corresponding to the desired delay) by controlling the input delay_sel, and provide a selected signal (CPD) as an output of the multiplexer 132. Thus, the CPD may include a delayed version of the clock signal (CLK). The delayed clock signal (CPD) can be combined with the clock signal CLK, for example, by any suitable logic operation, to generate the TEM window clock signal (TEM_CLK). The control input delay_sel enables dynamic adjustment of the duration of the TEM window. The microelectronic circuit 100 can thus adjust the delay of the delayed clock signal (CPD) based on the control input. This can result in adjustment of the TEM window duration.

[0067] The TEM window clock signal is generated based on the delayed clock signal (CPD) in this example in combination with the (non-delayed) clock signal (CLK), so that the TEM window can be linked to the corresponding clock edge. Therefore, changes in the clock signal (e.g. due to non-idealities of the microelectronic circuit 100) may not affect the position of the TEM window relative to the corresponding clock edge.

[0068] The clock signal (CLK) and the delayed clock signal (CDP) may be combined in any suitable manner, for example by means of logic elements (eg gates), such as for example Figure 2 133. However, it should be understood that the functions described herein may also be implemented in practice using different circuit elements, as is common in digital circuits: for example, having been taught the desired functions, a person skilled in the art may be able to come up with several alternative implementations that differ in, for example, the polarity of the signal and the resulting need for the use of circuit elements such as inverters, appropriately selected logic gates, etc.

[0069] Figure 3An example of a timing diagram of signals associated with generating a timing event monitoring clock signal based on a NOR operation between a clock signal and a delayed clock signal is shown. Figure 2 The TEM window clock generator circuit 130-1 shown in is provided. On the left, the clock signal (CLK) is delayed by a delay d1, corresponding to the corresponding number of delay elements selected by the control input delay_sel, to obtain a delayed clock signal (CPD). As defined by NOR133, when both CLK and CPD are low (LOW), the TEM_CLK signal becomes high. In this example, the logic high level of TEM_CLK defines the position of the TEM window. In this example, the TEM window is located before the corresponding clock edge. The TEM window ends at the clock edge. However, to be precise, the TEM window may also involve rise time and fall time, so the actual range of the TEM window may generally depend on CLK and / or CPD, and may not necessarily start and end at the precise moment of its associated trigger edge.

[0070] On the right, the clock signal (CLK) is delayed by a delay d2 which is longer than delay d1. The duration of the TEM window is shortened accordingly. However, it is noted that the position of the ends of the TEM window is maintained relative to the clock edge of CLK (substantially coincident with the clock edge). Providing (at least a portion of) the TEM window prior to the clock edge enables detection of timing events during the setup of the register circuit 110. Because the duration of the TEM window can be adjusted, dynamically adjustable setup monitoring is provided. Delay d1 and delay d2 can be adjusted from the range 0 ≤ d <T CLK_LOW Select from, where T CLK_LOW is the time for the clock signal (CLK) to reach a certain level, which, together with the delayed clock signal (low in this case), defines the TEM window. Therefore, the TEM window duration can range from 0 <d≤T CLK_LOW The value inside.

[0071] In addition, a second TEM window can be provided after the corresponding clock edge. This enables the detection of a hold violation. The second TEM window can start substantially at the corresponding edge of the clock signal (CLK). The hold phase may be more susceptible to random variations than the setup phase (e.g., due to a shorter path, the average effect is smaller (less averaging)), while the setup phase, for example, due to a longer path, the average effect is larger (more averaging). Therefore, in some applications, operating parameters (e.g., minimum operating voltage, VDD_min) can be derived based only on setup monitoring. The hold situation may persist. However, it is beneficial to reliability that setup and hold can be monitored separately.

[0072] Figure 4 An example of a TEM clock generator circuit configured to generate a TEM window clock signal based on a delayed clock signal is shown. Figure 2 In the example of , the TEM window clock generator circuit represented by reference numeral 130-2 in this example may include an input of a (master) clock signal (CLK), a tapped delay line 131 and a multiplexer (MUX) 132. However, the output of the TEM window clock generator 130-2 may be directly the delayed clock signal (CPD) (TEM_CLK=CPD) instead of its combination with the clock signal (CLK). This makes it possible to decouple the ends of the TEM window from the corresponding edges of the clock signal (CLK). Therefore, the delayed clock signal can indicate (e.g., define) the duration of the TEM window and its position relative to the corresponding edge of the clock signal (CLK).

[0073] In addition, the TEM window clock generator 130-2 can be configured to adjust the duty cycle of the delayed clock signal (CPD), for example, by extending or shortening the time that the delayed clock signal (CDP) stays at a logic high level. Since the TEM window can be defined by a certain level of the delayed clock signal, the duration of the TEM window can be adjusted by adjusting the duty cycle. In addition, the position of the TEM window relative to the corresponding edge of the clock signal (CLK) can be adjusted by adjusting the delay of the CPD, for example, by controlling the input delay_sel.

[0074] Figure 5 An example of a timing diagram of signals associated with generating a TEM clock signal based on a delayed clock signal is shown. Figure 4 1 is provided by the TEM window clock generator circuit 130-2 shown in FIG. On the left, the clock signal (CLK) is delayed by a delay d1 to obtain a delayed clock signal (CPD). CPD (in this case, the TEM_CLK signal) has a first duty cycle (duty_cycle_1), corresponding to the time when CPD is at a logic high level. In this example, the TEM window is defined by the logic low level of CPD / TEM_CLK. Therefore, a portion of the TEM window is before the corresponding clock edge. A portion of the TEM window is after the corresponding clock edge. The TEM window can continue on the corresponding clock edge.

[0075] On the right, the clock signal (CLK) is delayed by a delay d2 to obtain CPD / TEM_CLK. CPD / TEM_CLK has a second duty cycle (duty_cycle_2) that is longer than the first duty cycle. Since the TEM window is defined by the logic low level of CPD / TEM_CLK, the TEM window on the right is shorter than the TEM window on the left. Therefore, the duration of the TEM window can be adjusted by adjusting the duty cycle of the delayed clock signal (CPD).

[0076] Furthermore, the position of the TEM window relative to the corresponding edge of the clock signal (CLK) can be adjusted by the delay of the CPD. Therefore, the proportion of the TEM window before the clock edge can also be adjusted. This enables the behavior of setup monitoring and hold monitoring to be dynamically configured. Advantageously for reliability, both setup and hold can be monitored.

[0077] In one example, the delay can be adjusted so that the TEM window is completely before the clock edge, achieving something like Figure 3 Thus, at least a portion of the TEM window (i.e., the entire TEM window or a portion thereof) may be located before the corresponding clock edge. This approach may be referred to as preponing the TEM window (resulting in a preponed TEM window) or advancing the TEM window (resulting in an advanced TEM window). When completely located before the corresponding clock edge, the TEM window may end at the corresponding clock edge.

[0078] The TEM window can be decoupled from a time borrowing window. Time borrowing in a microelectronic circuit can refer to allowing a circuit element to temporarily borrow time from a subsequent stage, for example, if (one or more) subsequent circuit elements on the same processing path can be processed without destroying the data being processed, the circuit element is allowed to change the digital value later than expected. In other words, if the register circuit 110 can handle timing events (such as late changes in digital values) without destroying the data being processed, the logic unit or other parts of the processing path before such a register circuit are temporarily allowed to cause timing events. In order to enable time borrowing, timing events detected during the time borrowing window can be ignored. The occurrence of a time borrowing instance can be detected as a timing event during the time borrowing window. As described above, the time borrowing window can be separated (decoupled) from the time borrowing window.

[0079] Figure 6 An example of a timing event monitoring window clock generator circuit with calibration function is shown. Figure 2 In the example of FIG. 1 , the TEM window clock generator circuit indicated by reference numeral 130-3 in this example may include an input of a (master) clock signal (CLK), a tapped delay line 131, a multiplexer (MUX) 132, and a NOR gate 133, wherein the NOR gate 133 is configured to combine the clock signal (CLK) and the delayed clock signal (CPD). However, it is possible that the TEM window clock generator 130-3 is configured similarly to Figure 4 Thus, the calibration method described herein can be applied to TEM clock generator circuits 130 - 1 and 130 - 2, as well as other variations thereof.

[0080] For example, calibration may be performed because the sensitivity of the delay chain (e.g., TDL 131) to PVT (process, voltage, temperature) variations can result in large variations in the monitoring window, including both systematic and random variations due to PVT. Calibrating the delay chain on an ongoing basis enables the TEM window size (duration) to be kept accurate even with PVT variations. Furthermore, ensuring that the small monitoring window is reliable and accurate enables the overall timing overhead in the system to be significantly reduced, thereby enabling the microelectronic circuit 100 to be applied to more timing sensitive, faster applications.

[0081] To achieve this, the TEM window clock generator 130-3 may further include a time-to-digital converter (TDC) configured to convert the output of the TDL 131 to a digital value, such as in response to enabling calibration of the TEM window clock generator circuit 1303. An example of such a TDC is a capture register 134, which may be configured to capture the output of the TDL 131, such as at least some of the outputs of the delay elements (buffers) 131-1, 131-2, ..., 131-n. The capture output may be responsive to enabling calibration of the TEM window clock generator circuit 130-3, such as by providing a START signal to enable the clock signal (CLK) to propagate to the enable input of the capture register 134 through the AND gate 135. The clock period determination block 136 may be configured to determine the current length of the clock period (clock period) of the clock signal (CLK) based on the digital value provided by the TDC (e.g., the output of the TDL 131 captured at the capture register 134). The value of the capture register may be provided to the clock period determination block 136, for example, via an n-wide bus. The delay selection block 137 may be configured to (re)select one of the TDL outputs based on the current clock period length such that the desired delay relative to the current clock period length is (substantially) maintained. For example, the TDL output that provides the delay closest to the desired delay may be selected. This calibration function will be described further below.

[0082] In addition to being routed to the multiplexer (MUX) 132, the output of each delay element 131-1, 131-2, ..., 131-n can also be routed to the corresponding trigger (134-1, 134-2, ..., 134-n) of the capture register 134. Whenever the system needs to be calibrated, the clock signal (CLK) reaching the capture register 134 can be released (clock gating is removed) for one clock pulse. In this way, the TDL output can be captured into the capture register 134, for example, at the next positive edge of the clock signal (CLK). At this time, the capture register 134 can contain a pattern of digital values ​​(e.g., 0 and 1). By analyzing the captured pattern, the clock cycle determination block 136 can determine the clock period of the clock signal (CLK) according to the number of delay buffers (delay elements of TDL 131). The trigger at which the digital value changes for the first time (e.g., from 1 to 0) can be determined to represent the clock period according to the number of delay elements. For example, if the value changes from 1 to 0 in flip-flop number 20, the clock period can be determined to be equal to 20 buffer delays. This value can be denoted by clock_period.

[0083] Based on the clock_period, at the delay selection block 137, the tap point to be selected in the delay buffer chain to create the desired delayed version of the clock signal (CLK) can be calculated easily and accurately. In the case of the previous example, i.e., clock_period = 20, if a delay equal to 10% of the clock period is desired, the delay selection block 137 can select the tap point after the second buffer. Or, if a delay equal to 50% of the clock period is needed, the block 137 can select the tap point after the tenth buffer. Calculating the desired tap point based on the value of the capture register 134 can be implemented, for example, by combinational logic or software. In one example, the output of the TDL 131 and the output of the capture register 131 are provided as a multi-bit thermometer code, where b(0),..., b(m) = 1, b(m + 1),..., b(n) = 0, and where m < n. The parameter m varies with the delay. The clock

[0084] In addition, additional optimizations can be implemented to reduce the logic count. For example, not all buffer outputs can be captured into the capture register 134. For example, the first few delay buffer outputs can be ignored, for example, if the system always has a monitoring window greater than half of the clock period. Thus, the clock period can be determined at the block based on the outputs of a subset of the delay elements of the TDL 131. This subset can be determined based on a predetermined constraint on the clock period or based on the previously detected clock period length. Calibration of the TEM clock generator is able to maintain the desired relative delay with respect to the clock period, even when the microelectronic circuit 100 is subject to non-ideal conditions (e.g., when PVT variations occur). In combination with the dynamically adjustable TEM window duration, the calibration is also able to keep the currently configured TEM window stable.

[0085] As described above, calibration of the TEM window clock generator circuit 130 can be done in hardware, for example, by the TEM window clock generator circuit 130 itself. Or, calibration of the circuit can be initiated by software, storing the measurement result (i.e., the clock period) in a memory. Then the TEM window configuration (e.g., the selection of a specific TDL output) can be updated by software based on the stored measurement result.

[0086] However, the calibration method described herein can be applied to a fixed TEM window. Therefore, according to an example embodiment, a microelectronic circuit may include: at least one timing event detector circuit configured to generate a timing event observation signal in response to a change in a digital value at an input of an associated register circuit during a timing event monitoring window associated with a corresponding edge of a clock signal; and at least one timing event monitoring window clock generator circuit, wherein the timing event monitoring window clock generator circuit includes a tapped delay line for delaying the clock signal, and wherein the timing event monitoring window clock generator circuit is configured to select one of a plurality of outputs of the tapped delay line that corresponds to a desired delay. The timing event monitoring window clock generator circuit may also include a time-to-digital converter configured to convert the output of the tapped delay line into a digital value (e.g., a capture register configured to capture the output of the tapped delay line) in response to enabling calibration of the timing event monitoring window clock generator circuit. The timing event monitoring window clock generator circuit may also be configured to determine a current clock cycle length of the clock signal based on the digital value (e.g., the captured output of the tapped delay line), and reselect one of the plurality of outputs of the tapped delay line based on the current clock cycle length. This is done to substantially maintain the desired delay. The desired delay may be fixed. Thus, a calibration of the fixed configuration TEM window is provided. This allows the fixed configuration TEM window to remain stable regardless of changes in PVT.

[0087] Figure 7 An example of a microelectronic circuit including a TEM circuit associated with a replica path is shown, the replica path including a single-bit counter. Directly monitoring the critical path can be considered an accurate way to understand the real-time changes in circuit speed. This information can then be used for various operations, such as adjusting the operating voltage according to the speed of the circuit to ensure that the circuit always operates at the lowest possible voltage. However, this method may not be very effective in the case where it is difficult to ensure the activity on the monitored critical path. The example embodiments of the present disclosure provide good alternatives for these types of paths. For example, a critical path monitoring technology solution based on a TEM window can be combined with a critical path replica based on a single-bit counter, which can be activated, for example, by enabling a clock signal (CLK) to the circuit. The replica path can be configured to simulate the operation of one or more critical paths in the processing path of the microelectronic circuit 100.

[0088] Example embodiments of the present disclosure can solve the following problems:

[0089] - Combining monitoring with an easily activated duplicate path ensures that the system (eg, microelectronic circuit 100) can activate the duplicate path at any time and check the timing margin on the critical path without relying on the unpredictable behavior of the actual critical path.

[0090] -For technical solutions based directly on monitoring critical paths, since activation is random, the entire system solution can take into account the probability of activation. This means that the number of monitors (or monitored paths) may be higher than if activation is perfect (if the critical path is always active). Example embodiments of the present disclosure are able to increase the probability of activation to 100% because the system has control over activation. This means that the number of monitors can be greatly reduced.

[0091] - Because it may be uncertain when the critical path is active, the monitoring technique can be active most of the time to ensure that it does not miss any activity in the critical path. This results in wasted energy when the monitoring is active to wait for activity in the critical path. Example embodiments of the present disclosure enable the system to control activation. This means that whenever the system wants to check the timing margin, the replication and monitoring can be turned on, for example, only for two clock cycles. This ensures that the power overhead caused by the monitoring will be much lower than a system that monitors the critical path directly.

[0092] The use of TEM circuits associated with register circuits, the use of duplicate paths, and other similar arrangements can be generally described as the presence of a monitoring unit associated with a corresponding one of the processing paths. Each such monitoring unit can be configured to generate a TEO signal in response to an abnormal operation (e.g., a timing event) of the corresponding processing path. In the case of a register circuit equipped with a monitor, the monitoring unit can be a monitor circuit. In the case of a duplicate path, the monitoring unit can include a duplicate path and a circuit element (e.g., TEM circuit 120) that analyzes its output, and the observation signal can indicate that the output of the duplicate path is not the output that it should be.

[0093] exist Figure 7In the example of , a monitoring method based on a TEM window is combined with a system based on a replica path, wherein the replica path is implemented as a single-bit counter (one-bit counter) circuit. As previously described, the microelectronic circuit 100 may include a TEM circuit 120. However, a replica path based on a one-bit counter may be provided as a register circuit 110. The one-bit counter may include a trigger 112, such as a D flip-flop, receiving a digital value at its data input (D), which may also be provided to the TEM circuit 120. The trigger 112 may also receive a clock signal (CLK). The one-bit counter may also include an inverter 114 to provide an inverted feedback to its data input (D). The feedback path may include a delay chain (delay line), which includes one or more delay elements so that the delay of the delay chain matches the delay of the critical path.

[0094] The one-bit counter can be activated by enabling the clock signal of the one-bit counter. The clock signal can be enabled for two clock cycles, for example, one clock cycle for launch and one clock cycle for capture. Matching the delay of the feedback path of the one-bit counter to the critical path to be monitored solves the problem of unpredictability of activation because the critical path replica and the monitor can be activated at the same time in one clock cycle.

[0095] Alternative Figure 7 Other types of replica paths may also be used. For example, TEM clock generator circuit 130-1 or 130-2 may be used to implement a replica path. In this case, these circuits may be configured to have a configuration similar to Figure 7 The characteristics of a single-bit counter. For example, the delay of these circuits can be matched to the delay of (one or more) critical paths. This provides the following advantages:

[0096] - Because the system is able to directly activate the critical path copy at any time, the probability of activity is 100% (perfect activation). This means that the number of monitors (or monitored paths) required is significantly less than in a system where activation is unpredictable.

[0097] -Because the system can directly activate the critical path replica at any time, monitoring does not need to be enabled all the time. Thus, monitoring can be enabled for, say, two clock cycles while the replica path is activated. This ensures that the energy consumed by monitoring is significantly reduced.

[0098] - A critical path replica based on a single-bit counter does not require settling time. This means no energy is wasted waiting for the circuit to settle. In addition, window-based monitoring can be completed in two clock cycles. This means that measurement delays are minimal, so no additional timing margin is required to compensate for measurement or settling delays.

[0099] - Using a window-based monitoring scheme, the performance (or timing margin) of a replication path based on a single-bit counter can be easily measured.

[0100] Figure 8 An example of a method for operating a microelectronic circuit is shown.

[0101] At 801 , the method may include generating a timing event observation signal in response to detecting a change in a digital value at an input of an associated register circuit during a timing event monitoring window.

[0102] At 802, the method may include adjusting at least a duration of a timed event monitoring window.

[0103] Other features of the method derive directly from the functionality of the microelectronic circuit 100, as described throughout the specification and in the appended claims, and are therefore not repeated here. As described in connection with the various exemplary embodiments, different variants of the method may also be applied.

[0104] An apparatus, such as, for example, microelectronic circuit 100, a component of microelectronic circuit 100, or an apparatus (e.g., a computing device) including microelectronic circuit 100, can be configured to perform or cause to be performed any aspect of the method(s) described herein. In addition, an apparatus can include means for performing any aspect of the method(s) described herein. According to an example embodiment, the means includes the circuits described herein.

[0105] It will be apparent to those skilled in the art that the example embodiments may be implemented in various ways as technology advances. For example, a logical function may be replaced with a structurally different but operationally equivalent function by taking into account possible inversions and required logic conversions. Therefore, the present disclosure is not limited to the above examples, but they may vary within the scope of the claims.

Claims

1. A microelectronic circuit comprising: at least one timing event detector circuit configured to generate a timing event observation signal in response to a change in a digital value at an input of an associated register circuit during a timing event monitoring window; as well as A control input is provided for adjusting at least a duration of the timed event monitoring window.

2. The microelectronic circuit according to claim 1, wherein: The timing event monitoring windows are associated with corresponding edges of the clock signal.

3. The microelectronic circuit according to claim 2 further includes a timing event monitoring window clock generator circuit for generating a timing event monitoring window clock signal, wherein the timing event monitoring window clock signal indicates the duration of the timing event monitoring window and the position of the timing event monitoring window relative to the corresponding edge of the clock signal.

4. The microelectronic circuit according to claim 3, wherein: The timing event monitoring window clock generator circuit is configured to provide the timing event monitoring window clock signal to a single timing event detector circuit, a subset of the timing event detector circuits of the microelectronic circuit, or all of the timing event detector circuits of the microelectronic circuit.

5. The microelectronic circuit according to claim 3 or 4, wherein: The timed event monitoring window clock generator circuit includes a tapped delay line for delaying the clock signal.

6. A microelectronic circuit according to any one of claims 3 to 5, wherein: The timed event monitoring window clock generator circuit is configured as follows: delaying the clock signal to obtain a delayed clock signal; and The timed event monitoring window clock signal is generated based on a combination of the clock signal and the delayed clock signal.

7. The microelectronic circuit according to claim 6, wherein: The microelectronic circuit is configured to adjust a delay of the delayed clock signal based on the control input to adjust a duration of the timing event monitoring window.

8. The microelectronic circuit according to claim 5 and any one of claims 6 to 7, wherein: The duration of the timed event monitoring window is configured to be adjusted by selecting one of the plurality of outputs of the tapped delay line that corresponds to a desired delay.

9. A microelectronic circuit according to any one of claims 5 to 8, wherein: The combination of the clock signal and the delayed clock signal comprises a NOR operation.

10. The microelectronic circuit according to any one of claims 3 to 5, wherein: The timing event monitoring window clock generator circuit is configured to delay the clock signal to obtain a delayed clock signal, wherein the delayed clock signal indicates a duration of the timing event monitoring window and a position of the timing event monitoring window relative to a corresponding edge of the clock signal.

11. The microelectronic circuit according to claim 10, wherein: The microelectronic circuit is configured to adjust a duty cycle of the delayed clock signal to adjust a duration of the timed event monitoring window.

12. A microelectronic circuit according to claim 10 or 11, wherein: The microelectronic circuit is configured to adjust a delay of the delayed clock signal to adjust a position of the timing event monitoring window relative to a corresponding edge of the clock signal.

13. The microelectronic circuit according to claim 5 and any one of claims 8 to 12, wherein: The timing event monitoring window clock generator circuit includes a time-to-digital converter configured to convert a plurality of outputs of the tapped delay line into digital values ​​in response to enabling calibration of the timing event monitoring window clock generator circuit, wherein the timing event monitoring window clock generator circuit is further configured to: determining a current clock cycle length of the clock signal based on the digital value; as well as One of the plurality of outputs of the tapped delay line is reselected based on the current clock cycle length to substantially maintain the desired delay relative to the current clock cycle length of the clock signal.

14. The microelectronic circuit according to claim 13, wherein: The time-to-digital converter includes a capture register configured to capture multiple outputs of the tapped delay line, and wherein the timing event monitoring window clock generator circuit is configured to determine a current clock cycle length of the clock signal based on the captured multiple outputs of the tapped delay line.

15. A microelectronic circuit according to any one of claims 2 to 14, wherein: At least a portion of the timing event monitoring window precedes a corresponding edge of the clock signal.

16. The microelectronic circuit according to claim 15, wherein: The timed event monitoring window precedes a corresponding edge of the clock signal, and wherein the timed event monitoring window ends at the corresponding edge of the clock signal.

17. The microelectronic circuit according to claim 16, wherein: The second timing event monitoring window is located after a corresponding edge of the clock signal.

18. The microelectronic circuit of claim 15, wherein: A portion of the timing event monitoring window is located after a corresponding edge of the clock signal.

19. The microelectronic circuit according to any one of claims 1 to 18, further comprising: a plurality of processing paths, the plurality of processing paths comprising logic units and register circuits, wherein the register circuits are configured to temporarily store output values ​​of the logic units in synchronization with the clock signal; A replica path emulates the operation of a critical path of the plurality of processing paths, wherein the replica path includes a one-bit counter having feedback via a delay line matched to the critical path, and wherein an associated register circuit includes the one-bit counter.

20. A method for operating a microelectronic circuit, the method comprising: generating a timing event observation signal in response to detecting a change in a digital value at an input of an associated register circuit during a timing event monitoring window; as well as At least one duration of the timed event monitoring window is adjusted.

21. The method according to claim 20, wherein: The timing event monitoring windows are associated with corresponding edges of the clock signal.

22. The method according to claim 21, further comprising: A timed event monitoring window clock signal is generated, the timed event monitoring window clock signal indicating a duration of the timed event monitoring window and a position of the timed event monitoring window relative to a corresponding edge of the clock signal.

23. The method circuit of claim 22, further comprising: The timing event monitoring window clock signal is provided to a single timing event detector circuit, a subset of the timing event detector circuits of the microelectronic circuit, or all of the timing event detector circuits of the microelectronic circuit.

24. A method circuit according to claim 22 or claim 24, wherein: The timing event monitoring window is generated based on a tapped delay line configured to delay the clock signal.

25. The method according to any one of claims 22 to 24, further comprising: Delaying the clock signal to obtain a delayed clock signal; as well as The timed event monitoring window clock signal is generated based on a combination of the clock signal and the delayed clock signal.

26. The method according to claim 25, further comprising: A delay of the delayed clock signal is adjusted based on a control input to adjust a duration of the timed event monitoring window.

27. The method according to any one of claims 24 and 25 to 26, wherein: The duration of the timed event monitoring window is adjusted by selecting one of the plurality of outputs of the tapped delay line that corresponds to a desired delay.

28. The method according to any one of claims 24 to 27, wherein: The combination of the clock signal and the delayed clock signal comprises a NOR operation.

29. The method according to any one of claims 22 to 24, further comprising: The clock signal is delayed to obtain a delayed clock signal, wherein the delayed clock signal indicates a duration of the timed event monitoring window and a position of the timed event monitoring window relative to a corresponding edge of the clock signal.

30. The method of claim 29, further comprising: The duty cycle of the delayed clock signal is adjusted to adjust the duration of the timing event monitoring window.

31. The method of claim 29 or claim 30, further comprising: The delay of the delayed clock signal is adjusted to adjust the position of the timing event monitoring window relative to the corresponding edge of the clock signal.

32. The method according to any one of claims 24 and 27 to 31, wherein: The timing event monitoring window clock signal is generated based on a time-to-digital converter configured to convert a plurality of outputs of the tapped delay line into digital values ​​in response to enabling calibration of the timing event monitoring window clock generator circuit, the method further comprising: determining a current clock cycle length of the clock signal based on the digital value; and One of the plurality of outputs of the tapped delay line is reselected based on the current clock cycle length to substantially maintain the desired delay relative to the current clock cycle length of the clock signal.

33. The method of claim 32, wherein: The time-to-digital converter comprises a capture register configured to capture a plurality of outputs of the tapped delay line, the method further comprising: A current clock cycle length of the clock signal is determined based on the captured plurality of outputs of the tapped delay line.

34. The method according to any one of claims 21 to 33, wherein: At least a portion of the timing event monitoring window precedes a corresponding edge of the clock signal.

35. The method of claim 34, wherein: The timed event monitoring window precedes a corresponding edge of the clock signal, and wherein the timed event monitoring window ends at the corresponding edge of the clock signal.

36. The method of claim 35, wherein: The second timing event monitoring window is located after a corresponding edge of the clock signal.

37. The method of claim 34, wherein: A portion of the timing event monitoring window is located after a corresponding edge of the clock signal.

38. The method according to any one of claims 21 to 37, wherein: The microelectronic circuit comprises a plurality of processing paths, the processing paths comprising logic units and register circuits, wherein the register circuits are configured to temporarily store output values ​​of the logic units in synchronization with the clock signal, the method further comprising: Operation of a critical path of the plurality of processing paths is emulated by a replica path, wherein the replica path includes a one-bit counter with feedback via a delay line matched to the critical path, and wherein an associated register circuit includes the one-bit counter.

Images