Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor

Abstract

Provided are a multilayer ceramic capacitor having a high dielectric constant and high capacitance while suppressing a decrease in reliability due to oxygen vacancies, and a method for manufacturing the multilayer ceramic capacitor. A multilayer ceramic capacitor (10) according to the present invention is provided with: a multilayer body (12) having a plurality of internal electrode layers (16) including a first internal electrode layer (16a) and a second internal electrode layer (16b) arranged so as to face each other and to be separated from each other, and dielectric layers (14) including a ceramic material disposed between the internal electrode layers (16); and an external electrode (30) selectively connected to the plurality of internal electrode layers (16). The electrode layer of each of the plurality of internal electrode layers (16) contains a rare earth oxide, and the rare earth oxide in each of the plurality of internal electrode layers (16) is distributed along at least one of a pair of interfaces (Iu and Il) with the dielectric layer (14).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor and a method for manufacturing the laminated ceramic capacitor. Background Art

[0002] With the development of electronic technology in recent years, multilayer ceramic capacitors are required to be small and have high capacitance. In order to meet the demand for high capacitance, barium titanate (BaTiO) with high dielectric constant and high capacitance is generally used as the dielectric material of multilayer ceramic capacitors. 3 ) as the main ingredient.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Publication No. 1-26169 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] However, the above-mentioned prior art has the following disadvantages. That is, BaTiO 3 Due to its characteristics, oxygen vacancies are generated during firing in a reducing atmosphere. Oxygen vacancies cause the insulation resistance of the dielectric to decrease, which may reduce the reliability of the multilayer ceramic capacitor under high temperature load.

[0008] The present invention has been made in view of such a problem, and an object of the present invention is to provide a multilayer ceramic capacitor having a high dielectric constant and a high capacitance and a method for manufacturing the multilayer ceramic capacitor by suppressing a decrease in reliability due to oxygen vacancies.

[0009] Technical solutions to solve problems

[0010] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, and including a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; and a plurality of external electrodes, wherein the plurality of internal electrode layers include: a first internal electrode layer alternately stacked with the plurality of dielectric layers and exposed at the first end surface; and a second internal electrode layer alternately stacked with the plurality of dielectric layers and exposed at the second end surface, and the plurality of external electrodes include: a first external electrode connected to the first internal electrode layer; and a second external electrode connected to the second internal electrode layer, the first internal electrode layer and the second internal electrode layer contain a rare earth oxide, and the rare earth oxide in each electrode layer of the first internal electrode layer and the second internal electrode layer is distributed along at least any one of a pair of interfaces with the dielectric layer.

[0011] According to the multilayer ceramic capacitor of the present invention, the first internal electrode layer and the second internal electrode layer contain rare earth oxides, and the rare earth oxides in each of the first internal electrode layer and the second internal electrode layer are distributed along at least one of a pair of interfaces with the dielectric layer, so that the rare earth oxides contained in the interface on the internal electrode layer side absorb oxygen vacancies that move from the dielectric layer to the internal electrode layer. As a result, the accumulation of oxygen vacancies and the electric field concentration caused by them are suppressed in the dielectric layer near the dielectric layer side at the interface, and the reduction in insulation resistance can be suppressed. As a result, the reduction in the reliability of the dielectric layer can be suppressed.

[0012] Effects of the Invention

[0013] According to the present invention, a decrease in reliability due to oxygen vacancies can be suppressed, thereby providing a multilayer ceramic capacitor having a high dielectric constant and a high capacitance, and a method for manufacturing the multilayer ceramic capacitor.

[0014] The above objects, other objects, features and advantages of the present invention will become more apparent from the following description of specific embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention.

[0016] Figure 2 It is a front view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention.

[0017] Figure 3 yes Figure 1 Cross-sectional view at line III-III.

[0018] Figure 4 yes Figure 1 Cross-sectional view at line IV-IV.

[0019] Figure 5 yes Figure 3 Cross-sectional view at line VV of .

[0020] Figure 6 It is shown Figure 2 FIG. 1 is a diagram showing a structure in the vicinity of an internal electrode layer of a two-terminal multilayer ceramic capacitor according to a first embodiment of the present invention in a region R1.

[0021] Figure 7 is shown corresponding to Figure 3 A plan view showing the structure of an internal electrode layer of a two-terminal multilayer ceramic capacitor according to a first embodiment of the present invention.

[0022] Figure 8 It is shown Figure 7 FIG. 1 is a diagram showing a structure in the vicinity of an internal electrode layer of a two-terminal multilayer ceramic capacitor according to a first embodiment of the present invention in a region R2.

[0023] Fig. 9 It is shown Figure 2 FIG. 2 is a diagram showing a structure near an internal electrode layer in another example of the two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention in region R1.

[0024] Fig.10 It is shown Figure 7 FIG. 2 is a diagram showing a structure near an internal electrode layer in another example of the two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention in region R2.

[0025] Fig.11 It is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention.

[0026] Fig.12 It is a plan view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention.

[0027] Fig.13 It is a front view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention.

[0028] Fig.14 yes Fig.11 Cross-sectional view at line XIV-XIV of .

[0029] Fig.15 yes Fig.11 A cross-sectional view taken along line XV-XV of FIG.

[0030] Fig.16 yes Fig.14 Cross-sectional view at line XVI-XVI of .

[0031] Fig.17 yes Fig.14 Cross-sectional view at line XVII-XVII of . DETAILED DESCRIPTION

[0032] A. First Embodiment

[0033] 1. Two-terminal multilayer ceramic capacitors

[0034] As a multilayer ceramic capacitor according to a first embodiment of the present invention, a two-terminal multilayer ceramic capacitor 10 will be described.

[0035] Figure 1 It is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 2 It is a front view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 3 yes Figure 1 Cross-sectional view at line III-III. Figure 4 yes Figure 1 Cross-sectional view at line IV-IV. Figure 5 yes Figure 3 Cross-sectional view at line VV of .

[0036] like Figures 1 to 4 As shown, the multilayer ceramic capacitor 10 includes a multilayer body 12 and external electrodes 30 disposed on the surface of the multilayer body 12 .

[0037] like Figures 1 to 4 As shown, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped multilayer body 12 and external electrodes 30 disposed at both ends of the multilayer body 12 .

[0038] The laminate 12 has a plurality of laminated dielectric layers 14 and a plurality of internal electrode layers 16 laminated on the ceramic layer 14. Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b opposite to each other in the height direction x, a first side surface 12c and a second side surface 12d opposite to each other in the width direction y orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f opposite to each other in the length direction z orthogonal to the height direction x and the width direction y. In the laminate 12, the corners and the ridges are rounded. In addition, the so-called corners refer to the portions where three adjacent faces of the laminate intersect, and the so-called ridges refer to the portions where two adjacent faces of the laminate intersect. In addition, the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f may be partially or entirely formed with projections and depressions. The dielectric layer 14 and the internal electrode layer 16 are stacked in the height direction x.

[0039] The laminate 12 has an inner layer portion 18 composed of a single or multiple ceramic layers 14 and multiple internal electrode layers 16 arranged thereon. The internal electrode layer 16 has a first internal electrode layer 16a extending to a first end face 12e and a second internal electrode layer 16b extending to a second end face 12f. In the inner layer portion 18, multiple first internal electrode layers 16a and second internal electrode layers 16b are opposed to each other with the ceramic layer 14 interposed therebetween.

[0040] The stacked body 12 has a first main surface side outer layer portion 20a, which is located on the first main surface 12a side and is formed by a plurality of ceramic layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and a straight line on the outermost surface.

[0041] Similarly, the stack 12 has a second main surface side outer layer portion 20b, which is located on the second main surface 12b side and is formed by a plurality of ceramic layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and a straight line on the outermost surface.

[0042] The laminate 12 has a first side surface side outer layer portion 22a located on the first side surface 12c side and formed of a plurality of ceramic layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side.

[0043] Similarly, the laminate 12 has a second side outer layer portion 22b located on the second side 12d side and formed of a plurality of ceramic layers 14 located between the second side 12d and the outermost surface of the inner layer portion 18 on the second side 12d side.

[0044] The laminate 12 has a first end surface side outer layer portion 24a located on the first end surface 12e side and formed of a plurality of ceramic layers 14 located between the first end surface 12e and the outermost surface of the inner layer portion 18 on the first end surface 12e side.

[0045] Similarly, the laminate 12 has a second end surface side outer layer portion 24b located on the second end surface 12f side and formed of a plurality of ceramic layers 14 located between the second end surface 12f and the outermost surface of the inner layer portion 18 on the second end surface 12f side.

[0046] The first principal surface side outer layer portion 20 a is located on the first principal surface 12 a side of the laminate 12 and is an assembly of a plurality of ceramic layers 14 located between the first principal surface 12 a and the internal electrode layer 16 closest to the first principal surface 12 a .

[0047] The second principal surface side outer layer portion 20 b is located on the second principal surface 12 b side of the laminate 12 and is an assembly of a plurality of ceramic layers 14 located between the second principal surface 12 b and the internal electrode layer 16 closest to the second principal surface 12 b .

[0048] For example, the dielectric layer 14 can be formed of a dielectric material as a ceramic material. As such a dielectric material, for example, BaTiO 3 、CaTiO 3 、SrTiO 3 or CaZrO 3 In the case of containing the above dielectric material as a main component, depending on the desired properties of the laminate 12, for example, a material to which a secondary component such as a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound is added in an amount less than the main component may be used.

[0049] The size of the laminate 12 is not particularly limited.

[0050] The dielectric layer 14 is made of barium titanate (BaTiO 3 ) as a dielectric material as a main component. In this case, the main component is not particularly limited as long as it is a perovskite-type oxide containing barium (Ba) and titanium (Ti). That is, the compound can be BaTiO 3 , or BaTiO 3 A compound in which a part of Ba and / or Ti contained is replaced by other elements.

[0051] Specifically, part of Ba may be replaced by Sr and / or Ca, or may not be replaced. In addition, part of Ti may be replaced by Zr and / or Hf, or may not be replaced. 3The ratio of the A-site element (Ba, Sr, Ca, etc.) to the B-site element (Ti, Zr, Hf, etc.) of the perovskite compound is not strictly limited to 1:1. As long as the perovskite crystal structure is maintained, the ratio of the A-site element to the B-site element can be allowed to vary.

[0052] When the dielectric material described above is included as a main component, a material to which a secondary component such as a Mn compound, Fe compound, Cr compound, Co compound, or Ni compound is added in an amount smaller than that of the main component may be used, depending on the desired characteristics of the laminate 12 .

[0053] The thinner the dielectric layer 14 is, the larger the capacitance of the capacitor is, so the grain diameter is preferably 1 μm or less. As the thickness of the dielectric layer 14 becomes thinner, the grain size becomes smaller, but if the grain becomes too small, the relative dielectric constant decreases due to the size effect. Therefore, the size of the grain is appropriately designed according to the thickness of the dielectric layer 14.

[0054] The thickness of dielectric layer 14 in laminated body 12 after firing is preferably about 0.4 μm or more and 1.0 μm or less.

[0055] The number of laminated dielectric layers 14 is preferably 4 or more and 1000 or less. However, the number of dielectric layers 14 is the sum of the number of dielectric layers 14 constituting the inner layer portion 18 and the number of dielectric layers constituting the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b.

[0056] The stacked body 12 includes a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b as the plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are buried substantially parallel to the first main surface 12a and the second main surface 12b and are alternately arranged at equal intervals with the dielectric layer 14 sandwiched therebetween along the height direction x of the stacked body 12.

[0057] The first internal electrode layer 16a is arranged on the plurality of dielectric layers 14 and is located inside the stack 12. The first internal electrode layer 16a has a first opposing electrode portion 26a that is opposed to the second internal electrode layer 16b, and a first lead electrode portion 28a that is located on one end side of the first internal electrode layer 16a and extends from the first opposing electrode portion 26a to the first end face 12e of the stack 12. The end of the first lead electrode portion 28a is led out to the surface of the first end face 12e and exposed from the stack 12.

[0058] The shape of the first counter electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or the corners may be inclined (conical) in a plan view. In addition, the shape may be tapered in a plan view with an inclination in any direction.

[0059] The shape of the first lead electrode portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or may be inclined (conical) in a plan view. In addition, the shape may be tapered in a plan view with an inclination in any direction.

[0060] The width of the first counter electrode portion 26a of the first internal electrode layer 16a and the width of the first lead electrode portion 28a of the first internal electrode layer 16a may be formed to be the same width, or one of the widths may be formed to be smaller.

[0061] The second internal electrode layer 16b is arranged on the plurality of dielectric layers 14 and is located inside the stacked body 12. The second internal electrode layer 16b includes a second opposing electrode portion 26b opposed to the first internal electrode layer 16a, and a second lead electrode portion 28b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 26b to the second end face 12f of the stacked body 12. The end of the second lead electrode portion 28b is led out to the surface of the second end face 12f and exposed from the stacked body 12.

[0062] The shape of the second counter electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or the corners may be formed to be inclined (conical) in a plan view. In addition, the shape may be tapered in a plan view with an inclination in any direction.

[0063] The shape of the second lead electrode portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or the corners may be inclined (conical) in a plan view. In addition, the shape may be tapered in a plan view with an inclination in any direction.

[0064] The width of the second counter electrode portion 26b of the second internal electrode layer 16b and the width of the second lead electrode portion 28b of the second internal electrode layer 16b may be formed to be the same width, or one of the widths may be formed to be smaller.

[0065] The first internal electrode layer 16 a and the second internal electrode layer 16 b can be formed of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy.

[0066] The thickness of each of the first internal electrode layer 16 a and the second internal electrode layer 16 b is not particularly limited, but is preferably about 0.4 μm or more and 0.8 μm or less, for example.

[0067] The number of each of the first internal electrode layer 16 a and the second internal electrode layer 16 b is not particularly limited, but the total number is preferably 2 or more and 1000 or less.

[0068] Next, the internal electrode layer 16 is formed of a mixture of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, an alloy containing at least one of these metals such as an Ag-Pd alloy, and a material in which at least one of calcium oxide, magnesium oxide, and yttrium oxide is added to zirconium oxide as a rare earth oxide.

[0069] When the base electrode layer of the external electrode 30 described later includes a conductive resin layer, the metal constituting the internal electrode layer 16 and the metal constituting the conductive filler included in the conductive resin layer form a compound.

[0070] Furthermore, as Figure 3 An enlarged view of the main part of the region R1 Figure 6 As shown, in the first internal electrode layer 16a, an interface layer 29x containing the most rare earth oxide is arranged in the portion of the surface including the interface Iu constituting the interface with the dielectric layer 14 stacked thereon. On the other hand, an electrode main body layer 29z containing no rare earth oxide and formed of the above-mentioned conductive material is arranged in the back portion constituting the interface Il with the dielectric layer 14 stacked below the first internal electrode layer 16a. Furthermore, between the interface layer 29x and the electrode main body layer 29z, an intermediate layer 29y is arranged, and the intermediate layer 29y is a layer in which the content of rare earth oxide decreases as it moves away from the interface layer 29x and approaches the electrode main body layer 29z in the height direction x.

[0071] In addition, Figure 6 In the figure, the intermediate layer 29y is represented by a step-by-step change in the lightness and darkness of the color, but the distribution of the rare earth oxide in the intermediate layer 29y changes continuously.

[0072] Furthermore, if Figure 7 as well as Figure 8As shown, the first internal electrode layer 16a may have a structure in which the outline of the electrode main body layer 29z is exposed from the outline of the interface layer 29x when viewed in the height direction x. Specifically, at the front edge end Ef of the first opposing electrode portion 26a that is opposite to the second end face 12f of the stack 12, the interface layer 29x may be retreated from the electrode main body layer 29z to the first end face 12e side. In addition, at the first side edge end Es1 of the first opposing electrode portion 26a and the first lead electrode portion 28a that is opposite to the first side face 12c of the stack 12, the interface layer 29x may be retreated from the electrode main body layer 29z to the second side face 12d side. In addition, at the second side edge end Es2 of the first opposing electrode portion 26a and the first lead electrode portion 28a that is opposite to the second side face 12d of the stack 12, the interface layer 29x may be retreated from the electrode main body layer 29z to the first side face 12c side.

[0073] Therefore, the contour portion of the first internal electrode layer 16a surrounded by the front edge Ef, the first side edge Es1 and the second side edge Es2 on the LW plane within the stack 12 is composed only of the electrode main body layer 29z, and the remaining portion located closer to the center of the contour portion is composed of the stacking of the interface layer 29x and the electrode main body layer 29z.

[0074] like Figure 3 as well as Figure 4 As shown, the first internal electrode layer 16a and the second internal electrode layer 16b of the stacked body 12 are formed line-symmetrically with respect to the inner layer portion 18 with respect to the height direction x. Therefore, the above-mentioned structure of the first internal electrode layer 16a and various forms of the shape when viewed in the height direction x are also applicable to the second internal electrode layer 16b inverted in the length direction z. Specifically, the second internal electrode layer 16b is substantially rectangular in shape when viewed in the height direction x, and has a second opposing electrode portion 26b opposed to the first internal electrode layer 16a, and a second lead electrode portion 28b located at one end side of the second internal electrode layer 16b along the length direction z and led from the second opposing electrode portion 26b to the surface of the second end face 12f of the stacked body 12 and exposed from the stacked body 12. The second counter electrode portion 26b of the second internal electrode layer 16b corresponds to the first counter electrode portion 26a of the first internal electrode layer 16a, and the second lead electrode portion 28b of the second internal electrode layer 16b corresponds to the first lead electrode portion 28a of the first internal electrode layer 16a.

[0075] In addition, the first internal electrode layer 16a and the second internal electrode layer 16b may be alternately stacked with the dielectric layer 14 interposed therebetween, or the dielectric layer 14 having the second internal electrode layer 16b may be stacked after a plurality of dielectric layers 14 having the first internal electrode layer 16a are stacked. In this way, the stacking pattern of the first internal electrode layer 16a and the second internal electrode layer 16b can be changed according to the capacitance value to be achieved in the two-terminal multilayer ceramic capacitor 10.

[0076] The multilayer ceramic capacitor 10 having the above structure is characterized in that the first internal electrode layer 16a and the second internal electrode layer 16b of the internal electrode layer 16 contain rare earth oxides distributed along the interface Iu with the dielectric layer 14. In addition, the following description takes the first internal electrode layer 16a as an example based on the referenced figures, but is also applicable to the second internal electrode layer 116b side.

[0077] Furthermore, in the multilayer ceramic capacitor 10 of the present embodiment, as Figure 6 As shown in the middle layer 29y of the first internal electrode layer 16a of the internal electrode layer 16, the rare earth oxide is distributed in a manner that the content thereof decreases as it moves away from the interface layer 29x and approaches the electrode main body layer 29z along the thickness direction of each electrode layer of the internal electrode layer 16. As a result, each electrode layer of the internal electrode layer 16 can absorb oxygen vacancies not only at the interface Iu between the dielectric layer 14 and the internal electrode layer 16 but also inside the internal electrode layer 16. As a result, the inherent conductivity of the internal electrode layer 16 can be ensured, and the reduction in the insulation resistance of the dielectric layer 14 can be suppressed, thereby suppressing the reduction in reliability.

[0078] Next, the content of the rare earth oxide in the internal electrode layer 16 is preferably 0.1 wt % or more and 10 wt % or less when expressed as the following formula:

[0079] {(weight of rare earth oxide) / (weight of rare earth oxide+weight of main component metal of each of the plurality of internal electrode layers)}×100.

[0080] This can reduce the possibility that the electrical conductivity of the internal electrode layer 16 will be impaired, and suppress a decrease in the insulation resistance of the dielectric layer 14 .

[0081] That is, if the content of the rare earth oxide relative to the internal electrode layer 16 becomes less than 0.1% by weight, it may not be possible to fully absorb the oxygen vacancies moved from the dielectric layer 14 of the stacked body 12. On the other hand, if it becomes greater than 10% by weight of the rare earth oxide relative to the internal electrode layer 16, the proportion of the main component metal and other conductive components in the internal electrode layer 16 decreases, thereby increasing the resistance and possibly impairing the inherent conductive performance of the electrode layer.

[0082] In addition, for example, the content of the rare earth oxide with respect to the first internal electrode layer 16a of the internal electrode layer 16 is measured as follows. First, the laminate 12 is ground along the width direction y to a position where the W dimension becomes 1 / 2, so that the LT cross section is exposed, and the LT cross section exposed by grinding is analyzed by energy dispersive X-ray analysis and wavelength dispersive X-ray analysis (EDS, WDX / FE-WDX (for example, using a scanning electron microscope or electron probe microanalyzer manufactured by JEOL Ltd.)), and a calculated value calculated based on the analysis result is obtained. Here, when the internal electrode layer 16 is divided into five equal parts, the content of the rare earth oxide is higher on the interface side.

[0083] Furthermore, if Figure 7 and as Figure 7 An enlarged view of the main part of region R2 Figure 8 As shown in the structure when the first internal electrode layer 16a of the internal electrode layer 16 is observed in the height direction x, the first internal electrode layer 16a of the stacked ceramic capacitor 10 of this embodiment has an outline portion on the LW plane within the stacked body 12 that is composed only of the electrode main body layer 29z, and the remaining portion located at a position closer to the center than the outline portion has a structure composed of a stack of an interface layer 29x and an electrode main body layer 29z.

[0084] Thus, it is possible to suppress the increase in resistance of the internal electrode layer 16, suppress the reduction in insulation performance due to oxygen vacancies, and suppress the reduction in reliability of the dielectric layer 14. That is, in the internal electrode layer 16, the conductive material, such as Ni, which is the main component of the electrode layer, has a lower resistance than the rare earth oxide, and current flows more easily along the side of the contour portion than the side near the center of the LW plane of the internal electrode layer 16. The multilayer ceramic capacitor 10 of the present embodiment utilizes these circumstances, and by exposing the contour portion where current flows easily in the internal electrode layer 16, and providing the interface layer 29x in the center portion where current flows less easily, the influence of the increase in resistance caused by the addition of the interface layer 29x in the internal electrode layer 16 is suppressed.

[0085] In particular, in the first internal electrode layer 16a, the dimension of the contour portion of the electrode main body layer 29z exposed as a single body on the LW plane in the laminate 12 is preferably 2% or less of the overall dimension LE of the first internal electrode layer 16a in the length direction z, which is the extension direction of the first internal electrode layer 16a. Similarly, the dimension WH of the contour portion of the electrode main body layer 29z exposed as a single body in the width direction y, which is a direction orthogonal to the extension direction of the first internal electrode layer 16a, is preferably 2% or less of the overall dimension WE of the first internal electrode layer 16a in the width direction y.

[0086] Thus, it is possible to maintain a balance between suppressing the increase in resistance of the internal electrode layer 16 and suppressing the reduction in insulation performance due to oxygen vacancies, thereby suppressing the reduction in reliability of the dielectric layer 14. That is, if the size of the contour portion of the electrode main body layer 29z not containing the rare earth oxide exposed as a single body becomes larger than 2% of the size of the entire first internal electrode layer 16a, the proportion of the rare earth oxide in the internal electrode layer 16 decreases, and thus the oxygen vacancies of the dielectric layer 14 cannot be fully absorbed, and the reduction in insulation performance cannot be fully suppressed.

[0087] In the above description, the first internal electrode layer 16a is configured such that the entire contour portion surrounded by the front edge Ef, the first side edge Es1, and the second side edge Es2 on the LW plane in the stack 12 is composed only of the electrode main body layer 29z, but it may also be configured such that only one of the first side edge Es1 and the second side edge Es2 or the front edge Ef is composed only of the electrode main body layer 29z. In particular, it is preferred that only the electrode main body layer 29z is configured to have any larger size of the size of the first side edge Es1 and the second side edge Es2 along the length direction z or the size of the front edge Ef along the width direction y. Thus, the increase in the resistance of the internal electrode layer 16 can be suppressed and the reduction in the insulation performance caused by oxygen vacancies can be suppressed, and the reduction in the reliability of the dielectric layer 14 can be more effectively suppressed.

[0088] For example, the interface layer 29x in the first internal electrode layer 16a of the internal electrode layer 16 is measured as follows. First, the stacked body 12 is ground along the height direction x to a position where the T dimension becomes 1 / 2 so that the LW cross section is exposed, and the LW cross section exposed by grinding is photographed using a microscope (for example, VHX series manufactured by Keyence Corporation). Based on the photographed image, the dimensions of the interface layer 29x and the first internal electrode layer 16a in the length direction z and the width direction y, that is, the L dimension and the W dimension, are calculated. In addition, based on the dimensions, it is calculated whether the dimensions of the contour portion of the electrode main body layer 29z exposed as a single body are less than 2% of the overall dimensions of the first internal electrode layer 16a in terms of the length direction z and the width direction y, respectively.

[0089] Here, the term "no rare earth oxide" means that when the content of rare earth oxide is calculated as follows, the content of rare earth oxide is less than 0.1% by weight, and is considered as no rare earth oxide:

[0090] [(weight of rare earth oxide) / weight of rare earth oxide+weight of main component metal of each of the plurality of internal electrode layers]×100.

[0091] In addition, in the above description, Figure 6As shown in the first internal electrode layer 16a, the internal electrode layer 16 is formed as an interface layer 29x including a portion of the surface constituting the interface Iu with the dielectric layer 14 stacked above the first internal electrode layer 16a. Fig. 9 As shown in FIG. 1 , the first internal electrode layer 16a may also be configured to include the surface and back portions that respectively constitute the interface Iu and the interface Il with the pair of dielectric layers 14 stacked above and below it, forming a pair of interface layers 29x. In this case, the portion sandwiched by the pair of interface layers 29x and located in the center of the first internal electrode layer 16a along the height direction x forms the electrode main body layer 29z. Furthermore, a pair of intermediate layers 29y are formed between each of the pair of interface layers 29x and the electrode main body layer 29z, and the content of the rare earth oxide layer decreases as the distance from the interface layer 29x and the proximity to the electrode main body layer 29z are reached.

[0092] Thus, in the laminate 12, the insulation performance of each dielectric layer 14 sandwiched between the first internal electrode layer 16a and the second internal electrode layer 16b is improved from both the front and back sides thereof, and a decrease in the reliability of the dielectric layer 14 can be more effectively suppressed.

[0093] Furthermore, it can also be combined with Figure 6 In contrast to the illustrated example, the interface layer 29x is formed to include a portion of the surface constituting the interface 11 with the dielectric layer 14 stacked below the first internal electrode layer 16a.

[0094] In addition, in the above description, Figure 7 as well as Figure 8 As shown in FIG. 1 , the first internal electrode layer 16a is configured such that, on the LW plane in the stacked body 12, the contour portion is composed only of the electrode main body layer 29z, and the remaining portion located at the center of the contour portion is composed of the stack of the interface layer 29x and the electrode main body layer 29z. Fig.10 As shown, the first internal electrode layer 16a may also be configured to have an intermediate layer 29y sandwiched between the interface layer 29x and the electrode main body layer 29z. In this case, the intermediate layer 29y is a layer whose rare earth oxide content decreases as it moves away from the interface layer 29x and approaches the electrode main body layer 29z along the length direction z and the width direction y, respectively.

[0095] Thus, each electrode layer of the internal electrode layer 16 can absorb oxygen vacancies not only at the boundary between the dielectric layer 14 and the internal electrode layer 16, but also inside the internal electrode layer 16. As a result, the inherent conductivity of the internal electrode layer 16 can be ensured, and the reduction in insulation resistance of the dielectric layer 14 can be suppressed, thereby suppressing the reduction in reliability. Fig.10In the figure, the intermediate layer 29y is represented by a step-by-step change in the lightness and darkness of the color, but the distribution of the rare earth oxide layer in the intermediate layer 29y changes continuously.

[0096] Thus, the multilayer ceramic capacitor 10 according to the first embodiment of the present invention can suppress a reduction in reliability due to oxygen vacancies by including rare earth oxides distributed along the interfaces with the dielectric layer 14 in the first internal electrode layers 16 a and the second internal electrode layers 16 b of the internal electrode layers 16 .

[0097] Then, if Figures 1 to 4 As shown, external electrodes 30 are provided on the first side surface 12 c and the second side surface 12 d and the first end surface 12 e and the second end surface 12 f of the stacked body 12 .

[0098] The external electrode 30 includes a first external electrode 30 a and a second external electrode 30 b .

[0099] The first external electrode 30a is electrically connected to the first internal electrode layer 16a and is arranged on the surface of the first end face 12e. In addition, the first external electrode 30a extends from the first end face 12e of the stacked body 12 along the contour of the stacked body 12 and is also arranged on a portion of the first main face 12a and a portion of the second main face 12b, and a portion of the first side face 12c and a portion of the second side face 12d. In addition, the first external electrode 30a is formed at least on the surface of the first end face 12e, and is preferably also arranged on a portion of the first main face 12a and a portion of the second main face 12b. The first external electrode 30a is further preferably arranged by being more or less led around a portion of the first side face 12c and a portion of the second side face 12d.

[0100] The second external electrode 30b is electrically connected to the second internal electrode layer 16b and is arranged on the surface of the second end face 12f. In addition, the second external electrode 30b extends from the second end face 12f of the stacked body 12 along the contour of the stacked body 12 and is also arranged on a portion of the first main face 12a and a portion of the second main face 12b, and a portion of the first side face 12c and a portion of the second side face 12d. In addition, the second external electrode 30b is formed at least on the surface of the second end face 12f, and is preferably also arranged on a portion of the first main face 12a and a portion of the second main face 12b. The second external electrode 30b is further preferably arranged by being more or less led around a portion of the first side face 12c and a portion of the second side face 12d.

[0101] As an example of its internal structure, the external electrode 30 preferably includes a base electrode layer 32 including a metal component and a ceramic component and a plating layer 34 . The base electrode layer 32 includes a metal component and a ceramic component, and the plating layer 34 is disposed on the surface of the base electrode layer 32 .

[0102] The foundation electrode layer includes a first foundation electrode layer 32 a in the first external electrode 30 a and a second foundation electrode layer 32 b in the second external electrode 30 b .

[0103] The base electrode layer 32 preferably includes at least one layer selected from a sintered layer, a conductive resin layer, and a thin film layer. The sintered layer as the base electrode layer will be described below.

[0104] The sintered layer is obtained by applying a conductive paste containing a glass component and a metal to the laminate 12 and sintering it. The glass component of the sintered layer includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal of the sintered layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.

[0105] The sintered layer can also be obtained by simultaneously firing a stacked chip having an internal electrode layer 16 and a dielectric layer 14, which is the basis of the stacked body 12, and a conductive paste applied to the stacked chip. In addition, the sintered layer can also be obtained by applying a conductive paste to the stacked body 12 and sintering the stacked body 12 after the stacked chip is fired to obtain the stacked body 12. In addition, when the stacked chip and the conductive paste applied to the stacked chip are fired simultaneously, the sintered layer preferably uses a material to which a dielectric material is added instead of a glass component. In addition, the sintered layer can be a single layer or a multilayer.

[0106] When the first base electrode layer 32a and the second base electrode layer 32b are formed as sintered layers, the thickness thereof is preferably, for example, not less than 5 μm and not more than 30 μm. However, the thickness of the sintered layer refers to the L dimension of the central portion in the height direction x in the case of the first end face 12e or the second end face 12f, the T dimension of the central portion in the length direction z in the case of the first main face 12a or the second main face 12b, and the W dimension of the central portion in the length direction z in the case of the first side face 12c or the second side face 12d.

[0107] Next, the conductive resin layer as the base electrode layer 32 is described. When the conductive resin layer is used as the base electrode layer 32, the conductive resin layer may be directly disposed on the laminate 12, or may be disposed to further cover a sintered layer or other material layer that has been provided as a part of the base electrode layer 32.

[0108] In this case, the conductive resin layer may completely cover the sintered layer or other material layer, or may cover a portion thereof. Specifically, the first base electrode layer 32a and the second base electrode layer 32b as the conductive resin layer are preferably arranged so as to extend from the portion of the base electrode layer 32 located on the first end face 12e and the second end face 12f to the portion located on the first main face 12a and the second main face 12b, and the first side face 12c and the second side face 12d. On the other hand, the first base electrode layer 32a and the second base electrode layer 32b as the conductive resin layer may be arranged only on the portion located on the first end face 10e and the second end face 10f.

[0109] Furthermore, the thickness of the conductive resin layer is preferably about 5 μm or more and 30 μm or less, for example. The definition of the thickness of the conductive resin layer is the same as that of the above-mentioned sintered layer.

[0110] For example, the material of the conductive resin layer includes a metal component such as conductive particles and a thermosetting resin. Since the conductive resin layer includes a thermosetting resin, it is more flexible than a conductive layer including, for example, a plated film or a sintered product of a conductive paste. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the multilayer ceramic capacitor 10, the conductive resin layer functions as a buffer layer and can suppress the generation of cracks in the multilayer ceramic capacitor 10.

[0111] Next, as the resin suitable for the conductive resin layer, for example, various known thermosetting resins such as epoxy resin, phenolic resin, polyurethane resin, silicone resin, polyimide resin, etc. can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0112] Furthermore, the conductive resin layer preferably contains a curing agent together with the thermosetting resin. When using a thermosetting resin based on epoxy resin as the curing agent, various known compounds such as phenol, amine, acid anhydride, imidazole, active ester, and amide-imide can be used.

[0113] Furthermore, the resin contained in the conductive resin layer is preferably contained in an amount of 25% by volume or more and 65% by volume or less relative to the volume of the entire conductive resin.

[0114] On the other hand, the metal as the conductive particles contained in the conductive resin layer mainly bears the electrical conductivity of the conductive resin layer. Specifically, the conductive fillers are in contact with each other, thereby forming a conduction path inside the conductive resin layer.

[0115] The metal contained in the conductive resin layer is preferably contained in a ratio of 35 volume % or more and 75 volume % or less with respect to the volume of the entire conductive resin.

[0116] As the metal serving as the conductive particles contained in the conductive resin layer, Ag, Cu, or an alloy containing all or part of these can be used.

[0117] Furthermore, as conductive particles, particles in which the surface of metal particles is coated with Ag can also be used. In this case, as metals, Cu and Ni are preferably used. The reason for using particles coated with Ag on metal as conductive particles is that Ag has the lowest resistivity among metals and is therefore suitable for electrode materials, and because it is a noble metal, it is not oxidized and has high weather resistance. In addition, it is because the above-mentioned characteristics of Ag can be maintained and the metal of the base material can be made cheaper.

[0118] Furthermore, as the metal contained in the conductive resin layer, a material obtained by subjecting Cu to an anti-oxidation treatment can also be used.

[0119] Next, the outer shape of the metal contained in the conductive resin layer is not particularly limited, but a spherical, flat, or other metal can be used. In particular, in this case, it is preferred to use a mixture of spherical metal powder and flat metal powder. The shape of the conductive filler may also be spherical, flat, or the like. Furthermore, the average particle size of the metal contained in the conductive resin layer is not particularly limited. For example, the average particle size of the conductive filler may also be 0.3 μm or more and 10 μm or less. Furthermore, the conductive resin layer may be formed by a single layer or a plurality of layers.

[0120] Next, the thin film layer as the base electrode layer will be described. When the base electrode layer is provided by the thin film layer, the thin film layer is formed as a layer having an average thickness of 1 μm or less by deposition of metal particles.

[0121] Next, the plating layer is described. The plating layer includes the first plating layer 34a in the first external electrode 30a and the second plating layer 34b in the second external electrode 30b. Figures 2 to 4As shown in FIG. 1 , the plating layer 34 is formed to cover the entire surface so that the base electrode layer 32 is not exposed to the outside. Specifically, the first plating layer 34a and the second plating layer 34b are preferably provided from the portions of the first base electrode layer 32a and the second base electrode layer 32b located on the first end surface 12e and the second end surface 12f to further reach the portions located on the first main surface 12a and the second main surface 12b, and the first side surface 12c and the second side surface 12d. On the other hand, the first plating layer 34a and the second plating layer 34b may be provided only on the portions of the first base electrode layer 32a and the second base electrode layer 32b located on the first end surface 12e and the second end surface 12f.

[0122] For example, the plating layer 34 may include at least one metal selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0123] The plating layer 34 may be formed of a single layer or a plurality of layers. In the case of forming a plurality of layers, for example, a two-layer structure of Ni plating and Sn plating is preferred. By setting the layer directly in contact with the base electrode layer as a plating layer including Ni plating, it is possible to prevent the base electrode layer from being corroded by the solder used for mounting when mounting ceramic electronic components, especially when the base electrode layer is a conductive resin layer.

[0124] Furthermore, by providing a plated layer composed of Sn plating as an upper layer of a plated layer composed of Ni plating, when the multilayer ceramic capacitor 10 is mounted on a mounting substrate, wettability of solder used for mounting can be improved, thereby facilitating mounting.

[0125] The thickness of each of the plating layers 34 is preferably 4 μm or more and 10 μm or less.

[0126] The external electrode 30 may be formed only of a plating layer without providing the base electrode layer 32. In this case, by disposing a catalyst on the surface of the laminate 12 as a pretreatment, the external electrode 30 can be formed of a plating layer alone.

[0127] When the external electrode 30 is formed by a single plating layer, it is also preferable to include a lower layer formed on the surface of the laminate 12 and an upper layer formed on the surface of the lower layer, as in the case where the base electrode layer 32 is provided. On the other hand, the upper layer can be formed as needed, and the external electrode 30 can also be composed only of the plating of the lower layer. The upper layer and the lower layer are similar to the above-mentioned cases, for example, preferably including at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi or Zn, or an alloy containing the metal. The lower layer is preferably formed using Ni, and the upper layer is preferably formed using Sn or Au. The reasons why various metals are suitable are the same as in the above-mentioned cases.

[0128] Furthermore, for example, when the first internal electrode layer 16 a and the second internal electrode layer 16 b are formed using Ni, the lower plated electrode is preferably formed using Cu having good bonding properties with Ni.

[0129] The plating layer arranged without providing the base electrode layer 32 has the upper layer as the outermost layer, but another plating electrode may be formed on the surface of the upper layer.

[0130] The thickness of each plating layer disposed without providing the base electrode layer 32 is preferably 4 μm or more and 10 μm or less. In addition, the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99 volume % or more.

[0131] The dimension of the length direction z of the multilayer ceramic capacitor 10 including the multilayer body 12, the first external electrode 30a and the second external electrode 30b is set to L dimension, the dimension of the height direction x of the multilayer ceramic capacitor 10 including the multilayer body 12, the first external electrode 30a and the second external electrode 30b is set to T dimension, and the dimension of the width direction y of the multilayer ceramic capacitor 10A including the multilayer body 12, the first external electrode 30a and the second external electrode 30b is set to W dimension.

[0132] The dimensions of the multilayer ceramic capacitor 10 are as follows: L dimension in the length direction z is 0.4 mm to 1.6 mm, W dimension in the width direction y is 0.2 mm to 1.0 mm, and T dimension in the height direction x is 0.2 mm to 1.0 mm. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0133] Figure 1 The two-terminal type laminated ceramic capacitor 10 shown is Figure 6 As shown, the first internal electrode layer 16a of the internal electrode layer 16 contains a rare earth oxide in the interface layer 29x including the surface constituting the interface Iu with the dielectric layer 14 stacked thereon, so that the rare earth oxide contained in the interface layer 29x absorbs oxygen vacancies that move from the dielectric layer 14 to the internal electrode layer 16. As a result, the accumulation of oxygen vacancies and the electric field concentration caused by them are suppressed in the dielectric layer near the dielectric layer 14 side at the interface Iu, and the reduction of insulation resistance can be suppressed. As a result, the reduction of the reliability of the dielectric layer 14 can be suppressed. On the other hand, in the interface layer 29x near the first internal electrode layer 16a relative to the interface Iu, the rare earth oxide absorbs oxygen vacancies and is reduced to a rare earth element, so that conductivity can be ensured.

[0134] So, in Figure 1In the illustrated multilayer ceramic capacitor 10, the structure on the internal electrode layer 16 side suppresses the reduction in insulation resistance in the dielectric layer 14. Therefore, the dielectric layer 14 can be made of a material having the same composition as a conventional dielectric material, and the reliability of the dielectric layer 14 can be suppressed from being reduced with a low-cost structure.

[0135] 2. Method for manufacturing two-terminal multilayer ceramic capacitor

[0136] Next, a method for manufacturing a two-terminal multilayer ceramic capacitor will be described.

[0137] (Prepare)

[0138] First, a dielectric sheet for the dielectric layer 14 and a conductive paste for the internal electrode layer are prepared. In addition, a dielectric sheet on which the first internal electrode layer 16a is arranged, a dielectric sheet on which the second internal electrode layer 16b is arranged, and a dielectric sheet on which no internal electrode layer is arranged are prepared. The dielectric sheet and the conductive paste for the internal electrode each contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0139] Here, two kinds of conductive pastes are used to obtain the first internal electrode layer 16a and the second internal electrode layer 16b in the completed multilayer ceramic capacitor 10. Specifically, a conductive paste (hereinafter referred to as a first conductive paste) containing a conductive material such as a metal material as in the conventional example and a Dy conductive paste mixed with the first conductive paste are used. 2 O 3 , Y 2 O 3 ,La 2 O 3 、Nd 2 O 3 、CeO 2 A conductive paste (hereinafter referred to as a second conductive paste) obtained by mixing and stirring rare earth oxides such as .

[0140] (Production of laminated sheets)

[0141] Next, for example, a conductive paste for the internal electrode layer is printed on the dielectric sheet in a predetermined pattern corresponding to each shape of the internal electrode layer 16 by a printing method such as screen printing or gravure printing. Thus, the conductive paste is applied to the portion of the dielectric sheet where the first internal electrode layer 16a is to be arranged (hereinafter, such a dielectric sheet is referred to as a first coated dielectric sheet). Furthermore, the conductive paste is applied to the portion of the dielectric sheet where the second internal electrode layer 16b is to be arranged (hereinafter, such a dielectric sheet is referred to as a second coated dielectric sheet).

[0142] Specifically, taking screen printing as an example, a screen plate for printing the first internal electrode layer 16a and a screen plate for printing the second internal electrode layer 16b are prepared respectively, and a printer capable of printing these two screen plates on different dielectric sheets respectively can be used to print given patterns corresponding to each internal electrode layer 16.

[0143] In this process, a process is performed for obtaining the internal structure of each of the first internal electrode layer 16a and the second internal electrode layer 16b in the completed multilayer ceramic capacitor 10. Specifically, a two-step coating process is performed, namely, a first process of coating the first conductive paste on the surface of the dielectric sheet, and a second process of coating the second conductive paste on the surface coated with the first conductive paste after the first process of using the first conductive paste.

[0144] Alternatively, a coating process may be performed that includes three stages: a first process of using a first conductive paste, a second process of using a second conductive paste after the first process of using the first conductive paste, and a first process of applying the first conductive paste again on the coating surface of the second conductive paste after the second process of using the second conductive paste.

[0145] The first step using the first conductive paste is performed so as to have a shape suitable for the shape (planar shape) of each of the first internal electrode layer 16 a and the second internal electrode layer 16 b when viewed in the height direction x after completion.

[0146] Next, the coating shape obtained by the second step using the second conductive paste is preferably set to be smaller in the length direction z and the width direction y by 2% of the planar shape obtained by the first step using the first conductive paste. Thus, for each of the first internal electrode layer 16a and the second internal electrode layer 16b after completion, an electrode main body layer 29z having no rare earth oxide in the outline when viewed in the height direction x can be formed.

[0147] On the other hand, the coating shape using the second conductive paste may be the same as the planar shape obtained by the first step using the first conductive paste. For each of the completed first internal electrode layer 16a and the second internal electrode layer 16b, an electrode main body layer 29z in which no rare earth oxide exists at the edge when viewed in the height direction x can be formed. Furthermore, the coating shape using the second conductive paste may be such that, relative to the planar shape obtained by the first step using the first conductive paste, the dimension in either the length direction z or the width direction y is reduced by 2% of the planar shape obtained by the first step using the first conductive paste. In particular, it is preferred to reduce any larger dimension in the length direction z or the width direction y.

[0148] In addition, the physical thickness of printing, that is, the thickness of the coating surface in each of the first step using the first conductive paste and the second step using the second conductive paste can be arbitrary, but the thickness of the coating surface using the second conductive paste is preferably less than 50% of the thickness of the coating surface using the first conductive paste.

[0149] In this way, the first coated dielectric sheet and the second coated dielectric sheet are stacked alternately or in a desired arrangement order, thereby manufacturing a stacked product including the inner layer portion 18. By stacking the second coated dielectric sheet or the first coated dielectric sheet with the surface not coated with the conductive paste facing the first coated dielectric sheet or the second coated dielectric sheet with the surface coated with the second conductive paste, the second conductive paste coated surface and the surface of the dielectric sheet are in contact, so that the inner layer portion 18 can be obtained. Figure 6 or Fig. 9 The interlayer structure along the height direction x as shown.

[0150] Next, a predetermined number of dielectric sheets for outer layers without the pattern of the internal electrode layer printed thereon are stacked to form a portion of the second main surface side outer layer portion 20b on the second main surface 12b side. Then, a dielectric sheet with the pattern of the first internal electrode layer printed thereon and a dielectric sheet with the pattern of the second internal electrode layer printed thereon are stacked in sequence on the portion of the second main surface side outer layer portion 20b to form the structure of the present invention, thereby forming a portion of the inner layer portion 18. Thereafter, a predetermined number of dielectric sheets for outer layers without the pattern of the internal electrode layer printed thereon are stacked to form a portion of the first main surface side outer layer portion 20a on the first main surface 12a side. Thus, a laminated sheet is produced.

[0151] In the above description, the first step of applying the first conductive paste corresponds to the first step of the present invention, and the second step of applying the second conductive paste corresponds to the second step of the present invention, and they correspond to the coating step of the present invention. In addition, the step of stacking the first coated dielectric sheet and the second coated dielectric sheet alternately or in a desired arrangement order corresponds to the stacking step of the present invention.

[0152] Alternatively, as a two-step coating process, the second step of coating the second conductive paste on the surface of the dielectric sheet and the first step of coating the first conductive paste on the surface coated with the first conductive paste may be performed. In this case, the surface coated with the second conductive paste and the surface of the dielectric sheet are in contact with each other by the coating process of the conductive paste, and the following can be obtained: Figure 6 or Fig. 9 The interlayer structure along the height direction x as shown.

[0153] That is, the manufacturing method of the multilayer ceramic capacitor of the present invention is not limited by the order of performing the first step and the second step, or the respective coating objects of the first step and the second step, as long as the laminated sheet after manufacture can be in a state where the coating surface of the second conductive paste obtained by the second step of coating the second conductive paste is in contact with the surface of the dielectric sheet.

[0154] (Fabrication of stacked blocks)

[0155] Next, the laminated sheets are pressed in the lamination direction of the dielectric sheets by isostatic pressing or the like, thereby producing a laminated block.

[0156] (Preparation of laminated sheets)

[0157] The stacked block is cut into a given size to obtain a plurality of stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0158] (Production of laminated body)

[0159] The stacked small sheets are fired to produce the stacked body 12. The firing temperature depends on the material of the dielectric sheet and the material of the internal electrode layer, but is preferably 900°C or higher and 1400°C or lower.

[0160] During the firing process of the stacked chips, the rare earth oxide diffuses from the coating film using the second conductive paste to the coating film using the first conductive paste, thereby forming a thin film of the internal electrode layer 16 after firing. Figure 6 , Fig. 9 In addition, by adjusting the firing temperature and time of the stacked small pieces, or the coating thickness and composition of the first conductive paste and the second conductive paste, the internal electrode layer 16 after firing can have a structure in which the intermediate layer 29y is omitted.

[0161] (Formation of external electrodes)

[0162] (a) Sintered layer

[0163] In the following description, it is assumed that the base electrode layer is formed of a sintered layer. When forming the sintered layer, a conductive paste containing a glass component and a metal is prepared, applied, and then sintered to form the base electrode layer.

[0164] The first foundation electrode layer 32a of the first external electrode 30a and the second foundation electrode layer 32b of the second external electrode 30b are formed on the first end surface 12e and the second end surface 12f of the laminated body 12 obtained by firing.

[0165] When forming a sintered layer as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied by a dipping method, and then sintered to form a sintered layer as the base electrode layer 32. The temperature of the sintering treatment at this time is preferably 700° C. or higher and 900° C. or lower.

[0166] (b) Conductive resin layer

[0167] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the calcined layer, or the conductive resin layer may be formed directly on the laminate 12 without forming a calcined layer.

[0168] A conductive resin paste containing a thermosetting resin and a metal component is applied to the sintered layer or the laminate 12, and heat-treated at a temperature of 250°C or more and 550°C or more to heat-cure the resin, thereby forming a conductive resin layer. The atmosphere during the heat treatment is preferably N 2 In order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

[0169] As a method for applying the conductive resin paste, similar to the method of forming the base electrode layer from the baked layer, for example, a method of applying the conductive paste by extruding it from a slit or a roll transfer method can be used.

[0170] (c) Thin film layer

[0171] In addition, when the base electrode layer 32 is formed by a thin film layer, the base electrode layer can be formed by covering the portion other than the desired portion where the external electrode 30 is to be formed by masking or the like, and performing a thin film forming method such as sputtering or evaporation on the exposed desired portion. The base electrode layer formed by a thin film layer is set to a layer of 1 μm or less in which metal particles are deposited.

[0172] (Plating electrode)

[0173] Furthermore, the external electrodes may be formed by using only the plated layers as plated electrodes without providing the base electrode layer 32. In this case, the external electrodes may be formed by the following method.

[0174] Either or both of the first external electrode 30a and the second external electrode 30b may form a plated layer directly on the surface of the laminate 12 without providing the base electrode layer 32. That is, the two-terminal laminated ceramic capacitor 10 may also be a structure including a plated layer directly electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. When performing the plating process, either electrolytic plating or electroless plating may be used, but electroless plating requires pretreatment with a catalyst or the like in order to increase the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferably used. As a plating method, drum plating is preferably used. In addition, an upper plated electrode formed on the surface of the lower plated electrode may also be formed in the same manner as required.

[0175] (Production of coating layer)

[0176] Next, a plating layer is formed on the surface of the base electrode layer 32 , the surface of the conductive resin layer, or the surface of the lower plating electrode or the surface of the upper plating electrode as necessary.

[0177] In more detail, in the present embodiment, on the base electrode layer 32 as the sintered layer, a Ni coating is formed as the coating 34, and a Sn coating is formed as the upper coating 36. The Ni coating and the Sn coating are formed successively by, for example, a drum plating method. When the plating process is carried out, any one of electrolytic plating and electroless plating can also be adopted. However, electroless plating needs to use the pre-treatment of a catalyst etc. in order to improve the plating precipitation speed, and there is a shortcoming that the process is complicated. Therefore, it is usually preferred to adopt electrolytic plating.

[0178] As described above, the two-terminal multilayer ceramic capacitor according to the first embodiment is obtained.

[0179] B. Second Embodiment

[0180] 1. Three-terminal multilayer ceramic capacitor

[0181] As a laminated ceramic capacitor according to a second embodiment of the present invention, referring to Figures 11 to 17 A three-terminal multilayer ceramic capacitor 110 will be described.

[0182] Fig.11 It is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Fig.12 It is a plan view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Fig.13 It is a front view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Fig.14 yes Fig.11 Cross-sectional view at line XIV-XIV of . Fig.15 yes Fig.11 A cross-sectional view taken along line XV-XV of FIG. Fig.16 yes Fig.14 Cross-sectional view at line XVI-XVI of . Fig.17 yes Fig.14 Cross-sectional view at line XVII-XVII of .

[0183] The laminate 12 includes a plurality of laminated dielectric layers 14 and a plurality of internal electrode layers 116 laminated on the dielectric layers 14. The dielectric layers 14 and the internal electrode layers 116 are laminated in the height direction x.

[0184] The laminate 12 has the first principal surface 12a and the second principal surface 12b opposite in the height direction x, the first side surface 12c and the second side surface 12d opposite in the width direction y orthogonal to the height direction x, and the first end surface 12e and the second end surface 12f opposite in the length direction z orthogonal to the height direction x and the width direction y. In this laminate 12, the corners and the ridges are rounded. In addition, the so-called corners refer to the parts where the three adjacent faces of the laminate intersect, and the so-called ridges refer to the parts where the two adjacent faces of the laminate intersect. In addition, it is also possible to form concave-convex etc. on part or all of the first principal surface 12a and the second principal surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0185] The laminate 12 has an inner layer portion 18 composed of a single or multiple dielectric layers 14 and multiple internal electrode layers 116 arranged thereon. The internal electrode layer 116 has a first internal electrode layer 116a extending to the first end face 12e and the second end face 12f and a second internal electrode layer 116b extending to the second side face 12c and the second side face 12d. In the inner layer portion 18, the multiple first internal electrode layers 116a and the second internal electrode layers 116b are opposed to each other with the dielectric layer 14 interposed therebetween.

[0186] The stacked body 12 has a first main surface side outer layer portion 20a, which is located on the first main surface 12a side and is formed by a plurality of dielectric layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and a straight line on the outermost surface.

[0187] Similarly, the stack 12 has a second main surface side outer layer portion 20b, which is located on the second main surface 12b side and is formed by a plurality of dielectric layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and a straight line on the outermost surface.

[0188] Furthermore, the laminate 12 has a first side surface side outer layer portion 22a located on the first side surface 12c side and formed of a plurality of dielectric layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side.

[0189] Similarly, the laminate 12 has a second side surface outer layer portion 22b located on the second side surface 12d side and formed of a plurality of dielectric layers 14 located between the second side surface 12d and the outermost surface of the inner layer portion 18 on the second side surface 12d side.

[0190] Furthermore, the laminate 12 has a first end surface side outer layer portion 24a located on the first end surface 12e side and formed of a plurality of dielectric layers 14 located between the first end surface 12e and the outermost surface of the inner layer portion 18 on the first end surface 12e side.

[0191] Similarly, the laminate 12 has a second end surface side outer layer portion 24b located on the second end surface 12f side and formed of a plurality of dielectric layers 14 located between the second end surface 12f and the outermost surface of the inner layer portion 18 on the second end surface 12f side.

[0192] The first principal surface side outer layer portion 20a is located on the first principal surface 12a side. The first principal surface side outer layer portion 20a is an aggregate of a plurality of dielectric layers 14 located between the first principal surface 12a and the internal electrode layer 116 closest to the first principal surface 12a.

[0193] The second principal surface side outer layer portion 20b is located on the second principal surface 12b side. The second principal surface side outer layer portion 20b is an aggregate of a plurality of dielectric layers 14 located between the second principal surface 12b and the internal electrode layer 116 closest to the second principal surface 12b.

[0194] The material of the dielectric layer 14 is the same as that of the multilayer ceramic capacitor 10 , and therefore the description thereof will be omitted.

[0195] The average thickness of the dielectric layer 14 in the height direction x after firing is also the same as that of the multilayer ceramic capacitor 10 , and therefore the description thereof will be omitted.

[0196] The laminate 12 includes a plurality of first internal electrode layers 116a and a plurality of second internal electrode layers 116b as the plurality of internal electrode layers 116. The plurality of first internal electrode layers 116a and the plurality of second internal electrode layers 116b are buried so as to be alternately arranged at equal intervals along the height direction x of the laminate 12.

[0197] like Fig.16As shown, the first internal electrode layer 116a includes a first opposing electrode portion 126a opposed to the second internal electrode layer 116b, and a first lead electrode portion 128a led from the first opposing electrode portion 126a to the surface of the first end surface 12e of the stacked body 12. 1 and another first lead electrode portion 128a led out from the first counter electrode portion 126a to the surface of the second end face 12f of the stacked body 12. 2 Specifically, a first extraction electrode portion 128a 1 The other first lead electrode portion 128a is exposed on the surface of the first end surface 12e of the stacked body 12. 2 The first internal electrode layer 116 a is exposed on the surface of the second end surface 12 f of the laminate 12 . Therefore, the first internal electrode layer 116 a is not exposed on the surfaces of the first side surface 12 c and the second side surface 12 d of the laminate 12 .

[0198] like Fig.17 As shown, the second internal electrode layer 116b is substantially cross-shaped and includes a second opposing electrode portion 126b opposed to the first internal electrode layer 116a, and a second lead electrode portion 128b led from the second opposing electrode portion 126b to the surface of the first side surface 12c of the stack 12. 1 and another second lead electrode portion 128b led out from the second counter electrode portion 126b to the surface of the second side surface 12d of the stacked body 12. 2 Specifically, a second lead electrode portion 128b 1 The second lead electrode portion 128b is exposed on the surface of the first side surface 12c of the laminate 12. 2 The second internal electrode layer 116 b is exposed on the surface of the second side surface 12 d of the laminate 12 . Therefore, the second internal electrode layer 116 b is not exposed on the surface of the first end surface 12 e and the surface of the second end surface 12 f of the laminate 12 .

[0199] In addition, the four corners of the second opposing electrode portion 126b in the second internal electrode layer 116b are not chamfered, but may be chamfered. This can prevent the corners of the first opposing electrode portion 126a of the first internal electrode layer 116a from overlapping, and can prevent electric field concentration. As a result, insulation breakdown of the ceramic capacitor that may occur due to electric field concentration can be prevented.

[0200] The shapes of the first and second internal electrode layers 116a and 116b as viewed in the height direction x may be changed in the same manner as the first and second internal electrode layers 16a and 16b of the two-terminal multilayer ceramic capacitor 10 of the first embodiment.

[0201] The material composition of the first internal electrode layer 116a and the second internal electrode layer 116b and the composition within the layer in the height direction x are similar to those of the first internal electrode layer 16a and the second internal electrode layer 16b of the multilayer ceramic capacitor 10 of the first embodiment.

[0202] The thickness of each of the first internal electrode layer 116 a and the second internal electrode layer 116 b is not particularly limited, but is preferably about 0.4 μm or more and 0.8 μm or less, for example.

[0203] The number of each of the first internal electrode layer 116 a and the second internal electrode layer 116 b is not particularly limited, but the total number is preferably 2 or more and 1000 or less.

[0204] The external electrode 30 includes a first external electrode 30 a , a second external electrode 30 b , a third external electrode 30 c , and a fourth external electrode 30 d .

[0205] The first external electrode 30a is connected to the first internal electrode layer 116a and is disposed on the surface of the first end surface 12e. In addition, the first external electrode 30a extends from the first end surface 12e of the stacked body 12 and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first external electrode 30a is connected to a first lead electrode portion 128a of the first internal electrode layer 116a. 1 Electrical connection.

[0206] The second external electrode 30b is connected to the first internal electrode layer 116a and is disposed on the surface of the second end surface 12f. In addition, the second external electrode 30b extends from the second end surface 12f of the stacked body 12 and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second external electrode 30b is connected to the other first lead electrode portion 128a of the first internal electrode layer 116a. 2 Electrical connection.

[0207] The third external electrode 30c is connected to the second internal electrode layer 116b and is disposed on the surface of the first side surface 12c. In addition, the third external electrode 30c extends from the first side surface 12c of the stacked body 12 and is also disposed on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the third external electrode 30c is connected to a second lead electrode portion 128b of the second internal electrode layer 116b. 1 Electrical connection.

[0208] The fourth external electrode 30d is connected to the second internal electrode layer 116b and is disposed on the surface of the second side surface 12d. In addition, the fourth external electrode 30d extends from the second side surface 12d of the stacked body 12 and is also disposed on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the fourth external electrode 30d is connected to the other second lead electrode portion 128b of the second internal electrode layer 116b. 2 Electrical connection.

[0209] In the laminate 12, an electrostatic capacitor is formed by the first opposing electrode portion 126a of the first internal electrode layer 116a and the second opposing electrode portion 126b of the second internal electrode layer 116b being opposed to each other via the dielectric layer 14. Therefore, an electrostatic capacitor can be obtained between the first external electrode 30a and the second external electrode 30b connected to the first internal electrode layer 116a and the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode layer 116b, thereby exhibiting the characteristics of a capacitor.

[0210] The foundation electrode layer 32 includes a first foundation electrode layer 32 a , a second foundation electrode layer 32 b , a third foundation electrode layer 32 c , and a fourth foundation electrode layer 32 d .

[0211] The first base electrode layer 32a is connected to the first internal electrode layer 116a and is disposed on the surface of the first end surface 12e. In addition, the first base electrode layer 32a extends from the first end surface 12e and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first base electrode layer 32a and a first lead electrode portion 128a of the first internal electrode layer 116a are connected. 1 Electrical connection.

[0212] The second foundation electrode layer 32b is connected to the first internal electrode layer 116a and is arranged on the surface of the second end surface 12f. In addition, the second foundation electrode layer 32b extends from the second end surface 12f and is also arranged on a portion of the first main surface 12a and a portion of the second main surface 12b, and a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the second foundation electrode layer 32b and the other first extraction electrode portion 128a of the first internal electrode layer 116a are connected. 2 Electrical connection.

[0213] The third foundation electrode layer 32c is connected to the second internal electrode layer 116b and is disposed on the surface of the first side surface 12c. In addition, the third foundation electrode layer 32c extends from the first side surface 12c and is also disposed on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the third foundation electrode layer 32c and one second lead electrode portion 128b of the second internal electrode layer 116b are connected. 1 Electrical connection.

[0214] The fourth foundation electrode layer 32d is connected to the second internal electrode layer 116b and is disposed on the surface of the second side surface 12d. In addition, the fourth foundation electrode layer 32d extends from the second side surface 12d and is also disposed on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the fourth foundation electrode layer 32d and the other second extraction electrode portion 128b of the second internal electrode layer 116b are connected. 2 Electrical connection.

[0215] The plating layer 34 includes a first plating layer 34 a , a second plating layer 34 b , a third plating layer 34 c , and a fourth plating layer 34 d .

[0216] The first plating layer 34 a is arranged to cover the surface of the first foundation electrode layer 32 a .

[0217] The second plating layer 34b is arranged to cover the surface of the second foundation electrode layer 32b.

[0218] The third plating layer 34c is arranged to cover the surface of the third foundation electrode layer 32c.

[0219] The fourth plating layer 34d is arranged to cover the surface of the fourth foundation electrode layer 32d.

[0220] The material composition of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c and the fourth external electrode 30d of the three-terminal multilayer ceramic capacitor 110 and the structure within the layer are the same as the first external electrode 30a and the second external electrode 30b of the two-terminal multilayer ceramic capacitor 10 of the first embodiment.

[0221] The three-terminal multilayer ceramic capacitor 110 of the present embodiment is characterized in that the composition of the materials of the plurality of first internal electrode layers 116a and second internal electrode layers 116b constituting the internal electrode layer 116, the structure within the layer in the height direction x, and the structure on the layer when viewed in the height direction x are the same as the first internal electrode layer 16a and the second internal electrode layer 16b of the multilayer ceramic capacitor 10 of the first embodiment. That is, Fig.14 The structure of region R3 is Figure 6 or Fig. 9The structure of the first internal electrode layer 16a of the multilayer ceramic capacitor 10 of the first embodiment shown is the same. Fig.15 The structure of region R4 is Figure 8 or Fig.10 The structure of the first internal electrode layer 16a of the multilayer ceramic capacitor 10 according to the first embodiment shown is the same.

[0222] Thus, the three-terminal multilayer ceramic capacitor 110 of the present embodiment, like the multilayer ceramic capacitor 10 of the first embodiment, can suppress the reduction in reliability due to oxygen vacancies by including a rare earth oxide distributed along the interface with the dielectric layer 14. In addition, the three-terminal multilayer ceramic capacitor 110 of the present embodiment can adopt various structures similar to the structure that can be adopted by the multilayer ceramic capacitor 10 described in the first embodiment, and achieve various effects corresponding to the various structures.

[0223] 2. Method for manufacturing three-terminal multilayer ceramic capacitor

[0224] Next, a method for manufacturing a three-terminal multilayer ceramic capacitor will be described.

[0225] (Prepare)

[0226] First, a dielectric sheet for a dielectric layer and a conductive paste for an internal electrode layer are prepared. In addition, a dielectric sheet configured with a first internal electrode layer 116a, a dielectric sheet configured with a second internal electrode layer 116b, and a dielectric sheet not configured with an internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0227] Here, two kinds of conductive pastes are used to obtain the first internal electrode layer 116a and the second internal electrode layer 116b in the completed three-terminal multilayer ceramic capacitor 110. Specifically, a conductive paste containing a conductive material such as a metal material (hereinafter referred to as a first conductive paste) as in the conventional example and a Dy conductive paste mixed with the first conductive paste are used. 2 O 3 , Y 2 O 3 ,La 2 O 3 、Nd 2 O 3 、CeO 2 A conductive paste (hereinafter referred to as a second conductive paste) obtained by mixing and stirring rare earth oxides such as .

[0228] (Production of laminated sheets)

[0229] Next, a conductive paste for the internal electrode layer is printed on the dielectric sheet in a predetermined pattern corresponding to each shape of the internal electrode layer 116 by printing methods such as screen printing or gravure printing, for example. Thus, the conductive paste is applied to the portion of the dielectric sheet where the first internal electrode layer 116a is to be arranged (hereinafter, such a dielectric sheet is referred to as a first coated dielectric sheet). Furthermore, the conductive paste is applied to the portion of the dielectric sheet where the second internal electrode layer 116b is to be arranged (hereinafter, such a dielectric sheet is referred to as a second coated dielectric sheet).

[0230] Specifically, taking screen printing as an example, a screen plate for printing the first internal electrode layer 116a and a screen plate for printing the second internal electrode layer 116b are prepared respectively, and a printer that can print these two screen plates on different dielectric sheets respectively can print given patterns corresponding to each internal electrode layer 116.

[0231] In this process, a process is performed to obtain the internal structure of each of the first internal electrode layer 116a and the second internal electrode layer 116b in the completed three-terminal multilayer ceramic capacitor 110. Specifically, a two-stage coating process is performed, namely, a first process of coating the surface of the dielectric sheet with the first conductive paste, and a second process of coating the surface coated with the first conductive paste after the first process of applying the first conductive paste.

[0232] Alternatively, a coating process may be performed that includes three stages: a first process of using a first conductive paste, a second process of using a second conductive paste after the first process of using the first conductive paste, and a first process of applying the first conductive paste again on the coating surface of the second conductive paste after the second process of using the second conductive paste.

[0233] The first step using the first conductive paste is performed so as to have a shape suitable for the shape (planar shape) of each of the first internal electrode layer 116 a and the second internal electrode layer 116 b when viewed in the height direction x after completion.

[0234] Next, the coating shape obtained by the second step using the second conductive paste is preferably set to be such that the dimensions in the length direction z and the width direction y are reduced by 2% of the planar shape obtained by the first step using the first conductive paste. Thus, for each of the first internal electrode layer 116a and the second internal electrode layer 116b after completion, an electrode main body layer 29z having no rare earth oxide in the outline when viewed in the height direction x can be formed.

[0235] On the other hand, the coating shape using the second conductive paste may be the same as the planar shape obtained by the first step using the first conductive paste. For each of the completed first internal electrode layer 116a and the second internal electrode layer 116b, an electrode main body layer 29z in which no rare earth oxide exists at the edge when viewed in the height direction x can be formed. Furthermore, the coating shape using the second conductive paste may be such that, relative to the planar shape obtained by the first step using the first conductive paste, the dimension in either the length direction z or the width direction y is reduced by 2% of the planar shape obtained by the first step using the first conductive paste. In particular, it is preferred to reduce any larger dimension in the length direction z or the width direction y.

[0236] In addition, the physical thickness of printing, that is, the thickness of the coating surface in each of the first step using the first conductive paste and the second step using the second conductive paste can be arbitrary, but the thickness of the coating surface using the second conductive paste is preferably less than 50% of the thickness of the coating surface using the first conductive paste.

[0237] In this way, the first coated dielectric sheet and the second coated dielectric sheet are stacked alternately or in a desired arrangement order, thereby manufacturing a stacked product including the inner layer portion 18. By stacking the second coated dielectric sheet or the first coated dielectric sheet with the surface not coated with the conductive paste facing the first coated dielectric sheet or the second coated dielectric sheet with the surface coated with the second conductive paste, the second conductive paste coated surface and the surface of the dielectric sheet are in contact, so that the inner layer portion 18 can be obtained. Figure 6 or Fig. 9 The interlayer structure along the height direction x as shown.

[0238] Next, a predetermined number of dielectric sheets for outer layers without the pattern of the internal electrode layer printed thereon are stacked to form a portion of the second main surface side outer layer portion 20b on the second main surface 12b side. Then, a dielectric sheet with the pattern of the first internal electrode layer printed thereon and a dielectric sheet with the pattern of the second internal electrode layer printed thereon are sequentially stacked on the portion of the second main surface side outer layer portion 20b to form the structure of the present invention, thereby forming a portion of the inner layer portion 18. Thereafter, a predetermined number of dielectric sheets for outer layers without the pattern of the internal electrode layer printed thereon are further stacked to form a portion of the first main surface side outer layer portion 20a on the first main surface 12a side. Thus, a laminated sheet is produced.

[0239] In the above description, the first step of applying the first conductive paste corresponds to the first step of the present invention, and the second step of applying the second conductive paste corresponds to the second step of the present invention, and they correspond to the coating step of the present invention. In addition, the step of stacking the first coated dielectric sheet and the second coated dielectric sheet alternately or in a desired arrangement order corresponds to the stacking step of the present invention.

[0240] Alternatively, as a two-step coating process, the second step of coating the second conductive paste on the surface of the dielectric sheet and the first step of coating the first conductive paste on the surface coated with the first conductive paste may be performed. In this case, the surface coated with the second conductive paste and the surface of the dielectric sheet are in contact with each other by the coating process of the conductive paste, and the following can be obtained: Figure 6 or Fig. 9 The interlayer structure along the height direction x as shown.

[0241] That is, the manufacturing method of the multilayer ceramic capacitor of the present invention is not limited by the order of performing the first step and the second step, or the respective coating objects of the first step and the second step, as long as the laminated sheet after manufacture can be in a state where the coating surface of the second conductive paste obtained by the second step of coating the second conductive paste is in contact with the surface of the dielectric sheet.

[0242] (Fabrication of stacked blocks)

[0243] Next, the laminated sheets are pressed in the lamination direction of the dielectric sheets by isostatic pressing or the like, thereby producing a laminated block.

[0244] (Preparation of laminated sheets)

[0245] The stacked blocks are cut into predetermined sizes to produce stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0246] (Production of laminated body)

[0247] The stacked small sheets are fired to produce the stacked body 12. The firing temperature depends on the material of the dielectric sheet and the material of the internal electrode layer, but is preferably 900°C or higher and 1400°C or lower.

[0248] During the firing process of the stacked chips, the rare earth oxide diffuses from the coating film using the second conductive paste to the coating film using the first conductive paste, thereby forming a thin film of the internal electrode layer 116 after firing. Figure 6 , Fig. 9In addition, by adjusting the firing temperature and time of the stacked small pieces, or the coating thickness and composition of the first conductive paste and the second conductive paste, the internal electrode layer 116 after firing can have a structure in which the intermediate layer 29y is omitted.

[0249] (Formation of external electrodes)

[0250] (a) Sintered layer

[0251] In the following description, it is assumed that the base electrode layer is formed of a sintered layer. When forming the sintered layer, a conductive paste containing a glass component and a metal is prepared, applied, and then sintered to form the base electrode layer.

[0252] The third foundation electrode layer 32c of the third external electrode 30c is formed on the first side surface 12c of the laminated body 12 obtained by firing, and the fourth foundation electrode layer 32d of the fourth external electrode 30d is formed on the second side surface 12d of the laminated body 12.

[0253] When forming a sintered layer as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied and then sintered to form a sintered layer as the base electrode layer 32. The sintering temperature is preferably 700°C or more and 900°C or less.

[0254] Here, various methods can be used as a method for forming the sintered layer. For example, a method of applying the conductive paste by extruding it from a slit can be used. In the case of this method, by increasing the amount of conductive paste extruded, the base electrode layer 32 can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0255] In addition, the base electrode layer 32 can also be formed using a roller transfer method. In the case of the roller transfer method, when the base electrode layer 32 is formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b, the base electrode layer 32 can be formed on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during the roller transfer.

[0256] Next, the first foundation electrode layer 32a of the first external electrode 30a is formed on the first end surface 12e of the fired laminate 12, and the second foundation electrode layer 32b of the second external electrode 30b is formed on the second end surface 12f of the laminate 12.

[0257] In the case of forming a sintered layer as the base electrode layer 32, similarly to the formation of each base electrode layer 32 of the third external electrode 30c and the fourth external electrode 30d, a conductive paste containing a glass component and a metal component is applied, and then a sintering process is performed to form a sintered layer as the base electrode layer 32. The temperature of the sintering process at this time is preferably 700° C. or higher and 900° C. or lower.

[0258] In addition, as a method for forming a sintered layer of the base electrode layer 32 serving as the first external electrode 30a and the second external electrode 30b, a conductive paste for the base electrode layer is formed by an immersion method so as to extend not only to the first end face 12e and the second end face 12f but also to a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0259] In addition, regarding the sintering process, the third base electrode layer 32c of the third external electrode 30c, the fourth base electrode layer 32d of the fourth external electrode 30d, the first base electrode layer 32a of the first external electrode 30a, and the second base electrode layer 32b of the second external electrode 30b can be sintered simultaneously, or the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d and the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b can be sintered separately.

[0260] (b) Conductive resin layer

[0261] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the calcined layer, or the conductive resin layer may be formed directly on the laminate 12 without forming a calcined layer.

[0262] The conductive resin paste containing a thermosetting resin and a metal component is applied on the sintered layer or the laminate 12, and heat-treated at a temperature of 250°C to 550°C to heat-cure the resin, thereby forming a conductive resin layer. The atmosphere during the heat treatment is preferably N 2 In order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

[0263] As a method for applying the conductive resin paste, similar to the method of forming the base electrode layer 32 from a sintered layer, for example, a method of applying the conductive resin paste by extruding it from a slit or a roll transfer method can be used.

[0264] (c) Thin film layer

[0265] In addition, when the base electrode layer 32 is formed by a thin film layer, the base electrode layer can be formed by covering the portion other than the desired portion where the external electrode 30 is to be formed by masking or the like, and performing a thin film forming method such as sputtering or evaporation on the exposed desired portion. The base electrode layer formed by a thin film layer is set to a layer of 1 μm or less in which metal particles are deposited.

[0266] (Plating electrode)

[0267] Furthermore, the external electrodes may be formed by using only the plated layers as plated electrodes without providing the base electrode layer 32. In this case, the external electrodes may be formed by the following method.

[0268] Any one of the first external electrode 30a to the fourth external electrode 30d or each of them may also form a plating layer directly on the surface of the laminate 12 without providing the base electrode layer 32. That is, the three-terminal laminated ceramic capacitor 110 may also be a structure including a plating layer directly electrically connected to the first internal electrode layer 116a and the second internal electrode layer 116b. When performing the plating process, any one of electrolytic plating and electroless plating may also be used, but electroless plating requires pretreatment with a catalyst or the like in order to increase the plating deposition speed, and has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferably used. As a plating method, drum plating is preferably used. In addition, an upper plated electrode formed on the surface of the lower plated electrode may also be formed in the same manner as required.

[0269] (Production of coating layer)

[0270] Next, a plating layer is formed on the surface of the base electrode layer 32 , the surface of the conductive resin layer, or the surface of the lower plating electrode or the surface of the upper plating electrode as necessary.

[0271] In more detail, in the present embodiment, on the base electrode layer 32 as the sintered layer, a Ni coating is formed as the coating 34, and a Sn coating is formed as the upper coating 36. The Ni coating and the Sn coating are formed successively by, for example, a drum plating method. When the plating process is carried out, any one of electrolytic plating and electroless plating can also be adopted. However, electroless plating needs to use the pre-treatment of a catalyst etc. in order to improve the plating precipitation speed, and there is a shortcoming that the process is complicated. Therefore, it is usually preferred to adopt electrolytic plating.

[0272] As described above, the three-terminal multilayer ceramic capacitor 110 according to the present embodiment is manufactured.

[0273] In addition, although the embodiments of the present invention are disclosed by the above description, the present invention is not limited thereto.

[0274] That is, in the above-mentioned embodiments, the two-terminal multilayer ceramic capacitor 10 or the three-terminal multilayer ceramic capacitor 110 has an internal electrode layer 16 having an intermediate layer 29y between the interface layer 29x and the electrode main body layer 29z, but the intermediate layer 29y may be omitted.

[0275] In addition, in the above-mentioned embodiments, the two-terminal multilayer ceramic capacitor 10 and the three-terminal multilayer ceramic capacitor 110 are processed, but the multilayer ceramic capacitor of the present invention is not limited to these structures. In short, the multilayer ceramic capacitor of the present invention only needs to have a multilayer body having a plurality of internal electrode layers arranged opposite to each other and separated and a dielectric layer containing a ceramic material arranged between the plurality of internal electrode layers, and is not limited by other specific structures, such as the number and shape of the multilayer body, the external electrode, and the internal electrode layers connected to the external electrode.

[0276] Including the contents described above, the present invention can make various changes to the above-described embodiments in terms of structure, shape, material, quantity, position or configuration without departing from the scope of the technical idea and purpose of the present invention, which are also included in the present invention.

[0277] <1>

[0278] A multilayer ceramic capacitor comprising:

[0279] A laminate comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, and comprising a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; and

[0280] Multiple external electrodes,

[0281] in,

[0282] The plurality of internal electrode layers have:

[0283] a first internal electrode layer, which is alternately stacked with the plurality of dielectric layers and exposed at the first end surface; and

[0284] a second internal electrode layer, which is alternately stacked with the plurality of dielectric layers and exposed at the second end surface;

[0285] The plurality of external electrodes include:

[0286] a first external electrode connected to the first internal electrode layer; and

[0287] a second external electrode connected to the second internal electrode layer,

[0288] The first internal electrode layer and the second internal electrode layer contain rare earth oxides.

[0289] The rare earth oxide in each of the first internal electrode layer and the second internal electrode layer is distributed along at least one of a pair of interfaces with the dielectric layer.

[0290] <2>

[0291] exist <1> In the described multilayer ceramic capacitors,

[0292] The rare earth oxide in the electrode layers of each of the first internal electrode layer and the second internal electrode layer is distributed along the height direction of the stack of the first internal electrode layer and the second internal electrode layer so as to be greatest in one of a pair of interfaces with the dielectric layer and decrease as the distance from the one of the pair of interfaces with the dielectric layer increases.

[0293] <3>

[0294] exist <1> or <2> In the described multilayer ceramic capacitors,

[0295] The rare earth oxide in each of the electrode layers of the first internal electrode layer and the second internal electrode layer is distributed along the height direction of the stack of the first internal electrode layer and the second internal electrode layer so as to be greatest at both of a pair of interfaces with the dielectric layer and to decrease as the distance from the both of a pair of interfaces with the dielectric layer increases.

[0296] <4>

[0297] exist <1> to <3> In the multilayer ceramic capacitor described in any one of the items,

[0298] When the stack of the first and second internal electrode layers is viewed in the height direction, the rare earth oxide distribution in each of the first and second internal electrode layers increases from the boundary with the dielectric layer toward the center.

[0299] <5>

[0300] exist <1> to <4> In the multilayer ceramic capacitor described in any one of the items,

[0301] When observing the height direction of the stack of the first internal electrode layer and the second internal electrode layer, the rare earth oxide in the electrode layer of each of the first internal electrode layer and the second internal electrode layer is not included in the contour of the electrode layer of each of the first internal electrode layer and the second internal electrode layer, and in the portion of each of the first internal electrode layer and the second internal electrode layer along the length direction of the stack.

[0302] <6>

[0303] exist <5> In the described multilayer ceramic capacitors,

[0304] The proportion of the region that does not contain the rare earth oxide in the electrode layers of the first internal electrode layer and the second internal electrode layer, respectively, formed along their respective extension directions, is less than 2% of the overall size of the electrode layers of the first internal electrode layer and the second internal electrode layer, respectively, in the extension directions of the first internal electrode layer and the second internal electrode layer, respectively.

[0305] <7>

[0306] exist <1> to <6> In the multilayer ceramic capacitor described in any one of the items,

[0307] When observing the stacked body of the first internal electrode layer and the second internal electrode layer in the height direction,

[0308] The rare earth oxide in the electrode layer of each of the first internal electrode layer and the second internal electrode layer is not included in the portion of each of the first internal electrode layer and the second internal electrode layer along the direction orthogonal to the width direction of the stacked body within the contour of the electrode layer of each of the first internal electrode layer and the second internal electrode layer.

[0309] <8>

[0310] exist <7> In the described multilayer ceramic capacitors,

[0311] The proportion of the region that does not contain the rare earth oxide in the electrode layer of the first internal electrode layer and the second internal electrode layer, which is formed along a direction perpendicular to the extension direction of the first internal electrode layer and the second internal electrode layer, is less than 2% of the overall size of the electrode layer of the first internal electrode layer and the second internal electrode layer in the direction perpendicular to the extension direction of the first internal electrode layer and the second internal electrode layer.

[0312] <9>

[0313] exist <1> to <8> In the multilayer ceramic capacitor described in any one of the items,

[0314] The content of the rare earth oxide in each of the first internal electrode layer and the second internal electrode layer is 0.1 wt % or more and 10 wt % or less when calculated as follows:

[0315] {(weight of rare earth oxide) / (weight of rare earth oxide+weight of main component metal of each of the first internal electrode layer and the second internal electrode layer)}×100.

[0316] <10>

[0317] A multilayer ceramic capacitor comprising:

[0318] A laminate comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, and comprising a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; and

[0319] Multiple external electrodes,

[0320] in,

[0321] The plurality of internal electrode layers have:

[0322] a first internal electrode layer, which is alternately stacked with the plurality of ceramic layers and is exposed at the first end surface and the second end surface; and

[0323] The second internal electrode layer is alternately stacked with the plurality of ceramic layers and exposed on the first side surface and the second side surface.

[0324] The plurality of external electrodes include:

[0325] a first external electrode and a second external electrode connected to the first internal electrode layer; and

[0326] The third external electrode and the fourth external electrode are connected to the second internal electrode layer.

[0327] The first internal electrode layer and the second internal electrode layer contain rare earth oxides.

[0328] The rare earth oxide in each of the first internal electrode layer and the second internal electrode layer is distributed along at least any one of a pair of interfaces with the dielectric layer.

[0329] <11>

[0330] A method for manufacturing a laminated ceramic capacitor, the laminated ceramic capacitor comprising:

[0331] A laminate having a plurality of internal electrode layers arranged to be opposed to each other and spaced apart from each other and a dielectric layer containing a ceramic material disposed between the plurality of internal electrode layers; and

[0332] A plurality of external electrodes are provided on the surface of the stacked body and selectively connected to the plurality of internal electrode layers.

[0333] The method for manufacturing the multilayer ceramic capacitor comprises:

[0334] a coating step of coating a conductive paste constituting the plurality of internal electrode layers on a dielectric sheet corresponding to the dielectric layer; and

[0335] a lamination step of laminating another dielectric sheet coated with the conductive paste on the dielectric sheet coated with the conductive paste,

[0336] The coating process comprises:

[0337] The first step is to apply a first conductive paste containing a conductive material; and

[0338] The second step is performed before, after, or both before and after the first step, and comprises applying a second conductive paste containing a conductive material and a rare earth oxide.

[0339] By at least one of the laminating step and the applying step, a surface on which the second conductive paste is applied obtained by the second step of the applying step is brought into contact with a surface of the dielectric sheet.

[0340] Industrial Applicability

[0341] The present invention as described above has been made in view of such problems, and achieves an effect of being able to suppress a decrease in reliability due to oxygen vacancies, and is useful in application to, for example, a multilayer ceramic capacitor.

[0342] Description of Reference Numerals

[0343] 10 Two-terminal multilayer ceramic capacitors

[0344] 110 Three-terminal multilayer ceramic capacitors

[0345] 12 Laminated body

[0346] 12a 1st main side

[0347] 12b 2nd main side

[0348] 12c 1st side

[0349] 12d Side 2

[0350] 12e 1st end face

[0351] 12f Second end face

[0352] 14 Dielectric layer

[0353] 16, 116 Internal electrode layer

[0354] 16a, 116a First internal electrode layer

[0355] 16b, 116b Second internal electrode layer

[0356] 18 Inner layer

[0357] 20a First main surface side outer layer portion

[0358] 20b Second main surface side outer layer portion

[0359] 22c First side outer layer portion

[0360] 22d Second side outer layer portion

[0361] 24e 1st end surface side outer layer portion

[0362] 24f Second end surface side outer layer portion

[0363] 26a, 126a First opposing electrode portion

[0364] 26b, 126b Second opposing electrode portion

[0365] 28a, 128a 1 , 128a 2 First lead electrode

[0366] 28b, 128b 1 , 128b 2 Second lead electrode

[0367] 29x Interface Layer

[0368] 29y Middle Layer

[0369] 29z Electrode main layer

[0370] 30 External electrodes

[0371] 30a 1st external electrode

[0372] 30b Second external electrode

[0373] 30c 3rd external electrode

[0374] 32. Substrate electrode

[0375] 32a First base electrode layer

[0376] 32b Second base electrode layer

[0377] 32c The third base electrode layer

[0378] 32d 4th base electrode layer

[0379] 34 Plating layer

[0380] 34a 1st plating layer

[0381] 34b Second plating layer

[0382] 34c 3rd plating layer

[0383] 34d 4th coating layer

[0384] Il, Iu interface

[0385] Ef Leading edge

[0386] Es1 1st side edge

[0387] Es2 Second side edge

[0388] R1, R2, R3, R4 areas

[0389] x height direction

[0390] y width direction

[0391] z length direction.

Claims

1. A multilayer ceramic capacitor comprising: A laminate comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, and comprising a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; and Multiple external electrodes, in, The plurality of internal electrode layers have: a first internal electrode layer, which is alternately stacked with the plurality of dielectric layers and exposed at the first end surface; and a second internal electrode layer, which is alternately stacked with the plurality of dielectric layers and exposed at the second end surface; The plurality of external electrodes include: a first external electrode connected to the first internal electrode layer; and a second external electrode connected to the second internal electrode layer, The first internal electrode layer and the second internal electrode layer contain rare earth oxides. The rare earth oxide in each of the first internal electrode layer and the second internal electrode layer is distributed along at least one of a pair of interfaces with the dielectric layer.

2. The multilayer ceramic capacitor according to claim 1, wherein The rare earth oxide in the electrode layers of each of the first internal electrode layer and the second internal electrode layer is distributed along the height direction of the stack of the first internal electrode layer and the second internal electrode layer so as to be greatest in one of a pair of interfaces with the dielectric layer and decrease as the distance from the one of the pair of interfaces with the dielectric layer increases.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The rare earth oxide in each of the electrode layers of the first internal electrode layer and the second internal electrode layer is distributed along the height direction of the stack of the first internal electrode layer and the second internal electrode layer so as to be greatest at both of a pair of interfaces with the dielectric layer and to decrease as the distance from the both of a pair of interfaces with the dielectric layer increases.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein When the stack of the first and second internal electrode layers is viewed in the height direction, the rare earth oxide distribution in each of the first and second internal electrode layers increases from the boundary with the dielectric layer toward the center.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein When observing the height direction of the stack of the first internal electrode layer and the second internal electrode layer, the rare earth oxide in the electrode layer of each of the first internal electrode layer and the second internal electrode layer is not included in the contour of the electrode layer of each of the first internal electrode layer and the second internal electrode layer, and in the portion of each of the first internal electrode layer and the second internal electrode layer along the length direction of the stack.

6. The multilayer ceramic capacitor according to claim 5, wherein: The proportion of the region that does not contain the rare earth oxide in the electrode layers of the first internal electrode layer and the second internal electrode layer, respectively, formed along their respective extension directions, is less than 2% of the overall size of the electrode layers of the first internal electrode layer and the second internal electrode layer, respectively, in the extension directions of the first internal electrode layer and the second internal electrode layer, respectively.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein: When observing the stacked body of the first internal electrode layer and the second internal electrode layer in the height direction, The rare earth oxide in the electrode layer of each of the first internal electrode layer and the second internal electrode layer is not included in the portion of each of the first internal electrode layer and the second internal electrode layer along the direction orthogonal to the width direction of the stacked body within the contour of the electrode layer of each of the first internal electrode layer and the second internal electrode layer.

8. The multilayer ceramic capacitor according to claim 7, wherein: The proportion of the region that does not contain the rare earth oxide in the electrode layer of the first internal electrode layer and the second internal electrode layer, which is formed along a direction perpendicular to the extension direction of the first internal electrode layer and the second internal electrode layer, is less than 2% of the overall size of the electrode layer of the first internal electrode layer and the second internal electrode layer in the direction perpendicular to the extension direction of the first internal electrode layer and the second internal electrode layer.

9. The multilayer ceramic capacitor according to any one of claims 1 to 8, wherein The content of the rare earth oxide in each of the first internal electrode layer and the second internal electrode layer is 0.1 wt % or more and 10 wt % or less when calculated as follows: {(weight of rare earth oxide) / (weight of rare earth oxide+weight of main component metal of each of the first internal electrode layer and the second internal electrode layer)}×100.

10. A laminated ceramic capacitor comprising: A laminate comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, and comprising a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; and Multiple external electrodes, in, The plurality of internal electrode layers have: a first internal electrode layer, which is alternately stacked with the plurality of ceramic layers and is exposed at the first end surface and the second end surface; and The second internal electrode layer is alternately stacked with the plurality of ceramic layers and exposed on the first side surface and the second side surface. The plurality of external electrodes include: a first external electrode and a second external electrode connected to the first internal electrode layer; and The third external electrode and the fourth external electrode are connected to the second internal electrode layer. The first internal electrode layer and the second internal electrode layer contain rare earth oxides. The rare earth oxide in each of the first internal electrode layer and the second internal electrode layer is distributed along at least any one of a pair of interfaces with the dielectric layer.

11. A method for manufacturing a laminated ceramic capacitor, the laminated ceramic capacitor comprising: A laminate having a plurality of internal electrode layers arranged to be opposed to each other and spaced apart from each other and a dielectric layer containing a ceramic material disposed between the plurality of internal electrode layers; and A plurality of external electrodes are provided on the surface of the stacked body and selectively connected to the plurality of internal electrode layers. in, The method for manufacturing the laminated ceramic capacitor comprises: a coating step of coating a conductive paste constituting the plurality of internal electrode layers on a dielectric sheet corresponding to the dielectric layer; and a lamination step of laminating another dielectric sheet coated with the conductive paste on the dielectric sheet coated with the conductive paste, The coating process comprises: The first step is to apply a first conductive paste containing a conductive material; and The second step is performed before, after, or both before and after the first step, and comprises applying a second conductive paste containing a conductive material and a rare earth oxide. By at least one of the laminating step and the applying step, a surface on which the second conductive paste is applied obtained by the second step of the applying step is brought into contact with a surface of the dielectric sheet.

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