Systems, apparatus, and methods for pulse shaping in high voltage power systems

Abstract

A high voltage pulse power delivery system is provided that includes dedicated security features including fault detection and fault management. In addition to a normal communication cable, the pulsed power delivery system can provide remote power through a standard multi-conductor cable without dedicated conduits or isolation. This simplifies the installation of the device, increases the overall deployment speed, and significantly reduces the deployment cost. The pulsed power delivery system is further configured to transmit power through the pulsed current waveform.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 344,920, filed on May 23, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure describes systems and methods related to the field of high voltage power supply technology and safe power management and use of such high voltage power systems. For example, the high voltage power system may fall within the field of level 4 fault management power distribution systems, as described in more detail herein. Background Art

[0003] Effective power delivery systems for controlled environments (e.g., networking equipment within a building) are becoming increasingly common. However, the design and capabilities of existing power delivery systems are often insufficient for their intended use. For example, they may not provide enough power, or they may not be able to effectively reach remote locations.

[0004] Furthermore, existing systems have high equipment costs and high installation costs, while also generally not being compatible with power requirements or safety requirements, and not being durable. Summary of the invention

[0005] A pulser device included in a fault management power delivery system is described, the pulser device including a signal shaping component configured to: generate a pulsed power signal by pulsing the power signal according to a periodic pulsing scheme, wherein the pulses in the pulsed power signal include: a first signal smoothing portion generated at a rising edge of a pulse of the pulsed power signal; and a power delivery portion generated after the first signal smoothing portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram of an exemplary pulsed power delivery system is shown in accordance with some embodiments.

[0007] Figure 2 shows an example of a method that can be included in the Figure 1 A product hierarchy diagram of exemplary components in a pulsed power delivery system is shown in .

[0008] Figure 3 A graph mapping exemplary voltage on-off cycling that may be implemented in a pulsed power delivery system is shown in accordance with some embodiments.

[0009] Figure 4A A circuit diagram is shown of an exemplary safety detection that may be included in a pulsed power delivery system according to some embodiments.

[0010] Figure 4B A method for using a Figure 4A Flowchart of an exemplary fault detection and safety procedure for the safety detection circuit shown in FIG.

[0011] Figure 5A An exemplary circuit diagram of a pulsed power delivery system according to some embodiments is shown.

[0012] Figure 5B A flowchart is shown that describes an exemplary circuit operating procedure that can be used during a power delivery process, according to some embodiments. Figure 5A The circuit of the pulse power delivery system shown is implemented.

[0013] Figure 6 A voltage level diagram depicting different exemplary safety conditions that may occur when operating a pulsed power delivery system is shown in accordance with some embodiments.

[0014] Figure 7 An exemplary circuit diagram of a pulsed power delivery system according to some embodiments is shown.

[0015] Figure 8 A voltage graph depicting certain exemplary voltage characteristics that may occur when operating a pulsed power delivery system is shown in accordance with some embodiments.

[0016] Fig. 9 Exemplary circuit diagrams are shown that may be included in a pulsed power delivery system for clock recovery, ramp generation, cascading, and energy-limited current sources in accordance with some embodiments.

[0017] Fig.10 A circuit diagram is shown of an exemplary circuit that may be included in a pulsed power delivery system for detecting a fault condition in accordance with some embodiments.

[0018] Fig.11 A circuit diagram is shown of an exemplary circuit that may be included in a pulsed power delivery system for detecting a signal cycle length that may indicate a fault condition in accordance with some embodiments.

[0019] Fig.12 A circuit diagram is shown of an exemplary circuit that may be included in a pulsed power delivery system for detecting voltage levels in accordance with some embodiments.

[0020] Fig.13 A circuit diagram is shown of an exemplary circuit that may be included in a pulsed power delivery system for detecting phantom voltages that may indicate a fault condition, in accordance with some embodiments.

[0021] Fig.14 A circuit diagram is shown of an exemplary circuit that may be included in a pulsed power delivery system for routing a fault signal detected in the pulsed power delivery system in accordance with some embodiments.

[0022] Fig.15 An exemplary system diagram and exemplary pulsed power signals that may be generated by a pulsed power delivery system are shown in accordance with some embodiments.

[0023] Fig.16 An exemplary system diagram of a switch control system that may be used in a pulsed power delivery system according to some embodiments is shown.

[0024] Fig.17A An exemplary system diagram of a switch control system that may be used in a pulsed power delivery system for applying a signal shaping solution to address signal deficiencies, and an exemplary signal diagram of a corrected pulsed power signal, are shown in accordance with some embodiments.

[0025] Fig. 17B An exemplary flow chart of a signal shaping solution according to some embodiments is shown. Fig.17A The switch control system shown in is implemented on a pulsed power signal.

[0026] Fig.18 An exemplary system diagram of a pulsed power delivery system in a line-to-line topology is shown in accordance with some embodiments.

[0027] Fig.19 An exemplary system diagram of a pulsed power delivery system in a daisy-chain topology is shown in accordance with some embodiments.

[0028] Fig. 20 An exemplary system diagram of a pulsed power delivery system in a combined topology in which outputs from multiple pulsed power converters are combined is shown in accordance with some embodiments.

[0029] Fig.21 An exemplary system diagram of a pulsed power delivery system showing the RF communication link components involved when a single pulser module is coupled to a single pulsed power converter in accordance with some embodiments is shown.

[0030] Fig. 22 The pulser module and the like are shown according to some embodiments. Fig.21 An exemplary system diagram of an RF communication unit in a pulsed power converter is shown.

[0031] Fig.23An exemplary data packet structure and an exemplary timing diagram for transmitting the data packet structure according to some embodiments are shown.

[0032] Fig.24 A timing diagram depicting an exemplary synchronization strategy when operating three pulser modules is shown in accordance with some embodiments.

[0033] Fig.25 A timing diagram depicting an exemplary synchronization strategy when operating nine pulser modules is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0034] The methods, devices, systems, and other features discussed below may be embodied in a variety of different forms. However, not all of the depicted components are required, and some implementations may include additional, different, or fewer components than those explicitly described in this disclosure. The arrangement and type of components may be changed without departing from the spirit or scope of the solutions set forth herein. In addition, the described processes may be changed, including adding, deleting, or rearranging the order of operations without departing from the spirit or scope of the solutions set forth herein.

[0035] The present disclosure describes embodiments of a pulsed power delivery system that includes dedicated safety features, including fault detection and fault management. Wireless systems are installed in a variety of locations and venues. An exemplary pulsed power delivery system provides a remote power delivery solution that helps wireless system integrators design and deploy wireless systems. The solution can be ideal for large venues or complex installations that require centralized power that is cost-effective, safe, easy to install, and can reach greater distances. In this way, the pulsed power delivery system can be configured to remotely power electrical devices such as remote radios, small cells, security cameras, access control, indoor and outdoor distributed antenna systems (DAS).

[0036] Easy to install and designed for wireless solutions, the pulse power delivery system uses wiring methods that comply with communication wiring in accordance with NEC (National Electrical Code) guidelines. In addition to normal communication cables, the pulse power delivery system can also provide remote power through standard multi-conductor cables without dedicated conduits or isolation. This simplifies the installation of the equipment, increases the overall deployment speed, and significantly reduces the cost of deployment. The pulse power delivery system is further configured to transmit power through a pulsed current waveform (note that the pulsed power signal can be alternatively referred to as a pulsed current signal). The pulsed power delivery system also includes a fault prevention method, which further improves its safety features, as will be described in more detail herein.

[0037] Figure 1 A simplified system schematic diagram is shown that illustrates the equipment components that may be included in an exemplary pulse power delivery system 100. The pulse power supply 110 is configured to receive standard AC power (e.g., a 110 / 220V outlet or a 208V power source from a rack PDU), and then the pulse power supply 110 converts the received standard AC power to a higher voltage, limited current, DC power (e.g., 360V, up to 400V, or higher voltages, according to some embodiments). From the pulse power supply 110, power is transmitted in a pulsed current waveform through the multi-conductor cable power transmission line 102 to be received by the pulse power converter 120. The pulse power converter 120 is configured to convert the received pulse power to power that can be used by the end device (e.g., 48VDC power). The pulse power converters 120 are typically distributed throughout a building, close to one or more end device loads that require power for operation.

[0038] Figure 2 A more detailed system schematic diagram is shown, which shows exemplary device components in the pulse power supply 110 and how it communicates with the pulse power converter 120 in the pulse power delivery system 100. Figure 2 As shown, the pulse power supply 110 may include a chassis for accommodating one or more power modules 111, one or more pulser modules 112, and one or more management cards 115. The management card 115 may include a processor, as well as software, hardware, middleware, and / or circuitry to implement any one or more of the features described herein.

[0039] The back side of the pulse power supply 110 includes one or more openings 113 (e.g., three openings) for mounting a corresponding power module 111, and the front side of the pulse power supply 110 includes one or more openings 114 (e.g., nine openings) for mounting a corresponding pulser module 112. The front side also includes an opening for mounting a management card 115. Within the pulse power supply 110, the power module 111 is configured to receive standard AC power, convert it to a higher voltage, and then transmit it to the pulser module 112, wherein the pulser module 112 is configured to pulse the high voltage power according to a pulsing scheme and transmit it to the pulse power converter 120 via the transmission line 102.

[0040] After receiving the high voltage pulse power, the pulse power converter 120 is configured to convert the high voltage pulse power into a voltage usable by the device (e.g., 48V DC power) and deliver it to one or more terminal devices. The pulser module 112 is coupled to the transmission line 102 to monitor the voltage / power transmitted on the transmission line, wherein the pulser module 112 is configured to control one or more of the fault management safety features of the pulse power delivery system 100 described herein.

[0041] The pulsed power delivery system 100 can be, for example, an implementation of an NEC Class 4 power distribution system capable of supplying a voltage of up to 400V for a limited period (e.g., an on-time period) followed by a substantially reduced voltage for a period of time (e.g., an off-time). The reduced voltage supplied during the off-time can be a predetermined voltage (e.g., less than about 60V) with limited current capability. The on-time (ON-TIME) period and the off-time (OFF-TIME) period are typically in the millisecond range, wherein the on-time period can be greater than the off-time period (e.g., 2ms on-time, 1ms off-time), the on-time period can be less than the off-time period (e.g., 1ms on-time, 2ms off-time), or the on-time period can be substantially the same as the off-time period (e.g., 2ms on-time, 2ms off-time).

[0042] The disconnect time period can be used to determine an unsafe condition in a pulsed power delivery system. If an unsafe condition is detected, the circuit will prevent power from being connected to the line. For example, Figure 3 A voltage graph 300 is shown depicting exemplary voltage values ​​of a pulsed power signal transmitted over time by the pulser module 112 via the transmission line 102, where the pulsed power signal is received by the pulsed power converter 120. Figure 3 In the voltage diagram 300 shown, when the voltage is turned on (eg, V ON ) is longer than the voltage off time (for example, V OFF ). However, according to other embodiments, the voltage is turned on (e.g., V ON ) can be connected to the voltage disconnection time (for example, V OFF ) or is shorter than the disconnection time when the voltage is disconnected.

[0043] To implement safe fault detection in the pulse power delivery system 100, safety circuitry is included. For example, Figure 4AAn exemplary system diagram of a safety circuit system 400 that may be included in the pulser module 112 is shown. The safety circuit system 400 is configured to include both a detection circuit and a prevention circuit, wherein the detection circuit and the prevention circuit are isolated and independent from each other. Keeping the two circuits independent helps improve the reliability (e.g., functional safety failure time (FIT) rate) of the safety circuit system 400, and also ensures fail-safe operation of the safety circuit system 400. In addition, to improve the FIT rate of the safety circuit system 400, the only input to the safety circuit system 400 is a transmission line. The safety circuit system 400 is further designed to use discrete components (e.g., not using programmable devices) to improve its reliability.

[0044] The safety circuit system 400 includes a high voltage DC input 410 generated by the power module 111. The safety circuit system 400 also includes an output terminal 420 coupled to the transmission line 102. The safety circuit system 400 also includes a first switch 401 (e.g., a current distribution switch) coupled to the first logic / control circuit system 403 and the first safety sensing circuit system 405. The safety circuit system 400 also includes a second switch 402 (e.g., a power switch) coupled to the second logic / control circuit system 404 and the second safety sensing circuit system 406.

[0045] Figure 4B A flow chart 450 is shown describing an exemplary fault detection process that may be implemented by the pulser module 112 using the safety circuit system 400. At 451, a fault may be detected. The fault detection 451 may occur during a startup initialization step of the pulsed power delivery system 100. Additionally or alternatively, the fault detection 451 may occur after a period of normal operation of the pulsed power delivery system 100. The fault detection 451 may correspond to a fault condition including, for example, but not limited to, a person touching the transmission line 102, a load receiving pulsed power being disconnected during pulsed power transmission, an overvoltage condition being detected, an on-time period being detected to be too long, an off-time period being detected to be too short, and / or false on voltage sensing (e.g., detection of a voltage on at the output terminal that was not caused by the control system intentionally turning on).

[0046] At 452 , the power path is disconnected by opening the first switch 401 .

[0047] At 453 , the power path is disconnected by opening the second switch 402 .

[0048] At 454, after the fault condition is detected, the disconnected power path is maintained by keeping the first switch 401 and the second switch 402 open (ie, disconnected) for a predetermined length of time. For example, the predetermined time may be a minimum of at least 5 seconds.

[0049] After a predetermined length of time, the power path may be re-established.Alternatively, according to some embodiments, additional verification steps may be implemented before re-establishing the power path.

[0050] Figure 5A An exemplary system diagram including components of a pulsed power delivery system 500 including a safety detection circuit 512 is shown according to some embodiments. The pulsed power delivery system 500 includes a pulsed power pulser module 510, a pulsed power converter module 520, and a transmission line 102 connecting the two system components. Figure 5A , the component devices included in the pulsed power delivery system 500 may be a system architecture representation of the same components shown as being included in the pulsed power delivery system 100 .

[0051] The pulse power pulser module 510 includes a safety detection circuit 512, wherein the safety detection circuit 512 may be Figure 4A . A higher level system representation of certain components of the safety circuit system 400 shown in . The safety detection circuit 512 includes a circuit system component 518 (e.g., a zener diode or a window voltage comparator), wherein the safety detection circuit 512 can be configured to detect a change in the voltage across the transmission line 102 and / or detect a change in the characteristic impedance of the transmission line 102.

[0052] The pulse power pulser module 510 further includes a first switch 514 (for example, the first switch 514 can be Figure 4A 4 and 5. The safety circuit system 400 includes a first switch 401 and a second switch 402 as shown, which are included in the safety circuit system 400), a current source 513 in parallel with the switch 514, a second switch 516, a circuit system component 517 (e.g., a zener diode or a window voltage comparator), and a safety detection circuit 512. The second switch 516 and the circuit system component 517 together constitute a discharger circuit 511. The discharger circuit 511 discharges the transmission line 102 to a safe voltage during the disconnection time, during which time the transmission line 102 is checked for any faults. During the disconnection time, the safety voltage on the transmission line 102 is regulated by the current source 513 and the load detection circuit 521 included in the pulse power converter module 520, as described in more detail below.

[0053] The current source 525 and circuit system components 526 (e.g., a zener diode or a window voltage comparator) included in the pulse power converter module 520 together constitute a load detection circuit 521. The load detection circuit 521 provides a constant current drop on the transmission line 102 during the disconnect time. If the pulse power converter module 520 is not connected to the transmission line 102, the voltage will not be regulated to the predefined threshold. In this case, the pulse power pulser module 510 will fail to detect the pulse power converter module 520 during initialization, or detect that the pulse power converter module 520 is in a disconnected state during normal operation. In both cases, the load detection circuit 521 will disconnect the high voltage and put the transmission line 102 in a safe state until the pulse power converter module 520 is detected.

[0054] During the initialization or disconnect time, the voltage on the transmission line 102 is regulated by the current source 513 (on the pulse power pulser module 510) and the load detection circuit 521 (on the pulse power converter module 520). The load detection circuit 521 regulates the transmission line 102 to a safe voltage by dynamically changing the load resistance or by using the circuit system component 526. The load detection circuit 521 is coupled to a diode 524 and is further connected in parallel with a capacitor 522, which is connected in parallel with a load device 523, wherein the load device 523 is a terminal device configured to receive the pulse power in the pulse power delivery system 500. The combination of the capacitor 522 and the diode 524 acts as a pulse rectifier, which provides a DC bus voltage to the load.

[0055] Figure 5B A flow chart 550 is shown describing an exemplary circuit operating procedure during a power delivery process, wherein power is transferred according to a process controlled by the pulser module 112 using the safety detection circuit 512 .

[0056] At 551 , the first switch 514 is closed at the beginning of the on-time period to provide power from the power source 515 . The power is supplied to the load device 523 through the diode 524 .

[0057] At 552, the first switch 514 opens at the end of the on-time period, effectively stopping power transmission on the transmission line 102. The diode 524 operates to prevent reverse DC current from feeding back to the transmission line 102 from the capacitor 522 on the pulse power converter module 520 side.

[0058] At 553, the second switch 516 in the discharger circuit 511 is closed for a predetermined length of time (e.g., a short time that may be determined, for example, by the maximum capacity of the transmission line 102). By closing the second switch 516, this reduces the remaining voltage on the transmission line 102 to a safe voltage level defined by the reference voltage across the circuit system component 517 in the discharger circuit 511.

[0059] At 554, the current source 513 supplies a low current to the transmission line 102. For example, the low current may be 2 mA. Alternatively, according to some embodiments, the low current may be less than 2 mA, slightly greater than 2 mA, or within a range of a predetermined low current. The current source 525 included in the load detection circuit 521 provides a path to maintain / regulate the remaining line voltage to a value defined by the circuit system component 526 in the load detection circuit 521. According to a first example, the load detection circuit 521 implements a current sink as a load that draws current from the transmission line 102 to maintain the line voltage near the voltage value of the circuit system component 526 as long as the voltage is above a value defined by the circuit system component 526. According to a second example, the load detection circuit 521 implements a controlled current sink as a load and implements an analog window comparator that compares the line voltage with a reference voltage and switches the controlled current sink to maintain the line voltage within a predetermined window.

[0060] Figure 6 Three exemplary graphs 610 , 620 , 630 are shown that depict three different scenarios that may occur on the transmission line 102 and be handled by the safety detection circuit 512 .

[0061] The first graph 610 depicts a normal condition where, at the end of the off-time period, the line voltage detected on the transmission line 102 should be close to the voltage set across the circuitry component 526 (eg, a zener diode).

[0062] The second graph 620 depicts a disconnect condition where, at the end of the disconnect time period, the line voltage detected on the transmission line 102 will be higher than the voltage across the circuitry component 517 (eg, a zener diode or a window voltage comparator).

[0063] The third graph 630 depicts an unsafe condition where, at the end of the off time period, the line voltage detected on the transmission line 102 will be lower than the voltage across the circuitry component 518 (eg, a zener diode or a window voltage comparator).

[0064] Figure 7An exemplary system diagram of a pulsed power delivery system 500-1 is shown, wherein the components in the pulsed power delivery system 500-1 are the same as those shown for the pulsed power delivery system 500, except that in the embodiment described by the pulsed power delivery system 500-1, some parasitic capacitance elements 530 are found on the transmission line 102. The parasitic capacitance elements 530 are represented by capacitors, but in other embodiments, the parasitic capacitance elements 530 may also represent other circuit system components that impart parasitic capacitance characteristics.

[0065] Parasitic capacitance elements 530 are shown to represent undesirable elements that may be found on transmission line 102 in pulsed power delivery system 500-1, and also provide an opportunity to describe how these undesirable elements are addressed by safety detection circuit 512 in pulsed power delivery system 500-1. Essentially, pulsed power delivery system 500-1 is designed so that parasitic capacitance elements 530 do not alter the operation of safety detection circuit 512.

[0066] For example, Figure 8 Shown is a voltage graph 800 including a first voltage curve 801 and a second voltage curve 802. The first voltage curve 801 depicts the voltage characteristics of a first transmission line having a high parasitic capacitance, while the second voltage curve 802 depicts the voltage characteristics of a second transmission line having a low parasitic capacitance.

[0067] In the first voltage curve 801 representing the first transmission line with high parasitic capacitance, under normal conditions, it can be seen that the voltage slightly drops to the discharge voltage V discharge Below, then under unsafe conditions, it can be seen that the voltage drops significantly to the discharge voltage V discharge Below, in the case where the pulse power converter module 520 is disconnected (ie, another type of fault condition), it can be seen that the voltage rises slightly to the discharge voltage V discharge In the second voltage curve 802 representing the second transmission line with low parasitic capacitance, under normal conditions, it can be seen that the voltage drops significantly to the discharge voltage V discharge Below, then in unsafe conditions, the voltage can be seen to drop significantly to the discharge voltage V discharge Below and drops to the level marked as -V / 2, while in the case where the pulse power converter module 520 is disconnected (i.e., another type of fault condition), it can be seen that the voltage rises significantly to the discharge voltage V discharge above and rises to a value marked as surge voltage V surgeThus, pulse power delivery system 500 is able to establish threshold limits in such a way that parasitic capacitance found on transmission line 102 will not alter the operation of the safety detection mechanism of safety detection circuit 512. For example, the voltage threshold limits are set by discharge levels defined by circuit system component 517, current source 513, and a window voltage comparator in circuit system component 526.

[0068] For the purposes of this disclosure, the following definitions may be used:

[0069] Touch - The voltage drops below the defined threshold during the OFF time period.

[0070] Disconnected - A voltage increase above a defined threshold was detected during the disconnect time period.

[0071] Over Voltage - Excessive voltage across the output terminals was detected during the on-time period.

[0072] ON Timing - Detected that the on-time period sensed across the output terminals was determined to be too long.

[0073] OFF Timing - Detects that the OFF time period sensed across the output terminals is determined to be too short or too long.

[0074] "ON sense" - detection of a voltage switch-on at the output terminals that is not caused by the control system switching on.

[0075] Figures 9 to 13 An exemplary circuit diagram is shown that may be included in the pulser module 112 for generating some key signals used during operation. These signals are generated dependent on the output line state and will be used in various parts of the safety detection circuit 512.

[0076] Fig. 9 An exemplary circuit diagram of a circuit 900 that may be included within the pulser module 112 is shown. The circuit 900 includes components and / or mechanisms for preventing a single component failure from causing an unsafe condition that may be included in the pulser module 112.

[0077] The circuit 900 includes a first current source 901 and a second current source 902, wherein the first current source 901 and the second current source 902 are configured in a two-stage cascade configuration to prevent a single component failure from causing an unsafe condition. Each of the first current source 901 and the second current source 902 can be a 2mA current source. The first current source 901 is coupled to the input of the DC bus 903, and the output of the second current source 902 is coupled to the terminal block 904 and to a series of circuit components, the series of circuit components including a voltage regulation and sensing component 905, a pulse regeneration component 906, a sawtooth wave generator component 907, and an off-time end clock generator component 908. Each of the first current source 901 or the second current source 902 can be disabled from providing current, which is controlled by an independent safety detection circuit in the pulser module 112.

[0078] Specifically, the voltage regulation and sensing component 905 is configured to convert the line high voltage to a voltage level compatible with the electronic logic components (eg, sensing components).

[0079] The pulse regeneration component 906 acts as a comparator circuit together with the sawtooth wave generator component 907 and is configured to regenerate the on-time switching signal (OT_CLOCK) and the on-time ramp signal (ON_RAMP) from the transmission line.

[0080] The off-time end clock generator component 908 is configured to generate a pulse EOF_CLK at the end of the off-time period, the pulse EOF_CLK being determined by (eg Fig.10 ) fault detection logic latches 1003 and 1005 are used.

[0081] Fig.10 An exemplary circuit diagram of a circuit 1000 that may be included in the pulser module 112 is shown. The circuit 1000 includes components and / or mechanisms for detecting an unsafe condition and generating a detection signal when a “Touch” or “Disconnected” condition is detected on the transmission line 102.

[0082] The circuit 1000 includes an off-voltage sensing component 1001, which includes a dedicated voltage divider block for converting the line high voltage to a voltage level compatible with the electronic logic component. The off-voltage sensing component 1001 is used to assist in fault detection operations during the off-time of transmitting pulse power on the transmission line 102. The off-voltage sensing component 1001 also extends the off-time voltage and "cuts off" the on-time voltage.

[0083] The circuit 1000 includes a touch threshold comparator 1002, which is configured to compare the disconnection transition sensing voltage of the disconnection voltage sensing component 1001 with a predetermined threshold value V T When the input is higher than the threshold V T When the touch threshold comparator 1002 is at a logic level "high". The output is coupled to a logic latch 1003 so that at the end of the off time, if the transmission line 102 is in an unsafe condition (e.g., a line touch is detected), the logic latch 1003 will create a logic level "low" latch signal. When the line voltage is below a predetermined safe touch voltage level (e.g., below 60V) as detected by the VMINOK signal (e.g., voltage minimum normal is equivalent to 60V), the circuit 1000 remains at a logic level "high" (i.e., safe).

[0084] The circuit 1000 includes a disconnection threshold comparator 1004 configured to compare the disconnection transition sensing voltage from the disconnection voltage sensing component 1001 with a predefined threshold value V C When the input voltage is higher than V C The output of the disconnect threshold comparator 1004 will be logic “low” when the input voltage is below V C , the output of the disconnect threshold comparator 1004 will be logic "high". The output of the disconnect threshold comparator 1004 is then latched by the logic latch 1005 at the end of the disconnect time. If the transmission line 102 is detected to be disconnected from the load (converter), the latch output will remain at a logic "low" (i.e., not ready / disconnected). Otherwise, the latch output will remain at a logic "high" (ready / connected). Therefore, when the line voltage is below a safe touch (e.g., below 60V) as detected by the VMINOK signal, the circuit 1000 remains at a logic "high" level (i.e., safe).

[0085] Fig.11 An exemplary circuit diagram of a circuit 1100 that may be included in the pulser module 112 is shown. The circuit 1100 includes components and / or mechanisms for generating a signal that indicates that the on-time is too long at the end of a cycle for use in various portions of the safety detection circuit. Although the described embodiments are described as measuring both the on-time and the off-time as the cycle, other embodiments are also contemplated in which the cycle is measured from the on-time to the subsequent on-time (e.g., from the rising edge of the on-time to the rising edge of the subsequent on-time).

[0086] The circuit 1100 includes a sawtooth wave generator 1101, which is triggered by the off-time end clock generator and is configured to discharge the RC circuit at the end of the off-time. The voltage level of the output from the sawtooth wave generator 1101 reflects the time of the entire cycle. The circuit 1100 also includes a cycle exceeding maximum threshold detector 1103, which is configured to transition to a "low" logic level when the cycle is too short (for example, a problem with the system clock causes a longer pulse period).

[0087] The circuit 1100 further includes an on-time exceeding maximum threshold detector 1105 triggered by a ramp signal generated by the on-time RC circuit. The detector 1105 is configured to detect when the input voltage exceeds a predefined threshold V T 102, which corresponds to an excessively long on-time duration. The output of detector 1105 is coupled to logic latch 1106, wherein logic latch 1106 is configured to maintain logic latch 1106 at a "high" logic level (i.e., safe) when the line voltage is below 60V as detected by the VMINOK signal. Due to the possibility of increasing duty cycle, the detection may indicate an overvoltage condition on transmission line 102. In all cases, the detection indicates a system timing error, in which case logic latch 1106 can be configured to maintain circuit 1100 at a "low" logic level (i.e., a fault is detected).

[0088] The circuit 1100 also includes an end-of-on-time clock generator 1104 configured to generate a positive edge near the end of the on-time period.

[0089] Fig.12 An example circuit diagram of a circuit 1200 is shown that includes components and / or mechanisms for generating a signal indicating when the line voltage exits the maximum allowed voltage present on the line and a signal indicating that the line voltage is exiting a safe touch voltage (e.g., 60 V). The circuit 1200 can be used in different parts of a safety detection circuit included in the pulsed power delivery system 100.

[0090] The circuit 1200 includes an on / off voltage transition sensing component 1201 including a dedicated voltage divider block configured to convert the line high voltage to a voltage level compatible with electronic logic components (eg, 3.3V, or approximately 3.3V).

[0091] The circuit 1200 also includes an overvoltage detection component 1202 that is configured to go low when the line voltage is above the maximum allowed voltage (e.g., 385V, or approximately 385V). The output of the overvoltage detection component 1202 is latched into a logic latch 1204 at the end of the on-time period to generate a logic "low" signal when this condition occurs. When the line voltage is below 60V, as detected by the VMINOK signal, the circuit remains at a "high" logic level (i.e., safe).

[0092] The circuit also includes a high voltage detector component 1203, which is configured to go "high" to enable the safety detection circuit system when the line voltage exceeds the safe touch voltage (e.g., less than 60V). The circuit 1200 remains active during the off-time period, which occurs after the on-time period exceeds the safe touch voltage (e.g., 60V).

[0093] Fig.13 An exemplary circuit diagram of a circuit 1300 that may be included in the pulsed power pulser module 112 is shown.

[0094] Circuit 1300 includes a Match IO (MIO_NORMAL) detector latch 1301 that latches the level of a master timing PWM signal generated by the control system at the start of an on-time as detected from transmission line 102. If the master timing PWM signal is not high when transmission line 102 is detected going high, the output of latch 1301 will go low indicating a fault.

[0095] Fig.14 An exemplary circuit diagram of a circuit 1400 including circuitry and corresponding integration of fault signals analyzed by redundant circuits in the pulser module 112 is shown.

[0096] As discussed, the pulser module 112 may be configured to generate Fig.14 The following fault detection signals are shown: NO_TOUCH signal 1401, CONNECT signal 1402, VMAXOK signal 1403, ON_OK signal 1404, PERIOD_OK signal 1405, and MIO_OK signal 1406. When an unsafe condition is detected, one or more of these six fault detection signals will go low. The unsafe condition forces the output of latch 1410 to go low, which disables the corresponding switch and transmits a "high" signal to the MCU.

[0097] Each of the detection signals also reaches the MCU through its corresponding resistor 1421-1426 for error reporting. Resistors 1421-1426 are large enough so that the MCU cannot change the logic level presented at the input of AND component 1411. The activation of latch 1410 will start a delay of 3 to 5 seconds in fault clearing logic 1412. This output will time latch 1410, and if all detection signals become "high" (i.e., inactive state), the fault condition will clear. Although any detection signal is activated, the fault condition will remain.

[0098] The circuit 1400 also includes a power-on delay component 1413, which is configured to block the forced instantaneous clearing of the latch 1410 when turned on. The fault reset switch can also manually force a clear signal to the latch 1410. The circuit 1400 also includes a delayed end pulse component 1414, which is configured to convert the power-on delay signal into a pulse signal instead of a continuous logic high or logic low signal.

[0099] The circuits described here are fully redundant, meaning they can be copied. signal shaping

[0100] In the field of power electronics, switching high voltage signals on and off to control current or voltage in a power transmission line can be applied in certain implementations of packet-based power transmission applications (i.e., NEC Class 4 power supplies), which is a solution provided by the pulsed power delivery system 100. Here, the voltage is switched on and off at certain fixed intervals. The off time can be used to detect the state of the power transmission line 102.

[0101] The fundamental frequency of switching power between on-time and off-time can be in the low frequency range, however, depending on the period, slope of the transition and amplitude of the switching voltage, there is a chance of introducing high frequency spectrum / harmonics. This phenomenon is best understood as a Fourier spectrum representation of a trapezoidal clock signal.

[0102] The power transmission line is usually selected based on the rated current capacity and rated voltage level, therefore, the impedance of the cable is not necessarily matched to the high frequency (HF) impedance of the source and the HF impedance of the load. The HF impedance of the source and load is characterized as the source impedance and the power load impedance at the transition time. If the HF impedance does not match the power transmission line, reflections can be generated. Fig.15 As shown in the exemplary power system 1510 in FIG. 1 , a reflected signal in a power transmission line may travel back and forth multiple times between a power source 1511 and a powered sink 1512 (ie, a load) until the reflected signal is attenuated, which is undesirable on the transmission line.

[0103] Fig.15Also included is a corresponding exemplary pulsed power signal 1520, which outlines the expected pulsed signal in dashed form and also superimposes undesired signal reflections in solid form that may actually be generated by the power system 1510. Such reflections manifest as ringing, standing waves, and overshoots, as shown in the pulsed power signal 1520. This can result in high voltage spikes that can have damaging effects on installed equipment and / or create EMI / EMC issues. As shown in the pulsed power signal 1520, the actual signal propagating on the power transmission line has ringing and overshoots at the transition times and is different from the expected (ideal) signal. The propagation time of the reflected signal on the power transmission line determines the frequency content that forms the ripple signal.

[0104] Signal smoothing solutions are described herein that can eliminate or at least significantly reduce such overshoot phenomena and, therefore, reduce the undesirable negative effects resulting therefrom. Although the signal smoothing solutions are described as being applied to pulsed power signals generated by the pulsed power delivery system 100, the signal smoothing solutions can also be more broadly applied to other systems and different applications, such as, for example, motor control that may or may not use pulsed power.

[0105] By changing the slope of the switching signal at the transition time (e.g., rise and fall time), the reduction of the high frequency components of the switching signal and / or the reduction of the high harmonics of the switching signal can be achieved. Fig.17A ) to control the slope of the transition without additional power loss. This will be achieved by generating a higher rate switch control signal with a varying duty cycle at the transition time, incorporating a smoothing circuit at the output of the switcher. The higher rate of the switch control signal can be achieved in terms of a variable frequency with a varying duty cycle.

[0106] Fig.16 An exemplary simplified system diagram of a switch control system 1600 for generating pulsed power is shown, wherein the switch control system generates a switching power signal that can cause ripple and / or overshoot (hereinafter referred to as signal defects) on a power transmission line at a transition interval. The switch control system 1600 includes a switch control component 1603 located on a power transmission line 1602 supplied by a DC voltage source 1601. Also included is a Fig.16 16 is an exemplary control signal 1620, which illustrates the timing of the control signal 1620 used to control the opening and closing of the switch control component 1603. Fig.16Detailed Description of the Invention 1630 is an exemplary voltage power signal 1630 generated by the switch control system 1600, wherein the voltage power signal 1630 is shown to include undesirable signal defects 1631, 1632 at the beginning of a pulse (see signal defect 1631) and at the end of a pulse (see signal defect 1632).

[0107] Fig.17A An exemplary system diagram of a switch control system 1700 is shown, which now includes a smoothing circuit 1704 according to the current solution. The switch control system 1700 includes a switch control component 1703 located on a power transmission line 1702 supplied by a DC voltage source 1701. In addition to these power pulsing components, the switch control system 1700 additionally includes a smoothing circuit 1704 (i.e., a high voltage integrator). Unlike the pulsed power signal 1520 described earlier that simply goes high and then low for controlling the pulse power cycle, the smoothing circuit 1704 is configured to control the switch control signal 1720 so that the control switch control signal 1720 itself is pulsed multiple times (e.g., a predetermined number of times) when the control switch control signal 1720 rises and falls. This is achieved by pulsing the switch control component 1703 multiple times at the rising edge 1740, and pulsing the switch control component 1703 multiple times at the falling edge 1750. This results in modulating or shaping the rising and falling edges / portions of the overall switch control signal 1720, which is a shortened activation power signal 1745. For example, the overall switch control signal 1720 may be high or have an on-time of approximately 2 ms, with the rising edge 1740 of that time being approximately 50 μs, and the falling edge of that time being approximately 50 μs. Thus, in this embodiment, signal smoothing on the rising and falling edges comprises 5% or less of the overall pulse, with each comprising 2.5% or less of the overall pulse.

[0108] The length of time that the pulse is implemented in the rising edge 1740 and / or the falling edge 1750 can be adjusted to be longer or shorter (e.g., a predetermined length of time). For example, based on external factors (such as known physical characteristics of the transmission line cable), the time that the pulse is implemented in the rising edge 1740 and / or the falling edge 1750 can be adjusted to a longer or shorter amount of time (e.g., a predetermined amount of time).

[0109] As shown in the enlarged view of the rising edge 1740 portion of the switch control signal 1720, the rising edge 1740 includes a plurality of individual pulses 1741-1744. Although four pulses 1741-1744 are shown, in alternative embodiments, the number of pulses may be more or less than as shown. Fig.17A In addition, each subsequent pulse 1741-1744 is Fig.17A1741-1744 are equal in duration. The pulses in the falling edge 1750 may mirror the pulses in the rising edge 1740. Although both the rising edge 1740 and the falling edge 1750 are shown as including pulses, according to some embodiments, the pulses may be included in only one of the rising edge 1740 or the falling edge 1750. Also, although the pulses in the rising edge 1740 are shown as lasting approximately the same amount of time as the pulses in the falling edge 1750, according to some embodiments, the pulses may last for different amounts of time. For example, the rising edge 1740 may last for a period of time or a number of pulses that is less than or more than the duration of the falling edge 1750 or the number of pulses that last.

[0110] like Fig.17A As shown in the voltage signal 1730 in FIG. 1 , the voltage signal 1730 generated by the signal shaping / smoothing solution has a smoother rising edge, and no ripple and / or overshoot signal defects 1631 are found in the voltage power signal 1630 .

[0111] Different embodiments of the switch control signal 1720 controlled by the smoothing circuit 1704 can be adjusted based on the known physical characteristics of the transmission line cable. Therefore, the current solution of the smoothing circuit 1704 can detect the cable type, including one or more cable attributes, and select a specific signal shaping solution to match the detected cable type. The cable type can be detected based on the load characteristics of the cable, and the selected signal shaping solution will be optimized for the load characteristics of the specific type of cable. The cable attributes can also be input by the user so that the pulser module 112 determines the best signal shaping solution based on the received cable attributes.

[0112] Fig. 17B An exemplary flow chart 1760 is shown that describes a process for implementing the signal shaping solution described herein. The process is implemented, for example, by a pulser module 112 included in the pulsed power delivery system 100 .

[0113] At 1761, cable properties of a cable used as the transmission line 102 are collected. The cable properties may be collected according to any of the methods described herein. For example, the cable properties may be detected based on a load characteristic of the cable, which may be determined after a load detection test performed on the transmission line 102. The cable properties may be manually input into the pulse power delivery system 100. The cable properties may be looked up from a database, in which a user enters a cable identification, and the pulse power delivery system 100 looks up the cable identification in a database storing cables and their corresponding properties. Then, when a match is found from the database, the corresponding cable properties may be obtained. The cable properties may include one or more of the following: characteristic impedance, capacitance, inductance, DC impedance, AC impedance, or other measurable cable properties.

[0114] At 1762, the pulser module 112 may select a custom signal shaping solution based on the previously detected cable properties. In this way, the signal shaping of the switch control signal may be adjusted to suit the particular cable used as the transmission line 102. These adjustments may be in accordance with any one or more of the adjustments described herein. Alternatively, when no cable properties are specifically detected, or when a default signal shaping is selected to be applied, a default signal shaping may be selected.

[0115] At 1763 , the switch control signal previously selected at 1762 is generated and applied to the switch control components in the pulsed power delivery system 100 . RF data link on high voltage conductor pair

[0116] Pulsed current (i.e., fault-managed power distribution) is a method for transmitting and delivering high power (e.g., Class 4) in a more efficient and safe manner, where in the event of a fault (e.g., cable distribution), the power is momentarily disconnected. Pulsed current (PC) is a non-continuous direct current in which the direct current is divided into on / off intervals and a fault condition is tested in each interval before other pulses can be transmitted. PC power can be transmitted on copper conductor pairs, the same as DC power. When a fault is detected on the transmission line, the pulsed power delivery system (e.g., pulsed power delivery system 100) can be configured so that the control pulses stop immediately. This makes the copper conductors safe to touch, thereby simplifying installation procedures (e.g., no cable conduit required, no certified electrician required, etc.), and also reducing deployment time and cost.

[0117] Additionally, unlike AC power, PC power allows for centralized power management and distribution, power metering, and power backup without the need for cable conduits. Compared to Class 2 DC power (e.g., ESLV power, PoE, etc.), PC power is high voltage Class 4 power (e.g., up to 400V DC) that delivers more power over longer distances while also having the benefit of using thinner copper conductors. Some of the benefits of using thinner copper conductors can include reduced weight, reduced cost, space savings, easier installation, to mention some of the benefits of thinner wires.

[0118] As described, the pulse power delivery system 100 provides Class 4 PC power by repeatedly pulsing high voltage DC (i.e., 300V to 600V) on and off in a periodic manner for a predefined pulse duration. Before transmitting another high voltage pulse, a fully redundant and independent fault detection circuit system using independent hardware will check the transmission line 102 for one or more fault events, including but not limited to: cable touch or short circuit, cable disconnection, undervoltage, overvoltage, pulse timing deviation, or the presence of unsafe voltage during the disconnect time.

[0119] In addition to the features described above, the pulse power delivery system 100 also includes features for superimposing low data rate communication signals on the same transmission line 102 to provide a solution for system management, control, and data reporting of a scalable and manageable PC power distribution system. To achieve these features, various technologies and methods can be integrated to provide an RF (radio frequency) communication link over a high voltage single pair cable for PC applications such as the pulse power delivery system 100.

[0120] Fig.18 Another depiction of a pulsed power delivery system 100 is shown, wherein Fig.18 , the pulser module 112 is shown transmitting the pulsed power signal to the pulsed power converter 120 on the transmission line 102. The pulsed power delivery system 100 may include up to 12 pulser modules 112 that transmit on 12 PPP channels in a point-to-point manner through 12 single-pair transmission lines 102. The closed system can be expanded to connect with more closed systems under a centralized management point.

[0121] Fig.19 An exemplary pulsed power delivery system 1900 built on the architecture of the pulsed power delivery system 100 is shown. The interconnection between the pulser module 112 and the pulsed power converter 120 may be limited to the following: Fig.18 The pulse power delivery system 100 shown in the figure provides a point-to-point connection topology, but can also be modified to be used in a Fig.19Multiple pulse power converters 120 are coupled in a daisy chain topology as shown. In the exemplary pulse power delivery system 1900, a single pulser module 112 is configured to drive up to n PPC (pulse power converter) channels to connect to n pulse power converters 120-1 to 120-n, where n is an integer of 1 or greater. This may be achieved by daisy chaining n number of pulse power converters 120-1 to 120-n to a common transmission line 102. Each PPC channel may be addressed using a unique address assigned via an RF communication link at startup of the pulse power delivery system 1900.

[0122] Fig. 20 Another exemplary pulsed power delivery system 2000 built on the pulsed power delivery system 100 architecture is shown, wherein the pulsed power delivery system 2000 supports several PPC channels 2001, 2002, 2003, which are the outputs of multiple unique pulsed power converters 120-1, 120-2, 120-n, where n is an integer of 1 or greater. Each of the pulsed power converters 120-1, 120-2, 120-n is supplied with its own pulsed power signal from the corresponding pulser module 112-1, 112-2, 112-n, respectively. The PPC channels 2001, 2002, 2003 are combined into a combined output signal 2004 to support higher output power. To achieve the combination of multiple PPC channels 2001, 2002, 2003, the pulse power delivery system 2000 includes an integrated power combiner circuit 2010, which uses n controlled output switches, n reverse current / polarity blocking / protection controllers, n load sharing controllers, and a complex load startup algorithm. The load device is then configured to connect to the combined output signal 2004.

[0123] Fig.21 2 shows the system architecture of an exemplary single-channel pulsed power system 2100, in which the pulser module 112 is directly coupled to the pulsed power converter 120 via the single-channel transmission line 102. Fig.21 The system architecture shown incorporates the necessary subsystems to superimpose high voltage power and RF communication data over the pulsed transmission line 102 .

[0124] The pulser module 112 includes a pulser component 2106 (e.g., which may represent a combination of a pulser module and a power supply), wherein the pulser component 2106 is configured to take high voltage DC power (e.g., ±150V to ±200V) and split it into on / off intervals (e.g., 2ms on / 1ms off) to produce a pulsed power train on the transmission line 102. The output of this block is controlled by the redundant safety circuitry described herein (e.g., safety circuitry 400).

[0125] The train generated by the pulser component 2106 is fed to a high voltage / high power common mode rejection filter (CMRF) 2107. The CMRF 2107 provides near zero attenuation at the pulse power switching frequency (e.g., 333 Hz) and transitions to higher attenuation in a wide band at higher frequencies. The CMRF 2107 is configured to have a peak attenuation of 50 dB at the RF communication carrier frequency. This CMRF 2107 is used to prevent any in-band switching harmonics from intermodulating with the modulated RF signal.

[0126] The output of CMRF 2107 is fed into a high voltage / high power, very narrow band resonant bandstop filter (BSF) 2108. BSF 2108 is composed of high power and high voltage resonant inductors and capacitors to provide very high characteristic impedance (notch) at the RF communication carrier frequency and very low impedance in other cases. Without this BSF 2108, the RF signal will be shunted by electromagnetic interference (EMI) and the large capacitance capacitor on the left side of BSF 2108.

[0127] The RF communication signal is a half-duplex signal transmission modulated and demodulated in the RF communication unit 2110. The input and output of the RF communication unit 2110 are differential signals connected to a differential, high voltage, wideband, resonant bandpass filter (BPF) 2109. The BPF 2109 is composed of a high power and high voltage resonant inductor and an X1Y1 capacitor, which is used to provide a 3KV reinforced isolation barrier between the main circuit (HV) and the secondary circuit (LV) and to block the DC component so that only the low voltage, high frequency components in the filter band can be seen by the RF front end of the RF communication unit 2110. Fig.21 A specific system architecture for the RF communication unit 2110 is depicted in FIG.

[0128] Circuit system component 2111 and circuit system component 2112 provide synchronization signals for the data modulator / encoder and demodulator / decoder of RF communication unit 2110. The high voltage pulse current (PC) is first converted to a low voltage by a resistor network. The X1Y1 capacitor is used to provide 3KV reinforced isolation between the primary circuit (HV) and the secondary circuit (LV) within circuit system component 2111. The low voltage, isolated signal at the output of circuit system component 2111 represents a logic level pulse signal, which is used to generate reference signals for rising and falling edges in circuit system component 2112 and fed to RF communication unit 2110.

[0129] The RF communication signal at 1 MHz carrier frequency is superimposed on the 333 Hz HV pulse current at the transmission line 102. The 1 MHz carrier frequency is experimentally selected because average cable insertion losses up to 1 MHz are acceptable to compensate for the up to 50 dB attenuation caused by the 2 KM long cable and at the same time stay away from the dominant power switching frequency harmonics below 800 kHz.

[0130] The PPC in the transmission line 102 uses the same architecture / components as the BSF 2128, RF communication unit 2120, circuit system component 2121, and circuit system component 2122 included in the pulse power converter 120. The high voltage / high power common mode rejection filter (CMRF) 2123 provides near zero attenuation at the PP switching frequency (i.e., 333 Hz) and transitions to higher attenuation within a broadband at higher frequencies and around the harmonics of the DC-DC phase shift converter switching frequency in the converter circuit system component 2124. The CMRF 2123 is designed to have a peak attenuation of 50 dB at the RF communication carrier frequency. The CMRF 2123 is important to prevent any in-band switching harmonics generated by the converter circuit component 2124 from intermodulating with the RF signal. The converter circuit system 2124 converts the PC to a DC voltage that is fed back to the DC bus of the phase-shifted, full-bridge DC-DC converter. The output of the converter circuit system component 2124 is fed to a load device (e.g., load device 523). In this manner, the RF communication unit 2110 may communicate over the transmission line 102 to synchronize to the period of the pulse power signal by using circuitry components such as band-stop and band-pass filters.

[0131] As mentioned above, Fig. 22 A more detailed system diagram including components of the RF communication unit 2110 subsystem is shown. The RF communication unit 2110 is connected to the BPF 2109 using bidirectional communication through the differential RF front end 2201. The current compensated common mode rejection filter (CMRF) 2215 blocks common mode interference caused by high power DC-DC switching converters from entering the differential RF front end 2201. This is designed to provide a common mode impedance of 10KΩ to 15KΩ and a near zero differential impedance within the RF communication band.

[0132] The RF communication unit 2110 also includes an impedance matching network 2216, which can be tuned to match the transmission line impedance according to the characteristic impedance of the cable used in the transmission line 102 and the number of multiple branch points connected to the bus in the daisy chain use case. The impedance matching network 2216 also includes an RF limiter and provides capacitive coupling between the CMRF 2215 and the band pass filter (BPF) 2217.

[0133] BPF 2217 can be an 8th order Butterworth-Bessel 0.5, 200kHz passband, 1MHz center frequency active bandpass filter designed to provide 40dB to 48dB of in-band attenuation over the full range of signal strength (i.e., ±5mV to ±200mV) to remove any frequency components outside the RF communication signal band. BPF 2217 can be designed to have less than 220u Vrms noise, 800nV / √Hz spectral noise density at 1MHz, less than 7us group delay, and fast step response.

[0134] The RF communication unit 2110 may also include an amplifier 2218, wherein the amplifier 218 may be a multi-stage fully differential input demodulating logarithmic amplifier with a very fast voltage mode output. The amplifier 2218 may use a coherent detection technique to provide a very high dynamic range. The unique integration of all filtering at this stage and the front end allows the pulse power delivery system 100 to provide a demodulated output with up to 50 dB insertion loss on the cable of the transmission line 102. The single-ended output from the amplifier 2218 is fed to the RF detector 2219, wherein the RF detector 2219 is used to generate a demodulated output, which is represented as the envelope of the amplified input signal.

[0135] The demodulated signal from the RF detector 2219 is fed to a self-biased discriminator 2220, which includes a time-varying delay for providing a dynamic reference for the non-inverting input of a comparator in the pulsed power delivery system 100. The output of the discriminator 2220 is a digitized signal that is fed to a synchronous decoder 2221, which employs a bit-banging algorithm to decode the received data. The decoded data is analyzed and then stored in a memory storage device 2222 (e.g., a memory unit that may include a database).

[0136] For data transmission, binary data is fed from memory storage device 2223 (e.g., memory storage device 2223 may be the same as or different from memory storage device 2222) to encoder / modulator 2224. Encoder / modulator 2224 encodes the binary data from memory storage device 2223 and generates the corresponding baseband frequency (fm) and carrier frequency (fc) in digital form. The two outputs from encoder / modulator 2224 are synchronized to the rising edge of the pulse reference signal received from circuit system component 2112 before they are fed to digital intra-modulator 2225. The output of digital intra-modulator 2225 is then fed to a unidirectional, differential digital line driver 2226.

[0137] The RF communication unit 2110 may also include a differential high-Q resonant bandpass filter (BPF) 2227. The BPF 2227 has a narrowband tuned to the modulation frequency band. The output of the BPF 2227 is a balanced CW modulated RF signal connected to the impedance matching network 2216. During the data transmission cycle, the driving impedance of the transmitter will apply the impedance of the impedance matching network 2216. Meaning that the driving impedance is always fixed and lower than the detection impedance in the listening mode. Once the transmission cycle is completed, the line driver will be disabled and the RF communication unit 2110 will return to the detection mode impedance (i.e., listening mode).

[0138] Fig.23 An exemplary timing diagram 2310 is shown illustrating the timing of a periodic pulsed power signal 2312 and the transmission of data packets in a data signal 2311 over an RF communication link. Fig.23 Also shown is an exemplary data packet 2302 that may be included as part of a data signal 2311 for transmission via an RF communication link on transmission line 102. Encoding of the data by encoder / modulator 2224 and decoding of the data by decoder 2221 may be implemented to generate data such as Fig.23 The fixed data packet 2302 shown is as follows: - Start bit: Provides known power transmission line (PTL) state and initial identification. - Address bits: Indicates the remote node in both point-to-point or multipoint communication links. -Payload: The data transmitted. -CRC: Data transmission error detection. In the encoding / modulation implemented by encoder / modulator 2224, 8-bit words of data are mapped into 10-bit symbols to achieve DC balance and limited variance while providing sufficient state changes to allow reasonable clock recovery.

[0139] Depending on the characteristic impedance of the cable, whether more inductive or more capacitive, the on / off transition on the transmission line 102 can create a very low impedance state that shunts the RF signal for a very short time during the transition, which will change the "high" logic to "low" logic over a few bits. The current solution solves this problem by inserting an image of the 10-bit mapped symbol after each 10-bit symbol, thereby providing a simple and effective way of error correction for the data packet 2320. The image portion of the data bit is depicted in the data packet 2320 by underscore and prime notation.

[0140] The decoding / demodulation stage operated by decoder 2221 will parse the data, and each 10-bit code element is compared (cross) with its corresponding image for error correction. Even if all bits in the word are changed, the original word can still be recovered. The worst case occurs when the last 5 bits of the 10-bit code element and the first 5 bits of the 10-bit code element image are all changed. Even in this case, the original data can still be recovered because the last 5 bits of the 10-bit code element image are still not changed and can be used to correct the last 5 bits of the 10-bit code element. This scheme allows bit error correction to be performed for changes up to 10 bits. Now, if more than 10 bits (i.e. the entire word) are damaged, CRC will detect this error, and will request data retransmission to ensure that the damaged data will not be used incorrectly.

[0141] The length of the payload can be adjusted based on the on / off interval. Fig.23 In the illustrated data packet 2320, the data packet structure is a 2.00 ms on-time period and a 1 ms off-time period. In this case, the payload can accommodate 120 bits, which represent 6 data bytes, which are mapped to 10-bit symbols with their corresponding images.

[0142] In a point-to-point topology (see e.g., Fig.18 ) and / or daisy chain topology (see, e.g., Fig.19 ), the pulsed power delivery system 100 uses only a single pulser module 112 that switches on / off, alternating bits for data error correction. However, when multiple pulser modules 112 are shared for a multi-pair cable (e.g., a three-pair cable), crosstalk between pairs (e.g., crosstalk due to capacitive coupling) can also alter the RF signal during the on / off transitions. This can become a compounding problem if the on / off transitions of the multiple pulser modules 112 are asynchronous, which can result in more than 10 bits being corrupted and, therefore, unable to be recovered.

[0143] To solve this problem, a master clock can be introduced to provide synchronization between the pulser modules 112 using the same multi-pair cables. In these cases, a time slot number is assigned to each pulser module 112. Then, based on the time slot number, the pulser module 112 will add a phase shift to the master clock to create a trigger for generating a pulse current (PC) to reference the output of the pulser component 2106 of each pulser module 112.

[0144] Fig.24An exemplary timing diagram 2400 is shown, which depicts three pulsed current signals (PC signals) 2401, 2402, and 2403 at the transmission line 102, wherein each of the PC current signals 2401-2403 is generated by the first pulser module 241, the second pulser module, and the third pulser module, respectively. Fig.24 The timing diagram 2400 shown shows a scenario where three pulser modules generating three PC signals 2401, 2402 and 2403 are synchronized. Each of the PC signals 2401, 2402, 2403 is phase-shifted by 120 degrees from each other, which corresponds to a "1 ms delay x time slot number" from the master clock. In this case, only two pulser modules are active at the same time (i.e., the time when the pulser modules are at logic "high" at the same time). The on / off transition is configured to occur every 1 ms.

[0145] Fig.25 An exemplary timing diagram 2500 is shown, which depicts nine pulse current signals (PC signals) 2501-2509 at the transmission line 102, wherein each of the PC signals 2501-2509 is generated by a corresponding pulser module. The nine PC signals 2501-2509 generated by the corresponding pulser modules are synchronized. For example, each of the nine PC signals 2501-2509 is phase-shifted by 40 degrees from each other, which corresponds to "0.333 ms delay x time slot number" from the master clock. In this case, six pulser modules are active at the same time (i.e., the time when the pulser modules are at logic "high" at the same time). The on / off transition is shown to occur every 0.333 ms.

[0146] This synchronization strategy of on / off transitions between several pulser modules has other advantages, including reducing stress on the main power supply, reducing EMI, and providing stable power consumption at the system level. For example, utilizing a synchronization strategy can minimize or at least reduce the number of pulser modules 112 that need to be turned on at the same time, which in turn reduces the power that needs to be drawn from the power supply at the same time, which reduces the stress on the power supply. Although the embodiment has three PC signals (see, for example, Fig.24 ) and having nine PC signals (see, e.g., Fig.25 ), but this synchronization strategy may be employed in other embodiments that include different numbers of pulser modules that generate PC signals for transmission over multiple pairs of cables.

[0147] Although specific embodiments described herein have been shown and described, it will be apparent to those skilled in the art that changes and modifications may be made without departing from the teachings of the features described herein. For example, a pulsed power delivery system may include different combinations of components described herein and still be within the scope of the present disclosure. In addition, although the fault detection, signal smoothing, or error detection features are described as being implemented on the pulser device, according to other embodiments, the fault detection, signal smoothing, or error detection features may be implemented as a software-centric solution executed by a management card. For example, a management card may include a memory storage device and a processor, the memory storage device being configured to store instructions for implementing the fault detection, signal smoothing, or error detection features described herein, the processor being configured to execute the instructions stored on the memory storage device to control components of the pulsed power delivery system to implement the fault detection, signal smoothing, or error detection features.

[0148] The matter set forth in the foregoing description and accompanying drawings is provided by way of illustration only and not limitation. The actual scope is intended to be defined by the following claims in their proper context.

Claims

1. A pulser device, comprising: A signal shaping component, wherein the signal shaping component is configured to: Generating a pulsed power signal by pulsing the power signal according to a periodic pulsing scheme, wherein pulses in the pulsed power signal include: a first signal smooth portion generated at a rising edge of a pulse of the pulse power signal; and A power delivery portion is generated after said first signal smoothing portion.

2. The pulser device of claim 1, wherein the first signal smooth portion comprises 2.5% or less of the pulse.

3. The pulser device of claim 1, wherein the first signal smoothing portion comprises a plurality of fast pulses for the rising edge of the pulse.

4. The pulser device of claim 1, wherein the plurality of rapid pulses for rising edges of the pulses comprises a predetermined number of pulses.

5. The pulser device of claim 4, wherein the predetermined number of pulses comprises at least four pulses.

6. The pulser device of claim 1, wherein the plurality of rapid pulses for rising edges of the pulses last for a predetermined length of time.

7. The pulser device of claim 6, wherein the pulse lasts approximately 2 ms and the plurality of fast pulses for the rising edge of the pulse lasts approximately 2.5 ms.

8. The pulser device of claim 1, wherein the pulser device is configured to generate the first signal smooth portion based on characteristics of the transmission line.

9. The pulser device of claim 1, wherein the pulse further comprises a second signal smoothing portion generated at a falling edge of a pulse of the pulse power signal.

10. The pulser device of claim 9, wherein the second signal smooth portion comprises 2.5% or less of the pulses.

11. The pulser device of claim 9, wherein the second signal smoothing portion comprises a plurality of fast pulses for the falling edge of the pulse.

12. The pulser device of claim 9, wherein the plurality of rapid pulses for the falling edge of the pulse comprises a predetermined number of pulses.

13. The pulser device of claim 12, wherein the predetermined number of pulses comprises at least four pulses.

14. The pulser device of claim 9, wherein the plurality of rapid pulses for the falling edge of the pulses last for a predetermined length of time.

15. The pulser device of claim 14, wherein the pulse lasts approximately 2 ms and the plurality of fast pulses for the falling edge of the pulse lasts approximately 2.5 ms.

16. The pulser device of claim 9, wherein the pulser device is configured to generate the second signal smooth portion based on characteristics of the transmission line.

17. The pulser device of claim 1, wherein the signal shaping component comprises an LC filter and a freewheeling diode.

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