Chip test fixture mainboard and chip test host

Abstract

The invention discloses a chip testing jig main board, the jig main board comprises a first area and a second area, and the first area is in extensible coupling with an extension testing circuit; the second area is arranged around the first area, and the second area is provided with a plurality of output interfaces used for establishing electric connection or signal connection with a to-be-tested chip. The chip testing jig mainboard has the advantages of being extensible, small in size, long in service life, good in compatibility of to-be-tested chip types, high in operability and the like, and the testing efficiency can be greatly improved while the testing quality can be guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of display chip testing, and in particular to a chip testing fixture mainboard and a chip testing host. Background Art

[0002] During the screen production process, the screen control chip needs to be tested to ensure that the screen control chip is in good condition when leaving the factory. The same manufacturer often produces a variety of different screens at the same time. Different screens have different control chips, and different control chips need to be tested separately. In addition, even if the same chip is used, different types of tests need to be performed. The chip under test needs to be connected to the test fixture mainboard through different interfaces or different protocols. An existing test fixture mainboard is limited to providing MCU interface (MCU-LCD interface, 8080 bus standard proposed by Intel, I80 can refer to MCU-LCD screen, MCU interface can be divided into 8080 mode, 6800 mode, etc.), SPI (Serial Peripheral Interface, serial peripheral interface), QSPI (Quad Serial Peripheral Interface, four-wire serial peripheral interface) interface forms; some test fixture mainboards only include MIPI-DPHY (MIPI Display Physical Layer, which is a physical layer of MIPI, and its protocols include CSI and DSI, CSI is used for image access, and DSI is used for image output) interface or RGB interface. The RGB interface is a digital signal interface between the display device and other devices, mainly used to transmit color images and video signals. The RGB interface is also called DPI (display pixel interface) interface.

[0003] The existing test fixture mainboard has the problems of single test performance, relatively single protocol interface, and difficulty in adapting to the many test requirements of different types of chips, which hinders the further improvement of test efficiency and cannot meet the needs of chip mass production testing. Moreover, the existing test fixtures are large in size, which is not conducive to building a simple, convenient and efficient test platform on a limited experimental table. In addition, most of the existing test fixtures are connected to the chip under test in the form of a pin interface. Such an interface is generally connected using a DuPont line during testing. The DuPont line will be damaged after multiple plugging and unplugging, which is difficult to meet the needs of chip aging testing. Furthermore, the DuPont line connection is unstable. If the DuPont line is used for testing on a large scale or for large-scale chip testing, it is easy to limit the accuracy of the test. Summary of the invention

[0004] The purpose of the present invention is to provide a chip test fixture mainboard, which has the advantages of being expandable, small in size, long in service life, good in compatibility with the chip types to be tested, strong in operability, etc., and can greatly improve the test efficiency while ensuring the test quality.

[0005] To achieve the above object, the present invention provides a chip test fixture mainboard, which comprises:

[0006] a first area, the first area being extendably coupled to an extended test circuit board;

[0007] The second area is arranged around the first area, and a plurality of output interfaces are arranged in the second area for establishing electrical connection or signal connection with the chip to be tested.

[0008] Optionally, the first area includes a first pin module, the first pin module is used to connect to an extended test circuit board, and the first pin module is used to provide a test signal transmission path for the extended test circuit board.

[0009] Optionally, a third pin module is provided in the first area, and the third pin module is used to be electrically connected to the extended test circuit board to supply power to the extended test circuit board, or to be used for communication between a chip test fixture mainboard and the extended test circuit board.

[0010] Optionally, a second pin module is further provided in the first area, and the second pin module is used to connect to the extended test circuit board, and the second pin module is used to receive a frequency detection signal transmitted by the extended test circuit board.

[0011] Optionally, the first pin module includes multiple groups of first pins, and the third pin module includes multiple groups of third pins respectively, the multiple groups of first pins are arranged along the first direction, and the multiple groups of third pins are arranged along the second direction.

[0012] Optionally, relative to the first pin module, the second pin module is closer to the middle area of ​​the first area.

[0013] Optionally, a plurality of binding holes are provided in the first area, and the plurality of binding holes are used to fix the extended test circuit board.

[0014] Optionally, three binding holes are provided in the first area, and the three binding holes are located on non-straight lines.

[0015] Optionally, the three binding holes and the first pin module, the second pin module, and the third pin module are roughly located on the rectangular periphery of the first area.

[0016] Optionally, a plurality of packaging interfaces are provided in the second area, and the packaging interfaces are used to be directly or indirectly coupled to a furnace plate of the chip to be tested through transmission lines.

[0017] Optionally, the packaging interface includes an HDMI cable interface, a DuPont cable interface, or a coaxial cable interface, or a combination of any of the foregoing interfaces.

[0018] Optionally, the packaging interface includes an LCD driver IC coaxial line interface and / or an LCD driver IC DuPont line interface; or / and, a MIPI-DPHY output HDMI line interface and / or a MIPI-DPHY output DuPont line interface; or / and, a MIPI-CPHY output HDMI line interface and / or a MIPI-CPHY output DuPont line interface.

[0019] Optionally, the LCD driver IC coaxial cable interface, LCD driver IC DuPont line interface, MIPI-DPHY output HDMI line interface, MIPI-DPHY output DuPont line interface, MIPI-CPHY output HDMI line interface, and MIPI-CPHY output DuPont line interface are arranged in the lower part of the second area of ​​the test fixture mainboard.

[0020] Optionally, a memory card slot is provided in the second area.

[0021] The present invention also provides a chip testing host, including the chip testing fixture mainboard as described above, or including the chip testing fixture mainboard as described above and an extended testing circuit board.

[0022] In summary, compared with the prior art, the chip test fixture mainboard provided by the present invention has the following beneficial effects:

[0023] The chip test fixture mainboard of the present invention has the advantages of being expandable, small in size, long in service life, good in compatibility with the chip types to be tested, strong in operability, etc., and can greatly improve the test efficiency while ensuring the test quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The schematic diagram of the chip test fixture mainboard of the present invention includes a first area.

[0025] Figure 2 It is a schematic diagram of a chip test fixture mainboard including a second area of ​​the present invention.

[0026] Figure 3 It is a schematic diagram of the control circuit of the chip test fixture mainboard of the present invention.

[0027] Description of reference numerals:

[0028] Chip test fixture motherboard 10

[0029] First Area 100

[0030] The first pin module 110

[0031] The second pin module 120

[0032] The third pin module 130

[0033] Binding hole 140

[0034] Second area 200

[0035] Power switch 210

[0036] Test display control module 220 of the chip under test

[0037] Memory card slot 230

[0038] Drive control integrated interface 240

[0039] LCD driver IC coaxial cable interface 241

[0040] LCD driver IC Dupont line interface 242

[0041] Host computer communication interface 250

[0042] Main power interface 260

[0043] Debug interface 270

[0044] MIPI-DPHY output HDMI line interface 281

[0045] MIPI-DPHY output Dupont line interface 282

[0046] MIPI-CPHY output HDMI line interface 291

[0047] MIPI-CPHY output DuPont line interface 292 DETAILED DESCRIPTION

[0048] The following will be combined with the attached embodiment of the present invention Figure 1 ~Attached Figure 3 , the technical solutions, structural features, objectives achieved and effects in the embodiments of the present invention are described in detail.

[0049] It should be noted that the drawings are in a very simplified form and use non-precise proportions. They are only used to conveniently and clearly assist in explaining the embodiments of the present invention, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention.

[0050] It should be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only the elements explicitly listed, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0051] like Figure 1 As shown, the present invention provides a chip test fixture mainboard 10, which includes a first area 100 and a second area 200. The first area 100 can be extended to couple an extended test circuit board. The extended test circuit board is mainly used to extend the various voltage, current, diode, resistance and other tests of the chip to be tested, while the test fixture mainboard 10 itself can independently complete a small part of the voltage and current tests. The most important thing is that the test fixture mainboard 10 can independently complete the point screen, so that the aging test of the chip to be tested can be independently completed. And through the combination of the test fixture mainboard 10 extended connection extended test circuit board, dozens or hundreds of categories of voltage, current, and even frequency, resistance and diode of the chip to be tested can be tested, such as the voltage or current test required by the common power supplies such as the 3 power supplies VSN, VSP, IOVCC, 2 power supplies VCI, IOVCC commonly used in LCD chips, and the power supplies commonly used in backlights, as well as a large number of external voltage tests, etc. In particular, by extending the connection of the test fixture mainboard 10 and the extended test circuit board, the electrical properties of the chip under test can be monitored using the extended test circuit board while performing the aging test, wherein the test fixture mainboard 10 can be, for example, a printed circuit board to provide the first area where the circuit can be arranged, and the second area.

[0052] Specifically, a first pin module 110, a second pin module 120 and a third pin module 130 are provided in the first area 100 of the chip test fixture mainboard 10, and the extended test circuit board is provided with socket modules respectively matching the first pin module 110, the second pin module 120 and the third pin module 130. By coupling the first pin module 110, the second pin module 120 and the third pin module 130 with the matching socket modules of the extended test circuit board respectively, the extended test circuit board can be coupled to the mainboard 10 to achieve spatial overlap of the two.

[0053] The first pin module 110 is used to connect to the extended test circuit board. The first pin module 110 is used to provide the voltage and current measurement modules (such as ADC modules for sampling voltage or current) of the extended test circuit board with the measured signals (such as the three power supplies VSN, VSP, IOVCC and two power supplies VCI, IOVCC, etc. commonly used in LCD chips) to facilitate the extended test circuit board to perform sampling tests on these measured signals. The first pin module 110 includes two rows of parallel pins. When the chip test fixture mainboard 10 works alone without an external extended test circuit board (there is no external extended test circuit board on the first pin module 110). The two rows of parallel pins of the first pin module 110 are short-circuited one by one, and the power supply circuit on the chip test fixture mainboard 10 can provide power to the power pins on the chip test fixture mainboard 10 through the first pin module 110 (DuPont line is also required), for example, the LCD driver IC DuPont line interface 242, the MIPI-DPHY output DuPont line interface 282, and the MIPI-CPHY output DuPont line interface 292 can all include power pins, so that power can be provided to the power pins included in the LCD driver IC DuPont line interface 242, the power pins included in the MIPI-DPHY output DuPont line interface 282, and the power pins included in the MIPI-CPHY output DuPont line interface 292. When an extended test circuit board is externally connected to the chip test fixture mainboard 10, the pins on the first pin module 130 are connected to the corresponding sockets on the extended test circuit board to achieve the connection between the first pin module 110 and the extended test circuit board. 。

[0054] The second pin module 120 in the first area 100 is used to connect to the extended test circuit board, and the second pin module 120 is used to receive the frequency detection signal transmitted by the extended test circuit board. Since there is no frequency detection processing module on the extended test circuit board, the chip test fixture mainboard 10 receives the frequency detection signal received by the frequency detection interface on the extended test circuit board through the second pin module 120, and transmits the signal to the FPGA (Field-Programmable Gate Array) on the chip test fixture mainboard 10 for signal processing. The chip test fixture mainboard 10 is connected to the extended test circuit board through the second pin module 120, and the chip test fixture mainboard 10 can receive the frequency detection signal to realize the frequency detection function. Optionally, the second pin module can be considered to be set or omitted depending on whether the detection is needed.

[0055] In addition, the third pin module 130 in the first area 100 is used to electrically connect to the extended test circuit board to supply power to the extended test circuit board, for example, to provide power to the extended test circuit board. In fact, all power supplies required by the extended test circuit board can be provided by the third pin module 130, and the SPI communication between the chip test fixture mainboard 10 and the extended test circuit board can also be completed through the third pin module 130. SPI communication can achieve full-duplex communication, and has the advantages of high speed and high flexibility.

[0056] The first pin module 110 includes a plurality of groups of first pins, and the third pin module 130 includes a plurality of groups of third pins, respectively. The plurality of groups of first pins are arranged along the first direction, and the plurality of groups of third pins are arranged along the second direction. In this embodiment, the first direction and the second direction are arranged perpendicularly. In other embodiments, the first direction may also be arranged at an angle to the second direction, which is not perpendicular to the first direction. The first pin module 110 and the second pin module 120 are arranged perpendicularly or at an angle to each other to improve the stability of the connection between the chip test fixture mainboard 10 and the extended test circuit board.

[0057] And relative to the first pin module 110, the second pin module 120 is closer to the middle area of ​​one side edge of the first area 100. Such a configuration can further provide stable support between the chip test fixture mainboard 10 and the extended test circuit board when the distance between the first pin module 110 and the third pin module 130 is large, thereby improving the stability of the connection.

[0058] In this embodiment, the pins in the first pin module 110, the second pin module 120 and the third pin module 130 are all small-pin pins. The use of small-pin pins can reduce the volume of the first pin module 110, the second pin module 120 and the third pin module 130, which is beneficial to the arrangement of each module in the first area 100 on the chip test fixture mainboard 10, and improves the utilization efficiency of the space in the first area 100.

[0059] In other embodiments, the pins in the first pin module 110 , the second pin module 120 and the third pin module 130 may also be large-pin pins. The use of large-pin pins helps to improve the signal transmission quality between the extended test circuit board and the chip test fixture mainboard 10 .

[0060] A plurality of binding holes 140 are provided in the first area 100, and the plurality of binding holes 140 are used to fix the extended test circuit board. The extended test circuit board is provided with connection holes corresponding to the binding holes 140. When the extended test circuit board and the chip test fixture mainboard 10 are connected through the first pin module 110, the second pin module 120 and the third pin module 130, the binding holes 140 and the corresponding connection holes are additionally connected by physical means to strengthen the connection strength between the chip test fixture mainboard 10 and the extended test circuit board, and improve the connection reliability between the chip test fixture mainboard 10 and the extended test circuit board.

[0061] Preferably, three binding holes 140 are provided in the first area 100, and the three binding holes 140 are located on non-co-straight lines and are distributed at the vertex angles of the boundary of the area where the first pin module 110, the second pin module 120, and the third pin module 130 are not distributed. The three binding holes 140 can further achieve a more stable connection on the basis of the stable binding provided by the first pin module 110, the second pin module 120, and the third pin module 130, thereby improving the coupling quality between the extended test circuit board and the mainboard. The coupling method of the binding holes proposed in the present invention in conjunction with the first pin module 110, the third pin module 130 (and the second pin module 120) can reduce the setting of the binding holes 140 in the first area 100, avoid space occupation caused by a large number of binding holes, improve the coupling quality, and improve the space utilization rate in the first area 100. In this embodiment, the three binding holes 140 are respectively located at the upper left corner, upper right corner and lower right corner of the first area 100, that is, the three binding holes 140 and the first pin module 110, the second pin module 120, and the third pin module 130 are roughly located on a rectangular periphery.

[0062] The lower left corner of the first area 100 is the combined layout area of ​​the corresponding test fixture mainboard. In this area, dense input and output lines are arranged. Not setting the binding holes 140 in this area is conducive to the uniform wiring layout of this area to avoid electromagnetic interference. The positions of the three binding holes 140 are set in the first area 100 in this way, which can cooperate with the first pin module 110, the second pin module 120 and the third pin module 130, and are evenly distributed on the entire peripheral edge of the first area 100, so as to achieve combined fixation at multiple positions and improve the stability of the test fixture mainboard binding the extended test circuit board.

[0063] like Figure 2 As shown, the second area 200 is arranged around the first area 100, and the second area 200 is provided with a plurality of interfaces for connecting with the signals of the chip to be tested. The second area 200 is provided with a combination of at least one or more of the following structures: a power switch 210, a test display control module 220 of a chip to be tested, a memory card slot 230, a drive control integrated interface 240 (preferably, the drive control integrated interface 240 includes an LCD driver IC coaxial line interface 241 (for example, it can support RGB (Red, Green, Blue, red, green, blue) + SPI, SPI, QSPI, MCU and other protocols), an LCD driver IC DuPont line interface 242 (for example, it can support RGB + SPI, SPI, QSPI, MCU and other protocols), a host computer communication interface 250, a main power interface 260 and a debugging interface 270, a MIPI-DPHY output HDMI line interface 281, a MIPI-DPHY output DuPont line interface 282, a MIPI-CPHY output HDMI line interface 291, a MIPI-CPHY output DuPont line interface 292, etc. Among them, the LCD driver IC coaxial line interface 241, the LCD driver IC DuPont line interface 24 2. The MIPI-DPHY output DuPont line interface 282 and the MIPI-CPHY output DuPont line interface 292 are coupled to the corresponding matching signal lines in the direction perpendicular to the plane on the mainboard, and the remaining interfaces in the second area are coupled to the corresponding matching structures in the direction perpendicular to the side surface of the mainboard, so that in the process of building the test platform, it is beneficial to the coupling and arrangement of the coupling structure (such as signal lines, etc.), so as to facilitate the construction of a neat and easy-to-operate test platform. Further, the LCD driver IC coaxial line interface 241, the LCD driver IC DuPont line interface 242, the MIPI-DPHY output HDMI line interface 281, the MIPI-DPHY output DuPont line interface 282, the MIPI-CPHY output HDMI line interface 291, the MIPI-CPHY output DuPont line interface 292, etc. are distributed in the lower half of the second area of ​​the test fixture mainboard. When the tester builds the test platform or performs a test, this part is closer to the direction of the tester's arms, which is more convenient for the tester to build the test platform and perform test operations and observe test results.

[0064] The interfaces of the package provided in the second area 200 are used to couple directly or indirectly with the furnace board of the chip to be tested through transmission lines. Considering the limitations of testing through Dupont lines, it can only meet general testing needs, such as some non-aging tests, low-volume chip tests, etc., while chip aging tests (RA (Reliability Test)) are an important test need for mass production of chips today. In the optional embodiment provided by the present invention, when setting the Dupont line interface, different (such as HDMI, RGB+SPI) interfaces are added for the same protocol.

[0065] The functions of the second region structure are described in detail below:

[0066] The power switch 210 is used to control the conduction or cut-off of the entire power supply of the host including the test fixture mainboard.

[0067] The host computer communication interface 250 may include a USB-FS (Full Speed) interface, a USB-HS (High Speed) interface, a DAP (Debug Access Port) interface, a JTAG (Joint Test Action Group) interface, etc., which are used for communication between the host and the host computer.

[0068] The main power interface 260 and the debugging interface 270 can be set adjacent to the top of the test fixture mainboard 10 together with the host computer communication interface 250 and other interfaces. The main power interface 260 is used to connect to the power required by the host (or test fixture mainboard), and the debugging interface 270 is used for debugging the host.

[0069] The test display control module 220 of the chip to be tested is used for human-computer interaction during the test of the chip to be tested. Preferably, for example, the following four function control buttons may be included: an "enter" button, and the "enter" button is used to control the continued execution of the initialization code. The "loop" button is used to control the loop refresh, the "up" button is used to flip up the previous picture, and the "down" button is used to flip down the next picture. The setting of these four function buttons can meet most of the test adjustment interaction needs, avoiding the complication of the host structure caused by setting more function keys. However, optionally, the present embodiment is not limited to this. In the case of further test adjustment needs, adaptive function buttons can be added to meet actual needs.

[0070] The memory card slot 230 is used to place a memory card, such as an SD card. By placing an additional memory card in the card slot, the memory card can be used for image storage. The image is first stored in the memory card by naming. During the power-on screen test, the functional module FPGA on the test fixture mainboard can convert the image in the memory card into a protocol and send it to the chip under test, which is conducive to greatly shortening the communication time required for the test.

[0071] The drive control integrated interface 240 may include an SPI interface, a QSPI interface, an MCU interface, an RGB interface, and the like. Preferably, the drive control integrated interface 240 is provided with an LCD driver IC coaxial line interface 241 and an LCD driver IC DuPont line interface 242. The functions realized by the LCD driver IC coaxial line interface 241 and the LCD driver IC DuPont line interface 242 are roughly equivalent. When applied, one of the interfaces can be selected to build a test platform. In particular, since the LCD driver IC DuPont line interface 242 is in the form of a pin module, the LCD driver IC coaxial line interface 241 is arranged to be located at the edge side of the second area 200 relative to the LCD driver IC DuPont line interface 242. This is more conducive to the LCD driver IC coaxial line interface 241 not being scratched by the pins of the LCD driver IC DuPont line interface 242 when it is connected to a longer coaxial line.

[0072] By providing the LCD driver IC coaxial line interface 241 and / or the LCD driver IC DuPont line interface 242, the host including the test fixture mainboard 10 can further expand the signal to provide a large number of chips for testing. For example, by extending the connection signal transfer fixture through the LCD driver IC coaxial line interface 241 or the LCD driver IC DuPont line interface 242, the signal transfer fixture can perform large-scale branching of the drive control signal of the display panel to achieve a host test of a large number of chips to be tested.

[0073] The LCD driver IC coaxial line interface 241 can be set up to use the coaxial line to transmit signals. The coaxial line can meet the needs of long-distance signal transmission and is more resistant to extreme environments such as high temperature and high humidity. It is more suitable for aging testing than DuPont lines. The LCD driver IC DuPont line interface 242 also has its own advantages. Since the LCD driver IC DuPont line interface 242 is a pin module made of a number of pins, compared with the coaxial line connection method, the LCD driver IC DuPont line interface 242 itself can flexibly change the signal conditions of different pins.

[0074] MIPI-DPHY output HDMI line interface 281, MIPI-DPHY output DuPont line interface 282 are used for the construction of a test platform for the chip to be tested that supports MIPI-DPHY. MIPI-CPHY output HDMI line interface 291, MIPI-CPHY output DuPont line interface 292 are used for the construction of a test platform for the chip to be tested that supports MIPI-CPHY. Special MIPI-DPHY output HDMI line interface 281, MIPI-CPHY output HDMI line interface 291 allows the host to establish a connection with the chip to be tested through the HDMI line to provide a driver, and the HDMI line is easy to plug and unplug, suitable for long-distance signal transmission, and at least allows the host to maintain a predetermined distance with the chip to be tested during the test, such as a distance of more than 1.5 meters, thereby allowing the host to avoid being thrown into the furnace during the aging test process, and improving the service life of the host. Further, the MIPI-DPHY output HDMI line interface 281, MIPI-DPHY output DuPont line interface 282 are arranged at the lower right corner of the test fixture mainboard 10, and are opened toward the side of the mainboard. The MIPI-DPHY output HDMI line interface 281 and the MIPI-DPHY output DuPont line interface 282 are respectively adjacent to the MIPI-DPHY output HDMI line interface 281 and the MIPI-DPHY output DuPont line interface 282 of their corresponding DuPont lines, which facilitates the MIPI-DPHY output HDMI line interface 281 and the MIPI-DPHY output DuPont line interface 282 to share circuits, and the MIPI-CPHY output HDMI line interface 291 and the MIPI-CPHY output DuPont line interface 292 to share circuits, and can also facilitate the extraction of the HDMI line connected to the MIPI-DPHY output HDMI line interface 281 and the MIPI-CPHY output DuPont line interface 291 without being affected by the pins included in the MIPI-DPHY output DuPont line interface 282 and the MIPI-CPHY output DuPont line interface 292 (for example, scratches, etc.); such a setting is conducive to the arrangement of the circuits of the test fixture mainboard 10 itself, and is also conducive to the host including the test fixture mainboard 10 to establish connections with other test fixtures and the chip to be tested, so as to facilitate the construction of a neat and easy-to-operate test platform.

[0075] It can be seen that by arranging the various types of test interfaces listed above in the second area 200, it is easier to build a chip test platform and the built platform is more operable. Through the test interfaces of these categories set in the second area, the test fixture mainboard can be made suitable for various types of chips to be tested on the market, and the compatibility of the test objects of the test fixture mainboard can be improved. At the same time, there is more room for choice for the number of chips to be tested. In addition, the host including the test fixture mainboard 10 can also be applied to various aging test environments, which can improve the service life of the host and reduce the testing cost.

[0076] The circuit logic of the test fixture mainboard 10 is described in detail as follows:

[0077] like Figure 3 As shown, the test fixture mainboard 10 includes a control circuit, which includes a main control (for example, a main control microcontroller module), an FPGA (Field-Programmable Gate Array) module, a power regulation output circuit, a level conversion communication interface module, a signal conversion module (for example, a MIPI bridge chip module), a first storage (for example, SDRAM, SD card, etc.), a second storage (for example, SDRAM, etc.), etc.

[0078] The host including the test fixture mainboard 10 can complete self-debugging. For example, through the aforementioned debugging interface 270 access, a debugging program can be downloaded to debug the host (including the test fixture mainboard 10) to make it meet the working conditions of the chip test.

[0079] Among them, the main control single-chip microcomputer module is used to interact with the host computer signal, and the interactive data includes display data, touch data, etc. The host computer and the host can be connected to communicate through the aforementioned host computer communication interface 250, and the host computer communication interface 250 can be, for example, a USB2.0 HS_DP interface and a USB2.0 FS_TP interface, etc. In addition, the host computer and the main control single-chip microcomputer module are also connected through a program download debugging circuit, and the host computer burns the program into the main control single-chip microcomputer module through the program download debugging circuit. Specifically, the host computer and the program download debugging circuit can be connected through a USB2.0 interface, for example, and the program download debugging circuit and the main control single-chip microcomputer module can be connected through a JTAG (Joint Test Action Group, Joint Test Working Group) or UART (Universal Asynchronous Receiver / Transmitter, Universal Asynchronous Receiver / Transmitter) interface.

[0080] The main control microcontroller module is used to control the combined application of any other modules on the chip test fixture mainboard 10. Moreover, when the chip test fixture mainboard 10 is extended and connected with an extended test circuit board, the main control microcontroller module also controls some or all modules on the extended test circuit board. Figure 3As shown in the figure, the chip test fixture mainboard 10 is coupled to the extended test circuit board, and its power supply (e.g. 12V), SPI signal, BUSY signal (indicating whether the extended test circuit board is working), INT signal (indicating the signal for notifying the mainboard 10 to obtain data from the extended test circuit board), etc. can be interconnected with the extended test circuit board through the aforementioned third pin module 130. The main control microcontroller module also controls the aforementioned SPI signal, BUSY signal, INT signal, etc.

[0081] The FPGA module is controlled by the main control microcontroller module and is used to control the logic of functional modules such as SDRAM (Synchronous Dynamic Random Access Memory), level conversion communication interface, MIPI bridge chip, etc. on the chip test fixture mainboard 10. Most importantly, the FPGA is used to implement the communication protocol between the test fixture mainboard 10 and the chip to be tested. In addition, the FPGA module can also be set to assist in the data processing of the extended test circuit board. For example, Figure 3 The schematic chip test fixture mainboard 10 is coupled to the extended test circuit board, and the test frequency (e.g., freq_1, freq_2) of the extended test circuit board can be interconnected through the second pin module 120 and provided to the FPGA for processing, so that the FPGA module can also cooperate in data processing of the extended test circuit board.

[0082] The SD card is inserted into the memory card slot 230, and the FPGA module is electrically connected to the memory card slot 230 to read the data in the memory card inserted in the memory card slot 230. Therefore, during the power-on screen test, the FPGA can convert the image in the SD card into a protocol and send it to the chip under test, avoiding the temporary transmission of the image from the host computer, so as to greatly shorten the communication time required for the test.

[0083] The internal power conversion module includes a power regulation output circuit and a current limiting protection circuit module. The power regulation output circuit (for example, for outputting the three power supplies / two power supplies required by the chip) is controlled by the main control microcontroller module and is used to output the three power supplies VSP (Positive Voltage Supply, positive voltage supply) / VSN (Negative Voltage Supply, negative voltage supply) IOVCC required by common LCD drivers, or the two power supplies VCI and IOVCC required by common LCD drivers, and other common power supply voltages for display drivers. These voltages can be provided to the extended test circuit board through the first pin module 110. The input end of the power regulation output circuit is connected to an external power supply, and the external power supply is provided to the power regulation output circuit to be converted into the required internal power supply voltage category, and then converted into a suitable voltage and respectively provided to each module that needs electricity. After the chip test fixture mainboard 10 is extended to connect the extended test circuit board, these voltages can be transmitted to the extended test circuit board through the aforementioned first pin module 110, and are sampled by the extended test circuit board as the signal to be tested. The extended test circuit board will feed back the sampled data to the main control of the test fixture mainboard 10, and then feed back to the host computer to facilitate the test personnel to automatically obtain data, thereby realizing test automation.

[0084] The level conversion communication interface module is used to adjust the level of the DP (display signal) (for example, RGB / I80 (Inter8080-series) / SPI / QSPI) signal, and is also used to output the level of the TP (touch signal) signal, which may include, for example, SPI / IIC / int (interrupt) / reset, etc. The final output of the exemplary corresponding level conversion communication interface module can be output through the aforementioned drive control integrated interface 240 (preferably, LCD driver IC coaxial line interface 241, LCD driver IC DuPont line interface 242), or MIPI-DPHY output HDMI line interface 281, MIPI-DPHY output DuPont line interface 282 (interfaces 281 and 282 are included in the integrated interface 280), or MIPI-CPHY output HDMI line interface 291, MIPI-CPHY output DuPont line interface 292 (interfaces 291 and 292 are included in the integrated interface 290), etc.

[0085] The signal conversion module, such as the MIPI bridge chip module (the MIPI bridge chip module receives RGB+SPI and processes the RGB signal, and finally outputs the MIPI signal), is used to convert the RGB signal into a MIPI signal for output, and the MIPI signal may include MIPI-DPHY, MIPI-CPHY, etc. Thus, its output can be output through the aforementioned MIPI-DPHY output HDMI line interface 281 (or MIPI-DPHY output DuPont line interface 282), or MIPI-CPHY output HDMI line interface 291 (or MIPI-CPHY output DuPont line interface 292).

[0086] The first storage module may include SDRAM, Flash, SD card, etc., and the second storage module may include SDRAM. The first storage module may be used for the needs of the main control module, and the second storage module may be used for the needs of the FPGA module. For example, SDRAM can provide additional memory for FPGA, and FPGA realizes read and write operations by controlling SDRAM.

[0087] The control circuit of the test fixture mainboard 10 also includes an LED backlight circuit module, a key control module, an alarm module, an indicator light (the key control module, the alarm module, the indicator light, etc. are not shown in the figure), etc. The key control module is also controlled by the main control microcontroller module, for example, it is used to test the implementation of the display control module 220, etc. The LED backlight circuit module is controlled by the main control microcontroller module and is used to power the backlight module of the LCD display screen of the IC under test. The LED backlight circuit module is controlled by the dimming pulse timing to drive the backlight module of the display screen of the chip under test. Optionally, the output of the LED backlight circuit module can also be transmitted to the current detection interface of the extended test circuit board through the aforementioned first pin module 110 (the current detection interface is located at a part of the pin pins of the third pin module 130), so that the chip under test can obtain this type of current detection from the current detection interface of the extended test circuit board.

[0088] In summary, it can be seen that the chip test fixture mainboard 10 of the present invention can independently complete a part of the test work, and can also be extended to connect the extended test circuit board to merge and complete other test work. The host formed by combining with the extended test circuit board has a small volume and can support various test needs of chips of almost all working protocol types currently on the market, and can also reduce the test cost. Specifically, the present invention designs a middle area for the extended test circuit board to couple, provides a rich type of protocol interface, and arranges the rich type of protocol interface around the middle area of ​​the reserved extended test circuit board coupling, especially the interface that needs to be flexibly plugged and built is arranged in the lower part of the second area of ​​the test fixture mainboard 10, which can form a small area test fixture mainboard and a chip test host, which can meet the test needs of chips of different working protocol types, different quantity scales, and different test types, can improve the test quality while greatly improving the test efficiency, and can also reduce the test cost to meet the needs of chip mass production testing.

[0089] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A chip test fixture mainboard, characterized in that: The fixture mainboard includes: a first area, the first area being extendably coupled to an extended test circuit board; The second area is arranged around the first area, and a plurality of output interfaces are arranged in the second area for establishing electrical connection or signal connection with the chip to be tested.

2. The chip test fixture mainboard according to claim 1, characterized in that: The first area includes a first pin module, the first pin module is used to connect to an extended test circuit board, and the first pin module is used to provide a test signal transmission path for the extended test circuit board.

3. The chip test fixture mainboard according to claim 1 or 2, characterized in that: A third pin module is provided in the first area, and the third pin module is used to be electrically connected to the extended test circuit board to supply power to the extended test circuit board, or to be used for communication between a chip test fixture mainboard and the extended test circuit board.

4. The chip test fixture mainboard according to any one of claims 1 to 3, characterized in that: A second pin module is also provided in the first area. The second pin module is used to connect to the extended test circuit board and to receive a frequency detection signal transmitted by the extended test circuit board.

5. The chip test fixture mainboard as claimed in claim 4, characterized in that: The first pin module includes multiple groups of first pins, and the third pin module includes multiple groups of third pins respectively. The multiple groups of first pins are arranged along the first direction, and the multiple groups of third pins are arranged along the second direction.

6. The chip test fixture mainboard as claimed in claim 5, characterized in that: Compared with the first pin module, the second pin module is closer to the middle area of ​​the first area.

7. The chip test fixture mainboard according to claim 1, characterized in that: A plurality of binding holes are provided in the first area, and the plurality of binding holes are used to fix the extended test circuit board.

8. The chip test fixture mainboard as claimed in claim 7, characterized in that: Three binding holes are provided in the first area, and the three binding holes are located on non-coordinate lines.

9. The chip test fixture mainboard as claimed in claim 8, characterized in that: The three binding holes and the first pin module, the second pin module, and the third pin module are roughly located on the rectangular periphery of the first area.

10. The chip test fixture mainboard according to claim 1, characterized in that: A plurality of packaging interfaces are arranged in the second area, and the packaging interfaces are used to be directly or indirectly coupled to the furnace plate of the chip to be tested through transmission lines.

11. The chip test fixture mainboard according to claim 10, characterized in that: The packaging interface includes an HDMI line interface, a DuPont line interface, or a coaxial line interface, or a combination of any of the aforementioned interfaces.

12. The chip test fixture mainboard according to claim 10, characterized in that: The packaging interface includes an LCD driver IC coaxial line interface and / or an LCD driver IC DuPont line interface; or / and, a MIPI-DPHY output HDMI line interface and / or a MIPI-DPHY output DuPont line interface; or / and, a MIPI-CPHY output HDMI line interface and / or a MIPI-CPHY output DuPont line interface.

13. The chip test fixture mainboard according to claim 12, characterized in that: The LCD driver IC coaxial line interface, LCD driver IC DuPont line interface, MIPI-DPHY output HDMI line interface, MIPI-DPHY output DuPont line interface, MIPI-CPHY output HDMI line interface, and MIPI-CPHY output DuPont line interface are arranged in the lower part of the second area of ​​the test fixture mainboard.

14. The chip test fixture mainboard according to claim 1, characterized in that: A memory card slot is disposed in the second area.

15. A chip testing host, characterized in that: It comprises the chip test fixture mainboard as claimed in any one of claims 1 to 14, or comprises the chip test fixture mainboard as claimed in any one of claims 1 to 14 and an extended test circuit board.

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