Control method of test equipment and chip test system

Abstract

The invention relates to a control method of test equipment and a chip test system, the method is applied to a second controller in a test resource board card, the test resource board card further comprises a first controller and a third controller, and the second controller and the third controller are connected with the test equipment. The method comprises the following steps: receiving instruction data sent by the first controller; based on the instruction data, a corresponding operation type and a control mode are obtained, and the control mode comprises any one of a direct control mode, a preloading mode and a microinstruction mode; based on the control mode, obtaining control information corresponding to the instruction data; the control information is sent to the corresponding test equipment or sent to the corresponding test equipment through the third controller, and the test equipment executes the corresponding control action based on the control information, so that the problem that the test equipment control method cannot meet the requirements of different test scenes of the IC test is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit testing, and in particular to a control method for testing equipment and a chip testing system. Background Art

[0002] Integrated circuit (IC) testing applies a known test vector (pattern) to the IC under test, observes its output results, and compares them with the known correct output results to determine whether the chip's function, performance, and structure meet the requirements. During the test, the test vector can be converted into a corresponding test signal input into the IC under test through an arbitrary waveform generator, and the output results of the IC under test can be collected through a waveform collector. In addition, the input or output test signals can be collected and measured through test equipment such as oscilloscopes and multimeters. These test equipment need to be triggered and controlled based on the pattern's running process to cooperate with the chip test process, and have high requirements for time synchronization of the control.

[0003] In the existing test equipment control method, control instructions can be directly issued by the host computer. This method is inefficient and cannot achieve synchronization of multiple test channels, but it can be used for problem troubleshooting and location; or through the preload mode, the control instructions are stored in the DDR in advance, and the control instructions in the DDR are read out and sent to the test equipment according to the preload startup instructions. This method is suitable for IC batch testing, but the synchronization accuracy is low. None of the above methods can meet the needs of different test scenarios of IC testing. Summary of the invention

[0004] In this embodiment, a control method for a test device and a chip test system are provided to solve the problem that the control method for the test device in the related art cannot meet the requirements of different test scenarios of IC testing.

[0005] In a first aspect, a control method for a test device is provided in this embodiment, the method is applied to a second controller in a test resource board, the test resource board further includes a first controller and a third controller connected to the second controller, the second controller and the third controller are connected to a plurality of test devices, the method includes: receiving instruction data sent by the first controller; Based on the instruction data, obtaining a corresponding operation type and a control mode, wherein the control mode includes any one of a direct control mode, a preload mode and a microinstruction mode; Based on the control mode, obtaining control information corresponding to the instruction data; The control information is sent to a corresponding test device, or is sent to a corresponding test device through the third controller, and the test device performs a corresponding control action based on the control information.

[0006] In some embodiments, the instruction data includes an operation code and register information, and obtaining the corresponding operation type and control mode based on the instruction data includes: Determine, based on the operation code and the register information, an operation type corresponding to the instruction data, the operation type including any one of a read operation, a write operation, and a test device control; In a case where the operation type corresponding to the instruction data is test equipment control, a control mode corresponding to the instruction data is determined based on the register information.

[0007] In some embodiments, acquiring control information corresponding to the instruction data based on the control mode includes: When the control mode is a direct control mode, obtaining control information in the instruction data, and writing the control information into a register corresponding to the register information; When the control mode is the preload mode, corresponding control information is read based on the storage address in the instruction data.

[0008] In some embodiments, acquiring control information corresponding to the instruction data based on the control mode includes: When the control mode is a microinstruction mode, the pre-stored test vector is expanded into a corresponding microinstruction, wherein the microinstruction includes an event type and an event parameter; In the case where the event type of the microinstruction is instruction loading, reading corresponding control information from a memory based on a loading address in the event parameter; When the event type of the microinstruction is not instruction loading, the control information in the microinstruction is written into the register corresponding to the register information.

[0009] In some embodiments, after determining the operation type corresponding to the instruction data based on the operation code, the method further includes: When the operation type corresponding to the instruction data is a write operation, based on the storage address in the instruction data, writing the data to be written in the instruction data into the memory, wherein the data to be written is the control information in the preload mode or the test vector in the microinstruction mode; In the case where the operation type corresponding to the instruction data is a read operation, the register corresponding to the register information is read, or the memory is read based on the storage address to obtain the return data.

[0010] In a second aspect, a chip testing system is provided in this embodiment, the system comprising a host computer, a test resource board and a plurality of test devices connected in sequence, the test resource board comprising a first controller, a second controller and a third controller connected in sequence; the second controller and the third controller are connected to the plurality of test devices, and the first controller is communicatively connected to the host computer; The first controller is used to receive the instruction data sent by the host computer, and obtain corresponding return data based on the instruction data, or send the instruction data to the second controller; The second controller is used to control the multiple test devices based on the control method of the test device according to the first aspect, or send the instruction data to the third controller; The third controller is used to control the multiple test devices based on the instruction data or control information sent by the second controller.

[0011] In some embodiments, the first controller is connected to the second controller via a first high-speed communication interface and a serial interface, and the second controller is connected to the third controller via the first high-speed communication interface, the serial interface, and the second high-speed communication interface. The first high-speed communication interface is used for downlink transmission of the instruction data and uplink transmission of the return data; The second high-speed communication interface is used for downlink transmission of preloaded data; The serial interface is used for uplink transmission of self-test status data.

[0012] In some embodiments, the first controller, the second controller and the third controller each include a main control decoding module, a service decoding module, a service return module and a status readback module. The main control decoding module sends the instruction data to the corresponding functional module in the controller for processing based on the register information in the instruction data, or transmits the instruction data downlink to the next controller; The service decoding module decodes the instruction data to obtain corresponding control information; The service return module reads the status information of the external device corresponding to the instruction data to obtain the return data; The status read-back module reads the register corresponding to the instruction data to obtain the return data.

[0013] In some embodiments, the second controller further includes a microinstruction control module, a cache module, a preload control module and a service parameter selection module. The microinstruction control module expands the test vector stored in the cache module into a corresponding microinstruction; if the microinstruction is a load microinstruction, the load microinstruction is sent to the preload control module; if the microinstruction is not a load microinstruction, the control information in the microinstruction is sent to the service parameter selection module; The preloading control module reads the preloading data stored in the cache module and sends it to the service parameter selection module; The service parameter selection module is used to send the preloaded data or the control information to the third controller or a corresponding test device.

[0014] In some embodiments, the third controller further includes a preload parameter decoding module and a service parameter selection module. The preloading parameter decoding module receives the preloading data sent by the second controller, decodes to obtain corresponding control information and sends it to the service parameter selection module; The service parameter selection module sends the control information to the corresponding test device.

[0015] In some of the embodiments, the main control decoding module of the third controller receives the instruction data sent by the second controller, and based on the register information in the instruction data, sends the instruction data to the corresponding functional module in the third controller; The service decoding module of the third controller decodes the instruction data to obtain corresponding control information, and sends the control information directly to the corresponding test equipment, or sends it to the service parameter selection module.

[0016] In some embodiments, the first controller, the second controller and the third controller all include an uplink arbitration module. The uplink arbitration module of the third controller arbitrates the multiple uplink requests corresponding to the multiple return data, and sends the multiple return data to the second controller in sequence based on the arbitration result; The uplink arbitration module of the second controller arbitrates the return data sent by the third controller and the multiple uplink requests corresponding to the return data read by the second controller, and sends the return data to the first controller in sequence based on the arbitration result; The uplink arbitration module of the first controller arbitrates the return data sent by the second controller and the multiple uplink requests corresponding to the return data read by the first controller, and sends the return data to the host computer in sequence based on the arbitration result.

[0017] In some embodiments, the first controller determines whether the instruction data is valid based on the board domain in the instruction data; if valid, transparently transmits the instruction data to the second controller based on the register information in the instruction data; The second controller determines whether the instruction data is valid based on the sub-board card domain in the instruction data; if valid, the instruction data is transparently transmitted to the third controller based on the register information in the instruction data; the third controller sends the instruction data to the corresponding functional module for processing based on the register information in the instruction data.

[0018] In some embodiments, the number of the second controller and the third controller is multiple. The first controller is used to broadcast the instruction data to multiple second controllers, so that the multiple second controllers synchronously execute control over the test equipment.

[0019] Compared with the related art, the control method of the test equipment provided in this embodiment obtains the control instruction of the host computer by receiving the instruction data sent by the first controller; obtains the corresponding operation type and control mode based on the instruction data, and controls the test equipment through the control mode specified by the host computer, and the control mode includes direct control mode, preloading mode and microinstruction mode; obtains control information corresponding to the instruction data based on the control mode, including control parameters and control signals, etc.; sends the control information to the corresponding test equipment, or sends it to the corresponding test equipment through the third controller, and the test equipment performs the corresponding control action based on the control information, and controls the test equipment through the specified control mode, thereby solving the problem that the test equipment control method cannot meet the requirements of different test scenarios.

[0020] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 is a hardware structure block diagram of a chip testing system in some embodiments of the present application; Figure 2 is a flow chart of a control method of a test device in some embodiments of the present application; Figure 3 is a flowchart of obtaining operation types and control modes in some embodiments of the present application; Figure 4 is a flowchart of obtaining control information corresponding to instruction data in some embodiments of the present application; Figure 5 is a flowchart of obtaining control information corresponding to instruction data in other embodiments of the present application; Figure 6 is a flow chart of a control method of a test device according to some preferred embodiments of the present application; Figure 7 is a structural block diagram of a test resource board in some embodiments of the present application; Figure 8 is a structural block diagram of a first controller in some embodiments of the present application; Fig. 9 is a structural block diagram of a second controller in some embodiments of the present application; Fig.10 This is a structural block diagram of a third controller in some embodiments of the present application. DETAILED DESCRIPTION

[0022] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0024] The control method of the test equipment provided in the embodiment of the present application can be executed in the second controller of the test resource board in the chip testing system. Figure 1 is a block diagram of a chip testing system in some embodiments of the present application. Figure 1 As shown, the chip test system includes a host computer 10, a test resource board 20 (one is shown in the figure) and a plurality of test devices 30 connected in sequence. The test resource board includes a first controller 21, a second controller 22 and a third controller 23 connected in sequence, and the second controller 22 and the third controller 23 are connected to the plurality of test devices 30 (two are shown in the figure). It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the chip test system. Figure 1 More or fewer components as shown, or with Figure 1 The different configurations shown. The test equipment can be used to provide test resources for the chip under test.

[0025] In this embodiment, a control method for a test device is provided. Figure 2 is a flow chart of a control method of a test device in some embodiments of the present application, such as Figure 2 As shown, the process includes the following steps: Step S201, receiving instruction data sent by the first controller.

[0026] In this embodiment, the first controller, the second controller and the third controller may be FPGAs (field programmable gate arrays), wherein the first controller is a first FPGA, the second controller is a second FPGA, and the third controller is a third FPGA.

[0027] The main function of the first controller is to communicate and interact with the host computer and the second controller, identify and distribute the command data sent by the host computer, and the distribution objects are the functional modules in the first controller and the second controller; each functional module obtains the return data corresponding to the command data, or receives the return data sent from the second controller and returns it to the host computer; and controls the program loading of the second controller and the third controller, the online program upgrade of this board, etc. The main function of the second controller is to process the received command data and send the processed control information to the corresponding test equipment or the third controller; the third controller controls the peripheral DAC / ADC of the test equipment according to the control information. In this embodiment, the test equipment includes an arbitrary waveform generator AWG and a waveform collector DGT. The control information includes control signals and configuration parameters sent to the test equipment.

[0028] Step S202, based on the instruction data, obtaining a corresponding operation type and control mode, wherein the control mode includes any one of a direct control mode, a preload mode and a microinstruction mode.

[0029] In this embodiment, the second controller receives the instruction data sent by the first controller, and obtains the corresponding operation type and control mode according to the instruction data. The operation type may include a read operation, a write operation, and a test device control. The read operation includes reading the contents of each register or DDR of the second controller and the third controller, and reading the status information of the test device; the write operation includes writing contents to each register or DDR of the second controller, and writing contents to the register of the test device; the test device control includes sending control information to the test device through the second controller or the third controller to control the test device to perform the corresponding operation.

[0030] The control mode may include any one of a direct control mode, a preload mode and a microinstruction mode. The direct control mode means that the host computer directly sends control information to the test device through instruction data, and then the second controller forwards it to the third controller or the test device.

[0031] Preloading mode means that the control information to be sent is stored in DDR in advance. After the host computer sends the preloading instruction to the second controller, the second controller reads the control information and then sends it to the third controller or test equipment in sequence. The preloading mode can store different control instructions and configuration parameters of multiple test items in DDR in advance, and select the control information of the corresponding test item for reading according to the preloading instruction, which improves the test efficiency compared to the direct control mode.

[0032] The microinstruction mode refers to pre-storing the test instruction (pattern) in the DDR. After the second controller receives the start instruction sent by the host computer, it reads the corresponding pattern and expands it into a microinstruction, and realizes the control function of the test equipment through the operation of the microinstruction. Specifically, the microinstructions may include channel connection, channel disconnection, preloading, start and stop of the test equipment. Among them, the preloading microinstruction is used to realize the reading of preloaded data, which is pre-stored in the DDR and can be control information. Channel connection, channel disconnection, start and stop microinstructions are used to control the test equipment to perform corresponding operations. Since the execution cycle of each microinstruction strictly corresponds to the clock cycle, the microinstruction mode can realize the synchronous control of multiple or multiple types of test resource boards, and the synchronization accuracy is higher than that of the preloading mode.

[0033] Step S203: based on the control mode, obtain control information corresponding to the instruction data.

[0034] In different control modes, the second controller obtains control information corresponding to the instruction data in different ways, and the control information includes control signals and configuration parameters sent to the test equipment.

[0035] Step S204: sending the control information to the corresponding test device, or sending the control information to the corresponding test device through a third controller, and the test device performs a corresponding control action based on the control information.

[0036] According to the content of the control information, the control information is sent directly to the corresponding test equipment, or is sent to the corresponding test equipment through a third controller, and the test equipment performs the corresponding control action according to the control information.

[0037] Through steps S201 to S204, the control instructions of the host computer are obtained by receiving the instruction data sent by the first controller; based on the instruction data, the corresponding operation type and control mode are obtained, and the test equipment is controlled through the control mode specified by the host computer, and the control modes include direct control mode, preloading mode and microinstruction mode; based on the control mode, control information corresponding to the instruction data is obtained, including control parameters and control signals, etc.; by sending the control information to the corresponding test equipment, or sending it to the corresponding test equipment through the third controller, the test equipment executes the corresponding control action based on the control information, and controls the test equipment through the specified control mode, thereby solving the problem that the test equipment control method cannot meet the requirements of different test scenarios.

[0038] In some embodiments, the instruction data includes an operation code and register information. Figure 3 is a flowchart of obtaining operation types and control modes in some embodiments of the present application, such as Figure 3 As shown, the process includes the following steps: Step S301: determining the operation type corresponding to the instruction data based on the operation code and the register information, where the operation type includes any one of a read operation, a write operation and a test device control.

[0039] The instruction data received by the second controller complies with a pre-set format, which includes an operation code and register information. The operation code is used to describe the specific operation type, and the register information is the register field corresponding to the operation. Furthermore, it may also include information such as a board field, a sub-board field, a channel field, a data length, and a check bit. Depending on whether the sub-board field is consistent with the sub-board where the second controller is located, it can be determined whether the instruction data is valid for the second controller. If it is invalid, the instruction data is ignored. If it is valid, the operation type corresponding to the instruction data is determined according to the operation code and the register information.

[0040] Specifically, according to the operation code and register information, the instruction data can be divided into business decoding instructions, microinstruction decoding instructions, business return instructions, status read back instructions, microinstruction return instructions, third controller instructions, etc., among which status read back instructions, business return instructions, and microinstruction return instructions can be classified as read operations, which are used to read the data in the corresponding registers.

[0041] According to the register information corresponding to the service decoding instruction, the service decoding instruction is further divided into DDR write instruction, service control instruction and preload instruction. Among them, DDR write instruction can be classified as a write operation, which is used to write the content in the instruction data into DDR. Service control instruction and preload instruction can be classified as test equipment control. Microinstruction decoding instruction can also be classified as test equipment control.

[0042] Step S302: When the operation type corresponding to the instruction data is test equipment control, determine the control mode corresponding to the instruction data based on the register information.

[0043] The three types of instructions controlled by the test equipment include business control instructions, preload instructions, and microinstruction decoding instructions, among which business control instructions correspond to direct control mode, preload instructions correspond to preload mode, and microinstruction decoding instructions correspond to microinstruction mode. It should be noted that the microinstructions in the microinstruction mode can also be issued by preloading or directly issuing microinstructions, so the three control modes have certain associations or overlaps in some operation steps.

[0044] Through steps S301 to S302, the operation type corresponding to the instruction data is determined based on the operation code and register information to execute the corresponding operation; when the operation type corresponding to the instruction data is test equipment control, the control mode corresponding to the instruction data is determined based on the register information, and the control information corresponding to the instruction data is obtained in a corresponding manner based on different control modes to achieve control of the test equipment and meet the needs of different test scenarios of IC testing.

[0045] In some embodiments, Figure 4 is a flowchart of obtaining control information corresponding to instruction data in some embodiments of the present application, such as Figure 4 As shown, the process includes the following steps: Step S401, when the control mode is the direct control mode, obtain the control information in the instruction data, and write the control information into the register corresponding to the register information.

[0046] In direct control mode, the instruction data includes control information. The second controller can directly obtain the control information by parsing the instruction data and send it to the service parameter selection module in the second controller. The service parameter selection module updates the control information and writes it into the corresponding register and sends it to the corresponding test device or the third controller.

[0047] Step S402: when the control mode is the preload mode, read the corresponding control information based on the storage address in the instruction data.

[0048] In the preloading mode, the control information is pre-stored in the DDR. After receiving the preloading instruction, the second controller starts the preloading function, reads the DDR according to the storage address in the preloading instruction, obtains the corresponding control information, and sends it to the business parameter selection module. The business parameter selection module updates the control information and writes it to the corresponding register, and sends it to the corresponding test device or the third controller.

[0049] Through steps S401 to S402, in direct control mode, control information in the instruction data is obtained, the control information is written into the register corresponding to the register information, and the control parameters are directly sent to the corresponding test equipment, thereby completing direct control of the test equipment, and improving the flexibility of the test equipment control in the problem troubleshooting and locating scenario; in preloading mode, the corresponding control information is read based on the storage address in the instruction data, thereby improving the test efficiency.

[0050] In some embodiments, Figure 5 is a flowchart of obtaining control information corresponding to instruction data in other embodiments of the present application, such as Figure 5 As shown, the process includes the following steps: Step S501, when the control mode is the microinstruction mode, expand the pre-stored test vector into a corresponding microinstruction, wherein the microinstruction includes an event type and event parameters.

[0051] In the microinstruction mode, the second controller generates a corresponding microinstruction according to the pattern expansion pre-stored in the DDR, and the microinstruction includes an event type and an event parameter. Specifically, the format of the event type can be control object_operation type. Among them, the control object can be an arbitrary waveform generator AWG and a waveform collector DGT, and the operation type can be connection, disconnection, start, stop, and instruction loading. The event parameter can be the configuration parameter required in the process of controlling AWG and DGT. Furthermore, the microinstruction also includes an execution cycle number, which is used to control the execution time of the microinstruction and ensure the time accuracy of the execution.

[0052] Step S502, when the event type of the microinstruction is instruction loading, the corresponding control information is read from the memory based on the loading address in the event parameter.

[0053] Specifically, when the event type of the microinstruction is instruction loading, the preloading function is turned on, and the corresponding control information in the DDR is read according to the storage address and event parameters in the microinstruction. The control information may include control signals, waveform files, FIR (finite impulse response) coefficients, etc. The control information is sent to the business parameter selection module, and the business parameter selection module updates the control information and writes it into the corresponding register, and sends it to the corresponding test device or the third controller.

[0054] Step S503, when the event type of the microinstruction is not instruction load, write the control information in the microinstruction into the register corresponding to the register information.

[0055] In the case where the event type of the microinstruction is not instruction loading, the event type of the microinstruction may include connection, disconnection, start, and stop. According to the event type and event parameters, the corresponding control information may be sent to the service parameter selection module, and the service parameter selection module updates the control information and writes it into the corresponding register, and sends it to the corresponding test device or the third controller.

[0056] The service parameter selection module determines the corresponding sending object according to the control information. The sending object includes AWG, DGT and the third controller. The third controller is also connected to AWG and DGT, and can further process the received instruction information and send it to AWG and DGT. Therefore, it should be noted that the sending object is not completely equivalent to the control object in the microinstruction. In this embodiment, the control object is AWG and DGT, and the sending object also includes the third controller.

[0057] Through steps S501 to S503, when the control mode is the microinstruction mode, the pre-stored test vectors are expanded into corresponding microinstructions. When the event type of the microinstruction is instruction loading, the corresponding control information is read from the memory based on the loading address in the event parameter. When the event type of the microinstruction is not instruction loading, the control information in the microinstruction is written into the register corresponding to the register information, thereby realizing control of multiple test devices through multiple control methods, thereby improving the level of automated control of the test equipment.

[0058] In some embodiments, a specific control method for a read operation or a write operation is also provided. The method includes: When the operation type corresponding to the instruction data is a write operation, the data to be written in the instruction data is written into the memory based on the storage address in the instruction data, and the data to be written is the control information in the preload mode or the test vector in the microinstruction mode.

[0059] When the operation type corresponding to the instruction data is a read operation, the register corresponding to the register information is read, or the memory is read based on the storage address to obtain the return data.

[0060] When the operation type is a write operation, the instruction data includes the storage address of the DDR and the data to be written, and the data to be written can be a test vector or control information. The second controller writes the data to be written into the storage address corresponding to the DDR in advance, and reads it based on the preload instruction in the subsequent preload mode or microinstruction mode. If the data to be written is a test vector, the test vector is expanded into a microinstruction in the microinstruction mode, which improves the time synchronization and control efficiency of the test equipment controlled by the microinstruction; if the data to be written is control information, the efficiency of issuing the control information is improved through the preload mode, thereby improving the test efficiency.

[0061] The present embodiment is described and illustrated by a preferred embodiment below. The control method of the test equipment of the preferred embodiment is applied to the second FPGA in the test resource board, and the test resource board also includes a first FPGA and a third FPGA connected to the second FPGA, wherein the second FPGA and the third FPGA are both connected to the AWG and the DGT. Figure 6 is a flow chart of a control method of a test device in some preferred embodiments of the present application, such as Figure 6 As shown, the process includes the following steps: Step S601, receiving a frame of instruction data from a first FPGA; Step S602, decoding the instruction data, and dividing the instruction data into business decoding instructions, microinstruction decoding instructions, business return instructions, status readback instructions, microinstruction return instructions, and third FPGA instructions according to the operation code and register information; Step S603, when the instruction data is a status readback instruction or a microinstruction return instruction, read the corresponding register content to obtain the return data, package the return data and initiate an uplink request; Step S604, when the instruction data is a service return instruction, determining whether it is a read DDR instruction; Step S605, if it is a DDR read instruction, then perform a read operation on the DDR according to the storage address, obtain return data, package the return data and initiate an uplink request; Step S606: if it is not a DDR read instruction, read the corresponding register content to obtain the returned data, package the returned data and initiate an uplink request; Step S607, each uplink request is returned to the first FPGA in sequence after uplink arbitration; Step S608, when the instruction data is a third FPGA instruction, send the instruction to the third FPGA; Step S609, when the instruction data is a service decoding instruction, the service decoding instruction is divided into a DDR write instruction, a preload instruction and a service control instruction according to the register information; Step S610, for a DDR write instruction, write the data to be written in the instruction data into the DDR according to the storage address in the instruction data; Step S611, for the preload instruction, start the preload function, read the control information in the DDR according to the storage address in the instruction data, and send it to the service parameter selection module; Step S612: for a service control instruction, the control information in the service control instruction is sent to a service parameter selection module; Step S613, when the instruction data is a microinstruction decoding instruction, control the pattern to start running; Step S614, expanding the pattern pre-stored in the DDR into a corresponding microinstruction; Step S615, determining whether the microinstruction is an instruction load microinstruction; Step S616, if yes, then start the preloading function, read the control information in the DDR according to the storage address in the microinstruction and send it to the service parameter selection module; Step S617, if not, the control information in the microinstruction is sent to the service parameter selection module; Step S618: the service parameter selection module updates the received control information and writes it into the corresponding register and sends it to the corresponding test device or the third FPGA.

[0062] Through steps S601 to S618, the instruction data is decoded, and the operation type of the instruction data is obtained according to the operation code and register information. For read operations and write operations, the corresponding operations can be directly executed according to the operation code and register information, and the corresponding data can be uploaded through uplink arbitration to realize the reading of status information of the resource board and the pre-storage of pre-loaded data; for the control of the test equipment, the corresponding control mode is determined by identifying the instruction data, including direct control mode, pre-loading mode and micro-instruction mode, which are respectively suitable for different application scenarios; the direct control mode improves the flexibility of control and is suitable for problem location scenarios; the pre-loading mode improves the control efficiency and is suitable for batch testing scenarios; the micro-instruction mode improves the time synchronization accuracy and operation efficiency of control through micro-instruction control.

[0063] Some embodiments of the present application also provide a chip testing system, such as Figure 1As shown, the system includes a host computer 10, a test resource board 20 (one is shown in the figure) and multiple test devices 30 connected in sequence. The test resource board 20 includes a first controller 21, a second controller 22 and a third controller 23 connected in sequence; the second controller 22 and the third controller 23 are connected to multiple test devices 30 (two are shown in the figure), and the first controller 21 is communicatively connected to the host computer 10.

[0064] The first controller 21 is used to receive the instruction data sent by the host computer 10, and obtain the corresponding return data based on the instruction data, or send the instruction data to the second controller 22; The second controller 22 is used to control the plurality of test devices 30 based on the control method of the test device of the above embodiment, or to send instruction data to the third controller 23; The third controller 23 is used to control the plurality of test devices 30 based on the instruction data or control information sent by the second controller 22 .

[0065] In this embodiment, the first controller 21, the second controller 22 and the third controller 23 may be FPGAs (field programmable gate arrays), wherein the first controller 21 is a first FPGA, the second controller 22 is a second FPGA, and the third controller 23 is a third FPGA.

[0066] In some embodiments, Figure 7 is a structural block diagram of a test resource board in some embodiments of the present application, such as Figure 7 As shown, the first controller 21 and the second controller 22 are connected via the first high-speed communication interface T1 and the serial interface T3, and the second controller 22 and the third controller 23 are connected via the first high-speed communication interface T1, the serial interface T3, and the second high-speed communication interface T2.

[0067] The first high-speed communication interface T1 is used for downlink transmission of instruction data and uplink transmission of return data; the second high-speed communication interface T2 is used for downlink transmission of preloaded data; and the serial interface T3 is used for uplink transmission of self-test status data.

[0068] Specifically, the first high-speed communication interface T1 and the second high-speed communication interface T2 may be GTX high-speed communication interfaces. The serial interface T3 may be a HUART serial interface.

[0069] Among them, the first high-speed communication interface T1 is the main communication link between the three controllers, which is used for downlink transmission of command data and uplink transmission of return data. The communication protocol of the first high-speed communication interface T1 is the uplink and downlink communication protocol format for the host computer to communicate with the three controllers. The protocol format includes information such as operation code, board domain, sub-board domain, channel domain, data length, register, check bit, etc., which can be applied to any board in the system.

[0070] A second high-speed communication interface T2 is provided between the second controller and the third controller. The communication interface is unidirectional and transmits the preloaded data from the second controller to the third controller. The second high-speed communication interface T2 is an interface for directly transmitting preloaded parameters between the second controller and the third controller. The communication content only involves data, and a custom protocol can be used, including channel domains and registers, which is suitable for data transmission within the board with high real-time requirements.

[0071] The main function of the serial interface T3 is to transmit the initialization self-test status of the second controller and the third controller to the first controller, which is then packaged and uploaded to the host computer. The communication protocol can be the UART protocol, which includes a frame header, a frame footer, and a register, and is suitable for data transmission within the board that does not require high real-time performance.

[0072] The chip testing system of this embodiment realizes the downlink transmission of instruction data and the uplink transmission of return data through the first high-speed communication interface, and realizes the unidirectional downlink transmission of preloaded data through the second high-speed communication interface, thereby meeting the real-time requirements for data transmission during IC testing; the self-test status of the controller is uploaded through the serial interface, and data with low real-time requirements is transmitted through a dedicated serial interface, thereby avoiding the impact on data transmission with high real-time requirements, thereby improving data transmission efficiency.

[0073] In some embodiments, the first controller, the second controller and the third controller all include a main control decoding module, a service decoding module, a service return module and a status readback module. Taking the first controller as an example, Figure 8 is a structural block diagram of the first controller 21 in some embodiments of the present application, such as Figure 8 As shown, the first controller 21 includes a main control decoding module 212, a service decoding module 213, a service return module 214, and a status readback module 215. In a further embodiment, the first controller 21 may also include a communication module (not shown in the figure), a peripheral control module 216, and an uplink arbitration module 211.

[0074] The main control decoding module 212 sends the instruction data to the corresponding functional module in the controller 21 for processing based on the register information in the instruction data, or transmits the instruction data downstream to the next controller. For the first controller 21, the next controller is the second controller 22.

[0075] The service decoding module 213 decodes the instruction data to obtain corresponding control information, and further sends the control information to the peripheral control module 216 for controlling the corresponding external device.

[0076] The service return module 214 reads the status information of the external device corresponding to the instruction data through the peripheral control module 216 to obtain the return data.

[0077] The status read-back module 215 reads the register corresponding to the instruction data to obtain the return data.

[0078] The main function of the communication module is to communicate with the host computer and the second controller for data transmission. In a specific embodiment, the communication module communicates with the host computer using a standard communication interface, and the data format is a custom communication protocol format. After receiving the communication data through the interface, the communication module extracts valid information, removes the frame header and frame tail information, and sends it to the main control decoding module 212 for logical function control; and according to the arbitration result of the uplink arbitration module 211, the return data is sent to the host computer after adding the frame header and frame tail information according to the interface protocol. The communication module also adds the frame header and frame tail information to the valid information that the main control decoding module 212 needs to send to the second controller according to the interface protocol and sends it to the second controller.

[0079] Specifically, the service decoding module 213 decodes the instruction data into the corresponding register according to the register information, and then controls the corresponding peripheral to perform the corresponding operation through the peripheral control module 216 .

[0080] The service return module 214 packages the read return data according to the communication protocol format based on the operation code and register information of the instruction data, and initiates a request to the uplink arbitration module 211. When receiving the response from the uplink arbitration module 211, the packaged return data is sent to the uplink arbitration module 211.

[0081] The status readback module 215 reads data through a blocking read instruction operation. According to the operation code of the instruction data, the timeout time and the expected data information are obtained. When the status readback module 215 receives the instruction data, it will not immediately perform the data return operation, but will return data only when the internal state of the register is consistent with the expected data information issued, or it will return data even if it is inconsistent with the expected data information for a long time but reaches the timeout time. This operation form reduces the polling read operation of the host computer, which greatly improves the logic control and communication efficiency.

[0082] Similarly, the second controller and the third controller also include a main control decoding module, a service decoding module, a service return module, and a status readback module. The functions of each module are basically the same as those in the above embodiment. The main control decoding modules of the first controller, the second controller, and the third controller are described below through an embodiment.

[0083] The first controller determines whether the instruction data is valid based on the board domain in the instruction data; if valid, the instruction data is transparently transmitted to the second controller based on the register information in the instruction data.

[0084] The second controller determines whether the instruction data is valid based on the daughter card field in the instruction data; if valid, the instruction data is transparently transmitted to the third controller based on the register information in the instruction data.

[0085] The third controller sends the instruction data to the corresponding functional module for processing based on the register information in the instruction data.

[0086] Specifically, the main control decoding module of the first controller determines whether the instruction data is valid for the test resource board based on the board domain in the instruction data; if valid, the instruction data is transparently transmitted to the second controller based on the register information in the instruction data; or the instruction data is decoded by the business decoding module to obtain the corresponding control information, and the corresponding external device is controlled based on the control information; or the status information of the register or external device corresponding to the instruction data is read to obtain the return data.

[0087] Specifically, the instruction data may include information such as operation code, board domain, sub-board domain, channel domain, data length, register information, check bit, etc. The main control decoding module of the first controller determines whether the instruction data is valid for the test resource board according to the board domain in the instruction data. Specifically, the instruction data can be divided into broadcast instructions and unicast instructions. For unicast instructions, the board domain field can be compared with the slot number where the test resource board is located. If the comparison result is consistent, it is determined that the instruction data is valid for the test board, otherwise it is invalid; for broadcast instructions, the card domain field can be compared with the pre-defined board type information. If the comparison result is consistent, it is determined that the instruction data is valid for the test board, otherwise it is invalid.

[0088] If it is valid, the data of the test resource board is distributed to different modules or the second controller according to the operation code and register information. If it is invalid, the whole packet of data can be discarded.

[0089] Specifically, if the instruction data is a service return instruction, the main control decoding module forwards the instruction data to the service return module, the service return module reads the corresponding register data or status information of the external device, and packages the response information and initiates a request to the uplink arbitration module.

[0090] If the instruction data is a status readback instruction, the instruction data is forwarded to the status readback module, the status readback module reads the register corresponding to the instruction data, obtains the return data and initiates a request to the uplink arbitration module; after receiving the response of the uplink arbitration, the service return module or the status readback module sends the packaged return data to the uplink arbitration module and then to the host computer.

[0091] If the instruction data is a second controller instruction or a third controller instruction, the main control decoding module of the first controller will transmit the instruction data to the second controller; if the instruction data is a business decoding instruction, the instruction data will be forwarded to the business decoding module, the business decoding module will decode the instruction data to obtain corresponding control information, and send the control information to the peripheral control module, and the peripheral control module will control the corresponding external device based on the control information.

[0092] Similarly, the main control decoding module of the second controller determines whether the instruction data is valid for the sub-board card based on the sub-board card field in the instruction data. It should be noted that each test resource board may include multiple sub-board cards, and each sub-board card may include a second controller. In the case of validity, based on the register information in the instruction data, the instruction data is transparently transmitted to the third controller, or the instruction data is sent to the corresponding functional module in the second controller.

[0093] The main control decoding module of the third controller sends the instruction data to the corresponding functional module for processing based on the register information in the instruction data.

[0094] The chip testing system of this embodiment identifies the validity of instruction data through the main control decoding modules of the first controller and the second controller, and filters out instruction data that is invalid for the test resource board or sub-board; distributes instruction data according to the operation code and register information in the instruction data through the main control decoding module; divides the instruction data for processing through the communication method of instruction transparent transmission between the three controllers, thereby realizing effective allocation of instruction processing resources; cooperates with other functional modules of the first controller, the second controller, and the third controller to realize data reading and writing and multi-mode control of test equipment, thereby improving IC test efficiency and expanding the application scenarios of test equipment control.

[0095] In a further embodiment, Fig. 9 is a structural block diagram of the second controller in some embodiments of the present application, such as Fig. 9 As shown, the second controller also includes a microinstruction control module 226 , a cache module 227 , a preload control module 228 and a service parameter selection module 229 .

[0096] The microinstruction control module 226 expands the test vectors stored in the cache module 227 into corresponding microinstructions; when the microinstruction is a load microinstruction, the load microinstruction is sent to the preload control module 228; when the microinstruction is not a load microinstruction, the control information in the microinstruction is sent to the business parameter selection module 229.

[0097] The preloading control module 228 reads the preloading data stored in the cache module 227 and sends the preloading data to the service parameter selection module 229 .

[0098] The service parameter selection module 229 is used to send the preloaded data or control information to the third controller or the corresponding test equipment.

[0099] Specifically, the microinstruction control module 226 may include a test vector control submodule, a microinstruction decoding submodule and a microinstruction return submodule. The test vector control submodule reads the test vector stored in the cache module 227, and the microinstruction decoding submodule decodes the test vector to obtain the corresponding microinstruction.

[0100] If the microinstruction is a loading microinstruction, the test vector control submodule sends the loading microinstruction to the preloading control module 228 , and the preloading control module 228 reads the corresponding preloading data according to the storage address in the loading microinstruction, and the preloading data may be control information, and sends the preloading data to the service parameter selection module 229 .

[0101] If the microinstruction is not a loading microinstruction, the test vector control submodule sends the control information in the microinstruction to the service parameter selection module 229. After receiving the control information sent by the microinstruction control module 226 or the preloading control module 228, the service parameter selection module 229 determines whether the sending object of the control information is the third controller or the test equipment AWG, DGT according to the data format of the control information, and sends the control information to the corresponding sending object.

[0102] In some embodiments, the main control decoding module 222 of the second controller sends the instruction data to the business decoding module 223 for processing according to the register information in the instruction data. The business decoding module 223 then performs corresponding processing according to the operation code and register information of the instruction data. Specifically, if the instruction data is a write operation instruction, the write content in the instruction data is written to the corresponding address of the cache module 227.

[0103] If the instruction data is a test equipment control instruction, the control information in the instruction data is sent to the service parameter selection module 229. The service parameter selection module 229 sends the control information to the corresponding sending object.

[0104] If the instruction data is a preloading instruction, the instruction data is sent to the preloading control module 228, and the preloading function is controlled to be turned on. The preloading control module 228 reads the preloading data stored in the cache module 227 according to the storage address in the instruction data, and the preloading data may be control information. The preloading data is sent to the service parameter selection module 229. The service parameter selection module 229 sends the preloading data to the corresponding sending object.

[0105] The chip testing system of this embodiment obtains control information in different ways in the microinstruction mode, controls a variety of testing equipment, improves testing efficiency, and enriches the control methods of the testing equipment.

[0106] In some embodiments, Fig.10 is a structural block diagram of a third controller in some embodiments of the present application, such as Fig.10 As shown, the third controller 23 further includes a preload parameter decoding module 237 and a service parameter selection module 236 .

[0107] The preload parameter decoding module 237 receives the preload data sent by the second controller, decodes to obtain corresponding control information and sends it to the service parameter selection module 236; the service parameter selection module 236 sends the control information to the corresponding test device.

[0108] Specifically, the preloaded data refers to the control information sent by the second controller in the preload mode, or the control information read by the second controller based on the loading microinstruction in the microinstruction mode. The business parameter selection module 236 determines whether the sending object of the control information is the test equipment AWG, DGT or other external device according to the data format of the control information, and sends the control information to the corresponding sending object. Specifically, the control information can be a read or write operation performed on the external device. Specifically, the module structure of the business parameter selection module 236 of the third controller and the business parameter selection module 229 of the second controller can be the same or different.

[0109] In some embodiments, the main control decoding module of the third controller receives the instruction data sent by the second controller, and based on the register information in the instruction data, sends the instruction data to the corresponding functional module in the third controller. The service decoding module of the third controller decodes the instruction data to obtain corresponding control information, and sends the control information directly to the corresponding test equipment, or to the service parameter selection module.

[0110] Similar to the first controller and the second controller, the third controller also includes a service decoding module, a service return module and a status reading module.

[0111] When the service decoding module receives the instruction data, it decodes the instruction data and determines whether the instruction data is a pin precision measurement unit (PMU) instruction. If it is, the corresponding control information is directly sent to the PMU to implement the corresponding control function. If not, the decoded control information is sent to the service parameter selection module, which updates the register and sends the control information to the corresponding test equipment or external equipment to implement the corresponding control function.

[0112] The specific functions and specific examples of the service return module and the status readback module in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0113] The chip testing system of this embodiment receives the preloaded data and instruction data sent by the second controller through the third controller, decodes the preloaded data through the preloaded parameter decoding module to obtain the corresponding control information, decodes the instruction data through the main control decoding module to obtain the corresponding control information, and sends the control information to the corresponding test equipment through the business parameter selection module to control the test equipment. On the basis of the control of the test equipment by the second controller, the control function is further enriched and the degree of automation of the test equipment control is improved.

[0114] In some embodiments, the first controller, the second controller, and the third controller all include an uplink arbitration module. The uplink arbitration module of the third controller arbitrates the multiple uplink requests corresponding to the multiple return data, and sends the multiple return data to the second controller in sequence based on the arbitration result; The uplink arbitration module of the second controller arbitrates the return data sent by the third controller and the multiple uplink requests corresponding to the return data read by the second controller, and sends the return data to the first controller in sequence based on the arbitration result; The uplink arbitration module of the first controller arbitrates the return data sent by the second controller and the multiple uplink requests corresponding to the return data read by the first controller, and sends the return data to the host computer in sequence based on the arbitration result.

[0115] The chip testing system of this embodiment arbitrates the return data corresponding to multiple functional modules of this controller and the return data of the downstream controller through the upstream arbitration module, and uploads the multiple return data in sequence according to the arbitration result, ensuring that the return data is uploaded according to priority, thereby improving the efficiency of data uploading and avoiding data conflicts.

[0116] In some embodiments, there are multiple second controllers and multiple third controllers, and the first controller is used to broadcast instruction data to the multiple second controllers so that the multiple second controllers synchronously execute control over the test equipment.

[0117] In a specific embodiment, the first controller can be connected to four second controllers and four third controllers. During the program loading process, the first controller can use a broadcast instruction to load the program to the four second controllers or four third controllers at the same time, effectively improving the loading rate.

[0118] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0119] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0120] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0121] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0122] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A control method for a test device, characterized in that: The method is applied to a second controller in a test resource board, the test resource board also includes a first controller and a third controller connected to the second controller, the second controller and the third controller are connected to a plurality of test devices, and the method includes: receiving instruction data sent by the first controller; Based on the instruction data, obtaining a corresponding operation type and a control mode, wherein the control mode includes any one of a direct control mode, a preload mode and a microinstruction mode; Based on the control mode, acquiring control information corresponding to the instruction data; The control information is sent to a corresponding test device, or is sent to a corresponding test device through the third controller, and the test device performs a corresponding control action based on the control information.

2. The method according to claim 1, characterized in that The instruction data includes an operation code and register information, and obtaining a corresponding operation type and control mode based on the instruction data includes: Determine, based on the operation code and the register information, an operation type corresponding to the instruction data, the operation type including any one of a read operation, a write operation, and a test device control; In a case where the operation type corresponding to the instruction data is test equipment control, a control mode corresponding to the instruction data is determined based on the register information.

3. The method according to claim 2, characterized in that The acquiring control information corresponding to the instruction data based on the control mode includes: When the control mode is a direct control mode, obtaining control information in the instruction data, and writing the control information into a register corresponding to the register information; When the control mode is the preload mode, corresponding control information is read based on the storage address in the instruction data.

4. The method according to claim 2, characterized in that: The acquiring control information corresponding to the instruction data based on the control mode includes: When the control mode is a microinstruction mode, the pre-stored test vector is expanded into a corresponding microinstruction, wherein the microinstruction includes an event type and an event parameter; In the case where the event type of the microinstruction is instruction loading, reading corresponding control information from a memory based on a loading address in the event parameter; When the event type of the microinstruction is not instruction loading, the control information in the microinstruction is written into the register corresponding to the register information.

5. The method according to claim 2, characterized in that: After determining the operation type corresponding to the instruction data based on the operation code, the method further includes: When the operation type corresponding to the instruction data is a write operation, based on the storage address in the instruction data, writing the data to be written in the instruction data into the memory, wherein the data to be written is the control information in the preload mode or the test vector in the microinstruction mode; In the case where the operation type corresponding to the instruction data is a read operation, the register corresponding to the register information is read, or the memory is read based on the storage address to obtain the return data.

6. A chip testing system, characterized in that: The system comprises a host computer, a test resource board and a plurality of test devices connected in sequence, wherein the test resource board comprises a first controller, a second controller and a third controller connected in sequence; the second controller and the third controller are connected to the plurality of test devices, and the first controller is connected to the host computer in communication; The first controller is used to receive the instruction data sent by the host computer, and obtain corresponding return data based on the instruction data, or send the instruction data to the second controller; The second controller is used to control the multiple test devices based on the control method of the test device according to any one of claims 1 to 5, or send the instruction data to the third controller; The third controller is used to control the multiple test devices based on the instruction data or control information sent by the second controller.

7. The system according to claim 6, characterized in that The first controller is connected to the second controller via a first high-speed communication interface and a serial interface, and the second controller is connected to the third controller via the first high-speed communication interface, the serial interface, and the second high-speed communication interface. The first high-speed communication interface is used for downlink transmission of the instruction data and uplink transmission of the return data; The second high-speed communication interface is used for downlink transmission of preloaded data; The serial interface is used for uplink transmission of self-test status data.

8. The system according to claim 6, characterized in that The first controller, the second controller and the third controller each include a main control decoding module, a service decoding module, a service return module and a status readback module. The main control decoding module sends the instruction data to the corresponding functional module in the controller for processing based on the register information in the instruction data, or transmits the instruction data downlink to the next controller; The service decoding module decodes the instruction data to obtain corresponding control information; The service return module reads the status information of the external device corresponding to the instruction data to obtain the return data; The status read-back module reads the register corresponding to the instruction data to obtain the return data.

9. The system according to claim 8, characterized in that The second controller also includes a microinstruction control module, a cache module, a preload control module and a service parameter selection module. The microinstruction control module expands the test vector stored in the cache module into a corresponding microinstruction; when the microinstruction is a load microinstruction, the load microinstruction is sent to the preload control module; In the case where the microinstruction is not a loading microinstruction, sending the control information in the microinstruction to the service parameter selection module; The preloading control module reads the preloading data stored in the cache module and sends it to the service parameter selection module; The service parameter selection module is used to send the preloaded data or the control information to the third controller or a corresponding test device.

10. The system according to claim 8, characterized in that The third controller also includes a preload parameter decoding module and a service parameter selection module. The preloading parameter decoding module receives the preloading data sent by the second controller, decodes to obtain corresponding control information and sends it to the service parameter selection module; The service parameter selection module sends the control information to the corresponding test device.

11. The system according to claim 10, characterized in that The main control decoding module of the third controller receives the instruction data sent by the second controller, and sends the instruction data to the corresponding functional module in the third controller based on the register information in the instruction data; The service decoding module of the third controller decodes the instruction data to obtain corresponding control information, and sends the control information directly to the corresponding test equipment, or sends it to the service parameter selection module.

12. The system according to claim 6, characterized in that The first controller, the second controller and the third controller all include an uplink arbitration module, The uplink arbitration module of the third controller arbitrates the multiple uplink requests corresponding to the multiple return data, and sends the multiple return data to the second controller in sequence based on the arbitration result; The uplink arbitration module of the second controller arbitrates the return data sent by the third controller and the multiple uplink requests corresponding to the return data read by the second controller, and sends the return data to the first controller in sequence based on the arbitration result; The uplink arbitration module of the first controller arbitrates the return data sent by the second controller and the multiple uplink requests corresponding to the return data read by the first controller, and sends the return data to the host computer in sequence based on the arbitration result.

13. The system according to claim 6, characterized in that The first controller determines whether the instruction data is valid based on the board domain in the instruction data; if valid, transparently transmits the instruction data to the second controller based on the register information in the instruction data; The second controller determines whether the instruction data is valid based on the sub-board card domain in the instruction data; if valid, the instruction data is transparently transmitted to the third controller based on the register information in the instruction data; the third controller sends the instruction data to the corresponding functional module for processing based on the register information in the instruction data.

14. The system according to claim 6, characterized in that The number of the second controller and the third controller is multiple, The first controller is used to broadcast the instruction data to multiple second controllers, so that the multiple second controllers synchronously execute control over the test equipment.

Images