Image sensing device for sensing distance

Abstract

The invention relates to an image sensing device for sensing a distance. An image sensing device includes: a first pixel including a first single photon avalanche diode (SPAD), the first SPAD including a cathode for receiving a first bias voltage; a second pixel including a second SPAD, the second SPAD including an anode for receiving a second bias voltage; and a selection circuit coupled to the first pixel and the second pixel, and configured to select the first pixel or the second pixel to generate an output.

Description

Technical Field

[0001] The technology and implementation disclosed in this patent document generally relate to an image sensing device capable of detecting a distance of a target object and a method for sensing the distance. Background Art

[0002] Image sensing devices are devices that capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the development of the automotive, medical, computer, and communication industries, the demand for high-performance image sensing devices is increasing in various devices such as smart phones, wearable devices, digital cameras, game consoles, IOT (Internet of Things), robots, security cameras, and medical micro cameras.

[0003] Recently, image sensing devices have been actively used not only to acquire color images but also to sense the distance to a target object to be captured. In particular, a direct time of flight (D-ToF) method that directly or indirectly measures the duration in which light is reflected from a target object and returns to an image sensing device has been widely used. Summary of the invention

[0004] According to an embodiment of the disclosed technology, an image sensing device may include: a first pixel, the first pixel including a first single-photon avalanche diode (SPAD), the first SPAD including a cathode for receiving a first bias voltage; a second pixel, the second pixel including a second SPAD, the second SPAD including an anode for receiving a second bias voltage; and a selection circuit, the selection circuit is connected to the first pixel and the second pixel and is configured to select the first pixel or the second pixel to generate an output.

[0005] According to another embodiment of the disclosed technology, an image sensing device may include: a first pixel, the first pixel including a first single-photon avalanche diode (SPAD) having a first detection sensitivity; a second pixel, the second pixel including a second SPAD having a second detection sensitivity higher than the first detection sensitivity; and a selection circuit, the selection circuit being connected to the first pixel and the second pixel and configured to select the first pixel or the second pixel to generate an output.

[0006] According to another embodiment of the disclosed technology, an image sensing device may include: a plurality of single-photon avalanche diodes (SPADs), each SPAD being configured to receive a bias voltage to operate in a Geiger mode in which a reverse bias voltage exceeding a breakdown voltage occurs; and a selection circuit connected to the SPAD and configured to select any one of the SPADs to generate an output. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0008] Figure 1 is a block diagram illustrating an example of an imaging device based on some implementations of the disclosed technology.

[0009] Figure 2A is an example of some implementations based on the disclosed technology, included in Figure 1 A circuit diagram of an example of a first single photon avalanche diode (SPAD) included in a pixel in a pixel array is shown.

[0010] Figure 2B is an example of some implementations based on the disclosed technology, included in Figure 1 A circuit diagram of an example of a second SPAD included in a pixel in a pixel array shown.

[0011] Figure 3 is a graph illustrating an example of comparison results of characteristics between a first SPAD and a second SPAD based on some implementations of the disclosed technology.

[0012] Figure 4A is an example of some implementations based on the disclosed technology, Figure 1 A diagram showing an example of an array structure of a pixel array.

[0013] Figure 4B is an example of some implementations based on the disclosed technology, Figure 1 A diagram of another example of an array structure of a pixel array shown.

[0014] Figure 5 is an example of some implementations based on the disclosed technology, Figure 4A Diagram of an example of the sensor layer and logic layer of the array structure shown.

[0015] Figure 6 is an example of some implementations based on the disclosed technology, Figure 4B Diagram of an example of a sensor layer and logic layer of an array structure shown.

[0016] Fig. 7Ais an example of some implementations based on the disclosed technology, included in Figure 1 A circuit diagram of an example operation of a pixel in a pixel array is shown.

[0017] Figure 7B is an example of some implementations based on the disclosed technology, included in Figure 1 A circuit diagram of an example operation of a pixel in a pixel array is shown.

[0018] Figure 7C is an example of some implementations based on the disclosed technology, included in Figure 1 A circuit diagram of an example operation of a pixel in a pixel array is shown.

[0019] Fig. 8A is a schematic diagram illustrating examples of sensor layers based on some implementations of the disclosed technology.

[0020] Figure 8B is a schematic diagram illustrating another example of a sensor layer based on some implementations of the disclosed technology.

[0021] Figure 8C is an example of some implementations based on the disclosed technology, wherein Fig. 8A and Figure 8B A schematic diagram of an example of an arrangement structure of an optical structure is shown.

[0022] Fig.9A is a diagram illustrating an example of a planar structure of a first SPAD or a second SPAD based on some implementations of the disclosed technology.

[0023] Fig. 9B is a diagram illustrating another example of a planar structure of a first SPAD or a second SPAD based on some implementations of the disclosed technology.

[0024] Fig. 9C is a diagram illustrating another example of a planar structure of a first SPAD or a second SPAD based on some implementations of the disclosed technology.

[0025] Fig. 10A is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing an example of a cross-sectional structure taken along any one of the first to third lines shown.

[0026] Fig. 10B is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines shown.

[0027] Fig. 10C is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines shown.

[0028] Fig. 10D is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines shown.

[0029] Fig.10E is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines shown.

[0030] Fig.10F is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines shown.

[0031] Fig.11A is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines shown.

[0032] FIG. 11B to FIG. 11F is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing other examples of a cross-sectional structure taken along any one of the first to third lines shown.

[0033] Fig. 12A is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines shown.

[0034] Fig. 12B is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines shown.

[0035] Fig. 12C is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines shown.

[0036] Fig.13 is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines shown.

[0037] Fig.14Ais an example of some implementations based on the disclosed technology, Fig. 10A A diagram of an example of a modified embodiment of a cross-sectional structure is shown.

[0038] Fig. 14B is an example of some implementations based on the disclosed technology, Fig. 10A A diagram of another example of a modified embodiment of a cross-sectional structure is shown.

[0039] Fig.15 is a diagram illustrating an example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0040] Fig.16 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0041] Fig.17 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0042] Fig.18 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0043] Fig.19 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0044] Fig. 20 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0045] Fig.21 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0046] Fig.22A is an example of some implementations based on the disclosed technology, along the Fig.15 A diagram showing an example of a cross-sectional structure taken along the fourth line shown.

[0047] Fig. 22B is an example of some implementations based on the disclosed technology, along the Fig.19 A diagram showing an example of a cross-sectional structure taken along the fifth line shown.

[0048] Fig.23A is a diagram illustrating an example of a planar structure of pixels included in a pixel array based on some implementations of the disclosed technology.

[0049] Fig. 23B is an example of some implementations based on the disclosed technology, Fig.23AA cross-sectional view of an example of a planar structure is shown. DETAILED DESCRIPTION

[0050] This patent document provides implementations and examples of an image sensing device capable of detecting the distance of a target object and a method for sensing the distance, which can be used in a configuration to substantially solve one or more technical or engineering problems and alleviate limitations or disadvantages encountered in some other image sensing devices. Some implementations of the disclosed technology relate to an image sensing device capable of operating in a mode suitable for shooting (or photographing) conditions and a method for sensing the distance to a target object to be captured. Recognizing the above problems, the disclosed technology can provide an image sensing device, which includes a single photon avalanche diode (SPAD) pixel operable to detect single photons in incident light with different detection sensitivities, and uses one or more SPAD pixels that are appropriate for the situation to detect the distance from the SPAD pixel to the target object, thereby achieving optimal performance optimized for the imaging device.

[0051] Embodiments of the disclosed technology will now be described in detail, examples of which are illustrated in the accompanying drawings. As much as possible, the same reference numerals are used throughout the drawings to designate the same or similar components. Although the present disclosure allows for various modifications and alternative forms, its specific embodiments are illustrated by the examples in the accompanying drawings. However, the present disclosure should not be interpreted as being limited to the embodiments set forth herein.

[0052] In the following, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents and / or alternatives of the embodiments. The embodiments of the disclosed technology can provide a variety of effects that can be directly or indirectly recognized by the disclosed technology.

[0053] Various embodiments of the disclosed technology relate to an image sensing device capable of operating in a mode suitable for shooting (or photographing) conditions and a method for sensing a distance to a target object to be captured.

[0054] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

[0055] Figure 1 is a block diagram illustrating an example of an imaging device (ID) based on some implementations of the disclosed technology.

[0056] Reference Figure 1, the imaging device (1D) may refer to a device such as a digital still camera for capturing still images or a digital video camera for capturing moving images. For example, the imaging device (1D) may be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, or a smart phone, etc. The imaging device (1D) may include a device having both a lens and an image pickup element, so that the device can capture (or capture) a target object and thus be able to create an image of the target object. In some implementations, the imaging device (1D) may be a distance measuring device that measures the distance to the target object 1. For example, the imaging device (1D) may be implemented as a laser radar (Lidar) sensor.

[0057] The imaging device (ID) may include an image sensing device 100 and an image signal processor (ISP) 150 .

[0058] The image sensing device 100 may be a complementary metal oxide semiconductor image sensor (CIS) for converting incident light into an electrical signal and may include a light source 10, a lens module 20, a light source driver 30, a pixel array 110, a sensor driver 120, a readout circuit 130, and a timing controller 140.

[0059] The light source 10 can emit light to the target object 1 when receiving a control signal from the light source driver 30. The light source 10 can be a laser diode (LD) or a light emitting diode (LED) for emitting light having a specific wavelength band (for example, near infrared (NIR) light, infrared (IR) light, or visible light), or can be any one of a near infrared laser (NIR), a point light source, a monochromatic light source combined with a white lamp or a monochromator, and a combination of other laser sources. For example, the light source 10 can emit infrared light with a wavelength of 800nm ​​to 1000nm. In addition, the light emitted from the light source 10 can be a pulse light with a predetermined period, amplitude, and pulse width. Although for ease of description, Figure 1 Only one light source 10 is shown, but the scope or spirit of the disclosed technology is not limited thereto, and a plurality of light sources may also be arranged near the lens module 20 .

[0060] The lens module 20 may collect light reflected from the target object 1, and may focus the collected light onto the pixel (PX) of the pixel array 110. For example, the lens module 20 may include a focusing lens having a surface formed of glass or plastic, or another cylindrical optical element having a surface formed of glass or plastic. The lens module 20 may include a plurality of lenses arranged to focus on an optical axis.

[0061] The light source driver 30 may drive the light source 10 under the control of the timing controller 140. In particular, the light source driver 30 may control the waveform (eg, period, amplitude, pulse width, etc.) of the emission light (EL) output from the light source 10.

[0062] The pixel array 110 may include a plurality of pixels (PX) continuously arranged in a two-dimensional (2D) matrix structure (e.g., continuously arranged in a column direction and / or a row direction). Each of the plurality of pixels (PX) may generate a pixel signal by sensing incident light incident through the lens module 20 under the control of the sensor driver 120.

[0063] Each pixel (PX) may be an infrared pixel for generating a pixel signal by sensing incident light including a reached light (RL) generated when the emitted light (EL) from the light source 10 is reflected from the target object 1. Although, for ease of description, the present embodiment assumes that the reached light (RL) is light reflected from the target object 1 and incident on the pixel array 110, the scope or spirit of the disclosed technology is not limited thereto. For example, the light source 10 may be provided in a separate device other than the image sensing device 100, and when the emitted light (EL) emitted from the light source 10 is directly incident on the pixel array 110, the reached light (RL) may be obtained. In some implementations, the infrared pixel may be a depth pixel for calculating the distance to the target object 1. According to another embodiment, the infrared pixel may include a pixel for generating an infrared image by sensing only the infrared light incident from the scene without sensing the reflected light. According to yet another embodiment, the pixel (PX) may include a pixel for generating a color image by sensing the visible light incident from the scene. Hereinafter, a description will be given assuming that each pixel (PX) is a single photon avalanche diode (SPAD) pixel for detecting the distance from the PX to the target object 1 according to a direct time-of-flight (ToF) method. Figure 2A and Figure 2B To describe the more detailed structure and operation of each unit pixel (PX).

[0064] The sensor driver 120 may drive the pixels (PX) of the pixel array 110 in response to the timing signal output from the timing controller 140. For example, the sensor driver 120 may generate a control signal capable of selecting and controlling the pixels (PX) in at least one row line among a plurality of row lines included in the pixel array 110.

[0065] The readout circuit 130 may process a pixel signal received from the pixel array 110 under the control of the timing controller 140 , and may generate and store depth data for detecting a distance of the target object 1 .

[0066] Specifically, the readout circuit 130 may calculate a candidate time of flight (ToF) corresponding to a SPAD pulse generated by each pixel (PX) sensing incident light including the arriving light (RL), and may store the candidate time of flight (ToF) corresponding to the SPAD pulse in units of subframes. The readout circuit 130 may send the candidate time of flight (ToF) stored in units of subframes to the image signal processor 150 under the control of the timing controller 140. In the present embodiment, for ease of explanation, the term "candidate time of flight (ToF)" may be used interchangeably with the term "time of flight (ToF)" as needed.

[0067] The timing controller 140 may generate timing signals to control the light source driver 30, the sensor driver 120, and the readout circuit 130. In some implementations, the timing controller 140 may generate timing signals according to a pre-stored sequence, data received from the readout circuit 130, and / or a request received from the image signal processor 150. In some implementations, the timing controller 140 may include: a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, etc.

[0068] The image signal processor 150 may perform at least one image signal processing on the image data (IDATA) received from the image sensing device 100, and thus may generate processed image data. The image signal processor 150 may reduce noise of the image data (IDATA), and may perform various image signal processing (e.g., interpolation of the image data (IDATA), lens distortion correction, etc.) for image quality improvement of the image data.

[0069] The image data (IDATA) may include candidate flight times (ToF) stored for each subframe. The image signal processor 150 may generate a histogram of one frame by accumulating data stored in units of subframes, and may determine a target flight time (ToF) of one frame based on the histogram. The target flight time (ToF) may be determined for each pixel (PX), and the image signal processor 150 may determine the target distance (i.e., the distance to the target object 1 detected by each pixel PX) based on the candidate target flight time (ToF) of each pixel (PX). The target distance set (or cluster) of pixels (PX) included in the pixel array 110 may be referred to as a depth image hereinafter and may be included in the processed image data.

[0070] The image signal processor 150 may transmit the processed image data to a host device (not shown). The host device (not shown) may include a processor (e.g., an application processor) for processing image data that has been image signal processed (ISP) received from the image signal processor 150, a memory (e.g., a nonvolatile memory) for storing the ISP image data, a display device (e.g., a liquid crystal display (LCD)) for visually displaying the ISP image data, and the like.

[0071] The image signal processor 150 may transmit a control signal for controlling the operation (whether to operate, operation timing, operation mode, etc.) of the image sensing device 100 to the image sensing device 100 .

[0072] Figure 2A is an example of some implementations based on the disclosed technology, included in Figure 1 A circuit diagram of an example of a first single photon avalanche diode (SPAD) included in a pixel (PX) in the pixel array 110 is shown.

[0073] Reference Figure 2A , is included in Figure 1 At least one pixel (PX) in the pixel array 110 may include a first SPAD (SPAD_C). The first SPAD (SPAD_C) may detect a single photon of the arriving light (RL) reflected by the target object (1), and may generate a first voltage pulse (PLS1) corresponding to the detected single photon. The first voltage pulse (PLS1) may have a pulse shape in which a voltage temporarily increases in response to the detection of the single photon.

[0074] The first SPAD (SPAD_C) can be operated as a photodiode including a photosensitive PN junction. In such a SPAD, avalanche breakdown is triggered by a single photon incident in Geiger mode, where a reverse bias voltage caused by a cathode-anode voltage higher than the breakdown voltage occurs. Under this design, the first SPAD (SPAD_C) can be operated to generate a first voltage pulse (PLS1), and the process of triggering avalanche breakdown by a single photon and generating a voltage pulse is defined as an avalanche process hereinafter.

[0075] The cathode of the first SPAD (SPAD_C) may receive a first bias voltage (VB1) for applying a reverse bias voltage to the first SPAD (SPAD_C), the first bias voltage allowing the first SPAD (SPAD_C) to operate in a Geiger mode. In some implementations, the first bias voltage (VB1) may be a voltage such that a value obtained by subtracting a voltage of the first node (N1) from the first bias voltage (VB1) is higher than a breakdown voltage (V B ). The voltage of the first node (N1) may be initialized to the quenching voltage by the operation of an external circuit (e.g., a quenching circuit) connected to the first node (N1). Therefore, the first bias voltage (VB1) may be a voltage such that a value obtained by subtracting the quenching voltage from the first bias voltage (VB1) is a voltage higher than the breakdown voltage. For example, when the quenching voltage is a ground voltage (e.g., 0 V), the first bias voltage (VB1) may be a breakdown voltage (V B ) and overvoltage (V EX ) is the sum of the overvoltage (V EX ) may be a predetermined voltage for operating the first SPAD (SPAD_C) in Geiger mode.

[0076] The avalanche breakdown of the first SPAD (SPAD_C) can be triggered by a single photon to increase the voltage of the first node (N1) by an excess voltage (V EX ). An external circuit (e.g., a quenching circuit) connected to the first node (N1) may initialize the voltage of the first node (N1) to a quenching voltage, thereby performing a quenching and recharging operation in which the first SPAD (SPAD_C) returns to the Geiger mode. Thus, a voltage having an overvoltage (V EX )'s amplitude.

[0077] Figure 2B is an example of some implementations based on the disclosed technology, included in Figure 1 A circuit diagram of an example of a second SPAD included in a pixel (PX) in the pixel array 110 is shown.

[0078] Reference Figure 2B , is included in Figure 1 At least one pixel (PX) in the pixel array 110 may include a second SPAD (SPAD_A). In some implementations, each of the pixels (PX) included in the pixel array 110 may include a first SPAD (SPAD_C) or a second SPAD (SPAD_A).

[0079] The second SPAD (SPAD_A) may detect a single photon of the arriving light (RL) reflected by the target object 1, and may generate a second voltage pulse (PLS2) corresponding to the detected single photon. The second voltage pulse (PLS2) may have a pulse shape in which the voltage temporarily drops in response to the detection of the single photon.

[0080] Since the overall operation and characteristics of the second SPAD (SPAD_A) are similar to those of the first SPAD (SPAD_C), redundant descriptions thereof will be omitted herein, and the following description will be given centering on characteristic operations different from those of the first SPAD (SPAD_C).

[0081] The anode of the second SPAD (SPAD_A) may receive a second bias voltage (VB2) for applying a reverse bias voltage to the second SPAD (SPAD_A), the second bias voltage allowing the second SPAD (SPAD_A) to operate in the Geiger mode. In some implementations, the second bias voltage (VB2) may be a voltage such that a value obtained by subtracting the second bias voltage (VB2) from a voltage of the second node (N2) is higher than a breakdown voltage (V B ). By the operation of an external circuit (e.g., a quenching circuit) connected to the second node (N2), the voltage of the second node (N2) may be initialized to the quenching voltage. Therefore, the second bias voltage (VB2) may be a voltage such that a value obtained by subtracting the second bias voltage (VB2) from the quenching voltage is a voltage higher than the breakdown voltage. For example, when the quenching voltage is a ground voltage (e.g., 0 V), the second bias voltage (VB2) may have a relative value to the breakdown voltage (V B ) and overvoltage (V EX ) is the negative voltage of the sum of B +V EX )). Here, the overvoltage (V EX ) may be a predetermined voltage for operating the second SPAD (SPAD_A) in Geiger mode.

[0082] The avalanche breakdown of the second SPAD (SPAD_A) can be triggered by a single photon to reduce the voltage of the second node (N2) by an excess voltage (V EX ). An external circuit (e.g., a quenching circuit) connected to the second node (N2) may initialize the voltage of the second node (N2) to the quenching voltage, thereby performing a quenching and recharging operation in which the second SPAD (SPAD_A) returns to the Geiger mode. Therefore, a voltage having an overvoltage (V EX)'s amplitude.

[0083] Figure 3 is a graph illustrating an example of comparison results of characteristics between a first SPAD (SPAD_C) and a second SPAD (SPAD_A) based on some implementations of the disclosed technology.

[0084] Figure 3 The graphs of φ show the sensitivity of the first SPAD (SPAD_C) and the sensitivity of the second SPAD (SPAD_A) with respect to illumination (also referred to as "illuminance"). Here, the sensitivity may also be defined as the photon detection efficiency (PDE).

[0085] If you can Figure 2A It can be seen that when an avalanche process occurs in the first SPAD (SPAD_C) operating in Geiger mode when receiving a first bias voltage (VB1) through its cathode, the first SPAD (SPAD_C) can generate a first voltage pulse (PLS1) in which the voltage of the first node (N1) temporarily increases. In implementation, the carriers introduced into the first node (N1) to allow the first SPAD (SPAD_C) to generate the first voltage pulse (PLS1) are holes serving as positive (+) charges. Since holes have a relatively low mobility, the first SPAD (SPAD_C) can have a relatively low sensitivity.

[0086] When an avalanche process occurs in the second SPAD (SPAD_A) operating in Geiger mode when receiving a second bias voltage (VB2) through its anode, the second SPAD (SPAD_A) can generate a second voltage pulse (PLS2) in which the voltage of the second node (N2) temporarily drops. In implementation, the carrier introduced into the second node (N2) to allow the second SPAD (SPAD_A) to generate the second voltage pulse (PLS2) is an electron serving as a negative (-) charge. Since electrons have a relatively high mobility, the second SPAD (SPAD_A) can have a relatively high sensitivity.

[0087] Therefore, the first sensitivity of the first SPAD (SPAD_C) is different from the second sensitivity of the second SPAD (SPAD_A). In implementation, the first sensitivity of the first SPAD (SPAD_C) may be lower than the second sensitivity of the second SPAD (SPAD_A).

[0088] Based on the sensitivity characteristics of the first SPAD (SPAD_C) and the second SPAD (SPAD_A), for a certain range of illumination, one of the first SPAD (SPAD_C) and the second SPAD (SPAD_A) may be more suitable than the other of the first SPAD (SPAD_C) and the second SPAD (SPAD_A). For example, for an illumination range that is smaller than a specific illumination (SL) arbitrarily determined within the illumination range that the first SPAD (SPAD_C) and the second SPAD (SPAD_A) can detect light (e.g., a specific illumination determined as an intermediate value), the intensity of the incident light is relatively weak. Therefore, in order to increase the signal-to-noise ratio (SNR), the second SPAD (SPAD_A) having a higher sensitivity may be more suitable than the first SPAD (SPAD_C).

[0089] On the contrary, for an illumination range higher than the specific illumination (SL), the intensity of the incident light is relatively strong. Therefore, in order to reduce the number of erroneous (or false) detections of signals (or pulses) due to ambient light, a first SPAD (SPAD_C) with lower sensitivity may be more suitable than a second SPAD (SPAD_A). The degree of erroneous signal detection due to ambient light may be defined as a dark count rate (DCR).

[0090] In this way, since the first SPAD (SPAD_C) or the second SPAD (SPAD_A) may be more suitable depending on illumination conditions, the pixel array 110 includes both the first SPAD (SPAD_C) and the second SPAD (SPAD_A), and at least one of the first SPAD (SPAD_C) or the second SPAD (SPAD_A) may be selectively activated.

[0091] Figure 4A is an example of some implementations based on the disclosed technology, Figure 1 FIG. 4 is a diagram of an example of an array structure 400 a of the pixel array 110 shown.

[0092] Reference Figure 4A , the array structure 400a of the pixel array 110 may represent a portion of the pixel array 110, and the array structure 400a of the pixel array 110 may have a structure in which the array structure 400a is repeatedly arranged in each of a row direction and a column direction. Figure 4A Each pixel shown may have either a first SPAD (SPAD_C) or a second SPAD (SPAD_A), and thus the pixels may be distinguished by the type of SPAD included therein. For ease of description, SPAD type indication (SPAD_C, SPAD_A) and pixel type indication (SPAD_C, SPAD_A) may be used interchangeably. Figure 4A , the area represented by SPAD_C may refer to a first pixel (SPAD_C), which is a pixel including a first SPAD (SPAD_C), and the area represented by SPAD_A may refer to a second pixel (SPAD_A), which is a pixel including a second SPAD (SPAD_A).

[0093] The array structure 400a includes: first pixels (SPAD_C) arranged in a (4×2) matrix including four rows and two columns; and second pixels (SPAD_A) arranged in a (4×2) matrix including four rows and two columns. The first pixels (SPAD_C) arranged in the (4×2) matrix may form one block, and the second pixels (SPAD_A) arranged in the (4×2) matrix may form another block.

[0094] In an example, in the array structure 400a, a plurality of first pixels (SPAD_C) or a plurality of second pixels (SPAD_A) may be arranged in units of blocks (on a block basis). Figure 4A The example shows that one block includes pixels arranged in a (4×2) matrix structure, but other implementations are also possible. For example, without being limited to the (4×2) matrix structure, one block includes pixels arranged in a (M×N) matrix structure (wherein at least one of M and N is a natural number of 2 or greater).

[0095] According to the array structure 400a, pixels of the same type can be arranged adjacent to each other while minimizing the size of the area in which pixels of different types contact each other. By doing so, circuits for signal processing of pixels of the same type can be arranged more easily.

[0096] Figure 4B is an example of some implementations based on the disclosed technology, Figure 1 A diagram of another example of the array structure of a pixel array shown.

[0097] Reference Figure 4B , the array structure 400 b of the pixel array 110 may represent a portion of the pixel array 110 , and the array structure 400 b of the pixel array 110 may have a structure in which the array structure 400 b is arranged along the row direction and the column direction. Figure 4B Each pixel shown may have either a first SPAD (SPAD_C) or a second SPAD (SPAD_A), and thus the pixels may be distinguished by the type of SPAD included therein. For ease of description, SPAD type indication (SPAD_C, SPAD_A) and pixel type indication (SPAD_C, SPAD_A) may be used interchangeably. Figure 4B, the area represented by SPAD_C may refer to a first pixel (SPAD_C), which is a pixel including a first SPAD (SPAD_C), and the area represented by SPAD_A may refer to a second pixel (SPAD_A), which is a pixel including a second SPAD (SPAD_A).

[0098] The array structure 400b may include a first pixel (SPAD_C) and a second pixel (SPAD_A) alternately arranged in a row direction and a column direction. In the array structure 400b, the first pixels (SPAD_C) may be arranged adjacent to each other in a diagonal direction and spaced apart from each other by a distance of one pixel in a row direction or a column direction (hereinafter referred to as a pixel distance). In addition, the second pixels (SPAD_A) may be arranged adjacent to each other in a diagonal direction and spaced apart from each other by a distance of one pixel in a row direction or a column direction (ie, a pixel distance). Here, the pixel distance may refer to the width of the first pixel (SPAD_C) or the width of the second pixel (SPAD_A).

[0099] According to the array structure 400b, different types of pixels can be evenly arranged per unit area (e.g., 2×2 matrix), so that image processing (e.g., interpolation, etc.) can be performed more easily and the defocus phenomenon in which the lens module 20 incorrectly focuses on a specific block can be reduced.

[0100] Figure 5 is an example of some implementations based on the disclosed technology, Figure 4A A diagram of an example of a sensor layer and a logic layer of an array structure 400a is shown.

[0101] Reference Figure 4A and Figure 5 , the array structure 400a may have a stacked structure including a sensor layer and a logic layer. In implementation, the sensor layer may be disposed closer to the lens module 20 at an upper portion of the logic layer, and the logic layer may be disposed farther from the lens module 20 at a lower portion of the sensor layer. The sensor layer and the logic layer may correspond to different semiconductor substrates, and the electrical connection between the sensor layer and the logic layer may be implemented using a through silicon via (TSV) method or a bonding method (e.g., hybrid bonding, thermal compression (TC) bonding, etc.), etc.

[0102] The sensor layer may include a first SPAD (SPAD_C) and a second SPAD (SPAD_A) arranged in a format corresponding to the array structure 400 a .

[0103] The logic layer may include one or more circuits for driving a first SPAD (SPAD_C) or processing a signal output from the first SPAD (SPAD_C) (hereinafter collectively referred to as the "first SPAD circuit (SPAD_C circuit)"), and one or more circuits for driving a second SPAD (SPAD_A) or processing a signal output from the second SPAD (SPAD_A) (hereinafter collectively referred to as the "second SPAD circuit (SPAD_A circuit)").

[0104] The SPAD included in the sensor layer and the SPAD circuit included in the logic layer may correspond to each other according to a predetermined rule.

[0105] In some implementations, the SPADs of the sensor layer arranged in a (2×2) matrix and the SPAD circuits of the logic layer may be disposed at corresponding positions while having substantially the same area. For example, the SPADs of the sensor layer included in the first pixel group (PG1) and arranged in a (2×2) matrix are disposed at the upper left portion of the sensor layer, and the SPAD_C circuits corresponding to those SPADs in the first pixel group (PG1) are disposed at the upper left portion of the logic layer.

[0106] exist Figure 5 In the example of , the first SPAD (SPAD_C) arranged in a (2×2) matrix included in the first pixel group (PG1) and the first SPAD circuit (SPAD_C circuit) for the first SPAD (SPAD_C) of the first pixel group (PG1) may be arranged to overlap each other while having substantially the same area. Although the first pixel group (PG1) has been described as an example for ease of description, other pixels may also be arranged in units of a (2×2) matrix in substantially the same shape as the first pixel group (PG1).

[0107] According to Figure 5 The arrangement structure shown can further ensure the design margin of the first SPAD circuit (SPAD_C circuit) when the first SPADs (SPAD_C) of the first pixel group (PG1) share at least a portion of the first SPAD circuit (SPAD_C circuit).

[0108] Figure 6 is an example of some implementations based on the disclosed technology, Figure 4B A diagram of an example of a sensor layer and a logic layer of an array structure 400b is shown.

[0109] Reference Figure 4B and Figure 6, the array structure 400b may have a stacked structure including a sensor layer and a logic layer. In implementation, the sensor layer may be disposed closer to the lens module 20 at an upper portion of the logic layer, and the logic layer may be disposed further away from the lens module 20 at a lower portion of the sensor layer. The sensor layer and the logic layer may correspond to different semiconductor substrates, and the electrical connection between the sensor layer and the logic layer may be implemented using a through silicon via (TSV) method or a bonding method (e.g., hybrid bonding, thermal compression (TC) bonding, etc.), etc.

[0110] The sensor layer may include a first SPAD (SPAD_C) and a second SPAD (SPAD_A) arranged in a format corresponding to the array structure 400 b .

[0111] The logic layer may include one or more first SPAD circuits (SPAD_C circuits) for driving a first SPAD (SPAD_C) or processing a signal output from the first SPAD (SPAD_C), and one or more second SPAD circuits (SPAD_A circuits) for driving a second SPAD (SPAD_A) or processing a signal output from the second SPAD (SPAD_A).

[0112] The SPAD included in the sensor layer and the SPAD circuit included in the logic layer may correspond to each other according to a predetermined rule.

[0113] In some implementations, the SPADs arranged in the diagonal direction of the sensor layer and the SPAD circuits of the logic layer can be arranged to partially overlap each other while having substantially the same area. Figure 6 In the implementation shown, although the second pixel group (PG2) includes two first SPADs (SPAD_C) arranged in a diagonal direction, only one of the first SPADs (SPAD_C) of the second pixel group (PG2) located at the upper left corner of the sensor layer overlaps with the first SPAD circuit (SPAD_C circuit) of the logic layer. Figure 6 In the illustrated implementation, although the second pixel group (PG2) includes two second SPADs (SPAD_A) arranged in a diagonal direction, only one of the second SPADs (SPAD_A) of the second pixel group (PG2) overlaps with the second SPAD circuit (SPAD_A circuit) of the logic layer.

[0114] exist Figure 6In the example, the first SPAD (SPAD_C) arranged diagonally included in the second pixel group (PG2) and the first SPAD circuit (SPAD_C circuit) of the first SPAD (SPAD_C) for the second pixel group (PG2) can be arranged to partially overlap each other while having substantially the same area. In addition, the second SPAD (SPAD_A) arranged diagonally included in the second pixel group (PG2) and the second SPAD circuit (SPAD_A circuit) of the second SPAD (SPAD_A) for the second pixel group (PG2) can be arranged to partially overlap each other while having substantially the same area. Although the second pixel group (PG2) has been described as an example for ease of description, other pixels may also be arranged in units of a (2×2) matrix in substantially the same shape as the second pixel group (PG2).

[0115] According to Figure 6 In the arrangement structure shown, when the first SPAD (SPAD_C) of the second pixel group (PG2) shares at least a portion of the first SPAD circuit (SPAD_C circuit), the design margin of the first SPAD circuit (SPAD_C circuit) can be further ensured. In addition, when the second SPAD (SPAD_A) of the second pixel group (PG2) shares at least a portion of the second SPAD circuit (SPAD_A circuit), the design margin of the second SPAD circuit (SPAD_A circuit) can be further ensured.

[0116] Fig. 7A is an example of some implementations based on the disclosed technology, included in Figure 1 A circuit diagram of an example operation of a pixel in a pixel array is shown.

[0117] Reference Fig. 7A , a first pixel signal processing path 700-1 for processing signals generated from a first SPAD (SPAD_C) and a second SPAD (SPAD_A) is shown. Although the first pixel signal processing path 700-1 is illustrated with one first SPAD (SPAD_C) and one second SPAD (SPAD_A), other implementations are possible. For example, it should be noted that the first pixel signal processing path 700-1 can include multiple first SPADs (SPAD_C) and / or multiple second SPADs (SPAD_A) as needed.

[0118] The first pixel signal processing path 700-1 may include a first SPAD (SPAD_C), a second SPAD (SPAD_A), a first quenching transistor (QX_C), a second quenching transistor (QX_A), a first control transistor (CX_C), a second control transistor (CX_A), a mode selector 710, a first buffer (BF1), a first inverter (IV1), a time-to-digital converter (TDC) 720, and a TDC memory 730. Here, the first SPAD (SPAD_C), the first quenching transistor (QX_C), the first control transistor (CX_C), and the first buffer (BF1) may be included in the first SPAD pixel 701. The second SPAD (SPAD_A), the second quenching transistor (QX_A), the second control transistor (CX_A), and the first inverter (IV1) may be included in the second SPAD pixel 702.

[0119] The first SPAD (SPAD_C) may correspond to Figure 2A The first SPAD (SPAD_C) shown, and the second SPAD (SPAD_A) may correspond to Figure 2B The second SPAD (SPAD_A) is shown.

[0120] The first quenching transistor (QX_C) may be an N-channel MOSFET (NMOS) transistor including a gate terminal receiving a quenching control signal (Rq), a drain terminal connected to the first node (N1), and a source terminal receiving a quenching voltage (Vq). The quenching control signal (Rq) may have a first voltage higher than the quenching voltage (Vq) by a threshold voltage (or the threshold voltage or more) of the first quenching transistor (QX_C), a second voltage equal to the quenching voltage (Vq), or a third voltage lower than the quenching voltage (Vq) by a threshold voltage (or the threshold voltage or less) of the second quenching transistor (QX_A).

[0121] When the quenching control signal (Rq) has a first voltage, the first quenching transistor (QX_C) is turned on and can supply the quenching voltage (Vq) to the first node (N1). Alternatively, when the quenching control signal (Rq) has a second voltage or a third voltage, the first quenching transistor (QX_C) can be turned off so as not to supply the quenching voltage (Vq) to the first node (N1).

[0122] The second quenching transistor (QX_A) may be a P-channel MOSFET (PMOS) transistor including a gate terminal receiving a quenching control signal (Rq), a drain terminal connected to the second node (N2), and a source terminal receiving a quenching voltage (Vq).

[0123] When the quenching control signal (Rq) has the third voltage, the second quenching transistor (QX_A) is turned on and can supply the quenching voltage (Vq) to the second node (N2). Alternatively, when the quenching control signal (Rq) has the first voltage or the second voltage, the second quenching transistor (QX_A) can be turned off so as not to supply the quenching voltage (Vq) to the second node (N2).

[0124] The first control transistor (CX_C) may be a PMOS transistor including a gate terminal receiving a selection signal (RS), a drain terminal connected to a cathode of the first SPAD (SPAD_C), and a source terminal receiving a mode selection voltage (V_MS). The mode selection voltage (V_MS) may have a first bias voltage (VB1) higher than the selection signal (RS) by a threshold voltage of the first control transistor (CX_C) or more, a deactivation voltage equal to the selection signal (RS), or a second bias voltage (VB2) lower than the selection signal (RS) by a threshold voltage of the second control transistor (CX_A) or less.

[0125] When the mode selection voltage (V_MS) has a first bias voltage (VB1), the first control transistor (CX_C) is turned on to supply the first bias voltage (VB1) to the cathode of the first SPAD (SPAD_C). Alternatively, when the mode selection voltage (V_MS) has a second bias voltage (VB2) or a deactivation voltage, the first control transistor (CX_C) may be turned off so as not to supply the first bias voltage (VB1) to the cathode of the first SPAD (SPAD_C).

[0126] The second control transistor (CX_A) may be an NMOS transistor including a gate terminal receiving a selection signal (RS), a drain terminal connected to an anode of the second SPAD (SPAD_A), and a source terminal receiving a mode selection voltage (V_MS).

[0127] When the mode selection voltage (V_MS) has the second bias voltage (VB2), the second control transistor (CX_A) is turned on to supply the second bias voltage (VB2) to the anode of the second SPAD (SPAD_A). Alternatively, when the mode selection voltage (V_MS) has the first bias voltage (VB1) or the deactivation voltage, the second control transistor (CX_A) may be turned off so as not to supply the second bias voltage (VB2) to the anode of the second SPAD (SPAD_A).

[0128] In this embodiment, for ease of description, it is assumed that each of the quenching voltage (Vq) and the selection signal (RS) has a ground voltage (e.g., 0V), but other implementations are possible. For example, the quenching voltage (Vq) and the selection signal (RS) can be changed within the operable range of the SPAD (SPAD_C, SPAD_A) and the transistor (CX_C, CX_A, QX_C, QX_A).

[0129] In addition, the first control transistor (CX_C) and the second control transistor (CX_A) may be referred to as a control circuit for selectively activating the first SPAD (SPAD_C) and the second SPAD (SPAD_A), the first control transistor (CX_C) and the second control transistor (CX_A) are merely examples of such a control circuit, and the scope of the configuration for selectively activating the first SPAD (SPAD_C) and the second SPAD (SPAD_A) is not limited thereto.

[0130] The mode selector 710 may be included as Figure 1 The quenching voltage (Vq), the quenching control signal (Rq), and the selection signal (RS) supplied to the first SPAD pixel 701 and the second SPAD pixel 702 may be supplied from the sensor driver 120 .

[0131] The mode selector 710 may generate a mode selection voltage (V_MS) according to a mode selection signal (MS). The mode selection signal (MS) may be generated by the image sensing device 100, the image signal processor 150, or an external device (eg, an application processor) using illumination information.

[0132] The illuminance information may include an illuminance value output by an illuminance sensor (not shown) included in the imaging device (ID) and / or an illuminance value estimated according to the frequency of occurrence of the image data (IDATA) per subframe. Here, the illuminance sensor (not shown) may detect light of a specific wavelength band (e.g., light having the same wavelength band as the light emitted by the light source 10), and may output an illuminance value in response to the detected light. To this end, the illuminance sensor (not shown) may include an optical filter for selectively receiving light of a specific wavelength band.

[0133] The illumination information may be an example of information used as a basis for the mode selection signal (MS). According to another embodiment, other information (e.g., power information indicating a power consumption state of the imaging device ID, user selection information indicating a mode selected by a user, and temperature information indicating a temperature state of the imaging device ID) may also be used as a basis for the mode selection signal (MS). According to yet another embodiment, the mode selection signal (MS) may be determined based on at least one of the illumination information, the power information, the user selection information, or the temperature information.

[0134] When the illuminance value is greater than or equal to a predetermined threshold illuminance (or when the current illuminance is a first illuminance greater than or equal to the predetermined threshold illuminance), the mode selection signal (MS) may be at a logic high level. Here, the threshold may be a value determined experimentally so that the suitability of the first SPAD (SPAD_C) for detecting the arriving light (RL) is equal to the suitability of the second SPAD (SPAD_A) for detecting the arriving light (RL). The mode selector 710 receiving the mode selection signal (MS) at a logic high level may output a first bias voltage (VB1).

[0135] When the first bias voltage (VB1) is applied to each of the first control transistor (CX_C) and the second control transistor (CX_A), the first control transistor (CX_C) may be turned on and the second control transistor (CX_A) may be turned off. Therefore, the first SPAD (SPAD_C) may enter the Geiger mode, while the second SPAD (SPAD_A) may not enter the Geiger mode. When a photon is incident on the first SPAD (SPAD_C), an avalanche process may occur so that the voltage of the first node (N1) may increase by an overvoltage (V EX ). The quenching control signal (Rq) may be transitioned from the second voltage to the first voltage at a predetermined time point (e.g., a time point at which the avalanche process is completed), thereby performing a quenching operation and a recharging operation of the first SPAD (SPAD_C). As a result, the voltage of the first node (N1) may return to the quenching voltage (Vq), and a first voltage pulse (PLS1) may be output from the first node (N1). In addition, when the quenching operation and the recharging operation of the first SPAD (SPAD_C) are completed, the quenching control signal (Rq) may be transitioned from the first voltage to the second voltage.

[0136] When the illuminance value is less than the predetermined threshold illuminance (or when the current illuminance is a second illuminance less than the predetermined threshold illuminance), the mode selection signal (MS) may be at a logic low level. The mode selector 710 receiving the logic low level mode selection signal (MS) may output a second bias voltage (VB2).

[0137] When the second bias voltage (VB2) is applied to each of the first control transistor (CX_C) and the second control transistor (CX_A), the first control transistor (CX_C) may be turned off and the second control transistor (CX_A) may be turned on. Therefore, the first SPAD (SPAD_C) may not enter the Geiger mode, while the second SPAD (SPAD_A) may enter the Geiger mode. When a photon is incident on the second SPAD (SPAD_A), an avalanche process may occur so that the voltage of the second node (N2) may drop by more than the voltage (V EX ). The quenching control signal (Rq) may be transitioned from the second voltage to the third voltage at a predetermined time point (e.g., a time point at which the avalanche process is completed), thereby performing a quenching operation and a recharging operation of the second SPAD (SPAD_A). As a result, the voltage of the second node (N2) may return to the quenching voltage (Vq), and a second voltage pulse (PLS2) may be output from the second node (N2). In addition, when the quenching operation and the recharging operation of the second SPAD (SPAD_A) are completed, the quenching control signal (Rq) may be transitioned from the third voltage to the second voltage.

[0138] That is, the mode selector 710 can activate the first SPAD (SPAD_C) or the second SPAD (SPAD_A) by generating a mode selection voltage (V_MS) based on a mode selection signal (MS) that changes according to the illumination. Therefore, the activated first SPAD (SPAD_C) can detect photons incident thereon and can output a first voltage pulse (PLS1), or the activated second SPAD (SPAD_A) can detect photons incident thereon and can output a second voltage pulse (PLS2).

[0139] The first buffer (BF1) can sample the analog first voltage pulse (PLS1) generated at the first node (N1), can convert the analog first voltage pulse (PLS1) into a digital pulse signal having a waveform opposite to the first voltage pulse (PLS1), and can invert and output the digital pulse signal having a waveform opposite to the first voltage pulse (PLS1). To this end, the first buffer BF1 may include two inverters connected in cascade. Here, the sampling method can be implemented as a method of converting a voltage pulse into a pulse signal with a logic level of 0 or 1 depending on whether the level of the voltage pulse is equal to or greater than a threshold level, but the scope of the disclosed technology is not limited thereto. The first voltage pulse (PLS1) generated at the first node (N1) may have a waveform in which the first voltage pulse (PLS1) increases instantaneously from the quenching voltage (Vq) through an avalanche process, and then returns to the quenching voltage (Vq) through a quenching operation and a recharging operation. Therefore, since the first inverter of the first buffer (BF1) converts the voltage pulse into a digital pulse signal having a waveform opposite to the first voltage pulse (PLS1), the output signal of the first inverter may have a waveform in which the output signal of the first inverter has a logic level 1, then instantaneously transitions to a logic level 0 in response to the generation of the first voltage pulse (PLS1), and finally returns to a logic level 1. The second inverter of the first buffer (BF1) may invert a digital pulse signal having a waveform opposite to the first voltage pulse (PLS1) received through the first inverter, and may output an inverted digital pulse signal. That is, the output signal of the second inverter may have a waveform in which the output signal of the second inverter has a logic level 0, then instantaneously transitions to a logic level 1 in response to the generation of the first voltage pulse (PLS1), and then returns to a logic level 0.

[0140] The output signal of the first buffer (BF1) may be referred to as a first SPAD pulse serving as a digitized pulse of the first voltage pulse (PLS1).

[0141] The first inverter (IV1) can sample the analog second voltage pulse (PLS2) generated at the second node (N2), and can convert the analog second voltage pulse (PLS2) into a digital pulse signal having a waveform opposite to that of the second voltage pulse (PLS2). The second voltage pulse (PLS2) generated at the second node (N2) can have a waveform in which the second voltage pulse (PLS2) immediately drops from the quenching voltage (Vq) through an avalanche process, and then returns to the quenching voltage (Vq) through a quenching operation and a recharging operation. Therefore, since the first inverter (IV1) converts the voltage pulse into a digital pulse signal having a waveform opposite to that of the second voltage pulse (PLS2), the output signal of the first inverter (IV1) can have a waveform in which the output signal of the first inverter (IV1) has a logic level 0, then instantly transitions to a logic level 1 when the second voltage pulse (PLS2) is generated, and finally returns to a logic level 0.

[0142] The output signal of the first inverter ( IV1 ) may be referred to as a second SPAD pulse which is used as a digitized pulse of the second voltage pulse ( PLS2 ).

[0143] The first SPAD pulse output from the first SPAD pixel 701 and the second SPAD pulse output from the second SPAD pixel 702 may be transmitted to the TDC 720 as a pixel signal (PX_OUT).

[0144] The TDC 720 may calculate the time delay between the pulse of the pixel signal (PX_OUT) and the reference pulse of the emission light (EL), and may generate TDC data representing the time delay. The TDC 720 may obtain the time point of generating the reference pulse of the emission light (EL) from the timing controller 140 that controls the light source driver 30, or may regard a predetermined time point (e.g., a time point before a predetermined time from the start point of the subframe) as the generation time point of the reference pulse. The TDC data output by the TDC 720 may represent the candidate time of flight (ToF) described above.

[0145] The TDC 720 may be activated or deactivated according to a TDC enable signal supplied from the timing controller 140. The TDC enable signal may have an activation level (e.g., logic level 1) when it is necessary to generate TDC data of the pixel 701 or 702 (e.g., during each subframe), and may have a deactivation level (e.g., logic level 0) when it is not necessary to generate TDC data of the pixel 701 or 702.

[0146] The TDC memory 730 may store TDC data, and may output the stored TDC data as image data to the image signal processor 150 in predetermined units (eg, in sub-frame units).

[0147] The TDC 720 and the TDC memory 730 may be included in Figure 1 The readout circuit 130 may be provided to correspond to one column of the pixel array 110, but the scope of the disclosed technology is not limited thereto.

[0148] According to this embodiment, a SPAD suitable for the current illumination among the first SPAD (SPAD_C) and the second SPAD (SPAD_A) having different sensitivities can be selectively activated, and the activated SPAD can be used to detect the distance to the target object 1, so that unnecessary power consumption can be reduced and the distance to the target object 1 can be measured more accurately.

[0149] Figure 7B is an example of some implementations based on the disclosed technology, included in Figure 1 A circuit diagram of an example operation of a pixel in a pixel array is shown.

[0150] Reference Figure 7B , a second pixel signal processing path 700-2 for processing signals generated from a first SPAD (SPAD_C) and a second SPAD (SPAD_A) is shown. Although the second pixel signal processing path 700-2 is illustrated as including one first SPAD (SPAD_C) and one second SPAD (SPAD_A), other implementations are possible, and it should be noted that the second pixel signal processing path 700-2 may include multiple first SPADs (SPAD_C) and / or multiple second SPADs (SPAD_A) as desired.

[0151] Except for some differences, the second pixel signal processing path 700-2 is similar to Fig. 7A The first pixel signal processing path 700-1 is substantially the same as that of the first pixel signal processing path 700-1, and for the sake of brevity, its redundant description will be omitted herein. Fig. 7A The characteristics of different characteristics are described as the center Figure 7B The second pixel signal processing path 700-2.

[0152] The first control transistor (CX_C) may be a PMOS transistor including a gate terminal receiving a mode selection voltage (V_MS'), a drain terminal connected to a cathode of the first SPAD (SPAD_C), and a source terminal receiving a first bias voltage (VB1). The mode selection voltage (V_MS') may have a first activation voltage lower than the first bias voltage (VB1) by a threshold voltage of the first control transistor (CX_C) or less, or a second activation voltage higher than the second bias voltage (VB2) by a threshold voltage of the second control transistor (CX_A) or more.

[0153] When the mode selection voltage (V_MS') has a first activation voltage, the first control transistor (CX_C) is turned on to supply the first bias voltage (VB1) to the cathode of the first SPAD (SPAD_C). Alternatively, when the mode selection voltage (V_MS') has a second activation voltage, the first control transistor (CX_C) may be turned off so as not to supply the first bias voltage (VB1) to the cathode of the first SPAD (SPAD_C).

[0154] The second control transistor (CX_A) may be an NMOS transistor including a gate terminal receiving the mode selection voltage (V_MS′), a drain terminal connected to the anode of the second SPAD (SPAD_A), and a source terminal receiving the second bias voltage (VB2).

[0155] When the mode selection voltage (V_MS') has the second activation voltage, the second control transistor (CX_A) is turned on to supply the second bias voltage (VB2) to the anode of the second SPAD (SPAD_A). Alternatively, when the mode selection voltage (V_MS') has the first activation voltage, the second control transistor (CX_A) may be turned off so as not to supply the second bias voltage (VB2) to the anode of the second SPAD (SPAD_A).

[0156] The first control transistor (CX_C) and the second control transistor (CX_A) may be referred to as a control circuit for selectively activating the first SPAD (SPAD_C) and the second SPAD (SPAD_A), the first control transistor (CX_C) and the second control transistor (CX_A) are merely examples of such a control circuit, and the scope of the configuration for selectively activating the first SPAD (SPAD_C) and the second SPAD (SPAD_A) is not limited thereto.

[0157] The mode selector 710 may generate a mode selection voltage (V_MS′) according to a mode selection signal (MS).

[0158] When the illuminance value is greater than or equal to the predetermined threshold illuminance (or when the current illuminance is the first illuminance greater than or equal to the predetermined threshold illuminance), the mode selection signal (MS) may be at a logic high level. The mode selector 710 receiving the mode selection signal (MS) of the logic high level may output a first activation voltage.

[0159] When a first activation voltage is applied to each of the first control transistor (CX_C) and the second control transistor (CX_A), the first control transistor (CX_C) may be turned on and the second control transistor (CX_A) may be turned off. Therefore, the first SPAD (SPAD_C) may enter the Geiger mode, while the second SPAD (SPAD_A) may not enter the Geiger mode. When a photon is incident on the first SPAD (SPAD_C), an avalanche process may occur so that the voltage of the first node (N1) may increase by an overvoltage (V EX ). The quenching control signal (Rq) may be transitioned from the second voltage to the first voltage at a predetermined time point (e.g., a time point at which the avalanche process is completed), thereby performing a quenching operation and a recharging operation of the first SPAD (SPAD_C). As a result, the voltage of the first node (N1) may return to the quenching voltage (Vq), and a first voltage pulse (PLS1) may be output from the first node (N1). In addition, when the quenching operation and the recharging operation of the first SPAD (SPAD_C) are completed, the quenching control signal (Rq) may be transitioned from the first voltage to the second voltage.

[0160] When the illuminance value is less than the predetermined threshold illuminance (or when the current illuminance is a second illuminance less than the predetermined threshold illuminance), the mode selection signal (MS) may be at a logic low level. The mode selector 710 receiving the logic low level mode selection signal (MS) may output a second activation voltage.

[0161] When the second activation voltage is applied to each of the first control transistor (CX_C) and the second control transistor (CX_A), the first control transistor (CX_C) may be turned off and the second control transistor (CX_A) may be turned on. Therefore, the first SPAD (SPAD_C) may not enter the Geiger mode, while the second SPAD (SPAD_A) may enter the Geiger mode. When a photon is incident on the second SPAD (SPAD_A), an avalanche process may occur so that the voltage of the second node (N2) may drop by more than the voltage (V EX ). The quenching control signal (Rq) may be transitioned from the second voltage to the third voltage at a predetermined time point (e.g., a time point at which the avalanche process is completed), thereby performing a quenching operation and a recharging operation of the second SPAD (SPAD_A). As a result, the voltage of the second node (N2) may return to the quenching voltage (Vq), and a second voltage pulse (PLS2) may be output from the second node (N2). In addition, when the quenching operation and the recharging operation of the second SPAD (SPAD_A) are completed, the quenching control signal (Rq) may be transitioned from the third voltage to the second voltage.

[0162] That is, the mode selector 710 can activate the first SPAD (SPAD_C) or the second SPAD (SPAD_A) by generating a mode selection voltage (V_MS') based on a mode selection signal (MS) that changes according to the illumination. Therefore, the activated first SPAD (SPAD_C) can detect photons incident thereon and can output a first voltage pulse (PLS1), or the activated second SPAD (SPAD_A) can detect photons incident thereon and can output a second voltage pulse (PLS2).

[0163] Figure 7C is an example of some implementations based on the disclosed technology, included in Figure 1 A circuit diagram of an example operation of a pixel in a pixel array is shown.

[0164] Reference Figure 7C , a third pixel signal processing path 700-3 for processing signals generated from a first SPAD (SPAD_C) and a second SPAD (SPAD_A) is shown. Although the third pixel signal processing path 700-3 is illustrated with one first SPAD (SPAD_C) and one second SPAD (SPAD_A), other implementations are possible, and it should be noted that the third pixel signal processing path 700-3 may include multiple first SPADs (SPAD_C) and / or multiple second SPADs (SPAD_A) as desired.

[0165] The third pixel signal processing path 700-3 may include: a first SPAD (SPAD_C), a second SPAD (SPAD_A), a first quenching transistor (QX_C), a second quenching transistor (QX_A), a second buffer (BF2), a second inverter (IV2), an output selector 750, a TDC 760, and a TDC memory 770. Here, the first SPAD (SPAD_C), the first quenching transistor (QX_C), and the second buffer (BF2) may be included in the first SPAD pixel 703. The second SPAD (SPAD_A), the second quenching transistor (QX_A), and the second inverter (IV2) may be included in the second SPAD pixel 704.

[0166] Apart from some differences, Figure 7C The third pixel signal processing path 700-3 and Fig. 7A The first pixel signal processing path 700-1 is similar to the first pixel signal processing path 700-1, and for the sake of brevity, its redundant description will be omitted herein. Fig. 7A The characteristics of different characteristics are described as the center Figure 7C The third pixel signal processing path 700-3.

[0167] The third pixel signal processing path 700-3 may not include the mode selector 710 and the control transistors (CX_C, CX_A). That is, the first SPAD (SPAD_C) and the second SPAD (SPAD_A) may receive the first bias voltage (VB1) and the second bias voltage (VB2), respectively. Therefore, regardless of the mode, the first SPAD (SPAD_C) and the second SPAD (SPAD_A) may enter the Geiger mode so that the first SPAD pixel 703 may independently generate the first SPAD pulse according to the photon detection, and the second SPAD pixel 704 may independently generate the second SPAD pulse according to the photon detection.

[0168] The operations of the second buffer (BF2) and the second inverter (IV2) may be substantially the same as the operations of the first buffer (BF1) and the first inverter (IV1), respectively.

[0169] The output selector 750 may select at least one of the first SPAD pulse and the second SPAD pulse as a pixel signal (PX_OUT) according to a mode selection signal (MS), and may output the selected SPAD pulse.

[0170] When the illuminance value is greater than or equal to a predetermined threshold illuminance, the mode selection signal (MS) may be at a logic high level. The output selector 750 receiving the mode selection signal (MS) at a logic high level may output a first SPAD pulse as a pixel signal (PX_OUT).

[0171] When the illuminance value is less than a predetermined threshold illuminance, the mode selection signal (MS) may be at a logic low level. The output selector 750 receiving the mode selection signal (MS) at a logic low level may output a second SPAD pulse as a pixel signal (PX_OUT).

[0172] According to another embodiment, when the illuminance value is within a predetermined range of a predetermined threshold illuminance or when there is a request from an external device, the mode selection signal (MS) may be at a third logic level. The output selector 750 receiving the mode selection signal (MS) of the third logic level may output each of the first SPAD pulse and the second SPAD pulse as a pixel signal (PX_OUT). At this time, each of the first SPAD pulse and the second SPAD pulse may be output through an independent signal line, or may be output sequentially through one signal line.

[0173] Figure 7C The operation of TDC 760 and TDC memory 770 can be respectively related to Fig. 7A The operations of the TDC 720 and the TDC memory 730 are substantially the same.

[0174] The image sensing device according to the present embodiment can use the SPAD more suitable for the current illumination among the first SPAD (SPAD_C) and the second SPAD (SPAD_A) having different sensitivities to detect the distance of the target object 1. If necessary, the image sensing device can use both the first SPAD (SPAD_C) and the second SPAD (SPAD_A) to detect the distance of the target object 1, thereby obtaining a more accurate distance.

[0175] In this embodiment, the image sensing device selects any one of the first SPAD pixel including the first SPAD (SPAD_C) and the second SPAD pixel including the second SPAD (SPAD_A) according to the illumination information. Fig. 7A and Figure 7B An embodiment is shown in which the first SPAD pixel 701 or the second SPAD pixel 702 is selected by activating the first SPAD pixel 701 or the second SPAD pixel 702 . Figure 7C An embodiment of selecting the output signal of at least one of the first SPAD pixel 703 or the second SPAD pixel 704 is shown.

[0176] Figure 7C The output selector 750 and Fig. 7A or Figure 7B Each of the mode selectors 710 may be collectively referred to as a selection circuit or included in a selection circuit because each of the output selector 750 or the mode selector 710 may select the first SPAD pixel or the second SPAD pixel.

[0177] Fig. 8A is a schematic diagram illustrating examples of sensor layers based on some implementations of the disclosed technology.

[0178] Fig. 8A A cross-sectional structure 800 - 1 schematically showing a region corresponding to the second SPAD (SPAD_A) among the sensor layers is illustrated.

[0179] The cross-sectional structure 800 - 1 may include a semiconductor substrate 802 , a microlens 804 , and a first optical structure 810 .

[0180] The semiconductor substrate 802 may include a top surface and a bottom surface facing away from each other. For example, the semiconductor substrate 802 may be or include a P-type or N-type bulk substrate, may be or include a substrate formed by growing a P-type or N-type epitaxial layer on a P-type bulk substrate, or may be or include a substrate formed by growing a P-type or N-type epitaxial layer on an N-type bulk substrate. The second SPAD (SPAD_A) may be formed inside the semiconductor substrate 802, and will be described later with reference to the following. Fig.9AThe specific structure of the second SPAD (SPAD_A) is described with reference to FIG. The semiconductor substrate 802 may include at least one of silicon (Si), silicon carbide (SiC) or gallium nitride (GaN).

[0181] The microlens 804 may be formed below the semiconductor substrate 802 and may be formed in a convex hemispherical shape so that the microlens 804 can increase light receiving (Rx) efficiency by increasing the light focusing power of the incident light. An outer coating (not shown) may be additionally formed above or below the microlens 804 so that the outer coating can suppress flare characteristics by preventing irregular reflection or diffuse reflection of the incident light received from the lens module 20.

[0182] The first optical structure 810 may be disposed on the bottom surface of the semiconductor substrate 802 onto which light is incident, and may improve the light receiving (Rx) efficiency of the second SPAD (SPAD_A) by scattering the incident light. The first optical structure 810 may include a concave-convex structure (hereinafter referred to as an uneven structure) 815 periodically disposed on the bottom surface of the semiconductor substrate 802. In some implementations, each uneven structure 815 may be formed in a quadrangular pyramid shape or a cylindrical shape. The width and depth of each uneven structure 815, the spacing between the uneven structures 815, and the number of uneven structures 815 may be determined experimentally according to the size and internal structure of the second SPAD pixel and the thickness of the semiconductor substrate 802.

[0183] For example, the uneven structure 815 may be formed by various techniques, such as selectively wet-etching the bottom surface of the semiconductor substrate 802 and gap-filling the semiconductor substrate 802 with a material having a refractive index different from that of the semiconductor substrate 802 .

[0184] When the first optical structure 810 is disposed in a region corresponding to the second SPAD (SPAD_A), the sensitivity of the second SPAD (SPAD_A) having higher sensitivity than the first SPAD (SPAD_C) can be further increased. According to another embodiment, in order to facilitate manufacturing processing, the uneven structure 815 can be included not only in the region corresponding to the second SPAD (SPAD_A), but also in the region corresponding to the first SPAD (SPAD_C).

[0185] Figure 8B is a schematic diagram illustrating another example of a sensor layer based on some implementations of the disclosed technology.

[0186] Figure 8B A cross-sectional structure 800 - 2 schematically showing a region corresponding to a first SPAD (SPAD_C) among the sensor layers is illustrated.

[0187] The cross-sectional structure 800-2 may include a semiconductor substrate 802, a microlens 804, and a second optical structure 850. Since the cross-sectional structure 800-2 is substantially the same as the cross-sectional structure 800-1 except for some differences, redundant descriptions thereof will be omitted herein for the sake of brevity, and hereinafter, the cross-sectional structure 800-2 will be described in the same manner as the cross-sectional structure 800-1. Fig. 8A The characteristics of different characteristics are described as the center Figure 8B Cross-sectional structure 800-2.

[0188] The first SPAD (SPAD_C) may be formed inside the semiconductor substrate 802 and will be referred to later. Fig.9A The specific structure of the first SPAD (SPAD_C) is described below.

[0189] The second optical structure 850 may be disposed on the bottom surface of the semiconductor substrate 802 on which light is incident, and may reduce the light receiving (Rx) efficiency of the first SPAD (SPAD_C) by blocking (reflecting or absorbing) a portion of the incident light. The second optical structure 850 may include a light blocking structure 855 disposed in at least a partial area of ​​the microlens 804 (or a pixel including the microlens 804) on the bottom surface of the semiconductor substrate 802. In some implementations, the light blocking structure 855 may be disposed at the edge of the microlens 804 to form an opening through which the incident light may pass near the center of the microlens 804. The light blocking structure 855 may be disposed at the edge of the microlens 804 to prevent crosstalk with peripheral pixels. The width, position, and number of the light blocking structure 855 may be determined experimentally based on the size and internal structure of the first SPAD pixel and the thickness of the semiconductor substrate 802.

[0190] For example, the light blocking structure 855 can be formed by selectively wet etching the bottom surface of the semiconductor substrate 802 and gap-filling the semiconductor substrate 802 with a material having high light reflectivity or high light absorbency (e.g., tungsten (W), aluminum (Al), copper (Cu) or alloys thereof).

[0191] When the second optical structure 850 is disposed in a region corresponding to the first SPAD (SPAD_C), the sensitivity of the first SPAD (SPAD_C) having lower sensitivity than the second SPAD (SPAD_A) can be further reduced. According to another embodiment, in order to facilitate manufacturing processing, the light blocking structure 855 can be included not only in the region corresponding to the first SPAD (SPAD_C), but also in the region corresponding to the second SPAD (SPAD_A).

[0192] Figure 8C is an example of some implementations based on the disclosed technology, wherein Fig. 8A and Figure 8B A schematic diagram of an example of an array structure of an optical structure is shown.

[0193] Figure 8C The first optical structure 810 and the second optical structure 850 are shown in FIG. Figure 4A An example 800a of an arrangement of the array structure 400a of the pixel array 110 is shown.

[0194] The light blocking structure 855 may be disposed in each pixel including the first SPAD (SPAD_C) to block (reflect or absorb) a portion of incident light, and thus may reduce light reception (Rx) efficiency of the first SPAD (SPAD_C).

[0195] An uneven (or concavo-convex) structure 815 may be provided in each pixel including the second SPAD (SPAD_A) to scatter incident light, thereby increasing light receiving (Rx) efficiency of the second SPAD (SPAD_A).

[0196] exist Figure 8C In the example shown, the light blocking structure 855 may be disposed on all pixels each including the first SPAD (SPAD_C), and the uneven structure 815 may be disposed on all pixels each including the second SPAD (SPAD_A), but the scope of the disclosed technology is not limited thereto. For example, the light blocking structure 855 may be placed on only some of the pixels each including the first SPAD (SPAD_C), or the uneven structure 815 may be placed on only some of the pixels each including the second SPAD (SPAD_A).

[0197] In some implementations, pixels including the first SPAD (SPAD_C) may have light blocking structures 855 that are different from each other. For example, at least one of the width, depth, period (or spacing), or number of the light blocking structures 855 provided in the respective pixels including the first SPAD (SPAD_C) may be different for each pixel. In some implementations, pixels including the second SPAD (SPAD_A) may have uneven structures 815 that are different from each other. For example, at least one of the width, depth, period (or spacing), or number of the uneven structures 815 provided in the respective pixels including the second SPAD (SPAD_A) may be different for each pixel.

[0198] Since the second optical structure 850 is selectively set in the pixel including the first SPAD (SPAD_C), and the first optical structure 810 is selectively set in the pixel including the second SPAD (SPAD_A), the sensitivity difference between the first SPAD (SPAD_C) and the second SPAD (SPAD_A) can be further increased, so that the suitability of the first SPAD (SPAD_C) for high illumination and the suitability of the second SPAD (SPAD_A) for low illumination can be further increased.

[0199] In some implementations, a structure for increasing or decreasing the sensitivity of a first SPAD (SPAD_C) or a second SPAD (SPAD_A) (hereinafter referred to as including Fig.9A The first optical structure 810 and the second optical structure 850 may be combined with each other to adjust the sensitivity of the first SPAD (SPAD_C) or the second SPAD (SPAD_A), or may be combined with the first optical structure 810 and the second optical structure 850.

[0200] In some implementations, to facilitate manufacturing processing, a structure for increasing or decreasing the sensitivity of a first SPAD (SPAD_C) or a second SPAD (SPAD_A) may be disposed in substantially the same manner not only in a region corresponding to the first SPAD (SPAD_C) but also in a region corresponding to the second SPAD (SPAD_A).

[0201] Fig.9A is a diagram illustrating an example of a planar structure of a first SPAD or a second SPAD based on some implementations of the disclosed technology.

[0202] Reference Fig.9A , schematically showing a planar structure 900 - 1 of a first SPAD (SPAD_C) or a second SPAD (SPAD_A).

[0203] The first SPAD (SPAD_C) may include a cathode and an anode, through which the cathode receives a first bias voltage (VB1), and through which the anode outputs a first voltage pulse (PLS1). In addition, the second SPAD (SPAD_A) may include an anode and a cathode, through which the anode receives a second bias voltage (VB2), and through which the cathode outputs a second voltage pulse (PLS2).

[0204] Each of the cathode of the first SPAD (SPAD_C) and the anode of the second SPAD (SPAD_A) can be defined as a bias node (BN) through which a bias voltage is received. In addition, each of the anode of the first SPAD (SPAD_C) and the cathode of the second SPAD (SPAD_A) can be defined as an output node (ON) through which a voltage pulse is output.

[0205] The planar structure 900 - 1 may include an output node (ON) and a bias node (BN), and may correspond to a first SPAD (SPAD_C) or a second SPAD (SPAD_A).

[0206] That is, when the planar structure 900-1 corresponds to the first SPAD (SPAD_C), the output node (ON) may correspond to the anode of the first SPAD (SPAD_C), and the bias node (BN) may correspond to the cathode of the first SPAD (SPAD_C). Conversely, when the planar structure 900-1 corresponds to the second SPAD (SPAD_A), the output node (ON) may correspond to the cathode of the second SPAD (SPAD_A), and the bias node (BN) may correspond to the anode of the second SPAD (SPAD_A).

[0207] The output node (ON) may have a circular shape disposed at the center of the SPAD.

[0208] The bias node (BN) may have a ring (or donut) shape surrounding the output node (ON) while being spaced apart from the output node (ON) by a predetermined distance.

[0209] When the distance between the bias node (BN) and the output node (ON) becomes shorter than desired, an edge breakdown (or tunneling) phenomenon may occur, in which charge flows directly from the bias node (BN) to the output node (ON) instead of flowing into the output node (ON) due to an avalanche process. As a result, the distance between the bias node (BN) and the output node (ON) may be determined experimentally to prevent the edge breakdown phenomenon. In addition, the distance between the bias node (BN) and the output node (ON) may be arranged to remain substantially constant.

[0210] Fig. 9B is a diagram illustrating another example of a planar structure of a first SPAD or a second SPAD based on some implementations of the disclosed technology.

[0211] Reference Fig. 9B , schematically showing a planar structure 900 - 2 of a first SPAD (SPAD_C) or a second SPAD (SPAD_A).

[0212] The planar structure 900 - 2 is substantially the same as the planar structure 900 - 1 except for some differences, and the following description will focus on these differences.

[0213] The output node (ON) may be formed in a rectangular shape with rounded corners and placed at the center of the SPAD. Since the output node (ON) has a rectangular shape with rounded corners, the output node (ON) may be set so that the distance between the bias node (BN) and the output node (ON) is not shorter than a desired distance, thereby minimizing the edge breakdown phenomenon.

[0214] The bias node (BN) may be formed in a rectangular ring shape surrounding the output node (ON) while being spaced apart from the output node (ON) by a predetermined distance.

[0215] Fig. 9C is a diagram illustrating another example of a planar structure of a first SPAD or a second SPAD based on some implementations of the disclosed technology.

[0216] Reference Fig. 9C , schematically showing a planar structure 900 - 3 of a first SPAD (SPAD_C) or a second SPAD (SPAD_A).

[0217] The planar structure 900 - 3 is substantially the same as the planar structure 900 - 1 except for some differences, and the following description will focus on these differences.

[0218] The output node (ON) may be formed in a rectangular shape placed at the center of the SPAD with angled corners.

[0219] The bias node (BN) may be formed in a rectangular ring shape surrounding the output node (ON) while being spaced apart from the output node (ON) by a predetermined distance.

[0220] The area of ​​the output node (ON) may correspond to the area of ​​the active region capable of detecting photons. As the area size of the output node (ON) increases, the sensitivity may increase, but the possibility of generating noise due to environmental noise (also referred to as background noise) may also increase. In addition, as the area size of the output node (ON) increases, the possibility of edge breakdown phenomenon occurring may also increase.

[0221] Assuming that the output nodes (ON) included in the planar structures (900-1 to 900-3) have the same width (e.g., width along the horizontal direction), the planar structure 900-3 in which the output node (ON) (i.e., the maximum output node ON) has the largest area can have the highest sensitivity, the planar structure 900-2 in which the output node (ON) has the second largest area can have the second highest sensitivity, and the planar structure 900-1 in which the output node (ON) has the smallest area can have the lowest sensitivity.

[0222] In some implementations, to further increase the sensitivity difference between the first SPAD (SPAD_C) and the second SPAD (SPAD_A), the first SPAD (SPAD_C) may be formed as a planar structure 900 - 1 , and the second SPAD (SPAD_A) may be formed as a planar structure 900 - 3 .

[0223] Fig. 10A is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing an example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0224] Reference Fig. 10A , schematically showing the 9A to 9C A cross-sectional structure 1000 - 1 taken along any one of the first to third lines (A-A′, B-B′, CC′). FIG. 10A to FIG. 10F The cross-sectional structure shown (1000-1 to 1000-6) can be 9A to 9C Each of the planar structures (900-1 to 900-3) corresponds to a cross-sectional structure obtained when the first SPAD (SPAD_C) is formed. Although it is assumed that each of the cross-sectional structures (1000-1 to 1000-6) is a structure formed on an N-type substrate (N-substrate) doped with N-type impurities (e.g., group V elements), other implementations are possible, and it should be noted that each of the cross-sectional structures may be or include a structure formed in a well region doped with N-type impurities in a P-type substrate doped with P-type impurities (e.g., group III elements) as required.

[0225] The cross-sectional structure 1000 - 1 may include a first P-type region 1010 , a second P-type region 1020 , a first N-type region 1110 , a second N-type region 1120 , and a third N-type region 1130 .

[0226] The first P-type region 1010 may correspond to an output node (ON) of the planar structure ( 900 - 1 to 900 - 3 ), and may be a region doped with P-type impurities.

[0227] The second P-type region 1020 may surround the first P-type region 1010 and may have a greater width than the first P-type region 1010 and a greater depth than the first P-type region 1010. In the following description, the width may refer to a horizontal width (i.e., a left-right width), and the depth may refer to a depth from the top surface of the substrate. The second P-type region 1020 may be a region doped with P-type impurities at a lower doping concentration than the first P-type region 1010.

[0228] The first N-type region 1110 may be disposed in contact with a top surface of the N-type substrate, and may be a region doped with N-type impurities.

[0229] The second N-type region 1120 may contact the bottom surface of the first N-type region 1110, and at the same time may have the same width as the first N-type region 1110 and have a greater depth than the first N-type region 1110. The second N-type region 1120 may be a region doped with N-type impurities at a lower doping concentration than the first N-type region 1110.

[0230] The third N-type region 1130 may be in contact with the bottom surface of the second N-type region 1120, and at the same time may have the same width as the second N-type region 1120 and have a greater depth than the second N-type region 1120. The third N-type region 1130 may be a region doped with N-type impurities at a lower doping concentration than the second N-type region 1120. In addition, the third N-type region 1130 may be a region doped with N-type impurities at a higher doping concentration than the N-type substrate.

[0231] The first N-type region 1110, the second N-type region 1120, and the third N-type region 1130 may correspond to the bias node (BN) of the planar structure (900-1 to 900-3). In more detail, the first N-type region 1110 may correspond to the bias node (BN) of the planar structure 900-1, the second N-type region 1120 may correspond to the bias node (BN) of the planar structure 900-2, and the third N-type region 1130 may correspond to the bias node (BN) of the planar structure 900-3.

[0232] An N-type region including first N-type region 1110 , second N-type region 1120 , third N-type region 1130 , and an N-type substrate, and a P-type region including first P-type region 1010 and second P-type region 1020 may form a first SPAD (SPAD_C).

[0233] Electrons and holes 1001 of the arriving light (RL) transmitted through the bottom surface of the N-type substrate may cause photoelectric conversion to generate electrons and holes 1001. Although for ease of description, Fig. 10AIt is shown that three holes 1001 are generated at specific positions by the arriving light (RL), but other implementations are also possible, and it should be noted that at least one hole 1001 is generated at any position within the cross-sectional structure 1000-1 so that an avalanche process can be performed. When the avalanche process according to photons is performed, the doping concentration increases in the order of the second P-type region 1020 and the first P-type region 1010, so that amplification of carriers (i.e., holes 1001) can occur in the direction of the first P-type region 1010. Since the second P-type region 1020 causes amplification of carriers to increase the detection speed of the carriers and result in increased sensitivity, the second P-type region 1020 can be defined as a multiplier region.

[0234] As the doping concentration decreases in the order of the first N-type region 1110, the second N-type region 1120, the third N-type region 1130, and the N-type substrate, the electric field (or reverse bias) caused by the first bias voltage (VB1) applied to the first N-type region 1110 can affect a deeper position within the N-type substrate. Therefore, even if the photon has reached a deep position within the N-type substrate, the avalanche process can be performed and the sensitivity of the first SPAD (SPAD_C) can be improved.

[0235] In addition, the third N-type region 1130 is formed to extend to a deep position close to the bottom surface of the N-type substrate, thereby facilitating isolation of the pixel from adjacent pixels.

[0236] On the other hand, the second P-type region 1020 forms a PN junction with the N-type substrate between the first N-type region 1110 and the first P-type region 1010 , thereby preventing edge breakdown between the first N-type region 1110 and the first P-type region 1010 .

[0237] Fig. 10B is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0238] Reference Fig. 10B , schematically showing the 9A to 9C A cross-sectional structure 1000 - 2 taken along any one of the first to third lines (A-A′, B-B′, CC′).

[0239] The cross-sectional structure 1000 - 2 is substantially the same as the cross-sectional structure 1000 - 1 except for some differences, and the following description will focus on these differences.

[0240] The cross-sectional structure 1000 - 2 may include a first P-type region 1010 , a second P-type region 1020 , a first N-type region 1110 , a second N-type region 1120 , and a third N-type region 1130 .

[0241] The second P type region 1020 may be disposed in contact with both left and right sides of the first P type region 1010 and may have a greater depth than the first P type region 1010. The second P type region 1020 may be a region doped with P type impurities at a lower doping concentration than the first P type region 1010.

[0242] The second P-type region 1020 may not be disposed under the first P-type region 1010 , and the first P-type region 1010 may be opened, so that the size of the multiplier region is reduced and the sensitivity of the first SPAD (SPAD_C) is reduced.

[0243] On the other hand, the second P-type region 1020 may form a PN junction with the N-type substrate between the first N-type region 1110 and the first P-type region 1010 , thereby preventing edge breakdown between the first N-type region 1110 and the first P-type region 1010 .

[0244] Fig. 10C is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0245] Reference Fig. 10C , schematically showing the 9A to 9C A cross-sectional structure 1000 - 3 taken along any one of the first to third lines (A-A′, B-B′, CC′).

[0246] The cross-sectional structure 1000 - 3 is substantially the same as the cross-sectional structure 1000 - 1 except for some differences, and the following description will focus on these differences.

[0247] The cross-sectional structure 1000 - 3 may include a first P-type region 1010 , a second P-type region 1020 , a third P-type region 1030 , a first N-type region 1110 , a second N-type region 1120 , and a third N-type region 1130 .

[0248] The second P-type region 1020 may be disposed in contact with the third P-type region 1030 at both the left and right sides of the first P-type region 1010, and may have a greater depth than the first P-type region 1010 and the third P-type region 1030. The second P-type region 1020 may be a region doped with P-type impurities at a lower doping concentration than the first P-type region 1010.

[0249] The second P-type region 1020 may not be disposed under the first P-type region 1010 to reduce the multiplier region, thereby reducing the sensitivity of the first SPAD (SPAD_C).

[0250] On the other hand, the second P-type region 1020 may form a PN junction with the N-type substrate between the first N-type region 1110 and the first P-type region 1010 , thereby preventing edge breakdown between the first N-type region 1110 and the first P-type region 1010 .

[0251] The third P-type region 1030 may be arranged to surround the first P-type region 1010 while being in contact with the second P-type region 1020 within the second P-type region 1020, and may have a greater depth than the first P-type region 1010 and a smaller depth than the second P-type region 1020. The third P-type region 1030 may be a region doped with P-type impurities not only at a lower doping concentration than the first P-type region 1010 but also at a higher doping concentration than the second P-type region 1020.

[0252] The third P-type region 1030 may be disposed below the first P-type region 1010 to expand the multiplier region so that the sensitivity of the first SPAD (SPAD_C) may be increased and may also serve as a double guard ring for the second P-type region 1020 to prevent edge breakdown.

[0253] Fig. 10D is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0254] Reference Fig. 10D , schematically showing the 9A to 9C A cross-sectional structure 1000 - 4 taken along any one of the first to third lines (A-A′, B-B′, CC′).

[0255] The cross-sectional structure 1000 - 4 is substantially the same as the cross-sectional structure 1000 - 1 except for some differences, and the following description will focus on these differences.

[0256] The cross-sectional structure 1000 - 4 may include a first P-type region 1010 , a second P-type region 1020 , a third P-type region 1030 , a first N-type region 1110 , a second N-type region 1120 , and a third N-type region 1130 .

[0257] The third P-type region 1030 may be disposed in contact with the bottom surface of the second P-type region 1020, and may have the same width as the second P-type region 1020 and a greater depth than the second P-type region 1020. The third P-type region 1030 may be a region doped with P-type impurities at a lower doping concentration than the second P-type region 1020.

[0258] The third P-type region 1030 may be disposed under the second P-type region 1020 to expand the multiplier region, thereby increasing the sensitivity of the first SPAD (SPAD_C).

[0259] Fig.10E is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0260] Reference Fig.10E , schematically showing the 9A to 9C A cross-sectional structure 1000 - 5 taken along any one of the first to third lines (A-A′, B-B′, CC′).

[0261] The cross-sectional structure 1000-5 is substantially the same as the cross-sectional structure 1000-1 except for some differences, and the following description will focus on these differences.

[0262] The cross-sectional structure 1000 - 5 may include a first P-type region 1010 , a second P-type region 1020 , a third P-type region 1030 , a first N-type region 1110 , and a second N-type region 1120 .

[0263] The third P-type region 1030 may be disposed on the entire region of the first SPAD (SPAD_C) while contacting the bottom surface of the second P-type region 1020 and the bottom surface of the second N-type region 1120, and may have a greater depth than the second P-type region 1020 and the second N-type region 1120. The third P-type region 1030 may be a region doped with P-type impurities at a lower doping concentration than the second P-type region 1020.

[0264] Due to the third P-type region 1030 , the third N-type region 1130 may be omitted.

[0265] The third P-type region 1030 may be disposed on the entire area of ​​the first SPAD (SPAD_C) to expand the multiplier region, thereby increasing the sensitivity of the first SPAD (SPAD_C).

[0266] In some implementations, the third P-type region 1030 may be formed integrally with the third P-type region of an adjacent pixel.

[0267] Fig.10Fis an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0268] Reference Fig.10F , schematically showing the 9A to 9C A cross-sectional structure 1000-6 taken along any one of the first to third lines (A-A', B-B', CC').

[0269] The cross-sectional structure 1000-6 is substantially the same as the cross-sectional structure 1000-1 except for some differences, and the following description will focus on these differences.

[0270] The cross-sectional structure 1000 - 6 may include a first P-type region 1010 , a second P-type region 1020 , a first N-type region 1110 , a second N-type region 1120 , and a third N-type region 1130 .

[0271] The third N-type region 1130 may be disposed on the entire region of the first SPAD (SPAD_C) while contacting the bottom surface of the second P-type region 1020 and the bottom surface of the second N-type region 1120, and may have a greater depth than the second P-type region 1020 and the second N-type region 1120. The third N-type region 1130 may be a region doped with N-type impurities at a lower doping concentration than the second N-type region 1120.

[0272] The electric field (or reverse bias) caused by the first bias voltage (VB1) applied to the first N-type region 1110 can affect a larger area at a deeper position within the N-type substrate due to the third N-type region 1130. In addition, the electric field caused by the first bias voltage (VB1) can affect the entire first SPAD (SPAD_C), so that the first SPAD (SPAD_C) can be driven with a first bias voltage (VB1) lower than the first bias voltage (VB1) that must be applied to the cross-sectional structure 1000-1, thereby reducing power consumption.

[0273] However, as the third N-type region extends to the bottom surface of the second P-type region 1020, the avalanche process may not occur not only through the PN junction between the third N-type region and the second P-type region, but also through the smaller area for detecting photons in the N-type substrate, thereby reducing the sensitivity of the first SPAD (SPAD_C).

[0274] In some implementations, the third N-type region 1130 may be formed integrally with the third N-type region of an adjacent pixel.

[0275] Fig.11A is an example of some implementations based on the disclosed technology, along the 9A to 9CA diagram showing another example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0276] Reference Fig.11A , schematically showing the 9A to 9C A cross-sectional structure 1100 - 1 is taken along any one of the first to third lines (A-A′, B-B′, and CC′). FIG. 11A to FIG. 11F The cross-sectional structures shown (1100-1 to 1100-6) may be 9A to 9C Each of the planar structures (900-1 to 900-3) corresponds to a cross-sectional structure obtained when the second SPAD (SPAD_A) is formed. Although it is assumed that each of the cross-sectional structures (1100-1 to 1100-6) is a structure formed on a P-type substrate (P-substrate) doped with P-type impurities, other implementations are possible, and it should be noted that each cross-sectional structure may be or include a structure formed in a well region doped with P-type impurities in an N-type substrate doped with N-type impurities as required.

[0277] The cross-sectional structure 1100 - 1 may include a first N-type region 2110 , a second N-type region 2120 , a first P-type region 2010 , a second P-type region 2020 , and a third P-type region 2030 .

[0278] FIG. 11A to FIG. 11F The materials, structures and functions of the first to third P-type regions (2010 to 2030) shown in FIG. FIG. 10A to FIG. 10F The materials, structures and functions of the first to third P-type regions (1010 to 1030) are substantially the same, and FIG. 11A to FIG. 11F The materials, structures and functions of the first to third N-type regions (2110 to 2130) shown in FIG. FIG. 10A to FIG. 10F The materials, structures and functions of the first to third N-type regions (1110 to 1130) are substantially the same. If a difference occurs between the first to third P-type regions (2010 to 2030) and the first to third P-type regions (1010 to 1030), or if a difference occurs between the first to third N-type regions (2110 to 2130) and the first to third N-type regions (1110 to 1130), a detailed description thereof will be given later.

[0279] The first N-type region 2110 may correspond to an output node (ON) of the planar structure ( 900 - 1 to 900 - 3 ), and may be a region doped with N-type impurities.

[0280] The second N-type region 2120 may surround the first N-type region 2110 and may have a greater width and a greater depth than the first N-type region 2110. The second N-type region 2120 may be a region doped with N-type impurities at a lower doping concentration than the first N-type region 2110.

[0281] The first P-type region 2010 may correspond to a bias node (BN) of the planar structure ( 900 - 1 to 900 - 3 ), and may be a region doped with P-type impurities.

[0282] The second P-type region 2020 may contact the bottom surface of the first P-type region 2010, and at the same time may have the same width as the first P-type region 2010 and have a greater depth than the first P-type region 2010. The second P-type region 2020 may be a region doped with P-type impurities at a lower doping concentration than the first P-type region 2010.

[0283] The third P-type region 2030 may be in contact with the bottom surface of the second P-type region 2020, and at the same time may have the same width as the second P-type region 2020 and have a greater depth than the second P-type region 2020. The third P-type region 2030 may be a region doped with P-type impurities at a lower doping concentration than the second P-type region 2020. In addition, the third P-type region 2030 may be a region doped with P-type impurities at a higher doping concentration than the P-type substrate.

[0284] A P-type region including the first P-type region 2010 , the second P-type region 2020 , the third P-type region 2030 , and the P-type substrate and an N-type region including the first N-type region 2110 and the second N-type region 2120 may form a second SPAD (SPAD_A).

[0285] Electrons 1101 and holes of the arriving light (RL) transmitted through the bottom surface of the P-type substrate may cause photoelectric conversion to generate electrons 1101 and holes. Although for ease of description, Fig.11A It is shown that three electrons 1101 are generated at a specific position by the arriving light (RL), but other implementations are possible, and it should be noted that at least one electron 1101 is generated at any position within the cross-sectional structure 1100-1, so that an avalanche process can be performed. When the avalanche process according to photons is performed, the doping concentration increases in the order of the second N-type region 2120 and the first N-type region 2110, so that amplification of carriers (i.e., electrons 1101) can occur in the direction of the first N-type region 2110. Since the second N-type region 2120 causes amplification of carriers to increase the detection speed of the carriers and result in increased sensitivity, the second N-type region 2120 can be defined as a multiplier region.

[0286] As the doping concentration decreases in the order of the first P-type region 2010, the second P-type region 2020, the third P-type region 2030, and the P-type substrate, the electric field (or reverse bias) caused by the second bias voltage (VB2) applied to the first P-type region 2010 can affect a deeper position within the P-type substrate. Therefore, even if the photon has reached a deep position within the P-type substrate, the avalanche process can be performed and the sensitivity of the second SPAD (SPAD_A) can be improved.

[0287] In addition, the third P-type region 2030 is formed to extend to a deep position close to the bottom surface of the P-type substrate, thereby facilitating isolation of the pixel from adjacent pixels.

[0288] On the other hand, the second N-type region 2120 forms a PN junction with the P-type substrate between the first P-type region 2010 and the first N-type region 2110 , thereby preventing edge breakdown between the first P-type region 2010 and the first N-type region 2110 .

[0289] FIG. 11B to FIG. 11F is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing other examples of the cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0290] Reference FIG. 10B to FIG. 10F as well as FIG. 11B to FIG. 11F , schematically showing the 9A to 9C A cross-sectional structure (1100-2 to 1100-6) taken along any one of the first to third lines (A-A', B-B', CC').

[0291] Except for some differences that the cross-sectional structure (1000-2 to 1000-6) has a conductivity type opposite to that of the cross-sectional structure (1100-2 to 1100-6), the cross-sectional structure (1100-2 to 1100-6) is basically the same as the cross-sectional structure (1000-2 to 1000-6), and also for the sake of brevity, its redundant description will be omitted herein, and the following description will focus on these differences.

[0292] Fig. 12A is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0293] Reference Fig. 10A and Fig. 12A , schematically showing the 9A to 9CThe cross-sectional structure 1200-1 may correspond to any of the first to third lines (A-A', B-B', and CC'). Fig. 10A A modified example of the cross-sectional structure 1000 - 1 is shown.

[0294] Apart from some differences, Fig. 12A The cross-sectional structure 1200 - 1 is substantially the same as the cross-sectional structure 1000 - 1 , and the following description will focus on the differences.

[0295] The third N-type region 1130 may be in contact with the bottom surface of the second N-type region 1120 and may have a greater depth than the second N-type region 1120 at the same time. The third N-type region 1130 may extend horizontally toward the center of the cross-sectional structure 1200-1 to have a greater width than the second N-type region 1120. However, the third N-type regions 1130 disposed on both sides of the cross-sectional structure 1200-1 do not extend to contact each other, but form an open region near the center of the cross-sectional structure 1200-1. The size of the open region may be determined experimentally in consideration of the sensitivity of the first SPAD (SPAD_C) and the size of the noise caused by the ambient light (AL).

[0296] The light incident on the first SPAD (SPAD_C) may include the arrival light (RL) reflected from the target object 1 and the ambient light (AL) causing the ambient noise. Due to the influence of the lens module 20 and the microlens 804 that focus the arrival light (RL) on the pixel array 110, the arrival light (RL) may be concentrated at the center of the first SPAD (SPAD_C) compared to the ambient light (AL) being uniformly incident on the entire first SPAD (SPAD_C).

[0297] The third N-type region 1130 may interfere with the transmission of light, so that the third N-type region 1130 is disposed in the remaining region except for the opening region located near the center of the first SPAD (SPAD_C). As a result, the third N-type region 1130 may minimize the occurrence of an avalanche process caused by ambient light (AL), and may cause an avalanche process caused by the arriving light (RL) concentrated at the center of the first SPAD (SPAD_C), thereby reducing the influence of noise caused by the ambient light (AL).

[0298] Fig. 12B is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0299] Reference Fig. 10B and Fig. 12B , schematically showing the 9A to 9C The cross-sectional structure 1200-2 may correspond to any one of the first to third lines (A-A', B-B', and CC'). Fig. 10B A modified example of the cross-sectional structure 1000 - 2 is shown.

[0300] Apart from some differences, Fig. 12B The cross-sectional structure 1200 - 2 is substantially the same as the cross-sectional structure 1000 - 2 , and the following description will focus on the differences.

[0301] The third N-type region 1130 may contact the bottom surface of the second N-type region 1120 and at the same time may have a greater depth than the second N-type region 1120. The third N-type region 1130 may horizontally extend toward the center of the cross-sectional structure 1200-2 to have a greater width than the second N-type region 1120. However, the third N-type regions 1130 disposed on both sides of the cross-sectional structure 1200-2 do not extend to contact each other, but form an open region near the center of the cross-sectional structure 1200-2.

[0302] Since the functions and effects of the third N-type region 1130 of the cross-sectional structure 1200 - 2 are substantially the same as those of the third N-type region 1130 of the cross-sectional structure 1200 - 1 , repeated description thereof will be omitted herein for the sake of brevity.

[0303] Fig. 12C is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0304] Reference Fig. 10C and Fig. 12C , schematically showing the 9A to 9C The cross-sectional structure 1200-3 may correspond to any one of the first to third lines (A-A', B-B', and CC'). Fig. 10C A modified example of the cross-sectional structure 1000 - 3 is shown.

[0305] Apart from some differences, Fig. 12C The cross-sectional structure 1200 - 3 is substantially the same as the cross-sectional structure 1000 - 3 , and the following description will focus on the differences.

[0306] The third N-type region 1130 may contact the bottom surface of the second N-type region 1120 and at the same time may have a greater depth than the second N-type region 1120. The third N-type region 1130 may horizontally extend toward the center of the cross-sectional structure 1200-3 to have a greater width than the second N-type region 1120. However, the third N-type regions 1130 disposed on both sides of the cross-sectional structure 1200-3 do not extend to contact each other, but form an open region near the center of the cross-sectional structure 1200-3.

[0307] Since the functions and effects of the third N-type region 1130 of the cross-sectional structure 1200 - 3 are substantially the same as those of the third N-type region 1130 of the cross-sectional structure 1200 - 1 , repeated description thereof will be omitted herein for the sake of brevity.

[0308] although FIG. 12A to FIG. 12C They are exemplified FIG. 10A to FIG. 10C , but other implementations are possible and are FIG. 11A to FIG. 11C The same technical idea can be realized in the modified example of . That is, the third P-type region 2030 of each of the cross-sectional structures (1100-1 to 1100-3) can extend toward the center of each of the cross-sectional structures (1100-1 to 1100-3), while forming an opening region near the center of each of the cross-sectional structures (1100-1 to 1100-3).

[0309] Fig.13 is an example of some implementations based on the disclosed technology, along the 9A to 9C A diagram showing another example of a cross-sectional structure taken along any one of the first to third lines (AA′, BB′, CC′) shown.

[0310] Reference Fig. 10D and Fig.13 , schematically showing the 9A to 9C The cross-sectional structure 1300 is taken along any of the first to third lines (A-A', B-B', and CC'). The cross-sectional structure 1300 may correspond to Fig. 10D A modified example of the cross-sectional structure 1000 - 4 is shown.

[0311] Apart from some differences, Fig.13 The cross-sectional structure 1300 is substantially the same as the cross-sectional structure 1000 - 4 , and the following description will focus on the differences.

[0312] The cross-sectional structure 1300 may include a third P-type region (1030-1, 1030-2) vertically arranged in place of the third P-type region 1030. The third P-type region 1030-1 may have a greater width than the third P-type region 1030-2, and may have a smaller width than the second P-type region 1020. That is, as the P-type regions (1020, 1030-1, 1030-2) are sequentially arranged in the vertical direction, the highest P-type region 1020 has the largest width, the middle P-type region 1030-1 has an intermediate width, and the lowest P-type region 1030-2 has the smallest width.

[0313] Since the reaching light (RL) is infrared (IR) light, the reaching light (RL) may have a relatively large penetration depth within the semiconductor substrate compared to the ambient light (AL) having a high ratio of visible light.

[0314] Since the multiplier region corresponding to the P-type region (1020, 1030-1, 1030-2) is a region where there is a high possibility of generating an avalanche process due to incident light, the P-type region (1020, 1030-1, 1030-2) is arranged to have a reduced width in the vertical direction, so that the number of occurrences of the avalanche process caused by ambient light (AL) with a relatively small penetration depth can be minimized.

[0315] In addition, the third P-type region 1030-1 may have a higher doping concentration than the third P-type region 1030-2, and may have a lower doping concentration than the second P-type region 1020. That is, the doping concentrations of the P-type regions (1020, 1030-1, 1030-2) sequentially stacked in the vertical direction may decrease in a downward direction of the stacked structure including the P-type regions (1020, 1030-1, 1030-2).

[0316] Therefore, as the electric field from the P-type regions (1020, 1030-1, 1030-2) to the first P-type region 1010 increases, the intensity of the arriving light (RL) incident near the center of the first SPAD (SPAD_C) decreases, and the penetration depth of the arriving light (RL) within the semiconductor substrate also decreases, so that an avalanche process caused by the arriving light (RL) can be performed, thereby improving the sensitivity of the first SPAD (SLAD_C).

[0317] Furthermore, although the above embodiment has disclosed an example in which the number of third P-type regions (1030-1, 1030-2) is set to 2 for ease of description, other implementations are possible, and it should be noted that three or more P-type regions may be used as needed.

[0318] although Fig.13 Already made public Fig. 10D, but other implementations are possible and Fig.11D The same technical concept can also be implemented in the modified embodiment of the present invention. That is, the third N-type region 2130 of the cross-sectional structure 1100-4 can be replaced by two or more third N-type regions, whose widths gradually decrease in the downward direction from the top surface to the bottom surface of the third N-type region 1130, and whose doping concentrations also gradually decrease in the same downward direction.

[0319] Fig.14A is an example of some implementations based on the disclosed technology, Fig. 10A A diagram of an example of a modified embodiment of a cross-sectional structure is shown.

[0320] Reference Fig. 10A and Fig.14A , schematically showing the Fig. 10A A cross-sectional structure 1400 - 1 is a modified example of the cross-sectional structure 1000 - 1 .

[0321] Apart from some differences, Fig.14A The cross-sectional structure 1400 - 1 is substantially the same as the cross-sectional structure 1000 - 1 , and the following description will focus on the differences.

[0322] The cross-sectional structure 1400-1 may include a plurality of first P-type regions (1010-1 to 1010-3) instead of one first P-type region 1010. The plurality of first P-type regions (1010-1 to 1010-3) may have substantially the same characteristics as the first P-type region 1010 (eg, same material, same function).

[0323] The plurality of first P-type regions (1010-1 to 1010-3) may be arranged at predetermined intervals within the second P-type region 1020. Fig.14A It is shown that the number of the first P-type regions (1010-1 to 1010-3) is set to 3 for ease of description, but other implementations are possible, and at least two or at least four first P-type regions may also be included in the cross-sectional structure as needed. The plurality of first P-type regions (1010-1 to 1010-3) may be physically isolated from each other, but may be electrically connected to each other to operate as an output node (ON). The electrical connection between the plurality of first P-type regions (1010-1 to 1010-3) may be achieved by metal wires of an interconnect layer (also referred to as a wiring layer) disposed above the semiconductor substrate, but the scope of the disclosed technology is not limited thereto.

[0324] Compared with a case where one first P-type region having an area identical to that of each of the first P-type regions (1010-1 to 1010-3) is provided, a plurality of first P-type regions (1010-1 to 1010-3) are arranged, and the cross-sectional structure 1400-1 includes a plurality of first P-type regions (1010-1 to 1010-3), so that the detection efficiency of carriers to be transmitted through the avalanche process can be further increased.

[0325] In addition, compared to the case where multiple first P-type regions (1010-1 to 1010-3) are interconnected to form one first P-type region, the first P-type regions (1010-1 to 1010-3) are separately arranged to reduce the detection efficiency of carriers to be transmitted through the avalanche process caused by ambient light (AL), thereby reducing the impact of noise.

[0326] Fig. 14B is an example of some implementations based on the disclosed technology, Fig. 10A A diagram of another example of a modified embodiment of a cross-sectional structure is shown.

[0327] Reference Fig. 10A and Fig. 14B , schematically showing the Fig. 10A A cross-sectional structure 1400 - 2 is a modified example of the cross-sectional structure 1000 - 1 .

[0328] Apart from some differences, Fig. 14B The cross-sectional structure 1400 - 2 is substantially the same as the cross-sectional structure 1000 - 1 , and the following description will focus on the differences.

[0329] The cross-sectional structure 1400-2 may include a plurality of first P-type regions (1010-1 to 1010-3) and a plurality of second P-type regions (1020-1 to 1020-3) instead of one first P-type region 1010 and one second P-type region 1020. The plurality of first P-type regions (1010-1 to 1010-3) may have substantially the same characteristics (e.g., the same material, the same function) as the first P-type region 1010. The plurality of second P-type regions (1020-1 to 1020-3) may have substantially the same characteristics (e.g., the same material, the same function) as the second P-type region 1020.

[0330] A plurality of first P-type regions (1010-1 to 1010-3) and a plurality of second P-type regions (1020-1 to 1020-3) may be arranged in pairs at predetermined intervals within the N substrate. A first detection region consisting of a first P-type region 1010-1 and a second P-type region 1020-1 surrounding the first P-type region 1010-1, a second detection region consisting of a first P-type region 1010-2 and a second P-type region 1020-2 surrounding the first P-type region 1010-2, and a third detection region consisting of a first P-type region 1010-3 and a second P-type region 1020-3 surrounding the first P-type region 1010-3 may be arranged to be spaced apart from each other by a predetermined distance. In addition, although Fig. 14B It is shown that the number of detection areas is set to 3 for ease of description, but other implementations are possible, and at least two or at least four detection areas may also be included in the cross-sectional structure as needed. The plurality of first P-type regions (1010-1 to 1010-3) may be physically isolated from each other, but may be electrically connected to each other to operate as an output node (ON). The electrical connection between the plurality of first P-type regions (1010-1 to 1010-3) may be achieved by a metal wire of an interconnect layer (i.e., a wiring layer) disposed above the semiconductor substrate, but the scope of the disclosed technology is not limited thereto.

[0331] Compared to the case where one detection region having the same area as that of each detection region is provided, the cross-sectional structure 1400 - 2 includes the plurality of detection regions, so that the detection efficiency of carriers to be transferred through the avalanche process can be further increased.

[0332] In addition, compared with the case where multiple first P-type regions (1010-1 to 1010-3) are interconnected to form one first P-type region, the first P-type regions (1010-1 to 1010-3) are separately arranged for each detection region to reduce the detection efficiency of carriers to be transmitted through the avalanche process caused by ambient light (AL), thereby reducing the impact of noise.

[0333] Fig.15 is a diagram illustrating an example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0334] Reference Fig.15 , schematically shows a planar structure 1500 of a sensor layer of first to fourth pixels (PX1 to PX4). Each of the first to fourth pixels (PX1 to PX4) may correspond to Figure 1 The pixels (PX) included in the pixel array 110 will be described using the first to fourth pixels (PX1 to PX4) as an example. Fig.15 The planar structure 1500 is shown, but the substantially same structure may be applied to other pixels (PX) as needed.

[0335] The first pixel to the fourth pixel (PX1 to PX4) may be the same type of SPAD pixels (i.e., the same type of SPAD pixels). In implementation, the SPADs respectively included in the first pixel to the fourth pixel (PX1 to PX4) may be the first SPAD (SPAD_C) or the second SPAD (SPAD_A), and may correspond to the same SPAD. When the SPAD included in each of the first pixel to the fourth pixel (PX1 to PX4) is the first SPAD (SPAD_C), each of the output nodes (ON1 to ON4) may correspond to the anode of the first SPAD (SPAD_C), and each of the bias nodes (BN1a to BN4d) may correspond to the cathode of the first SPAD (SPAD_C). When the SPAD included in each of the first to fourth pixels (PX1 to PX4) is a second SPAD (SPAD_A), each of the output nodes (ON1 to ON4) can correspond to the cathode of the second SPAD (SPAD_A), and each of the bias nodes (BN1a to BN4d) can correspond to the anode of the second SPAD (SPAD_A).

[0336] The first pixel (PX1) may include not only a cross-shaped first output node (ON1) disposed at the center of the first pixel (PX1), but also bias nodes (BN1a to BN1d) spaced a predetermined distance from the first output node (ON1) and disposed at vertices of the first pixel (PX1).

[0337] Since the first bias nodes (BN1a to BN1d) are set at the vertices of the first pixel (PX1), the first output node (ON) can be formed in a cross shape to prevent an edge breakdown phenomenon that occurs when the distance between the first output node (ON1) and each of the first bias nodes (BN1a to BN1d) becomes shorter than required.

[0338] Since the second to fourth pixels ( PX2 to PX4 ) have structures corresponding to the first pixel ( PX1 ), repeated descriptions thereof will be omitted herein for the sake of brevity.

[0339] Since the bias nodes (BN1a to BN4d) are disposed at the vertices of the first to fourth pixels (PX1 to PX4), adjacent bias nodes (eg, BN1b and BN2a, or BN1d, BN2c, BN3b, and BN4a) of adjacent pixels may be integrally formed.

[0340] Since adjacent bias nodes are formed integrally, the difficulty of the process for forming the bias nodes can be improved, and the design margin of the interconnection line (i.e., wiring) for supplying the bias voltage can be ensured. In addition, since the number of bias nodes to which the bias voltage must be supplied is reduced, the power consumption required for supplying the bias voltage can also be reduced.

[0341] Fig.16 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0342] Reference Fig.16 , schematically shows a planar structure 1600 of a sensor layer of first to fourth pixels (PX1 to PX4). The planar structure 1600 is substantially the same as the planar structure 1500 except for some differences, and the following description will focus on these differences.

[0343] In such Fig.16 In the illustrated implementation, each of the first to fourth output nodes (ON1 to ON4) of the first to fourth pixels (PX1 to PX4) may have a circular shape.

[0344] In this implementation, since the first output node (ON1) has a circular shape, the circular first output node (ON1) can prevent the distance between the first output node (ON1) and each of the first bias nodes (BN1a to BN1d) from being shorter than required, thereby minimizing the number of occurrences of the edge breakdown phenomenon. Although the above description is provided for the first output node (ON1), a similar description can be applied to other output nodes, that is, the second output node to the fourth output node (ON2 to ON4).

[0345] Fig.17 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0346] Reference Fig.17 , schematically shows a planar structure 1700 of a sensor layer of first to fourth pixels (PX1 to PX4). The planar structure 1700 is substantially the same as the planar structure 1500 except for some differences, and the following description will focus on these differences.

[0347] Each of the first to fourth output nodes (ON1 to ON4) of the first to fourth pixels (PX1 to PX4) may have a circular shape.

[0348] The first bias node (BN1) of the first pixel (PX1) may be spaced apart from the output node (ON1) and disposed at the periphery of the output node (ON1). In an implementation, the first bias node (BN1) may be disposed along a boundary (or edge) of the first pixel (PX1). In an implementation, the first bias node (BN1) may surround the output node (ON1). The second bias node (BN2) of the second pixel (PX2) may be spaced apart from the output node (ON2) and disposed at the periphery of the output node (ON2). In an implementation, the second bias node (BN2) may be disposed along a boundary (or edge) of the second pixel (PX2). In an implementation, the second bias node (BN2) may surround the output node (ON2). The third bias node (BN3) of the third pixel (PX3) may be spaced apart from the output node (ON3) and disposed at the periphery of the output node (ON3). In an implementation, the third bias node (BN3) may be arranged along a boundary (or edge) of the third pixel (PX3). In an implementation, the third bias node (BN3) may surround the output node (ON3). The fourth bias node (BN4) of the fourth pixel (PX4) may be spaced apart from the output node (ON4) and arranged at the periphery of the output node (ON4). In an implementation, the fourth bias node (BN4) may be arranged along a boundary (or edge) of the fourth pixel (PX4). In an implementation, the fourth bias node (BN4) may surround the output node (ON4).

[0349] Since the bias nodes (BN1 to BN4) are disposed along the boundaries of the first to fourth pixels (PX1 to PX4), adjacent bias nodes (eg, BN1 to BN4) of adjacent pixels may be integrally formed.

[0350] Fig.18 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0351] Reference Fig.18 , schematically shows a planar structure 1800 of a sensor layer of first to fourth pixels (PX1 to PX4). The planar structure 1800 is substantially the same as the planar structure 1500 except for some differences, and the following description will focus on these differences.

[0352] Each of the first to fourth output nodes (ON1 to ON4) of the first to fourth pixels (PX1 to PX4) may have a circular shape.

[0353] The first bias node to the fourth bias node (BN1a to BN4d) of the first pixel to the fourth pixel (PX1 to PX4) may be spaced apart from the output node (ON1 to ON4) and be disposed at the vertex of the corresponding pixel (PX1 to PX4). In an implementation, the first bias node to the fourth bias node (BN1a to BN4d) may surround at least some portions of the output node (ON1 to ON4). In an implementation, the first bias node to the fourth bias node (BN1a, BN1b, BN1c, BN1d) of the first pixel (PX1) may form a circular shape so that the distance to the corresponding output node (ON1) becomes constant. In an implementation, the first bias node to the fourth bias node (BN1a, BN1b, BN1c, BN1d) of the first pixel (PX1) may have an inner boundary arranged along a circular shape. The first bias node to the fourth bias node (BN1a, BN1b, BN1c, BN1d) of the first pixel (PX1) may have an outer boundary arranged along the edge of the corresponding pixel (PX1 to PX4). The first bias node to the fourth bias node (BN2a, BN2b, BN2c, BN2d) of the second pixel (PX2) may form a circular shape so that the distance to the corresponding output node (ON2) becomes constant. The first bias node to the fourth bias node (BN3a, BN3b, BN3c, BN3d) of the third pixel (PX3) may form a circular shape so that the distance to the corresponding output node (ON3) becomes constant. The first bias node to the fourth bias node (BN4a, BN4b, BN4c, BN4d) of the fourth pixel (PX4) may form a circular shape so that the distance to the corresponding output node (ON4) becomes constant. Therefore, it is possible to prevent an edge breakdown phenomenon that occurs when the distances between the corresponding output nodes (ON1 to ON4) and the first to fourth bias nodes (BN1a to BN4d) become shorter than a required distance at a specific position.

[0354] Since the bias nodes (BN1a to BN4d) are set at the vertices of the first to fourth pixels (PX1 to PX4), adjacent bias nodes (for example, BN1b and BN2a, or BN1d, BN2c, BN3b and BN4a) of adjacent pixels can be formed integrally.

[0355] Fig.19 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0356] Reference Fig.19 , schematically shows a planar structure 1900 of a sensor layer of first to fourth pixels (PX1 to PX4). The planar structure 1900 is substantially the same as the planar structure 1500 except for some differences, and the following description will focus on these differences.

[0357] In the planar structure 1900, the first pixel to the fourth pixel (PX1 to PX4) may further include the first to fourth guard rings (GR1 to GR4), respectively. The first to fourth guard rings (GR1 to GR4) may surround the first to fourth output nodes (ON1 to ON4) and may be spaced apart from the first to fourth output nodes (ON1 to ON4) by a predetermined distance. The first guard ring (GR1) may surround the first output node (ON1) and may be spaced apart from the first output node (ON1) by a predetermined distance, the second guard ring (GR2) may surround the second output node (ON2) and may be spaced apart from the second output node (ON2) by a predetermined distance, the third guard ring (GR3) may surround the third output node (ON3) and may be spaced apart from the third output node (ON3) by a predetermined distance, and the fourth guard ring (GR4) may surround the fourth output node (ON4) and may be spaced apart from the fourth output node (ON4) by a predetermined distance.

[0358] The first to fourth guard rings (GR1 to GR4) may electrically separate the first to fourth output nodes (ON1 to ON4) from adjacent first to fourth bias nodes (BN1a to BN4d), and thus may prevent an edge breakdown phenomenon.

[0359] The conductivity type of the first to fourth guard rings (GR1 to GR4) may be the same as that of the first to fourth output nodes (ON1 to ON4), or may be the same as that of the first to fourth bias nodes (BN1a to BN4d).

[0360] Fig. 20 is a diagram illustrating another example of a planar structure of multiple pixels based on some implementations of the disclosed technology.

[0361] Reference Fig. 20 , schematically shows a planar structure 2000 of a sensor layer of first to fourth pixels (PX1 to PX4). The planar structure 2000 is substantially the same as the planar structure 1500 except for some differences, and the following description will focus on these differences.

[0362] In the planar structure 2000 , the first to fourth pixels ( PX1 to PX4 ) may further include first to fourth guard rings ( GR1 a to GR4 d ), respectively.

[0363] In some implementations, each of the first guard rings (GR1a to GR1d) has two portions extending in different directions. Fig. 20In the illustrated implementation, each of the first guard rings (GR1a to GR1d) has a first portion extending in a horizontal direction and a second portion extending in a vertical direction. In an example, each of the first guard rings (GR1a to GR1d) may have a clamp shape surrounding at least some portion of each of the first bias nodes (BN1a to BN1d), and may be spaced apart from each of the first bias nodes (BN1a to BN1d) by a predetermined distance. In more detail, the first guard ring (GR1a) may have a clamp shape surrounding the first bias node (BN1a), and may be spaced apart from the first bias node (BN1a) by a predetermined distance. The first guard ring (GR1b) may have a clamp shape surrounding the first bias node (BN1b), and may be spaced apart from the first bias node (BN1b) by a predetermined distance. The first guard ring (GR1c) may have a clamp shape surrounding the first bias node (BN1c) and may be spaced apart from the first bias node (BN1c) by a predetermined distance. The first guard ring (GR1d) may have a clamp shape surrounding the first bias node (BN1d) and may be spaced apart from the first bias node (BN1d) by a predetermined distance.

[0364] The first guard rings (GR1a to GR1d) may electrically separate the first bias nodes (BN1a to BN1d) from the adjacent first output node (ON1), and thus may prevent an edge breakdown phenomenon.

[0365] The conductivity type of the first guard ring (GR1a to GR1d) may be the same as the conductivity type of the first output node (ON1), or may be the same as the conductivity type of the first bias node (BN1a to BN1d).

[0366] Each of the second to fourth guard rings (GR2a to GR4d) may have a structure and a conductivity type corresponding to those of the first guard rings (GR1a to GR1d).

[0367] Fig.21 is a diagram illustrating another example of a planar structure for multiple pixels based on some implementations of the disclosed technology.

[0368] Reference Fig.21 , schematically shows a planar structure 2100 of a sensor layer of first to fourth pixels (PX1 to PX4). The planar structure 2100 is substantially the same as the planar structure 1500 except for some differences, and the following description will focus on these differences.

[0369] In the planar structure 2100, the first pixel to the fourth pixel (PX1 to PX4) may further include the first to fourth guard rings (GR1 to GR4), respectively. In more detail, the first guard ring (GR1) may be arranged to contact the first output node (ON1) while surrounding the first output node (ON1). The second guard ring (GR2) may be arranged to touch the second output node (ON2) while surrounding the second output node (ON2). The third guard ring (GR3) may be arranged to contact the third output node (ON3) while surrounding the third output node (ON3). The fourth guard ring (GR4) may be arranged to contact the fourth output node (ON4) while surrounding the fourth output node (ON4). In addition, each of the first to fourth guard rings (GR1 to GR4) may extend in an upward direction, a downward direction, a left direction, and a right direction based on each of the first to fourth output nodes (ON1 to ON4), and may have an overall shape similar to a cross shape. Therefore, the first to fourth guard rings (GR1 to GR4) may be formed integrally.

[0370] The first to fourth guard rings (GR1 to GR4) may electrically separate the first to fourth output nodes (ON1 to ON4) from the first to fourth bias nodes (BN1a to BN4d), and thus may prevent an edge breakdown phenomenon.

[0371] The conductivity type of the first to fourth guard rings (GR1 to GR4) may be the same as the conductivity type of the first to fourth output nodes (ON1 to ON4). Therefore, the multiplier region may be enlarged, thereby improving the sensitivity of the SPAD.

[0372] Figures 19 to 21 The guard ring shown has been described as being applied to Fig.15 Example of a guard ring of a planar structure 1500, but Figures 19 to 21 The guard ring shown can also be similarly applied to Figures 16 to 18 Plane structure (1600 to 1800).

[0373] Fig.22A is an example of some implementations based on the disclosed technology, along the Fig.15 A diagram showing an example of a cross-sectional structure taken along the fourth line (DD') shown.

[0374] Reference Fig.15 and Fig.22A , schematically showing the Fig.15 The cross-sectional structure 2200-1 of the first pixel (PX1) and the fourth pixel (PX4) taken along the fourth line (D-D') of FIG. Fig.22A Illustrated along the Fig.15 The cross-sectional structure 2200-1 of the first pixel (PX1) and the fourth pixel (PX4) taken along the fourth line (D-D') of FIG. 2200-1 is similar to that of FIG. Figures 16 to 18 The planar structures are basically the same, so the following description will focus on these differences.

[0375] The cross-sectional structure 2200-1 may include: a first output node (ON1) and a fourth output node (ON4) arranged to be spaced apart from each other within a semiconductor substrate, a first bias node (BN1a) arranged on the left side of the first output node (ON1), a first bias node (BN1d) and a fourth bias node (BN4a) set between the first output node (ON1) and the fourth output node (ON4), and a fourth bias node (BN4d) arranged on the right side of the fourth output node (ON4).

[0376] Each of the first bias node (BN1a, BN1d) and the fourth bias node (BN4a, BN4d) may have a greater depth than each of the first output node (ON1) and the fourth output node (ON4). The first bias node (BN1a, BN1d) and the fourth bias node (BN4a, BN4d) are formed at a deep position close to the bottom surface of the semiconductor substrate so that the movement of carriers (C) generated in a specific pixel is interrupted, thereby facilitating isolation of the pixel from adjacent pixels.

[0377] The carriers (C) generated by the avalanche process caused by photons incident on a specific pixel can be transmitted to the corresponding output nodes (ON1, ON4) through the electric field of the first bias node (BN1a, BN1d) and the fourth bias node (BN4a, BN4d) formed at a deep position near the bottom surface of the semiconductor substrate, so that the final carriers (C) can be detected.

[0378] Fig. 22B is an example of some implementations based on the disclosed technology, along the Fig.19 A diagram showing an example of a cross-sectional structure taken along the fifth line (EE') shown.

[0379] Reference Fig.19 and Fig. 22B , schematically showing the Fig.19 A cross-sectional structure 2200-2 of the first pixel (PX1) and the fourth pixel (PX4) taken along the fifth line (EE') of FIG.

[0380] Although for ease of description, Fig. 22B Illustrated along the Fig.19The cross-sectional structure 2200-2 of the first pixel (PX1) and the fourth pixel (PX4) taken along the fifth line (EE') of FIG. 2200-2 is similar to that of FIG. Fig. 20 and Fig.21 The planar structures are basically the same, so the following description will focus on these differences.

[0381] The cross-sectional structure 2200-2 may include: a first output node (ON1) and a fourth output node (ON4) arranged to be spaced apart from each other within a semiconductor substrate, a first bias node (BN1a) arranged on the left side of the first output node (ON1), a first bias node (BN1d) and a fourth bias node (BN4a) set between the first output node (ON1) and the fourth output node (ON4), a fourth bias node (BN4d) arranged on the right side of the fourth output node (ON4), a first guard ring (GR1) set on both the left and right sides of the first output node (ON1), and a fourth guard ring (GR4) set on both the left and right sides of the fourth output node (ON4).

[0382] Fig. 22B The first output node (ON1) and the fourth output node (ON4) and the first bias node (BN1a, BN1d) and the fourth bias node (BN4a, BN4d) are connected to Fig.22A The nodes are basically the same, and similarly, repeated descriptions thereof will be omitted herein.

[0383] The depth of each of the first guard ring (GR1) and the fourth guard ring (GR4) may be less than the depth of each of the first bias node (BN1a, BN1d) and the fourth bias node (BN4a, BN4d), and may be greater than the depth of each of the first output node (ON1) and the fourth output node (ON4).

[0384] The first guard ring (GR1) and the fourth guard ring (GR4) may electrically separate the first output node (ON1) and the fourth output node (ON4) from the first bias node (BN1a, BN1d) and the fourth bias node (BN4a, BN4d), and thus may prevent an edge breakdown phenomenon.

[0385] Fig.23A is a diagram illustrating an example of a planar structure of pixels included in a pixel array based on some implementations of the disclosed technology.

[0386] Reference Fig.16 and Fig.23A , schematically illustrates a planar structure 2300 - 1 of a sensor array of pixels (PX) included in the pixel array 110 .

[0387] The following will be based on Fig.16 The planar structure 2300-1 is described by taking the modified implementation of the first pixel (PX1) as an example, but the technical concept of the disclosed technology can also be basically equally applied to Figures 15 to 21 Other pixels shown.

[0388] The planar structure 2300-1 may include: a plurality of first bias nodes (BN1a to BN1d) disposed at vertices of the planar structure 2300-1, a circular first bias node (BN1e) disposed at the center of the planar structure 2300-1, and a first output node (ON1) surrounding the first bias node (BN1e).

[0389] That is, with Fig.16 Unlike the first pixel (PX1) of FIG. 2300-1, a first bias node (BN1e) may be added to the pixel including the planar structure 2300-1 and may be disposed at the center of the pixel. The first bias node (BN1e) may be defined as a central bias node.

[0390] The first output node (ON1) may be spaced apart from the first bias node (BN1e) by a predetermined distance and may have a ring shape surrounding the first bias node (BN1e). Fig.23A In the example, since the first bias node (BN1e) has a circular shape, the first output node (ON1) may have a ring shape, so that the distance between the first output node (ON1) and the first bias node (BN1e) may be kept constant.

[0391] The scope of the disclosed technology is not limited thereto, and the first output node (ON1) may have a ring shape corresponding to the shape of the first bias node (BN1e) so that the distance between the first output node (ON1) and the first bias node (BN1e) may be kept constant.

[0392] Fig. 23B is an example of some implementations based on the disclosed technology, Fig.23A A cross-sectional view of an example of a planar structure is shown.

[0393] Reference Fig.23A and Fig. 23B , schematically shows that when following Fig.23A The sixth line (F-F') intercepts Fig.23A The cross-sectional structure 2300-2 is obtained when the planar structure 2300-1 is obtained. Fig. 23BThe cross-sectional structure 2300-2 taken along the backslash ("\") direction is illustrated as an example, but other implementations are possible, and substantially the same description may also be applied to other cross-sectional structures taken along the slash (" / ") direction, and also for the sake of brevity, repeated descriptions thereof will be omitted herein.

[0394] The cross-sectional structure 2300-2 may include: first output nodes (ON1) arranged to be spaced apart from each other within the semiconductor substrate, a first bias node (BN1e) disposed between the first output nodes (ON1), a first bias node (BN1a) arranged on the left side of the left first output node (ON1), and a first bias node (BN1d) arranged on the right side of the right first output node (ON1). The depth of the first output node (ON1) may be greater than the depth of each of the first bias nodes (BN1a, BN1d, BN1e), but the scope of the disclosed technology is not limited thereto.

[0395] The first bias node (BN1e) may receive a bias voltage (VB) for enabling the SPAD corresponding to the cross-sectional structure 2300-2 to enter the Geiger mode. Here, the bias voltage (VB) may be the first bias voltage (VB1) or the second bias voltage (VB2), but in the following description, it is assumed that the bias voltage (VB) is the first bias voltage (VB1).

[0396] In addition, the first bias node ( BN1 a , BN1 d ) may be connected to the ground and may receive a ground voltage (eg, 0 V).

[0397] Due to the voltage difference between the first bias nodes (BN1a, BN1e), a first current (I1) can flow through the semiconductor substrate between the first bias nodes (BN1a, BN1e). In addition, due to the voltage difference between the first bias nodes (BN1d, BN1e), a second current (I2) can flow through the semiconductor substrate between the first bias nodes (BN1d, BN1e). Fig. 23B The paths of the first current ( I1 ) and the second current ( I2 ) shown are merely examples, the scope of the disclosed technology is not limited thereto, and the first current ( I1 ) and the second current ( I2 ) may flow through various paths.

[0398] In addition, when the bias voltage (VB) is the second bias voltage (VB2), the first current I1 and the second current I2 may flow in opposite directions.

[0399] Carriers (C) generated by photons incident on the semiconductor substrate may move with the flow of the first current (I1) or the second current (I2) and may trigger avalanche breakdown due to an electric field directed toward the first output node (ON1).

[0400] In other words, even if carriers (C) generated by photons incident on the semiconductor substrate have difficulty in generating an avalanche process, an avalanche process can be induced by moving the carriers (C) via a current flowing between bias nodes, thereby increasing the sensitivity of the corresponding SPAD.

[0401] exist FIG. 8A to FIG. 23B In, various structures for increasing or decreasing the sensitivity (PDE or DCR) of the SPAD are described. According to an embodiment of the disclosed technology, a first SPAD (SPAD_C) and a second SPAD (SPAD_A) having different characteristics can be set in the pixel array 110. Therefore, a first SPAD (SPAD_C) and a second SPAD (SPAD_A) optimized according to the design purpose of the imaging device (ID) can be selected. For example, in order to expand the dynamic range by maximizing the sensitivity difference between the first SPAD (SPAD_C) and the second SPAD (SPAD_A), a structure for minimizing the sensitivity can be selected for the first SPAD (SPAD_C), and the selected structure can then be applied to the first SPAD (SPAD_C), and a structure for maximizing the sensitivity can be selected for the second SPAD (SPAD_A), and the selected structure can then be applied to the second SPAD (SPAD_A).

[0402] In addition, as necessary, the structures of the first SPADs (SPAD_C) included in one pixel array 110 may be different from each other, or the structures of the second SPADs (SPAD_A) included in one pixel array 110 may be different from each other.

[0403] For example, in a region where the light receiving efficiency (or the amount of light received per unit area) is degraded by being disposed near the edge of the pixel array 110, a structure capable of increasing sensitivity may be applied to the first SPAD (SPAD_C). In a region where the light receiving efficiency (or the amount of light received per unit area) is increased by being disposed near the optical axis of the pixel array 110, a structure capable of reducing sensitivity may be applied to the first SPAD (SPAD_C).

[0404] The structure and operation of the SPAD and the pixel, the position of the impurity regions of the SPAD and the pixel, the doping concentration, etc. are merely examples and may be changed within the scope of the technical idea to which the disclosed technology can be applied.

[0405] As is apparent from the above description, image sensing devices based on some implementations of the disclosed technology may include single photon avalanche diode (SPAD) pixels with different sensitivities, and one or more SPAD pixels that are appropriate for the situation may be used to detect the distance of a target object, thereby achieving optimal performance optimized for the imaging device.

[0406] Embodiments of the disclosed technology can provide various effects that can be directly or indirectly identified through the above-mentioned patent documents.

[0407] Those skilled in the art will appreciate that the disclosed technology can be implemented in other specific ways than those described herein. In addition, claims that are not explicitly presented in the appended claims can be presented in combination as embodiments, or included as new claims by subsequent amendments after submitting this application.

[0408] Although a number of exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be devised based on what is described and / or illustrated in this patent document.

[0409] CROSS-REFERENCE TO RELATED APPLICATIONS

[0410] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0096705 filed on July 25, 2023, Korean Patent Application No. 10-2023-0166739 filed on November 27, 2023, and Korean Patent Application No. 10-2024-0082106 filed on June 24, 2024, the disclosures of which are incorporated herein by reference in their entirety as part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: A first pixel, wherein the first pixel comprises a first single photon avalanche diode (SPAD), and the first SPAD comprises a cathode for receiving a first bias voltage; a second pixel, the second pixel comprising a second SPAD, the second SPAD comprising an anode for receiving a second bias voltage; as well as A selection circuit is coupled to the first pixel and the second pixel and selects the first pixel or the second pixel to generate an output.

2. The image sensing device according to claim 1, wherein: The selection circuit comprises: A mode selector activates the first pixel or the second pixel in response to a mode selection signal based on at least one of illumination information, power information, user selection information, or temperature information.

3. The image sensing device according to claim 2, wherein: The first pixel comprises: a first control transistor coupled between the cathode of the first SPAD and the mode selector and receiving a mode selection voltage in response to the mode selection signal, and The second pixel comprises: A second control transistor is coupled between the anode of the second SPAD and the mode selector and receives the mode selection voltage.

4. The image sensing device according to claim 3, wherein: The first control transistor is turned on in response to the mode selection voltage being the first bias voltage to transmit the first bias voltage to the cathode of the first SPAD.

5. The image sensing device according to claim 3, wherein: The second control transistor is turned on in response to the mode selection voltage being the second bias voltage to transfer the second bias voltage to the anode of the second SPAD.

6. The image sensing device according to claim 3, wherein: The first control transistor is a PMOS transistor, and The second control transistor is an NMOS transistor.

7. The image sensing device according to claim 2, wherein: The first pixel comprises: a first control transistor coupled between the cathode of the first SPAD and a node to which the first bias voltage is applied and receiving a mode selection voltage in response to the mode selection signal, and The second pixel comprises: A second control transistor is coupled between the anode of the second SPAD and a node to which the second bias voltage is applied and receives the mode selection voltage.

8. The image sensing device according to claim 7, wherein: The first control transistor is turned on in response to the mode selection voltage being at a first activation voltage lower than the first bias voltage to transmit the first bias voltage to the cathode of the first SPAD.

9. The image sensing device according to claim 7, wherein: The second control transistor is turned on in response to the mode selection voltage being at a second activation voltage higher than the second bias voltage to transfer the second bias voltage to the anode of the second SPAD.

10. The image sensing device according to claim 2, wherein: The mode selector activates the first pixel in response to the illuminance information indicating that the illuminance value is equal to or greater than a predetermined threshold.

11. The image sensing device according to claim 2, wherein: The mode selector activates the second pixel in response to the illuminance information indicating that the illuminance value is less than a predetermined threshold.

12. The image sensing device according to claim 1, wherein: The selection circuit comprises: An output selector selects an output signal of the first pixel or an output signal of the second pixel as a pixel output signal in response to a mode selection signal based on illumination information.

13. The image sensing device according to claim 12, wherein: The output selector selects the output signal of the first pixel in response to the illuminance information indicating that a illuminance value is equal to or greater than a predetermined threshold value.

14. The image sensing device according to claim 12, wherein: The output selector selects the output signal of the second pixel in response to the illuminance information indicating that the illuminance value is less than a predetermined threshold.

15. The image sensing device according to claim 1, wherein: The first pixels and the second pixels are alternately arranged along a first direction.

16. The image sensing device according to claim 1, wherein: The first pixels and the second pixels form a first block and a second block, respectively, each of the first block and the second block having an (M×N) matrix structure, Wherein, at least one of M and N is a natural number of 2 or greater, In the first block, the first pixel is arranged adjacent to another first pixel, and In the second block, the second pixel is arranged adjacent to another second pixel.

17. The image sensing device according to claim 1, wherein: Each of the first pixel and the second pixel comprises: a sensor layer, the sensor layer comprising the first SPAD or the second SPAD; and A logic layer, wherein the logic layer includes a circuit for driving the first SPAD or the second SPAD.

18. The image sensing device according to claim 1, wherein: The second pixel further includes: A first optical structure increases the sensitivity of the second SPAD.

19. The image sensing device according to claim 18, wherein: The first optical structure also includes: A plurality of uneven structures are formed to scatter light incident on the second pixel.

20. The image sensing device according to claim 1, wherein: The first pixel further includes: A second optical structure reduces the sensitivity of the first SPAD.

21. The image sensing device according to claim 1, wherein: The first pixel comprises: a first output node disposed at the center of the first pixel and corresponding to an anode of the first SPAD; and A first bias node is disposed around the first output node and corresponds to the cathode of the first SPAD.

22. The image sensing device according to claim 1, wherein: The first pixel comprises: a first P-type region disposed on a top surface of a semiconductor substrate and corresponding to an anode of the first SPAD; and A first N-type region is spaced apart from the first P-type region and corresponds to the cathode of the first SPAD.

23. The image sensing device according to claim 1, wherein: The first pixel comprises: a first output node disposed at the center of the first pixel and corresponding to an anode of the first SPAD; and A first bias node is provided at each vertex of the first pixel and corresponds to the cathode of the first SPAD.

24. The image sensing device according to claim 1, wherein: The first pixel comprises: a center bias node disposed at a center of the first pixel and corresponding to the cathode of the first SPAD; a first output node disposed around the central bias node and corresponding to an anode of the first SPAD; and A first bias node is disposed at each vertex of the first pixel.

25. An image sensing device, comprising: A first pixel, the first pixel comprising a first single photon avalanche diode (SPAD) having a first detection sensitivity; a second pixel including a second SPAD having a second detection sensitivity higher than the first detection sensitivity; as well as A selection circuit is coupled to the first pixel and the second pixel and selects the first pixel or the second pixel to generate an output.

26. An image sensing device, comprising: a plurality of single photon avalanche diodes (SPADs), each SPAD receiving a bias voltage to operate in a Geiger mode in which a reverse bias voltage exceeding a breakdown voltage occurs; as well as A selection circuit is coupled to the plurality of SPADs and selects any one of the plurality of SPADs to generate an output.

Images