Microlens manufacturing method and image sensor manufacturing method

Abstract

The invention provides a manufacturing method of a micro lens and a manufacturing method of an image sensor. The manufacturing method of the micro lens comprises the following steps: forming a graphical photoresist layer on a hard mask layer; etching the hard mask layer by taking the patterned photoresist layer as a mask, and simultaneously etching and removing the patterned photoresist layer and exposing the semiconductor substrate to obtain a patterned hard mask layer positioned on the semiconductor substrate; etching the semiconductor substrate by taking the patterned hard mask layer as a mask, and simultaneously etching and removing the patterned hard mask layer to obtain a micro lens formed in the semiconductor substrate; wherein the etching selection ratio of the semiconductor substrate relative to the hard mask layer is greater than the etching selection ratio of the semiconductor substrate relative to the patterned photoresist layer. Therefore, under the condition that the morphology of the patterned photoresist layer is not changed, through designing the high etching selection ratio of the semiconductor substrate compared with the hard mask layer, a micro lens morphology with a larger aspect ratio can be formed, the morphology quality of the micro lens is effectively improved, and the final device performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a microlens and an image sensor. Background Art

[0002] A microlens is a small lens that can provide good optical quality. A microlens array includes a plurality of microlenses formed in a one-dimensional or two-dimensional array on a semiconductor substrate.

[0003] Microlenses and microlens arrays are widely used in optical processing devices such as displays, stereoscopic imaging, fiber coupling, and detector arrays. With the development of integrated circuit technology, microlens arrays are widely used in image sensor technology, such as charge coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Generally speaking, CCD, CMOS and other forms of microlens arrays convert light patterns (such as images) into charge patterns.

[0004] As the size of semiconductor devices becomes smaller and smaller, how to form microlenses with good morphology has become a factor that the industry considers.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In view of the problems in the prior art, the purpose of the present invention is to provide a method for manufacturing a microlens and a method for manufacturing an image sensor, which overcomes the difficulties of the prior art and can improve the morphology quality of the microlens.

[0007] A first aspect of the present disclosure provides a method for manufacturing a microlens, comprising: providing a semiconductor substrate, and forming a hard mask layer on the semiconductor substrate; forming a patterned photoresist layer on the hard mask layer, wherein the patterned photoresist layer has an original microlens pattern; Using the patterned photoresist layer as a mask, etching the hard mask layer, while removing the patterned photoresist layer and exposing the semiconductor substrate, to obtain a patterned hard mask layer on the semiconductor substrate; Etching the semiconductor substrate using the patterned hard mask layer as a mask, while removing the patterned hard mask layer by etching, to obtain a microlens formed in the semiconductor substrate; Wherein, an etching selectivity ratio of the semiconductor substrate to the hard mask layer is greater than an etching selectivity ratio of the semiconductor substrate to the patterned photoresist layer.

[0008] In some embodiments, the photoresist layer and the hard mask layer have the same thickness, and when the hard mask layer is etched using the patterned photoresist layer as a mask, an etching selectivity ratio of the hard mask layer to the patterned photoresist layer is 1.

[0009] In some embodiments, during the process of etching the semiconductor substrate, an etching selectivity ratio of the semiconductor substrate to the hard mask layer is 8-40.

[0010] In some embodiments, the microlens manufacturing method further includes: In the process of etching the semiconductor substrate using the patterned hard mask layer as a mask, the etching selectivity ratio of the semiconductor substrate to the hard mask layer is adjusted by controlling etching process parameters.

[0011] In some embodiments, the etching process parameters include one or more of the following: Bias power, which ranges from 100 to 200W; Source power, which ranges from 300 to 600W; The flow ratio of hydrogen bromide gas to chlorine gas is in the range of 2 to 5; Oxygen flow rate, which ranges from 8 to 15 sccm; The etching chamber pressure ranges from 10 to 20 mT.

[0012] In some embodiments, adjusting the etching selectivity of the semiconductor substrate to the hard mask layer by controlling etching process parameters includes: The etching selectivity of the semiconductor substrate over the hard mask layer is determined according to the target aspect ratio of the microlens to be manufactured, and the etching selectivity of the semiconductor substrate over the hard mask layer is obtained by adjusting the etching process parameters.

[0013] In some embodiments, the hard mask layer is a stacked structure of one or more layers selected from the group consisting of a titanium nitride layer, a silicon nitride layer, and a silicon oxide layer.

[0014] In some embodiments, the microlens manufacturing method is also used to manufacture a microlens array, and multiple microlenses in the microlens array are manufactured in the same process.

[0015] In some embodiments, forming a patterned photoresist layer on the hard mask layer includes: forming a photoresist layer on the hard mask layer, wherein the photoresist layer covers the hard mask layer; Performing a first patterning on the photoresist layer using a photolithography technique; The photoresist layer after the first patterning is patterned for the second time using a hot melt method to obtain the patterned photoresist layer.

[0016] A second aspect of the present disclosure provides a method for manufacturing an image sensor, comprising: Providing a semiconductor substrate, and manufacturing a photodiode on the semiconductor substrate; forming an interlayer dielectric layer on the semiconductor substrate and the photodiode; A microlens corresponding to the photodiode is manufactured on the interlayer dielectric layer using the microlens manufacturing method of any of the above embodiments.

[0017] In the embodiment of the present disclosure, in the process of etching the hard mask layer using the patterned photoresist layer as a mask, the patterned photoresist layer is also etched at the same time, and when the patterned photoresist layer is completely removed, the original microlens pattern in the patterned photoresist layer is transferred to the hard mask layer. Then, the semiconductor substrate is etched using the patterned hard mask layer as a mask, and in this process, the patterned hard mask layer is also etched at the same time. When the patterned hard mask layer is etched and removed, a microlens is formed in the semiconductor substrate. In the process of etching the semiconductor substrate, since the semiconductor substrate has a higher etching selectivity than the hard mask layer, that is, under the same etching conditions, the etching rate of the semiconductor substrate is higher than the etching rate of the patterned hard mask layer, so that the semiconductor substrate is etched faster and deeper, when the patterned hard mask layer is removed, a groove with a higher aspect ratio than the original microlens pattern can be formed in the semiconductor substrate, which naturally makes the corresponding microlens taller and has a larger aspect ratio, that is, a larger curvature.

[0018] Therefore, without changing the morphology of the patterned photoresist layer, by designing a high etching selectivity of the semiconductor substrate compared to the hard mask layer, a microlens morphology with a larger aspect ratio can be formed, thereby effectively improving the quality of the microlens morphology and the final device performance.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.

[0021] Figure 1 The present invention provides a flowchart of a method for manufacturing a microlens according to an embodiment of the present invention.

[0022] Figure 2-Figure 8 For use Figure 1The structure diagram of each stage of the microlens manufacturing method is shown.

[0023] Fig. 9 A schematic diagram showing the relationship between bias power and etching selectivity in the microlens manufacturing method provided in an embodiment of the present disclosure.

[0024] Fig.10 A schematic diagram of the relationship between source power and etching selectivity in the microlens manufacturing method provided in an embodiment of the present disclosure.

[0025] Fig.11 A schematic diagram showing the relationship between the HBr / Cl2 flow ratio and the etching selectivity ratio in the microlens manufacturing method provided in an embodiment of the present disclosure.

[0026] Fig.12 A schematic diagram of the relationship between O2 flow rate and etching selectivity in the microlens manufacturing method provided in an embodiment of the present disclosure.

[0027] Fig.13 A schematic diagram of the relationship between the pressure ratio in the etching chamber and the etching selectivity ratio during the microlens manufacturing method provided in an embodiment of the present disclosure.

[0028] Fig.14 The present invention provides a flowchart of a method for manufacturing an image sensor according to an embodiment of the present invention.

[0029] Fig.15 For use Fig.14 The structural diagram of the image sensor produced by the manufacturing method of the image sensor shown. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0031] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0032] In addition, the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0033] In the related art, the method for making a microlens includes: using a patterned photoresist layer to directly transfer the microlens pattern to a semiconductor substrate. However, the microlens morphology obtained by this method has defects, especially when making a microlens with a high aspect ratio, the morphology of the microlens has edge collapse.

[0034] In order to solve the technical problems existing in related technologies, the microlens manufacturing method was studied and it was found that currently, a patterned photoresist layer with a microlens pattern is manufactured on a semiconductor substrate by photolithography and hot melt method, and then the microlens pattern in the patterned photoresist layer is transferred to the surface of the semiconductor substrate in a 1:1 manner by etching. In this process, the morphology of the patterned photoresist layer is an important factor affecting the final microlens morphology.

[0035] Research has found that in the process of preparing a patterned photoresist layer using the hot melt method, the molten photoresist has a certain contact angle with the surface of the semiconductor substrate. The contact angle is only related to the wettability of the photoresist material and the surrounding gas environment. In other words, when the photoresist material and the gas environment in the chamber remain constant, the contact angle will basically not change. This results in the inability to produce patterned photoresist layers of all aperture sizes and heights using the hot melt method. For example, when the aspect ratio of the microlens to be produced is high, the failure rate of the patterned photoresist layer is very high. Limited by the morphology of the patterned photoresist layer, the microlens morphology further collapses.

[0036] Although attempts can be made to change the gas environment in the chamber to adjust the morphology of the patterned photoresist layer, this will affect the performance of the semiconductor substrate itself.

[0037] After discovering the problems existing in the related art and their causes and trying various solutions, the embodiments of the present disclosure propose an improved method for manufacturing a microlens to obtain a microlens with good morphology.

[0038] like Figure 1 As shown, the microlens manufacturing method proposed in the embodiment of the present disclosure includes but is not limited to the following steps: Step 110: providing a semiconductor substrate, and forming a hard mask layer on the semiconductor substrate; Step 120: forming a patterned photoresist layer on the hard mask layer, wherein the patterned photoresist layer has an original microlens pattern; Step 130: etching the hard mask layer using the patterned photoresist layer as a mask, while removing the patterned photoresist layer and exposing the semiconductor substrate, thereby obtaining a patterned hard mask layer on the semiconductor substrate; Step 140: etching the semiconductor substrate using the patterned hard mask layer as a mask, and simultaneously removing the patterned hard mask layer by etching to obtain a microlens formed in the semiconductor substrate; Wherein, an etching selectivity ratio of the semiconductor substrate to the hard mask layer is greater than an etching selectivity ratio of the semiconductor substrate to the patterned photoresist layer.

[0039] In the embodiment of the present disclosure, in the process of etching the hard mask layer using the patterned photoresist layer as a mask, the patterned photoresist layer is also etched at the same time, and when the patterned photoresist layer is completely removed, the original microlens pattern in the patterned photoresist layer is transferred to the hard mask layer. Then, the semiconductor substrate is etched using the patterned hard mask layer as a mask, and in this process, the patterned hard mask layer is also etched at the same time. When the patterned hard mask layer is etched and removed, a microlens is formed in the semiconductor substrate. In the process of etching the semiconductor substrate, since the semiconductor substrate has a higher etching selectivity than the hard mask layer, that is, under the same etching conditions, the etching rate of the semiconductor substrate is higher than the etching rate of the patterned hard mask layer, so that the semiconductor substrate is etched faster and deeper, when the patterned hard mask layer is removed, a groove with a higher aspect ratio than the original microlens pattern can be formed in the semiconductor substrate, which naturally makes the corresponding microlens taller and has a larger aspect ratio, that is, a larger curvature.

[0040] Therefore, without changing the morphology of the patterned photoresist layer, by designing a high etching selectivity of the semiconductor substrate compared to the hard mask layer, a microlens morphology with a larger aspect ratio can be formed, thereby effectively improving the quality of the microlens morphology and the final device performance.

[0041] Each step of the microlens manufacturing method is described in detail below in conjunction with the structural schematic diagrams of each stage of the microlens manufacturing process.

[0042] like Figure 2 As shown, a semiconductor substrate 1 is provided, and a hard mask layer 2 is formed on the semiconductor substrate 1 .

[0043] In the embodiment of the present disclosure, the semiconductor substrate 1 provides a process operation basis for subsequent processes.

[0044] In an optional embodiment, the semiconductor substrate 1 may be a third generation wide bandgap semiconductor material such as silicon carbide or gallium nitride. In other embodiments, the material of the semiconductor substrate 1 may also be other materials such as silicon, germanium, silicon germanium, gallium arsenide or indium gallium, and the semiconductor substrate 1 may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the semiconductor substrate 1 may be a material suitable for process requirements or easy to integrate.

[0045] The hard mask layer 2 is used to transfer the microlens pattern. In order to obtain a high selectivity ratio between the semiconductor substrate 1 and the hard mask layer 2, the material of the hard mask layer 2 relative to the semiconductor substrate 1 may be appropriately selected.

[0046] In one embodiment, the hard mask layer 2 may be a stacked structure of one or more layers selected from a titanium nitride (TiN) layer, a silicon nitride (SiN) layer, and a silicon oxide (SiO2) layer. According to the material of the hard mask layer 2, a corresponding manufacturing method is selected to manufacture the hard mask layer 2 so that the hard mask layer 2 covers the semiconductor substrate 1.

[0047] In this embodiment, the material of the hard mask layer 2 affects its subsequent etching selectivity relative to the semiconductor substrate 1. The etching selectivity of the semiconductor substrate 1 relative to the hard mask layer 2 is greater than the etching selectivity of the semiconductor substrate 1 relative to the subsequent patterned photoresist layer to achieve a final high aspect ratio microlens.

[0048] For example, in the subsequent process of etching the semiconductor substrate 1 , the etching selectivity of the semiconductor substrate 1 to the hard mask layer 2 is 8 to 40, and a suitable material of the hard mask layer 2 can be selected according to the etching selectivity range.

[0049] In one embodiment, the hard mask layer 2 may be deposited using chemical vapor deposition (CVD).

[0050] Next, a patterned photoresist layer is formed on the hard mask layer 2 using the following method: like Figure 3 As shown, a photoresist layer 3 is formed on the hard mask layer 2, and the photoresist layer 3 entirely covers the hard mask layer 2; like Figure 4 As shown, the photoresist layer 3 is patterned for the first time using photolithography technology; like Figure 5 As shown, the photoresist layer 3 (such as Figure 4 The second patterning is performed as shown to obtain the final patterned photoresist layer 30.

[0051] refer to Figure 4 and Figure 5As shown, after the first patterning by photolithography, the photoresist layer 3 after the first patterning is cylindrical, and its sidewalls are vertical. Among them, the photolithography technology includes exposure and development. During exposure, a specific wavelength of light is used to selectively irradiate the photoresist layer 3 covering the hard mask layer 2, so that the photosensitive agent in the photoresist layer 3 undergoes a photochemical reaction, thereby causing the chemical composition of the irradiated area (photosensitive area) of the positive photoresist or the unirradiated area (non-photosensitive area) of the negative photoresist to change. These areas with changed chemical composition can be dissolved in a specific developer in the next development process. In the next development process, by adding a developer after the exposure process is completed, the photosensitive area of ​​the positive photoresist and the non-photosensitive area of ​​the negative photoresist will be dissolved in the developer. After this step is completed, the pattern in the photoresist layer 3 can be revealed.

[0052] Then, the second patterning is performed using a hot melt method. The hot melt method uses high temperature to cause the photoresist layer 3 after the first patterning to undergo hot melt reflow, and during the reflow process, the surface tension acts to form a curved surface, such as Figure 5 A pattern of a microlens array is formed in the patterned photoresist layer 30, and each spherical protrusion corresponds to a microlens.

[0053] In this embodiment, the process parameters of the hot melt method may refer to the relevant technologies well known to those skilled in the art, and will not be described in detail here.

[0054] In the embodiment of the present disclosure, an original microlens pattern, or a pseudo microlens pattern, is formed in the patterned photoresist layer 30 , which will be substantially completely transferred to the hard mask layer 2 later.

[0055] like Figure 6 As shown, the photoresist layer 30 (such as Figure 5 As shown in the figure, the hard mask layer 2 is etched with a mask, and the patterned photoresist layer 30 is etched away and the semiconductor substrate 1 is exposed, thereby obtaining a patterned hard mask layer 20 located on the semiconductor substrate 1.

[0056] In this embodiment, in the same etching chamber and under the same etching conditions, the hard mask layer 2 and the patterned photoresist layer 30 are etched simultaneously. When the patterned photoresist layer 30 is etched away, the original microlens pattern therein can be completely transferred to the patterned hard mask layer 20.

[0057] In one embodiment, the photoresist layer 3 and the hard mask layer 2 (such as Figure 3 The thickness of the hard mask layer 2 and the hard mask layer 30 can be the same. When the hard mask layer 2 is etched using the patterned photoresist layer 30 as a mask, the etching selectivity of the hard mask layer 2 compared to the patterned photoresist layer 30 is 1. Figure 5 and Figure 6When the patterned photoresist layer 30 is etched away, the microlens pattern in the finally formed patterned hard mask layer 20 is substantially the same as the original microlens pattern in the patterned photoresist layer 30 .

[0058] In another embodiment, the etching selectivity ratio of the hard mask layer 2 to the patterned photoresist layer 30 may be slightly greater than 1 or slightly less than 1, both of which can achieve the purpose of transferring the original microlens pattern.

[0059] In other embodiments, the etching selectivity of the hard mask layer 2 relative to the patterned photoresist layer 30 can be greater than 1, and the etching rate of the hard mask layer 2 is faster than that of the patterned photoresist layer 30. When the patterned photoresist layer 30 is etched away, the microlens pattern in the patterned hard mask layer 20 has a higher aspect ratio than the original microlens pattern in the patterned photoresist layer 30, which can further enhance the final microlens aspect ratio.

[0060] In the embodiment of the present disclosure, a dry etching process is used to etch the hard mask layer 2 and the patterned photoresist layer 30. The dry etching can achieve anisotropic etching, has a large etching rate in the vertical direction, and achieves complete transfer of the pattern. Among them, the etching parameters of the dry etching process can be selected according to the material of the hard mask layer 2 and the patterned photoresist layer 30, which can be achieved by those skilled in the art according to relevant technologies.

[0061] like Figure 7 As shown, the semiconductor substrate 1 is etched with the patterned hard mask layer 20 as a mask, and the patterned hard mask layer 20 is etched at the same time, and the dotted line indicates the position of the patterned hard mask layer 20 before etching; like Figure 8 As shown, when the patterned hard mask layer 20 (such as Figure 7 When the semiconductor substrate 1 is etched away, a portion of the depth of the etched portion in the semiconductor substrate 1 is obtained to obtain a microlens 10 formed in the semiconductor substrate 1.

[0062] In this embodiment, the etching selectivity ratio of the semiconductor substrate 1 to the patterned hard mask layer 20 is greater than that of the semiconductor substrate 1 to the patterned photoresist layer 30 (eg, Figure 5 This allows for a faster etching rate for the semiconductor substrate 1. When the patterned hard mask layer 20 is removed, the semiconductor substrate 1 can be etched deeper, thereby obtaining a microlens 10 with a larger aspect ratio.

[0063] In this embodiment, the patterned hard mask layer 20 has a comparable etching selectivity compared to the patterned photoresist layer 30, and the etching selectivity of the semiconductor substrate 1 to the patterned hard mask layer 20 is greater than that of the patterned hard mask layer 20 to the patterned photoresist layer 30, so that the original microlens pattern is completely transferred to the patterned hard mask layer 20, and then readjusted into a microlens 10 with a high aspect ratio. Figure 6 and Figure 8 As shown, the aspect ratio of the microlens 10 is significantly higher than the aspect ratio of the patterned hard mask layer 20 .

[0064] As described above, during the etching of the semiconductor substrate 1, the etching selectivity of the semiconductor substrate 1 to the patterned hard mask layer 20 is 8 to 40. This can be achieved by selecting the hard mask layer 2 (e.g. Figure 2 The etching selectivity ratio of the semiconductor substrate 1 to the hard mask layer 2 can be further adjusted by controlling etching process parameters to achieve dynamic adjustment of the etching selectivity ratio.

[0065] In the embodiment of the present disclosure, the hard mask layer 2 including a silicon oxide layer is taken as an example to illustrate the corresponding etching process parameter adjustment principle.

[0066] like Fig. 9 As shown, the etching process parameter is bias power (Bias Power), the horizontal axis represents Bias Power, and the vertical axis represents the etching selectivity ratio of the semiconductor substrate 1 relative to silicon oxide, taking polysilicon (poly silicon) as an example, which is expressed as PO / OX sel. Exemplarily, in the range of Bias Power of 100 to 200 W, the approximate adjustment range of PO / OX sel is 21 to 29. Therefore, by adjusting the Bias Power within the range of 100 to 200 W, the required PO / OX sel is obtained.

[0067] like Fig.10 As shown in the figure, the etching process parameter is source power, the horizontal axis represents source power, and the vertical axis represents PO / OX sel. For example, when source power is in the range of 300 to 600 W, the approximate adjustment range of PO / OX sel is 24 to 24.3. Fig. 9 Therefore, PO / OX sel can be fine-tuned in a narrow range.

[0068] like Fig.11As shown in the figure, hydrogen bromide (HBr) gas and chlorine (Cl2) gas are used in the etching process, and the etching process parameter is the flow ratio of HBr to Cl2, which is recorded as HBr / Cl2Ratio, and the vertical axis represents PO / OX sel. For example, in the range of HBr / Cl2Ratio of 2 to 5, the approximate adjustment range of PO / OX sel is 23.3 to 23.6. This etching selectivity adjustment range is relative to Fig. 9 Therefore, PO / OX sel can be fine-tuned in a narrow range.

[0069] like Fig.12 As shown, oxygen (O2) is used in the etching process, the etching process parameter is the O2 flow rate, denoted as O2Flow, and the vertical axis represents PO / OX sel. For example, in the range of O2Flow of 8 to 15 sccm, the approximate adjustment range of PO / OX sel is 19 to 28.5.

[0070] like Fig.13 As shown, the etching process parameter is the etching chamber pressure (pressure), which is the horizontal axis, and the vertical axis represents PO / OX sel. For example, the pressure ranges from 10 to 20 mT, and the approximate adjustment range of PO / OX sel is 14 to 39.

[0071] From above Figure 9-13 As shown, each etching process parameter has a different adjustment range for the etching selectivity. In practical applications, by adjusting at least one etching process parameter, the etching selectivity can be adjusted within the range of 8 to 40 to obtain a final high aspect ratio.

[0072] In the embodiment of the present disclosure, the etching process parameters are controlled to adjust the thickness of the semiconductor substrate 1 compared to the hard mask layer 2 (such as Figure 2 The etching selectivity ratio includes: The etching selectivity of the semiconductor substrate 1 over the hard mask layer 2 is determined according to the target aspect ratio of the microlens to be manufactured, and the etching selectivity of the semiconductor substrate 1 over the hard mask layer 2 is obtained by adjusting the etching process parameters.

[0073] In the embodiment of the present disclosure, the target aspect ratio of the microlens to be manufactured is determined in advance, and then the etching selectivity corresponding to the target aspect ratio is calculated, and the etching process parameters are further accurately adjusted accordingly to obtain the final desired etching selectivity.

[0074] In the embodiment of the present disclosure, when obtaining a microlens with a target aspect ratio, the patterned hard mask layer 20 (eg Figure 7In another embodiment, when the microlens with the target aspect ratio is obtained, the patterned hard mask layer 20 may not be removed at the same time. In this case, the remaining patterned hard mask layer 20 may be removed through a further removal step.

[0075] By using the method of the above embodiment, the semiconductor substrate can achieve a higher etching selectivity relative to the material of the hard mask layer, and the aspect ratio of the microlens will no longer be limited by the contact angle of the photoresist hot melt method, so that the preparation of ultra-high aspect ratio microlenses can be achieved. Furthermore, there are various methods for controlling the etching selectivity of the semiconductor substrate relative to the hard mask layer. For example, by controlling the etching process parameters, the curvature of the microlens preparation can be more easily controlled.

[0076] The microlens manufacturing method of the disclosed embodiment is not limited to microlenses, but can also be used to manufacture microlens arrays, such as Figure 8 As shown, the plurality of microlenses 10 in the microlens array are manufactured in the same process, thereby enabling the manufacture of a microlens array with controllable curvature.

[0077] The present disclosure also provides a method for manufacturing an image sensor. Fig.14 As shown, the production method includes but is not limited to the following steps: Step 1410: providing a semiconductor substrate, and manufacturing a photodiode on the semiconductor substrate; Step 1420: forming an interlayer dielectric layer on the semiconductor substrate and the photodiode; Step 1430: Use the microlens manufacturing method of any of the above embodiments to manufacture a microlens corresponding to the photodiode on the interlayer dielectric layer.

[0078] Combination Fig.15 , Fig.15 For use Fig.14 The image sensor manufactured by the provided image sensor manufacturing method comprises: A semiconductor substrate 100, on which a photodiode 200 is fabricated; An interlayer dielectric layer 300 formed on the semiconductor substrate 100 and the photodiode 200; The micro lens 400 is located on the interlayer dielectric layer 300 and corresponds to the photodiode 200 .

[0079] As above Fig.15 The image sensor shown is a CMOS image sensor, and each photodiode 200 may correspond to a microlens array composed of a plurality of microlenses 400 above. The microlenses 400 are used for focusing light, and the photodiode 200 is used for receiving the focused light and performing photoelectric conversion output.

[0080] In other embodiments of the present disclosure, the above-mentioned microlens manufacturing method can be applied to other semiconductor device manufacturing methods including microlenses or microlens arrays.

[0081] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for manufacturing a microlens, characterized in that: include: providing a semiconductor substrate, and forming a hard mask layer on the semiconductor substrate; forming a patterned photoresist layer on the hard mask layer, wherein the patterned photoresist layer has an original microlens pattern; Using the patterned photoresist layer as a mask, etching the hard mask layer, while removing the patterned photoresist layer and exposing the semiconductor substrate, to obtain a patterned hard mask layer on the semiconductor substrate; Etching the semiconductor substrate using the patterned hard mask layer as a mask, while removing the patterned hard mask layer by etching, to obtain a microlens formed in the semiconductor substrate; Wherein, an etching selectivity ratio of the semiconductor substrate to the hard mask layer is greater than an etching selectivity ratio of the semiconductor substrate to the patterned photoresist layer.

2. The method for manufacturing a microlens according to claim 1, characterized in that: The photoresist layer and the hard mask layer have the same thickness. When the hard mask layer is etched using the patterned photoresist layer as a mask, an etching selectivity ratio of the hard mask layer to the patterned photoresist layer is 1.

3. The method for manufacturing a microlens according to claim 2, characterized in that: In the process of etching the semiconductor substrate, an etching selectivity ratio of the semiconductor substrate to the hard mask layer is 8-40.

4. The method for manufacturing a microlens according to claim 1, characterized in that: The microlens manufacturing method further comprises: In the process of etching the semiconductor substrate using the patterned hard mask layer as a mask, the etching selectivity ratio of the semiconductor substrate to the hard mask layer is adjusted by controlling etching process parameters.

5. The method for manufacturing a microlens according to claim 4, characterized in that: The etching process parameters include one or more of the following: Bias power, the range is 0~200W; Source power, which ranges from 300 to 600W; The flow ratio of hydrogen bromide gas to chlorine gas is in the range of 2 to 5; Oxygen flow rate, which ranges from 8 to 15 sccm; The etching chamber pressure ranges from 10 to 20 mT.

6. The method for manufacturing a microlens according to claim 4, characterized in that: The step of adjusting the etching selectivity ratio of the semiconductor substrate to the hard mask layer by controlling etching process parameters comprises: The etching selectivity of the semiconductor substrate over the hard mask layer is determined according to the target aspect ratio of the microlens to be manufactured, and the etching selectivity of the semiconductor substrate over the hard mask layer is obtained by adjusting the etching process parameters.

7. The method for manufacturing a microlens according to claim 1, characterized in that: The hard mask layer is a stacked structure of one or more layers of a titanium nitride layer, a silicon nitride layer and a silicon oxide layer.

8. The method for manufacturing a microlens according to claim 1, characterized in that: The microlens manufacturing method is also used to manufacture a microlens array, and a plurality of microlenses in the microlens array are manufactured in the same process.

9. The method for manufacturing a microlens according to claim 1, characterized in that: The step of forming a patterned photoresist layer on the hard mask layer comprises: forming a photoresist layer on the hard mask layer, wherein the photoresist layer covers the hard mask layer; Performing a first patterning on the photoresist layer using a photolithography technique; The photoresist layer after the first patterning is patterned for the second time using a hot melt method to obtain the patterned photoresist layer.

10. A method for manufacturing an image sensor, characterized in that: include: Providing a semiconductor substrate, and manufacturing a photodiode on the semiconductor substrate; forming an interlayer dielectric layer on the semiconductor substrate and the photodiode; A microlens corresponding to the photodiode is manufactured on the interlayer dielectric layer using the microlens manufacturing method described in any one of claims 1 to 9.

Images