A visual modeling hybrid rate real-time simulation system

Abstract

The application discloses a visual modeling mixed rate real-time simulation system, which comprises a simulation computer, a model development computer, a simulation machine client computer, an automatic test computer, a signal conditioning board card, a fault injection unit, a measured unit, an FPGA model machine and a clock synchronization machine. The simulation computer is used for loading and running control of a simulation model; the model development computer is used for programming and development debugging of the simulation model; the simulation machine client computer is used for running monitoring of the simulation model; the automatic test computer is used for simulation test driving control of the simulation model in a signal loop; the signal conditioning board card is used for converting digital signals after running of the simulation model into analog signals; the fault injection unit is used for soft fault and fault injection functions of a fault mode; the measured unit is used for configuring an object to be tested; the FPGA model machine is used for loading and running compiled FPGA source code; and the clock synchronization machine is used for synchronization of model simulation.

Description

Technical Field

[0001] This invention relates to the field of model simulation, and more specifically to a real-time simulation system for visual modeling and hybrid rates. Background Technology

[0002] Currently, the design of aero-engine control systems and software mainly references some mainstream international processes, such as SAE ARP 4754, DO-178, and DO-331. ARP 4754 outlines the classic double-V process of system requirements analysis, system design, and system verification, while DO-178 presents a process from requirements and coding to integration testing. However, no universally applicable process or typical methodology has been established for implementing the system design process from system requirements to software requirements. Summary of the Invention

[0003] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0004] The purpose of this invention is to solve the above-mentioned problems and provide a real-time simulation system for visual modeling and hybrid rates. This system addresses the current challenges in conducting prototype verification, software integration verification, hardware and software integration verification, and fuel system joint verification (semi-physical verification) of commercial aero-engines based on the Model-Based Design (MBD) process. Due to the numerous specialties involved in system-level verification and unclear interfaces, it is difficult to locate and troubleshoot problems during the integration and operation of the real-time simulation system. This invention optimizes the professional layout of the simulation integration process, improves the efficiency of the division of labor in the simulation system integration, and enhances the quality and efficiency of simulation experiments.

[0005] The technical solution of this invention is as follows:

[0006] This invention provides a real-time simulation system for hybrid rate visualization modeling, comprising a simulation computer, a model development computer, a simulation client computer, an automatic test computer, a signal conditioning board, a fault injection unit, a unit under test, an FPGA model machine, and a clock synchronizer; wherein,

[0007] The simulation computer is used to load and control the operation of the simulation model;

[0008] The model development computer is used to complete the programming, development, and debugging of simulation models;

[0009] The client computer of the simulator is used to monitor the operation of the simulation model;

[0010] The automated test computer is used to perform simulation testing and drive control of the simulation model in the signal loop;

[0011] Signal conditioning boards are used to convert digital signals from simulation models into analog signals.

[0012] The fault injection unit is used to perform the function of injecting soft faults and reactive faults in fault modes.

[0013] The unit under test is used to configure the object being tested;

[0014] The FPGA model machine is used to load and run the compiled FPGA source code;

[0015] A clock synchronizer is used to synchronize the clock during model simulation.

[0016] According to one embodiment of the real-time simulation system for visual modeling with mixed rates according to the present invention, the simulation computer, the model development computer, the automatic testing computer, the simulation client computer, and the FPGA model unit form a computer local area network, and the deployment and operation of the real-time simulation system for visual modeling with mixed rates are completed through the constructed computer local area network.

[0017] According to one embodiment of the visualization modeling hybrid rate real-time simulation system of the present invention, the simulation computer, signal conditioning board, fault injection unit and the unit under test are connected one by one in a point-to-point series manner to form a signal loop, and the signal transmission, conversion and closed loop are completed through the constructed signal loop.

[0018] According to one embodiment of the real-time simulation system for hybrid rate visualization modeling of the present invention, the simulation computer includes a simulation control and operating environment, a simulator OS terminal, a compiler, a simulator operating environment scheduler, a simulator virtual network console server, a human-computer interaction device, a file receiver, and a model interface parser; wherein...

[0019] The simulation control and runtime environment is used to provide functions such as model scheduling, monitoring, test case loading, signal interconnection, and model and CPU core mapping within the simulation computer.

[0020] The emulator OS terminal is used to provide the operating application interface for the emulator;

[0021] A compiler is used to translate a high-level language into a binary target language;

[0022] The simulator runtime environment scheduler is used to schedule the simulator runtime environment;

[0023] The simulator virtual network console server provides a client login interface for remote network access to the simulator.

[0024] Human-computer interaction devices are used to provide a control interface for simulation models;

[0025] The file receiver is used to parse communication signals received through the simulator's hardware network interface;

[0026] The model interface resolver is used to call the model and convert the called model interface into a new standard interface.

[0027] According to an embodiment of the visualization modeling hybrid rate real-time simulation system of the present invention, the simulation control and operation environment includes a simulation environment state machine, a model allocator, a model signal interconnector, a model loader, a real-time operation monitor, and a use case loader; wherein...

[0028] The simulation environment state machine is used to uniformly schedule and execute the model allocator, model signal interconnector, model loader, real-time runtime monitor, and use case loader, and to receive scheduling and execution information from the model allocator, model signal interconnector, model loader, real-time runtime monitor, and use case loader.

[0029] The model assigner is used to assign simulation models;

[0030] Model signal interconnectors are used to interconnect signals between various simulation models;

[0031] The model loader is used to provide status information for use case execution;

[0032] The real-time runtime monitor is used to monitor the real-time operation of the simulation model;

[0033] The test case loader is used to load simulation test cases.

[0034] According to one embodiment of the visualization modeling hybrid rate real-time simulation system of the present invention, the simulation control and operation environment statically configures different models onto specific CPU cores through a model allocator and establishes the runtime sequence between models. Then, it performs simulation operation on each model according to the model runtime sequence, thereby realizing the parallel simulation strategy of the visualization modeling hybrid rate real-time simulation system.

[0035] According to one embodiment of the visual modeling hybrid rate real-time simulation system of the present invention, the model development computer includes a graphical modeling environment, a Makefile generator, a model code generator, a file sender, an FPGA code generator, an FPGA compiler, and an FPGA object code loader; wherein,

[0036] A graphical modeling environment is used to provide a graphical model development environment;

[0037] The Makefile generator is used to generate Makefiles;

[0038] Model code generators are used to convert slow model files into high-level language source code;

[0039] The file sender is used to send high-level language source code and the corresponding Make file to the simulation computer.

[0040] An FPGA code generator is used to convert high-speed model files into FPGA code;

[0041] An FPGA compiler is used to compile FPGA code;

[0042] The FPGA target code loader is used to load FPGA target code.

[0043] According to an embodiment of the real-time simulation system for hybrid rates in visual modeling of the present invention, the model development computer adopts a high-speed / low-speed model partitioning strategy, and builds low-speed and high-speed models respectively through a low-speed model development environment and a high-speed model development environment; wherein...

[0044] The low-speed model development environment includes a graphical modeling environment, a Makefile generator, a model code generator, and a file sender;

[0045] The high-speed model development environment includes a graphical modeling environment, an FPGA code generator, an FPGA compiler, and an FPGA object code loader.

[0046] According to an embodiment of the visualization modeling hybrid rate real-time simulation system of the present invention, the simulator client computer includes a virtual network console client, a remote simulator desktop interface, and a human-computer interaction device; wherein...

[0047] The virtual network console client interacts with the simulated computer via a local area network.

[0048] The remote simulator desktop interface is used to provide remote control commands;

[0049] Human-computer interaction devices are used to provide human-computer control commands.

[0050] According to an embodiment of the visualization modeling hybrid rate real-time simulation system of the present invention, the automatic test computer includes an operating system terminal and a test case transceiver; wherein, the operating system terminal is used to load test cases and test case scripts, and call the test case transceiver to complete the data transmission of test cases.

[0051] According to one embodiment of the visualization modeling hybrid rate real-time simulation system of the present invention, the FPGA model machine includes an FPGA target code loader, a FLASH memory, an FPGA chip, and a high-speed data communication interface; wherein,

[0052] The FPGA target code loader is used to load FPGA source code model binary files;

[0053] FLASH memory is used to store FPGA code loaded by the FPGA target code loader;

[0054] FPGA chips are used to run FPGA code stored in FLASH memory;

[0055] The high-speed data communication interface is used to read data from the high-speed model interface.

[0056] According to one embodiment of the real-time simulation system for visual modeling mixed rates of the present invention, the real-time simulation system for visual modeling mixed rates adopts an operating system with real-time characteristics and triggers real-time simulation through a software timer or a physical clock.

[0057] Compared with existing technologies, this invention offers the following advantages: For the simulation design of commercial aero-engine models, this invention provides a visual modeling hybrid-rate real-time simulation system. It offers a standardized implementation process for each stage of engine model simulation design, enabling the construction of high- and low-speed models through a graphical interface, thereby achieving unified modeling of the hybrid model. Furthermore, this invention divides the high- and low-speed models, running them on different physical entities, ensuring the physical isolation of the hybrid system and the independence between the high- and low-speed models, thus significantly improving the efficiency of fault location during simulation. Simultaneously, this invention employs a parallel simulation strategy loading different models onto different CPU cores, ensuring true parallel operation of the hybrid model, improving the performance of model simulation, and increasing real-time confidence. Attached Figure Description

[0058] The above-described features and advantages of the present invention will be better understood after reading the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings. In the drawings, components are not necessarily drawn to scale, and components having similar related characteristics or features may have the same or similar reference numerals.

[0059] Figure 1 This is an architecture diagram illustrating an embodiment of the visualization modeling hybrid rate real-time simulation system of the present invention.

[0060] Figure 2 This is a data interaction diagram illustrating an embodiment of the visualization modeling hybrid rate real-time simulation system of the present invention.

[0061] Symbol explanation:

[0062] (1): Simulation computer,

[0063] (2): Model development computer,

[0064] (3): Emulator client computer,

[0065] (4): Automatic testing computer,

[0066] (5): Signal conditioning board,

[0067] (6): Fault injection unit,

[0068] (7): Unit under test (UUT)

[0069] (8): FPGA model machine,

[0070] (9): Clock synchronizer

[0071] (1.0): Simulation Control and Operating Environment

[0072] (1.1): Emulator OS terminal,

[0073] (1.2): Compiler,

[0074] (1.3): Model Allocator

[0075] (1.4) Model signal interconnector,

[0076] (1.5): Model loader

[0077] (1.6): Real-time running monitor,

[0078] (1.7): Use Case Loader

[0079] (1.8): Simulation environment state machine,

[0080] (1.9): Simulator runtime environment scheduler,

[0081] (1.10): Virtual network console server for emulators,

[0082] (1.20): File receiver,

[0083] (1.21): Model dynamic library files,

[0084] (1.22): Model executable file,

[0085] (1.23): Model and CPU core binding relationship and timing files,

[0086] (1.24): Mode signal binding relationship file,

[0087] (1.25): Simulation engineering operation data,

[0088] (1.26): Human-computer interaction devices,

[0089] (1.27): Model Interface Parser

[0090] (1.28) Model Interface Encapsulation Source Code

[0091] (2.1): Graphical modeling environment

[0092] (2.2): Low-speed model files

[0093] (2.3): Makefile generator

[0094] (2.4): Model code generator

[0095] (2.5): High-level language source code,

[0096] (2.6): Makefile template,

[0097] (2.7): Make file,

[0098] (2.8): File sender

[0099] (2.11): FPGA source code,

[0100] (2.12): FPGA source code,

[0101] (2.13): FPGA code generator

[0102] (2.14): FPGA compiler,

[0103] (2.15): FPGA target code,

[0104] (2.16): FPGA target code loader,

[0105] (3.1): Virtual network console client,

[0106] (3.2): Remote simulator desktop interface,

[0107] (3.3): Human-computer interaction devices

[0108] (4.1): Test cases,

[0109] (4.2): Test control script,

[0110] (4.3): Operating system terminal,

[0111] (4.4): Use Case Transceiver

[0112] (8.01): FPGA target code loader,

[0113] (8.02): FLASH memory,

[0114] (8.03): FPGA chip,

[0115] (8.04): High-speed data communication interface. Detailed Implementation

[0116] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the aspects described below with reference to the accompanying drawings and specific embodiments are merely exemplary and should not be construed as limiting the scope of protection of the present invention in any way.

[0117] An embodiment of a real-time simulation system for visual modeling of hybrid rates is disclosed herein. Figure 1 This is an architecture diagram illustrating an embodiment of the visual modeling hybrid rate real-time simulation system of the present invention. Figure 1 As shown, this embodiment includes a simulation computer (1), a model development computer (2), a simulation client computer (3), an automatic test computer (4), a signal conditioning board (5), a fault injection unit (FIU) (6), a unit under test (UUT) (7), an FPGA model machine (8), and a clock synchronizer (9). The simulation computer (1) is used to load and control the simulation model; the model development computer (2) is used to program and debug the simulation model; the simulation client computer (3) is used to monitor the operation of the simulation model; the automatic test computer (4) is used to drive and control the simulation test of the simulation model in the signal loop; the signal conditioning board (5) is used to convert the digital signal after the simulation model runs into an analog signal; the fault injection unit (6) is used to inject soft faults and reactive faults in the fault mode; the unit under test (7) is used to configure the object under test; the FPGA model machine (8) is used to load and run the compiled FPGA source code; and the clock synchronizer (9) is used to synchronize the clock during model simulation.

[0118] Specifically, in this embodiment, the simulation computer (1), model development computer (2), automatic testing computer (4), simulation client computer (3), and FPGA model machine (8) constitute a computer local area network (0). The deployment and operation of the visualization modeling hybrid rate real-time simulation system are completed through the constructed computer local area network (0). The specific process is as follows:

[0119] The client computer (3) logs in and remotely controls the simulation computer (1) via the remote login client. Then, the model development computer (2) completes the graphical modeling and model code generation. The generated high-level language source code (with model dynamic library) and Make file of the low-speed model are sent to the simulation computer (1) via UDP protocol. The simulation computer (1) generates and loads the model source file into an executable model file. For the FPGA code of the high-speed model, the model development computer (2) sends the generated high-speed model FPGA code to the FPGA model machine (8) via UDP protocol. The FPGA model machine (8) moves the binary FPGA target code that has completed communication reception to the FLASH memory. After power-on, the code in the FLASH memory is loaded into the FPGA chip and runs at high speed in real time. The automatic test computer (4) sends the test case compilation, test case file and test case execution script file to the simulation computer (1) for control. In this way, through the above collaborative operation, the deployment and operation of the visual modeling and mixed-rate real-time simulation system are completed. At this time, the visual modeling and mixed-rate real-time simulation system can support the simultaneous simulation testing of high-level language models and FPGA language models.

[0120] Furthermore, in this embodiment, the simulation computer (1), signal conditioning board (5), fault injection unit (6), and unit under test (7) are connected one by one in a point-to-point series manner to form a signal loop. The signal transmission, conversion, and closed loop are completed through the constructed signal loop. The specific process is as follows:

[0121] The simulation computer (1) transmits the continuous and switching signals of the simulation model to the signal conditioning board (5) via a cable. Simultaneously, the simulation computer (1) transmits the bus signals (such as ARINC, TTP, 1553B, 422 / 485 / 232, etc.) in the model to the signal conditioning board (5) via another cable. The signal conditioning board (5) conditions the received analog and switching signals into electrical signals with corresponding physical and electrical characteristics and transmits them to the fault injection unit (6). The fault injection unit (6) disconnects and short-circuits the corresponding signal cable loops to inject the corresponding fault. The signal output from the signal conditioning board (5) via the fault injection unit (6) forms a direct loop or an excitation-response secondary loop through the unit under test (7), thereby simulating a real electrical signal with open and short circuit functions.

[0122] Furthermore, in this embodiment, the simulation computer (1) includes a simulation control and operation environment SCRE (1.0), a simulator OS terminal (1.1), a compiler (1.2), a simulator operation environment scheduler (1.9), a simulator virtual network console server (1.10), a human-computer interaction device (1.26), a file receiver (1.20), and a model interface parser (1.27). Among them, the Simulation Control and Operation Environment (SCRE) (1.0) is used to provide the functions of model scheduling, monitoring, test case loading, signal interconnection, and model and CPU kernel mapping within the simulation computer (1); the Simulation OS terminal (1.1) is used to provide the operation application interface of the simulation machine; the compiler (1.2) is used to convert high-level languages ​​into binary target languages; the Simulation Runtime Environment Scheduler (1.9) is used to schedule the simulation runtime environment; the Simulation Virtual Network Console Server (1.10) is used to provide the simulation client login interface for remote network access; the Human-Computer Interaction Device is used to provide the simulation model control operation interface; the File Receiver (1.20) is used to parse the communication signals received through the simulation hardware network interface; and the Model Interface Parser (1.27) is used to call the model and convert the called model interface into a new standard interface model interface encapsulation source code. Figure 2 This is a data interaction diagram illustrating an embodiment of the visual modeling hybrid rate real-time simulation system of the present invention. (See attached diagram.) Figure 2 The internal data flow of the simulation computer (1) is as follows:

[0123] The file receiver (1.20) receives model and script files sent from the file sender (2.8) via the computer's local area network (0) and places their output in the model dynamic library file (1.21). The model interface resolver (1.27) identifies the model dynamic library file from the model dynamic library file (1.21), then generates the model interface encapsulation source code (1.28), and then calls the compiler (1.2) in the simulator's OS terminal (1.1) to load the model interface encapsulation source code (1.28). At this point, if the compilation and linking pass, the Model executable file (1.22) is output; if it fails, fault diagnosis information is output, and the system returns to the graphical modeling environment (2.1) to restart the modeling and compilation debugging process.

[0124] The simulator runtime environment scheduler (1.9) is used to receive test control scripts (4.2) sent by the test case loader (4.4) via the computer local area network (0). At the same time, the simulator runtime environment scheduler (1.9) receives operation instructions sent by the simulator virtual network console server (1.10). The simulator runtime environment scheduler (1.9) schedules and selects between the test case control scripts (4.1) automatically loaded via the network and the operation instructions from the (3.2) remote simulator interactive interface, and outputs the scheduling instruction information to the SCRE state machine (1.8). It also receives the operation feedback information of the simulation control and runtime environment SCRE (1.0) from the SCRE state machine (1.8), and completes the interactive control of the simulation control and runtime environment SCRE (1.0) and other external components in sequence.

[0125] Furthermore, in this embodiment, the Simulation Control and Runtime Environment (SCRE) (1.0) includes a simulation environment state machine (1.8), a model allocator (1.3), a model signal interconnector (1.4), a model loader (1.5), a real-time runtime monitor (1.6), and a use case loader (1.7). The simulation environment state machine (1.8) is used to uniformly schedule the execution of the model allocator (1.3), model signal interconnector (1.4), model loader (1.5), real-time runtime monitor (1.6), and use case loader (1.7), and receives scheduling execution information fed back from these components. The model allocator (1.3) is used to allocate simulation models; the model signal interconnector (1.4) is used to interconnect signals between simulation models; the model loader (1.5) is used to provide status information for test case execution; the real-time runtime monitor (1.6) is used to monitor the real-time operation of simulation models; and the test case loader (1.7) is used to load simulation test cases. The internal flow of the simulation control and runtime environment (1.0) is as follows:

[0126] The model allocator (1.3) receives the Model executable file (1.22), configures it via human-computer interaction, and generates the binding relationship between the Model and the CPU core, as well as the timing file (1.23). Simultaneously, the model signal interconnector (1.4), after human-computer interaction configuration, generates the Model signal binding relationship file (1.24). The real-time run monitor (1.6) generates the simulation project running data (1.25). The test case loader (1.7) reads and parses test cases sent from the operating system terminal (4.3) via the computer local area network (0), outputs the parsed data to the model loader (1.5), and obtains the test case execution status information from the model loader (1.5). Additionally, the test case loader (1.7) also needs to feed back the test case execution record information to the operating system terminal (4.3).

[0127] Furthermore, in this embodiment, the Simulation Control and Runtime Environment (SCRE) (1.0) statically configures different models onto specific CPU cores through the model allocator (1.3), establishes the runtime sequence between models, and generates corresponding (1.16) Model and CPU core binding relationships and timing file scripts by the model loader (1.5). When the Simulation Control and Runtime Environment (SCRE) (1.0) runs, after the model loader (1.5) loads the (1.16) script, the simulation machine operating system loads it onto the specific CPU core, and each model runs in parallel according to its characteristic timing sequence, thereby realizing the parallel simulation strategy of the visual modeling hybrid rate real-time simulation system.

[0128] Further, in this embodiment, the model development computer (2) includes a graphical modeling environment (2.1), a Make file generator (2.3), a model code generator (2.4), a file sender (2.8), an FPGA code generator (2.13), an FPGA compiler (2.14), and an FPGA target code loader (2.16). The graphical modeling environment (2.1) is used to provide a graphical model development environment; the Make file generator (2.3) is used to generate Make files; the model code generator (2.4) is used to convert low-speed model files into high-level language source code; the file sender (2.8) is used to send the high-level language source code and the corresponding Make file to the simulation computer (1); the FPGA code generator (2.13) is used to convert high-speed model files into FPGA code; the FPGA compiler (2.14) is used to compile the FPGA code; and the FPGA target code loader is used to load the FPGA target code.

[0129] In this embodiment, the graphical modeling environment (2.1) provided by the visual modeling hybrid rate real-time simulation system runs on the model development computer (2), and hybrid model simulation is performed through this graphical environment. During operation, graphical operations such as mouse drag, copy, paste, and double-click can be used to complete the configuration of operands and operators represented by various graphical symbols, thereby realizing the completion of the text language compilation corresponding to the logic or algorithm through the graphical operation of the mouse, and completing the model construction. In addition, this embodiment can configure the simulation environment of the model through the graphical model development environment, thereby completing the configuration of model simulation and computing engine (such as step size, settlement unit, diagnostic options, etc.), and complete the simulation operation control (start, pause and end) through mouse operation. Furthermore, the graphical model development environment of this embodiment can separately compile software models and hardware models. By configuring different source code generators, it can generate software source files (such as C language source code files) or hardware FPGA source files (such as VHDL language source code files) from the graphical language model. Then, by associating different compilers, it can generate binary files that can run on a real-time operating system from the software language source files, or generate binary files that can run on an FPGA chip from the hardware language source files.

[0130] Specifically, in this embodiment, the model development computer (2) adopts a high-speed / low-speed model partitioning strategy, building low-speed and high-speed models respectively through a low-speed model development environment and a high-speed model development environment. The low-speed model development environment includes a graphical modeling environment (2.1), a Make file generator (2.3), a model code generator (2.4), and a file sender (2.8). The high-speed model development environment includes a graphical modeling environment (2.1), an FPGA code generator (2.13), an FPGA compiler (2.14), and an FPGA object code loader (2.16). The model development computer (2) builds the low-speed and high-speed models respectively through the low-speed and high-speed model development environments. The low-speed model building process is as follows:

[0131] The low-speed model file (2.2) output by the graphical modeling environment (2.1) is used as input to the model code generator (2.4), and the high-level language source code (2.5) (C / Ada / Fortran, etc.) is output. At the same time, the low-speed model file (2.2) and the Make file template (2.6) are used as input to the Make file generator (2.3), and the Make file (2.7) is output. Then, the high-level language source code (2.5) and the Make file (2.7) are sent to the simulation computer (1) via the computer local area network (0) through the file sender (2.8). At the same time, the simulation computer (1) transmits the feedback diagnostic information to the graphical modeling environment (2.1) through the computer local area network (0), and displays it in the graphical modeling environment (2.1).

[0132] For the construction of a high-speed model, the high-speed model development environment needs to be combined with an FPGA model machine (8). The FPGA model machine (8) includes an FPGA object code loader (8.01) for loading the FPGA source code model binary file, a FLASH memory (8.02) for storing the loaded FPGA code, an FPGA chip (8.03) for running the FPGA code, and a high-speed data communication interface (8.04) for reading high-speed model interface data. The high-speed model construction process is as follows:

[0133] The high-speed model file (2.12) output by the graphical modeling environment (2.1) is used as input to the FPGA code generator (2.13). Then, the FPGA source code (2.11) output by the FPGA code generator (2.13) is used as input to the FPGA compiler (2.14) to generate FPGA target code (2.15). The FPGA target code (2.15) is loaded into the FPGA target code loader (8.01) of the FPGA model machine (8) after being communicated by the FPGA target code loader (2.16) via the computer local area network (0). The FPGA target code loader (8.01) then moves and stores the FPGA target code in the onboard FLASH memory (8.02) of the FPGA model machine (8). After the FPGA model machine (8) is powered on, it automatically loads the FPGA code in the FLASH memory (8.02) into the FPGA chip (8.03), executes the high-speed model in parallel, and continuously refreshes the high-speed data communication interface (8.04) to complete high-speed data reading and writing. The FPGA target code loader (8.01) simultaneously completes the loading of the FPGA chip (8.03) and the acquisition of the running status diagnostic information, and after communication via the computer local area network (0), it is loaded into the FPGA target code loader (2.16).

[0134] Furthermore, in this embodiment, the simulator client computer (3) includes a virtual network console client (3.1), a remote simulator desktop interface (3.2), and a human-computer interaction device (3.3). The virtual network console client (3.1) interacts with the simulator computer (1) via a computer local area network (0), the remote simulator desktop interface (3.2) provides remote control commands, and the human-computer interaction device (3.3) provides human-computer control commands. Its internal process is as follows:

[0135] The human-computer interaction device (3.3) and the remote simulator desktop interface (3.2) exchange operation commands. The remote simulator desktop interface (3.2) transmits control information to the virtual network console client (3.1) and receives interface information from the simulator from the virtual network console client (3.1). At the same time, the virtual network console client (3.1) exchanges information with the simulator virtual network console server (1.10) of the simulator computer (1) through the computer local area network (0).

[0136] Furthermore, in this embodiment, the automatic test computer (4) includes an operating system terminal (4.3) and a test case transceiver (4.4). The operating system terminal (4.3) is used to load test cases and test case scripts, and call the test case transceiver (4.4) to complete the data transmission of test cases, and to complete the test case execution information from the simulator runtime environment scheduler (1.9) via the computer local area network (0).

[0137] Furthermore, in this embodiment, the visual modeling hybrid rate real-time simulation system adopts an operating system with real-time characteristics, and triggers real-time simulation through a software timer or a physical clock.

[0138] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0139] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps are described above in a generalized manner in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the invention.

[0140] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration.

[0141] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read and write information to / from the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and storage medium may reside as discrete components in the user terminal.

[0142] In one or more exemplary embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software as a computer program product, the functionality may be stored or transmitted as one or more instructions or code on or through a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, encompassing any medium that facilitates the transfer of a computer program from one location to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Any connection is also legitimately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. As used in this article, disk and disc include compact discs (CDs), laser discs, optical discs, digital multi-purpose discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

Claims

1. A real-time simulation system for visual modeling and hybrid rates, characterized in that, This includes simulation computers, model development computers, simulation client computers, automatic test computers, signal conditioning boards, fault injection units, units under test, FPGA model machines, and clock synchronizers; among them, The model development computer is used to program, develop, and debug simulation models, which include low-speed and high-speed models. The low-speed model is converted into high-level language source code, and the high-speed model is converted into FPGA code. The simulation computer is used to load and control the operation of low-speed models; The FPGA model machine is used to load and run high-speed models, including loading and running the compiled FPGA source code. The client computer of the simulator is used to monitor the operation of the simulation model; The automated test computer is used to perform simulation testing and drive control of the simulation model in the signal loop; Signal conditioning boards are used to convert digital signals from simulation models into analog signals. The fault injection unit is used to perform the function of injecting soft faults and reactive faults in fault modes. The unit under test is used to configure the object being tested; A clock synchronizer is used to synchronize the clock during model simulation.

2. The real-time simulation system for visual modeling and hybrid rates according to claim 1, characterized in that, The simulation computer, model development computer, automatic testing computer, simulation client computer, and FPGA model unit form a computer local area network (LAN). The deployment and operation of the visualization modeling hybrid rate real-time simulation system are completed through the constructed LAN.

3. The real-time simulation system for visual modeling and hybrid rates according to claim 1, characterized in that, The simulation computer, signal conditioning board, fault injection unit, and unit under test are connected one by one in a point-to-point series manner to form a signal loop. The signal transmission, conversion, and closed loop are completed through the constructed signal loop.

4. The real-time simulation system for visual modeling and hybrid rates according to claim 1, characterized in that, The simulation computer includes a simulation control and operation environment, a simulation OS terminal, a compiler, a simulation runtime environment scheduler, a simulation virtual network console server, human-computer interaction devices, a file receiver, and a model interface parser; among which, The simulation control and runtime environment is used to provide functions such as model scheduling, monitoring, test case loading, signal interconnection, and model and CPU core mapping within the simulation computer. The emulator OS terminal is used to provide the operating application interface for the emulator; A compiler is used to translate a high-level language into a binary target language; The simulator runtime environment scheduler is used to schedule the simulator runtime environment; The simulator virtual network console server provides a client login interface for remote network access to the simulator. Human-computer interaction devices are used to provide a control interface for simulation models; The file receiver is used to parse communication signals received through the simulator's hardware network interface; The model interface resolver is used to call the model and convert the called model interface into a new standard interface.

5. The real-time simulation system for visual modeling and hybrid rates according to claim 4, characterized in that, The simulation control and runtime environment includes a simulation environment state machine, a model distributor, a model signal interconnector, a model loader, a real-time runtime monitor, and a use case loader; among them, The simulation environment state machine is used to uniformly schedule and execute the model allocator, model signal interconnector, model loader, real-time runtime monitor, and use case loader, and to receive scheduling and execution information from the model allocator, model signal interconnector, model loader, real-time runtime monitor, and use case loader. The model assigner is used to assign simulation models; Model signal interconnectors are used to interconnect signals between various simulation models; The model loader is used to provide status information for use case execution; The real-time runtime monitor is used to monitor the real-time operation of the simulation model; The test case loader is used to load simulation test cases.

6. The real-time simulation system for visual modeling and hybrid rates according to claim 5, characterized in that, The simulation control and operation environment statically configures different models onto specific CPU cores through a model allocator and establishes the runtime sequence between models. Then, it performs simulation operation on each model according to the model runtime sequence, realizing the parallel simulation strategy of the visual modeling hybrid rate real-time simulation system.

7. The real-time simulation system for visual modeling and hybrid rates according to claim 1, characterized in that, The model development computer includes a graphical modeling environment, a Makefile generator, a model code generator, a file sender, an FPGA code generator, an FPGA compiler, and an FPGA object code loader; among them, A graphical modeling environment is used to provide a graphical model development environment; The Makefile generator is used to generate Makefiles; Model code generators are used to convert slow model files into high-level language source code; The file sender is used to send high-level language source code and the corresponding Make file to the simulation computer. An FPGA code generator is used to convert high-speed model files into FPGA code; An FPGA compiler is used to compile FPGA code; The FPGA target code loader is used to load FPGA target code.

8. The real-time simulation system for visual modeling and hybrid rates according to claim 7, characterized in that, The model development computer employs a high-speed / low-speed model partitioning strategy, building low-speed and high-speed models respectively through low-speed and high-speed model development environments; wherein... The low-speed model development environment includes a graphical modeling environment, a Makefile generator, a model code generator, and a file sender; The high-speed model development environment includes a graphical modeling environment, an FPGA code generator, an FPGA compiler, and an FPGA object code loader.

9. The real-time simulation system for visual modeling and hybrid rates according to claim 1, characterized in that, The emulator client computer includes a virtual network console client, a remote emulator desktop interface, and human-computer interaction devices; among which, The virtual network console client interacts with the simulated computer via a local area network. The remote simulator desktop interface is used to provide remote control commands; Human-computer interaction devices are used to provide human-computer control commands.

10. The real-time simulation system for visual modeling and hybrid rates according to claim 1, characterized in that, The automated test computer includes an operating system terminal and a test case transceiver; the operating system terminal is used to load test cases and test case scripts, and to call the test case transceiver to complete the data transmission of the test cases.

11. The real-time simulation system for visual modeling and hybrid rates according to claim 1, characterized in that, The FPGA model machine includes an FPGA target code loader, FLASH memory, FPGA chip, and high-speed data communication interface; among which, The FPGA target code loader is used to load FPGA source code model binary files; FLASH memory is used to store FPGA code loaded by the FPGA target code loader; FPGA chips are used to run FPGA code stored in FLASH memory; The high-speed data communication interface is used to read data from the high-speed model interface.

12. The real-time simulation system for visual modeling and hybrid rates according to claim 1, characterized in that, The visualization modeling hybrid rate real-time simulation system adopts a real-time operating system and triggers real-time simulation through a software timer or physical clock.

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