High-precision reference current generation circuit and fast-starting ultra-low-noise LDO

Abstract

The application relates to the technical field of power management, in particular to a high-precision reference current generation circuit and a fast-starting ultra-low-noise LDO. The high-precision reference current generation circuit comprises an input reference current generation circuit configured as a negative feedback loop and generating a reference current according to a band-gap reference voltage VREF; a high-precision output current generation circuit configured as a negative feedback loop and generating two output currents according to the reference current in proportion; and a fast-starting current generation circuit configured as a comparison control circuit and generating a fast-starting current by controlling the on-off of a switch tube through comparing voltage values converted by the two output currents. The high-precision reference current generation circuit has the characteristic of high output current precision; the fast-starting ultra-low-noise LDO can work under a low voltage difference, has the characteristics of low output voltage noise and fast starting speed, and avoids the problem of low output voltage precision caused by low reference current precision when the input-output voltage difference is small.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power management technology in integrated circuits, in particular to a high-precision reference current generating circuit and a fast-starting ultra-low noise LDO. BACKGROUND

[0002] A low-dropout linear regulator (LDO) is a kind of circuit widely used in the field of power management technology, and the LDO can provide a stable power supply voltage for the subsequent devices. With the development of electronic devices towards lower power consumption, higher speed and higher integration, the working voltage of digital chips such as FPGA, DSP, CPU and GPU in high-performance electronic devices is becoming lower and lower, and the interference of power supply noise on the working performance of the digital chips is gradually increasing. Therefore, the LDO is required to provide lower output voltage noise in such application scenarios. In addition, low-noise power supply is also required for radio frequency and analog devices sensitive to noise such as radio frequency amplifiers, PLLs and high-precision A / D converters. Therefore, ultra-low noise LDO has become an important direction of LDO technology development.

[0003] An LDO is composed of a bandgap reference, an error amplifier, a power tube and a feedback resistor, and the output voltage noise of the LDO is mainly composed of bandgap reference voltage noise, equivalent input voltage noise of the error amplifier and feedback resistor thermal noise. Since the feedback coefficient β of the LDO is not greater than 1, the bandgap reference voltage noise and the equivalent input voltage noise of the error amplifier are amplified by 1 / β times and then superimposed on the output voltage. The smaller the β is, the larger the output voltage noise will be. In order to reduce the output voltage noise of the LDO, an ultra-low noise LDO adopts a unit gain negative feedback structure with β=1, which does not amplify the bandgap reference voltage noise and the equivalent input voltage noise of the error amplifier, and eliminates the influence of the feedback resistor thermal noise on the output voltage noise. The equivalent input voltage noise of the error amplifier can be reduced by increasing the gain of the error amplifier, and a lower reference voltage noise can be obtained by using an external capacitor and an on-chip resistor to form a low-pass filter. However, in the prior art, the on-chip large resistor and the off-chip large capacitor prolong the reference voltage establishment time, resulting in a long LDO start-up time. SUMMARY

[0004] The purpose of the present application is to provide a high-precision reference current generating circuit and a fast-starting ultra-low noise LDO. A high-precision output reference current is generated by a high-gain current input operational amplifier, an ultra-low noise reference voltage is generated by an RC parallel filter circuit composed of an external resistor and a capacitor, and an additional charging path is provided for the RC parallel filter circuit by a fast-starting current generating circuit composed of a comparator, a switch tube and a current source during the reference voltage establishment process, so as to realize the fast start of the ultra-low noise LDO.

[0005] The purpose of the present application is achieved by the following technical solutions:

[0006] In a first aspect of the present invention, the present invention provides a high-precision reference current generating circuit, comprising:

[0007] An input reference current generating circuit is configured as a negative feedback loop to generate a reference current according to a bandgap reference voltage VREF;

[0008] The high-precision output current generation circuit is configured as a negative feedback loop to generate two output currents in proportion to the reference current;

[0009] The fast-start current generating circuit is configured as a comparison control circuit, which controls the on and off of the switch tube by comparing the voltage values ​​obtained by converting the two output currents to generate a fast-start current.

[0010] Furthermore, the input reference current generating circuit includes an amplifier AMP1, an NMOS tube M0 and a resistor R0, the non-inverting input terminal of the amplifier AMP1 is connected to the internal bandgap reference voltage VREF, the inverting input terminal is connected to the positive terminal of R0 and the source of M0, the output terminal of the amplifier AMP1 is connected to the gate of the M0 tube; the negative terminal of the resistor R0 is grounded; the drain of the M0 tube is connected to the high-precision output current generating circuit and generates a reference current.

[0011] Furthermore, the high-precision output current generating circuit includes resistors R1 and R2, an amplifier AMP2, and PMOS tubes M1 and M2. The non-inverting input terminal of the amplifier AMP2 is connected to the negative terminal of the resistor R1, and is also connected to the drain of the M0 tube in the input reference current generating circuit. The inverting input terminal is connected to the negative terminal of the resistor R2, and is also connected to the sources of the M1 tube and the M2 tube. The output terminal is connected to the gates of the M1 tube and the M2 tube; the positive terminals of the resistors R1 and R2 are both connected to the input power supply VIN; the drain of the M1 tube is connected to the fast start-up current generating circuit, and the drain of the M1 tube serves as the external port VFSS to generate an output current; the drain of the M2 tube is connected to the fast start-up current generating circuit, and the drain of the M2 tube serves as the external port VSET to generate an output current.

[0012] Furthermore, the amplifier AMP2 includes a resistor R3, transistors Q1 and Q2, an NMOS transistor M4, a capacitor C0, and bias current sources IB1, IB2, and IB3; the negative end of R1 is connected to the emitter of the Q1 transistor, the negative end of R2 is connected to the emitter of the Q2 transistor, the base of the Q1 transistor is connected to the base of the Q2 transistor, and is also connected to the positive end of the resistor R3 and one end of the capacitor C0, the other end of the capacitor C0 is connected to the collector of the Q2 transistor and the gate of the M4 transistor, and is also connected to the positive end of the bias current source IB3, the negative end of R3 is connected to the source of the M4 transistor, and is also connected to the positive end of the bias current source IB2, the drain of M4 is connected to the input power supply VIN, the collector of the Q1 transistor is connected to the positive end of the bias current source IB1, and an output voltage VO is generated, and the negative ends of the bias current sources IB1, IB2, and IB3 are all connected to ground.

[0013] Furthermore, a PMOS transistor M6 is added between the collector of transistor Q1 and the positive terminal of bias current source IB1, and a PMOS transistor M7 is added between the collector of transistor Q2 and the positive terminal of bias current source IB3. At the same time, a resistor R4, a PMOS transistor M5 and a bias current source IB4 are also added. The source of transistor M6 is connected to the collector of transistor Q1, the drain of transistor M6 is connected to the positive terminal of bias current source IB1, the source of transistor M7 is connected to the collector of transistor Q2, and the drain of transistor M7 is connected to the positive terminal of bias current source IB3. The gates of transistors M6 and M7 are short-circuited together and connected to the gate and drain of transistor M5. At the same time, they are also connected to the positive terminal of bias current source IB4. The negative terminal of IB is grounded. The source of transistor M5 is connected to the negative terminal of R4, and the positive terminal of R4 is connected to the input power supply VIN. Resistor R4, transistor M5 and bias current source IB4 provide bias voltage for transistors M6 and M7.

[0014] Furthermore, the external port VFSS is connected to a resistor RF. The external port VSET is connected to a capacitor CS and a resistor RS. Furthermore, the fast startup current generation circuit includes a comparator COMP1, a PMOS transistor M3, and a current source IS. The comparator COMP1 has a non-inverting input connected to the drains of transistors M2 and M3 in the high-precision output current generation circuit, an inverting input connected to the drain of transistor M1 in the high-precision output current generation circuit, and an output connected to the gate of transistor M3. The source of transistor M3 is connected to the negative terminal of current source IS. The positive terminal of IS is connected to the input power supply VIN, and generates a fast startup current.

[0015] In a second aspect of the present invention, the present invention provides a fast-start ultra-low noise LDO, which includes the high-precision reference current generation circuit as described in the first aspect of the present invention, an error amplifier, a buffer stage, a power tube MP0 and external resistors RF and RS, and an external capacitor CS.

[0016] Among them, the output port VFSS of the high-precision reference current generation circuit is connected to the positive end of the resistor RF, and the negative end of RF is grounded. The output port VSET is connected to the positive end of the resistor RS and the positive end of the capacitor CS, and is also connected to the inverting input end of the error amplifier, and the negative end of the resistor RS and the negative end of the capacitor CS are grounded; the non-inverting input end of the error amplifier is connected to the drain of the power tube MP0, and also serves as the output port VOUT of the LDO. The output end of the error amplifier is connected to the input end of the buffer stage, the output end of the buffer stage is connected to the gate of the power tube MP0, and the source of the MP0 tube is connected to the input power supply VIN.

[0017] Beneficial effects of the present invention:

[0018] The high-precision reference current generation circuit proposed in the present invention uses a current amplifier to output the reference current, and has the characteristics of high output current accuracy. The fast-start ultra-low-noise LDO proposed in the present invention can operate under low voltage difference, has the characteristics of low output voltage noise and fast startup speed, and at the same time avoids the problem of poor output voltage accuracy caused by low reference current accuracy when the input-output voltage difference is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic structural diagram of a high-precision reference current generating circuit according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic structural diagram of a high-precision reference current generating circuit according to another embodiment of the present invention;

[0021] Figure 3 This is a schematic structural diagram of a high-precision reference current generating circuit according to a preferred embodiment of the present invention;

[0022] Figure 4 This is a schematic structural diagram of a current input operational amplifier according to an embodiment of the present invention;

[0023] Figure 5 This is a schematic structural diagram of a high-gain current-input operational amplifier according to an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the structure of a fast-start ultra-low noise LDO according to an embodiment of the present invention;

[0025] Figure 7 This is a simulation diagram of the application of a high-precision reference current generating circuit according to an embodiment of the present invention;

[0026] Figure 8 4 is a simulation diagram of the output voltage noise spectrum of the ultra-low noise LDO according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0028] It should be noted that since the embodiments of the present invention focus on signal current or voltage, the description herein assumes that the inputs and outputs of each module / unit / device are current or voltage. Those skilled in the art will appreciate that, in reality, the inputs and outputs of each module / unit / device are signals. To facilitate understanding of the technical means and inventive features of the present invention, the present invention is further described with reference to the accompanying drawings.

[0029] The reference current generating circuit is a circuit specially designed to generate a high-precision, low-temperature drift reference current. Its main function is to provide a stable reference current for other circuits or systems to ensure the performance and stability of the entire system. The current reference current generating circuit adopts a current mirror structure. In order to improve the current matching accuracy, a cascode current mirror structure is usually adopted. However, when the LDO input-output voltage difference is low, this structure will seriously affect the current matching accuracy due to insufficient cascode tube voltage drop, resulting in poor reference current output accuracy of the LDO within a wide input voltage range. Based on this problem, an embodiment of the present invention provides a high-precision reference current generating circuit, such as Figure 1 As shown, the high-precision reference current generating circuit includes:

[0030] An input reference current generating circuit is configured as a negative feedback loop to generate a reference current according to a bandgap reference voltage VREF;

[0031] The high-precision output current generation circuit is configured as a negative feedback loop to generate two output currents in proportion to the reference current;

[0032] The fast-start current generating circuit is configured as a comparison control circuit, which controls the on and off of the switch tube by comparing the voltage values ​​obtained by converting the two output currents to generate a fast-start current.

[0033] In the embodiment of the present invention, a high-precision output reference current and a fast-start current are generated by cooperating with an input reference current generating circuit, a high-precision output current generating circuit, and a fast-start current generating circuit, thereby improving the reference voltage accuracy within a wide input voltage range, reducing the reference voltage establishment time, and reducing the reference voltage noise.

[0034] Figure 2 FIG. 1 is a schematic structural diagram of a high-precision reference current generating circuit according to another embodiment of the present invention; Figure 2As shown, the high-precision reference current generation circuit includes an input reference current generation circuit, a high-precision output current generation circuit, and a fast startup current generation circuit. The input reference current generation circuit consists of an amplifier AMP1, an NMOS transistor M0, and a resistor R0. The high-precision output current generation circuit consists of resistors R1 and R2, an amplifier AMP2, and PMOS transistors M1 and M2. The fast startup current generation circuit consists of a comparator COMP1, a PMOS transistor M3, and a current source IS.

[0035] In some embodiments, the input reference current generating circuit includes an amplifier AMP1, an NMOS tube M0 and a resistor R0, the non-inverting input terminal of the amplifier AMP1 is connected to the internal bandgap reference voltage VREF, the inverting input terminal is connected to the positive terminal of R0 and the source of M0, the output terminal of the amplifier AMP1 is connected to the gate of the M0 tube; the negative terminal of the resistor R0 is grounded; the drain of M0 is connected to the high-precision output current generating circuit and generates a reference current.

[0036] It can be understood that the input reference current generation circuit forms a negative feedback loop through the amplifier AMP1, NMOS tube M0 and resistor R0, clamping the voltage at the inverting input terminal of the amplifier AMP1 to VREF. The current flowing through the M0 tube is the reference current:

[0037]

[0038] In some embodiments, the high-precision output current generating circuit includes resistors R1 and R2, an amplifier AMP2, and PMOS tubes M1 and M2. The non-inverting input terminal of the amplifier AMP2 is connected to the negative terminal of the resistor R1, and is also connected to the drain of the M0 tube in the input reference current generating circuit. The inverting input terminal is connected to the negative terminal of the resistor R2, and is also connected to the sources of the M1 tube and the M2 tube. The output terminal is connected to the gates of the M1 tube and the M2 tube; the positive terminals of the resistors R1 and R2 are both connected to the input power supply VIN; the drain of the M1 tube is connected to the fast start-up current generating circuit, and the drain of the M1 tube serves as the external port VFSS to generate an output current; the drain of the M2 tube is connected to the fast start-up current generating circuit, and the drain of the M2 tube serves as the external port VSET to generate an output current.

[0039] In some preferred embodiments, the high-precision output current generating circuit generates a constant reference current through an external resistor and capacitor. An application example of a high-precision reference current generating circuit of the present invention is as follows: Figure 3As shown, the external port VFSS is connected to resistor RF, and the external port VSET is connected to resistor RS and capacitor CS. Resistors R1 and R2, amplifier AMP2, transistors M1 and M2, and the external resistors RF and RS form a negative feedback circuit that proportionally divides the input reference current Iin to generate two output currents, which are converted to voltages across resistors RF and RS. Assuming the width-to-length ratio of transistors M1 and M2 is 1:k, and R1 = R2, the voltage at the VFSS terminal is:

[0040]

[0041] VSET terminal voltage:

[0042]

[0043] If the external resistor RF=k*RS, the voltage at the VFSS terminal is equal to the voltage at the VSET terminal.

[0044]

[0045] In some embodiments, the fast startup current generating circuit includes a comparator COMP1, a PMOS tube M3 and a current source IS. The non-inverting input terminal of the comparator COMP1 is connected to the drain of the M2 tube and the drain of the M3 tube in the high-precision output current generating circuit, the inverting input terminal is connected to the drain of the M1 tube in the high-precision output current generating circuit, and the output terminal is connected to the gate of the M3 tube; the source of the M3 tube is connected to the negative terminal of the current source IS; the positive terminal of IS is connected to the input power supply VIN, and generates a fast startup current.

[0046] It should be noted that the fast-startup current generation circuit controls the on / off switching of switch M3 by comparing the VFSS voltage with the VSET voltage using comparator COMP1. During the VSET buildup process, due to the large capacitor connected to VSET, the VSET voltage is lower than the VFSS voltage, causing the comparator to output a low level. Switch M3 is then turned on, and an additional current IS is injected into the VSET terminal, enabling VSET to quickly build up. When the VSET voltage approaches the VFSS voltage, comparator COMP1 outputs a high level, turning off switch M3. The fast-startup current IS no longer affects the reference output current, and the VSET voltage slowly rises, ultimately maintaining a stable preset value. The inputs of comparator COMP1 have different width-to-length ratios: the MOS transistor connected to the positive terminal of CMOP1 has a larger width-to-length ratio than the MOS transistor connected to the negative terminal of CMOP1. This introduced comparator offset voltage causes the comparator output voltage to flip when the VSET voltage approaches the VFSS voltage, causing switch M3 to switch from on to off. After the fast-startup phase of the reference current generation circuit ends, the fast-startup current generation circuit no longer affects the output reference current.

[0047] In some embodiments of the present invention, for ease of description, an implementation of a current input operational amplifier consisting of resistors R1, R2 and amplifier AMP2 in a high-precision output current generating circuit is as follows: Figure 4 As shown. The power input operational amplifier includes resistors R1, R2, and R3, transistors Q1 and Q2, an NMOS transistor M4, a capacitor C0, and bias current sources IB1, IB2, and IB3. The positive terminals of R1 and R2 are short-circuited together and connected to the input power supply VIN. The negative terminal of R1 is connected to the emitter of Q1, and the negative terminal of R2 is connected to the emitter of Q2. The base of Q1 is connected to the base of Q2, and is also connected to the positive terminal of resistor R3 and one end of capacitor C0. The other end of capacitor C0 is connected to the collector of Q2 and the gate of M4, and is also connected to the positive terminal of bias current source IB3. The negative terminal of R3 is connected to the source of M4 and the positive terminal of bias current source IB2. The drain of M4 is connected to the input power supply VIN. The collector of Q1 is connected to the positive terminal of bias current source IB1, and an output voltage VO is generated. The negative terminals of bias current sources IB1, IB2, and IB3 are all connected to ground.

[0048] In some embodiments of the present invention, for the sake of convenience, an implementation of a high-gain current input operational amplifier composed of resistors R1, R2 and amplifier AMP2 in a high-precision output current generating circuit is as follows: Figure 5 As shown. Figure 4 Compared to the current-input operational amplifier of the present embodiment, this embodiment adds a PMOS transistor M6 between the collector of transistor Q1 and the positive terminal of bias current source IB1, and a PMOS transistor M7 between the collector of transistor Q2 and the positive terminal of bias current source IB3. Resistor R4, PMOS transistor M5, and bias current source IB4 are also added. The source of transistor M6 is connected to the collector of transistor Q1, and the drain of transistor M6 is connected to the positive terminal of bias current source IB1. The source of transistor M7 is connected to the collector of transistor Q2, and the drain of transistor M7 is connected to the positive terminal of bias current source IB3. The gates of transistors M6 and M7 are short-circuited together and connected to the gate and drain of transistor M5. They are also connected to the positive terminal of bias current source IB4. The negative terminal of IB is grounded. The source of transistor M5 is connected to the negative terminal of R4, and the positive terminal of R4 is connected to the input power supply VIN. Resistor R4, transistor M5, and bias current source IB4 provide bias voltage for transistors M6 and M7.

[0049] The present invention specifically implements a fast start ultra-low noise LDO, the structural block diagram of which is shown in the attached figure. Figure 6The LDO includes a high-precision reference current generating circuit, an error amplifier, a buffer stage, a power tube MP0, and external resistors RF and RS, and an external capacitor CS. The low-pass filter formed by RS and CS can reduce the reference voltage noise at the inverting terminal of the error amplifier, and the unit gain negative feedback loop formed by the error amplifier, the buffer, and the power tube can eliminate the noise introduced by the feedback resistor, and will not amplify and output the reference voltage noise and the input terminal equivalent noise of the error amplifier at the LDO output terminal, so that the structure can realize ultra-low noise output. In order to reduce noise, the capacitor CS connected at the VSET terminal will cause the LDO start-up time to become longer, and the high-precision reference current generating circuit will additionally inject a current IS to charge the VSET terminal during the LDO start-up stage. The high-precision reference current generating circuit outputs a current IVFSS:IVSET=1:k after the LDO stabilizes, and by selecting the external resistor RF to be k times the resistance value of RS, the final VFSS terminal voltage and the VSET terminal voltage are equal, and equal to the LDO output voltage VOUT. During the LDO start-up stage, the VFSS terminal voltage immediately rises to the preset LDO output voltage, and the VSET terminal voltage rises rapidly due to the additional injection of the current IS during the start-up stage, and the LDO output voltage VOUT rises with the VSET. When the VSET terminal voltage approaches the preset output voltage VFSS, the internal comparator COMP1 of the high-precision reference current generating circuit flips and cuts off the current IS charging path, and the VSET gradually rises to the final preset voltage. The LDO of the application realizes ultra-low noise voltage output, and during the start-up stage, the start-up current is increased to realize fast start-up of the ultra-low noise LDO.

[0050] Figure 7 The application is a simulation waveform diagram of the comparator output, the VFSS terminal voltage, and the VSET terminal voltage of the high-precision reference current generating circuit under a certain simulation condition. After the input voltage VIN is powered on, the VFSS terminal voltage is immediately established, the comparator output is at a low level, and the VSET terminal voltage rises rapidly. When the VSET terminal voltage approaches the VFSS terminal voltage, the comparator flips, the fast start-up current generating circuit is closed, and the VSET slowly rises to the preset value.

[0051] Figure 8 The application is a noise spectrum simulation diagram of the ultra-low noise LDO output voltage under a certain simulation condition. At a frequency of 1 kHz, the noise spectral density is reduced to 3.89nV / √Hz, and by increasing the external output capacitor, the LDO output voltage noise can be further reduced.

[0052] Although embodiments of the application have been shown and described, it is to be understood that the application is not limited to the details of the foregoing embodiment, and that various changes in form and details can be made without departing from the spirit and scope of the application. The scope of the application is defined by the appended claims and their equivalents.

Claims

1. A high-precision reference current generating circuit, characterized in that: include: An input reference current generating circuit is configured as a negative feedback loop to generate a reference current according to a bandgap reference voltage VREF; The input reference current generating circuit includes an amplifier AMP1, an NMOS tube M0 and a resistor R0, wherein the non-inverting input terminal of the amplifier AMP1 is connected to the internal bandgap reference voltage VREF, the inverting input terminal is connected to the positive terminal of R0 and the source of M0, the output terminal of the amplifier AMP1 is connected to the gate of the tube M0; the negative terminal of the resistor R0 is grounded; the drain of M0 is connected to the high-precision output current generating circuit and generates a reference current; The high-precision output current generation circuit is configured as a negative feedback loop to generate two output currents in proportion to the reference current; The high-precision output current generating circuit includes resistors R1 and R2, an amplifier AMP2, and PMOS tubes M1 and M2. The non-inverting input end of the amplifier AMP2 is connected to the negative end of the resistor R1 and is also connected to the drain of the M0 tube in the input reference current generating circuit. The inverting input end is connected to the negative end of the resistor R2 and is also connected to the source electrodes of the M1 tube and the M2 tube. The output end is connected to the gate electrodes of the M1 tube and the M2 tube. The positive ends of the resistors R1 and R2 are both connected to the input power supply VIN. The drain of the M1 tube is connected to the fast startup current generating circuit, and the drain of the M1 tube serves as the external port VFSS to generate one output current. The drain of the M2 tube is connected to the fast startup current generating circuit, and the drain of the M2 tube serves as the external port VSET to generate one output current. The fast-start current generating circuit is configured as a comparison control circuit, which controls the on / off of the switch tube by comparing the voltage values ​​obtained by converting the two output currents to generate a fast-start current; The fast startup current generating circuit includes a comparator COMP1, a PMOS transistor M3 and a current source IS. The non-inverting input terminal of the comparator COMP1 is connected to the drain of the M2 transistor and the drain of the M3 transistor in the high-precision output current generating circuit, the inverting input terminal is connected to the drain of the M1 transistor in the high-precision output current generating circuit, and the output terminal is connected to the gate of the M3 transistor; the source of the M3 transistor is connected to the negative terminal of the current source IS; the positive terminal of IS is connected to the input power supply VIN, and generates a fast startup current.

2. A high-precision reference current generating circuit according to claim 1, characterized in that: Amplifier AMP2 includes resistor R3, transistors Q1 and Q2, NMOS transistor M4, capacitor C0, and bias current sources IB1, IB2, and IB3; the negative end of R1 is connected to the emitter of transistor Q1, the negative end of R2 is connected to the emitter of transistor Q2, the base of transistor Q1 is connected to the base of transistor Q2, and is also connected to the positive end of resistor R3 and one end of capacitor C0. The other end of capacitor C0 is connected to the collector of transistor Q2 and the gate of transistor M4, and is also connected to the positive end of bias current source IB3. The negative end of R3 is connected to the source of transistor M4 and is also connected to the positive end of bias current source IB2. The drain of M4 is connected to the input power supply VIN. The collector of transistor Q1 is connected to the positive end of bias current source IB1, and an output voltage VO is generated. The negative ends of bias current sources IB1, IB2, and IB3 are all connected to ground.

3. The high-precision reference current generating circuit according to claim 2, characterized in that: A PMOS transistor M6 is added between the collector of the Q1 tube and the positive terminal of the bias current source IB1, and a PMOS transistor M7 is added between the collector of the Q2 tube and the positive terminal of the bias current source IB3. At the same time, a resistor R4, a PMOS transistor M5 and the bias current source IB4 are also added; the source of the M6 ​​tube is connected to the collector of the Q1 tube, the drain of the M6 ​​tube is connected to the positive terminal of the bias current source IB1, the source of the M7 tube is connected to the collector of the Q2 tube, and the drain of the M7 tube is connected to the positive terminal of the bias current source IB3. The gates of the M6 ​​and M7 tubes are short-circuited together and connected to the gate and drain of the M5 tube, and are also connected to the positive terminal of the bias current source IB4. The negative terminal of IB is grounded. The source of the M5 tube is connected to the negative terminal of R4, and the positive terminal of R4 is connected to the input power supply VIN; the resistor R4, the M5 tube and the bias current source IB4 provide bias voltage for the M6 ​​and M7 tubes.

4. The high-precision reference current generating circuit according to claim 1, characterized in that: The external port VFSS is connected to the resistor RF.

5. The high-precision reference current generating circuit according to claim 1, characterized in that: The external port VSET is connected to the capacitor CS and the resistor RS.

6. A fast-start ultra-low noise LDO, characterized in that: The LDO includes the high-precision reference current generating circuit as described in any one of claims 1-5, an error amplifier, a buffer stage, a power tube MP0 and external resistors RF and RS, and an external capacitor CS; wherein, the output port VFSS of the high-precision reference current generating circuit is connected to the positive end of the resistor RF, and the negative end of RF is grounded; the output port VSET is connected to the positive end of the resistor RS and the positive end of the capacitor CS, and is also connected to the inverting input of the error amplifier, and the negative end of the resistor RS and the negative end of the capacitor CS are grounded; the non-inverting input of the error amplifier is connected to the drain of the power tube MP0 and also serves as the output port VOUT of the LDO; the output of the error amplifier is connected to the input of the buffer stage, the output of the buffer stage is connected to the gate of the power tube MP0, and the source of the MP0 tube is connected to the input power supply VIN.

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