Multi-core-particle optical matrix calculation architecture

Abstract

The invention discloses a multi-core-particle optical matrix calculation framework, which is characterized in that a block matrix is adopted to decompose a large-scale optical matrix calculation chip into a plurality of small-scale optical matrix calculation core particles, and active and passive separation is adopted to decompose the optical matrix calculation chip into modulator array core particles, detector array core particles and optical matrix calculation core particles. Decomposing the M * N matrix A into m * n p * q matrixes Aij; an input N-dimensional vector X is decomposed into n-channel q-dimensional vectors Xj, and an output M-dimensional vector Y is decomposed into m p-dimensional vectors Yi. Input light passes through the n modulator array core particles to form n channel q-dimensional vectors, m * n q-dimensional vectors are formed after m beam splitting copying, the m * n q-dimensional vectors are input into the m * n optical matrix calculation core particles respectively and multiplied by Aij to obtain m * n p-dimensional vectors, m p-dimensional vectors are obtained after the light of the n channels passes through n channel multiplexing (wavelength division multiplexing, polarization multiplexing, mode multiplexing and the like and multi-dimensional multiplexing), and m * n p-dimensional vectors are obtained. And then detection is carried out, and large-scale matrix-vector multiplication calculation Y = AX is realized.

Description

Technical Field

[0001] The present invention belongs to the field of optical computing, and more specifically, relates to a multi-core optical matrix computing architecture. Background Art

[0002] From big data, cloud computing to artificial intelligence, the new generation of information technology has led to the rapid development of the intelligent era. Large scale, high computing power and low energy consumption are important trends in intelligent computing. However, as Moore's Law of semiconductors approaches its limit, problems such as chip power consumption and heat dissipation are becoming more and more serious, seriously limiting the development of large-scale integrated chips and further improving chip computing efficiency. In order to solve this problem, optical computing uses light waves as a carrier for information processing. It has the advantages of multi-dimensionality, large bandwidth, low latency, and low power consumption. It can accelerate matrix computing and provide a new computing architecture of "transmission is computing, structure is function". With the continuous development of artificial intelligence, the demand for optical computing is also increasing, and it is showing an important trend of high integration. Optical computing chips have attracted much attention in recent years because of their advantages of integrating optical matrix computing and integrated chips. At present, optical matrix computing acceleration chips can be roughly divided into four technical routes: matrix computing based on two-dimensional planar diffraction structure, matrix computing based on cascaded Mach-Zehnder interferometer, matrix computing based on microring resonator and wavelength division multiplexing, and matrix computing based on phase change material synapse array. Among them, matrix computing based on two-dimensional planar diffraction structure has extremely low power consumption but is not reconfigurable, and has high requirements for micro-nano processing technology; matrix computing based on phase change material synapse array has a low number of switching times and has the problem of late failure; and matrix computing based on wavelength division multiplexing has poor stability because the working wavelength of the microring resonator is highly sensitive to temperature and environment; in contrast, the technical solution based on cascaded Mach-Zehnder has strong reconfigurability and stable operation, and is more suitable for large-scale integration. Therefore, companies such as Lightmatter and Xizhi Technology currently use cascaded Mach-Zehnder technical solutions.

[0003] However, no matter which of the above integrated optical matrix computing implementation methods is used, there is a problem that it is difficult to support ultra-large-scale matrix computing. Due to the large size of integrated optical devices, the matrix scale that a single chip can support is small, much smaller than that of microelectronic chips, so it is difficult to support more complex neural network algorithms, and the classification tasks implemented are limited to simple data sets such as MNIST. In recent years, with the improvement of chip process, yield, complexity, and the emergence of chiplets and advanced packaging technology, the research on ultra-large-scale optical matrix multi-chiplet accelerated computing is of great value in promoting the further development of artificial intelligence and high-performance computing technology. Chiplets, also called small chipsets, decompose large chips according to computing or functional units, select appropriate different process steps according to their respective characteristics, combine with intermediate layers, and then interconnect and assemble various functional small chips through advanced packaging technology, similar to building Lego blocks. It has the advantages of strong scalability, high yield, low complexity, and low cost, which is of great significance for building ultra-large-scale photonic integrated chip systems for complex tasks. Summary of the invention

[0004] In view of the defects of the existing computing architecture, the purpose of the present invention is to provide a multi-core optical matrix computing architecture based on matrix blocking, aiming to solve the problem of limited scale of optical matrix computing chips.

[0005] To achieve the above-mentioned object, the present invention provides a multi-core optical matrix computing architecture, in which a large chip is decomposed into a number of small cores by matrix partitioning and separation of active modules and passive modules on the optical computing architecture, specifically including n modulator array cores, m×n optical matrix computing cores, m detector array cores and an optical adapter board for interconnecting the cores; the matrix partitioning decomposes the large chip in array and matrix mode according to the functional scale and manufacturing process; the active module includes a modulator array core and a detector array core; the passive module includes an optical matrix computing core; each of the modulator array cores includes q parallel modulators, each of the detector array cores includes p parallel detectors, and each of the optical matrix computing cores provides a p×q matrix computing sub-function, including q input ports and p output ports; the input light passes through the n modulator array cores, is modulated into q signal lights in each of the modulator array cores, and forms n-channel q-dimensional input vectors X after passing through the n modulator array cores. j , each channel q-dimensional input vector X j Through 1:m splitting, m copies are made, n channels and q-dimensional input vector X j After replication, m×n q-dimensional vectors are formed, which are input into m×n optical matrix calculation core particles respectively and correspond to the corresponding p×q matrix A ij Multiply them together to get m×n p-dimensional vectors. After the light from n channels is multiplexed through n channels, m p-dimensional output vectors Y are obtained.i , provided to the m detector array core particles for detection in sequence, and the multi-core particle optical matrix calculation results are obtained; the light of the n channels includes orthogonal channels of different wavelengths, orthogonal channels of different polarizations, orthogonal channels of different modes, orthogonal channels of other light wave dimensions, and orthogonal channels of different dimensional combinations; wherein, i = 1, 2, ..., m; j = 1, 2, ..., n. The goal of this architecture is to solve the accelerated calculation of the multiplication of the M×N ultra-large-scale matrix A and the N-dimensional vector X. The existing optical computing architecture is realized by directly constructing the computing chip corresponding to the M×N matrix. The present invention adopts the idea of ​​block matrix for large-scale matrix-vector multiplication calculation Y = AX (X is the input N-dimensional vector, Y is the output N-dimensional vector, A is an M×N matrix), and uses m×n p×q (M = m×p, N = n×q) optical matrices to calculate the core particle A ij (i=1,2,…,m;j=1,2,…,n) form a large-scale M×N matrix A, and then decompose the N-dimensional vector X into n q-dimensional vectors X i (i=1,2,…,n), the specific decomposition method is shown in formula (1)(2):

[0006]

[0007] X=(x1,x 2, …,x q, ……,x N-q+1 ,x N-q+2, …,x N ) T =(X1,X 2, …X n ) T (2)

[0008] Each vector X i Through a modulator array core particle loading, each modulator array core particle corresponds to a channel, and each port of the modulator array corresponds to an element of the vector. The modulated optical signal is coupled into the optical adapter board, and then divided into m paths through the beam splitter, and input into m optical matrix computing core particles respectively. Each core particle contains q input ports, which correspond to the q output ports of the modulator. The multi-layer adapter board can well separate the two optical signals and avoid a large number of waveguide crossings. With the first wavelength, the optical matrix computing core particle A is coupled after beam splitting. 11 Taking light as an example, the optical matrix calculation core particle A 11 The light intensity of the p output ports constitutes the vector Y 11 =A 11 X1, for the second wavelength coupled into core A 12 The light intensity of the p output ports constitutes the vector Y 12 =A 12 X2, and so on, the nth wavelength is coupled into core A1n The light intensity of the p output ports constitutes the vector Y 1n =A 1n X n .Y 11 , Y 12 ,…Y 1n After coupling into the optical adapter, the jth (j=1, 2, ..., p) channel of each optical signal array is rerouted together, and the channel multiplexing is realized through the multiplexing device, and finally received by the detector array core particle. This process completes the vector group Y 11 , Y 12 ,…Y 1n The corresponding elements of Y are added together, which is equivalent to 11 , Y 12 ,…Y 1n Add together and get the k-dimensional vector Y1=A 11 X1+A 12 X2+…+A 1n X n Note that the entire architecture consists of m detector array cores, each of which has a k-dimensional vector Y1, Y2, ...Y m Together they form the final M-dimensional vector, which is the output vector of the entire multi-core acceleration system. The calculation process is shown in the attached figure. Figure 2 As shown, X and Y are input and output vectors, A is the target matrix, and X j represents the input vector of the jth modulator array chip, Y i represents the vector received by the i-th detector array chip, satisfying the relationship Y=(Y1,Y2,…,Y m ) T ,X=(X1,X2,…,X n ) T .

[0009] Preferably, each of the modulator array core particles includes q modulators arranged in parallel, and the modulators are micro-ring modulators, micro-disk modulators, photonic crystal micro-cavity modulators, Mach-Zehnder modulators, electro-absorption modulators, modulators based on two-dimensional materials, or micro-ring and Mach-Zehnder combined structure modulators.

[0010] Preferably, each of the detector array core particles comprises p detectors arranged in parallel, and the detectors are germanium silicon photodetectors, avalanche detectors, III-V group-based photodetectors or detectors based on two-dimensional materials.

[0011] Preferably, the optical matrix computing core particle is a cascaded Mach-Zehnder interferometer, a microring resonator array, a phase change material synapse array or an on-chip two-dimensional planar diffraction structure; wherein the network type used by the cascaded Mach-Zehnder interferometer is a triangular network, a rectangular network or a non-universal fast Fourier transform (FFT) network.

[0012] Preferably, the optical adapter board includes a single-layer or multi-layer structure, each layer includes a waveguide array, an interlayer coupler, a 1:m beam splitter, an n-channel multiplexer, etc., and multi-layer waveguides are used to reduce the waveguide crossing of the interconnection between core particles; wherein the interlayer coupler uses an evanescent wave coupler to realize the coupling between the core particle layer and the optical adapter board layer and the coupling between different optical adapter board layers; the 1:m beam splitter uses a multimode interference coupler or other micro-nanostructure beam splitter to branch the signal light to each optical matrix calculation core particle; the n-channel multiplexer is used to multiplex and add the calculation results of each optical matrix calculation core particle, which includes but is not limited to a wavelength division multiplexer, a polarization multiplexer, a mode multiplexer, and can also be a multidimensional multiplexer that integrates multiple physical dimensions of optical waves such as wavelength, polarization, and mode.

[0013] Preferably, the input light enters the n modulator array cores or the optical adapter plate by coupling, and the coupling method is end-face coupling or vertical coupling.

[0014] Preferably, the material platform of the modulator array core particles is silicon, thin film lithium niobate, electro-optic polymer, group III-V, two-dimensional material, ferroelectric film, piezoelectric film, etc., and the material platform of the optical matrix computing core particles is silicon, silicon nitride, silicon dioxide, thin film lithium niobate; the material platform of the detector array core particles is epitaxial germanium on silicon, group III-V, two-dimensional material, etc.; the material platform of the optical adapter plate is silicon nitride, silicon dioxide, organic polymer material, etc.

[0015] Preferably, the multi-chip optical matrix computing architecture also includes a peripheral circuit module for driving and controlling the multi-chip system; the peripheral circuit module mainly includes two parts: a high-speed signal loading circuit and a low-speed multi-channel control power supply, wherein the high-speed signal loading circuit mainly includes a high-speed programmable logic array (FPGA), a high-speed (DAC), a high-speed (ADC), a high-speed driver amplifier (Driver), a high-speed transimpedance amplifier (TIA), etc. The high-speed FPGA is used to provide a digital electrical signal corresponding to the data to be calculated and processed, and an analog electrical signal is obtained through a high-speed DAC. After being amplified to a suitable level by a high-speed Driver, it is driven and loaded onto a modulator to obtain an optical signal, and then after optical matrix calculation, a detection electrical signal is obtained through a detector, appropriately amplified in combination with a high-speed TIA, and then a digital electrical signal is obtained through a high-speed ADC, and finally provided to a high-speed FPGA or a computer for processing; the low-speed multi-channel control power supply mainly includes a microprocessor (such as a single-chip microcomputer) or a low-speed FPGA, a low-speed multi-channel DAC, a low-speed power amplifier, etc., which are used to control and adjust the optical chip and each phase shifter of the chip, so as to flexibly configure the coefficients in the matrix of the optical matrix calculation.

[0016] Preferably, the modulator array core, the detector array core, the optical matrix computing core and the optical adapter board are integrated by direct bonding; the packaging method between the peripheral circuit module and the optical adapter board is 2.5D or 3D advanced packaging, and the electric chip and the optical adapter board are packaged on a ceramic adapter board or a printed circuit board (PCB) by wire bonding to achieve 2.5D packaging, or the electric chip is directly flip-chip bonded and combined with silicon through-via and other technologies to achieve 3D advanced packaging.

[0017] Through the above technical solution conceived by the present invention, compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. The present invention proposes a multi-core optical matrix computing architecture. Aiming at the technical difficulties of designing and processing ultra-large-scale optical matrix computing chips, such as high difficulty, low yield and high cost, a large-scale matrix computing system is constructed by using multiple small-scale matrix computing cores, which provides a new idea for realizing ultra-large-scale optical matrix computing.

[0019] 2. The present invention gives full play to the advantages of small core particle size and free combination, and can construct matrix computing systems of various sizes through the same optical matrix computing core particle unit, which is more flexible.

[0020] 3. The multi-chip interconnection method proposed in the present invention is universal and is not only suitable for optical matrix calculation acceleration, but can also be applied to other application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the multi-core optical matrix computing architecture.

[0022] Figure 2 It is a schematic diagram of the matrix decomposition and calculation principle of the multi-core optical matrix computing architecture.

[0023] Figure 3 It is a schematic diagram of a prototype system of a multi-chip optical matrix computing architecture, including n modulator array chips, m detector array chips, m×n optical matrix computing chips, and an optical adapter board for interconnecting multiple chips.

[0024] Figure 4 It is a schematic diagram of a specific example system structure of a multi-core optical matrix computing architecture.

[0025] Figure 5 This is a schematic diagram of the core-particle connection method of the multi-core optical matrix computing architecture.

[0026] Figure 6 It is a structural diagram based on the general architecture (including triangular network and rectangular network) in the cascaded Mach-Zehnder optical matrix computing architecture and the comparison of the expression capabilities of arbitrary unitary matrices with the fast Fourier transform (FFT) network architecture.

[0027] Figure 7 It is a schematic diagram of the structure of an optical adapter board.

[0028] Figure 8 It is a schematic diagram of the structure and principle of the wavelength division multiplexer on the silicon-silicon nitride interlayer coupler and the silicon nitride adapter board.

[0029] Fig. 9 It is a schematic diagram of the packaging method of optical core particles, electrical chips and optical adapter boards.

[0030] Fig.10 It is a schematic diagram of the optical core particle bonding scheme and the interconnection scheme between the electrical chip and the optical adapter board. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] In view of the problem that the scale of optical matrix computing chips is limited at present, the present invention provides a scalable multi-core optical matrix computing architecture. It aims to realize ultra-large-scale optical matrix accelerated computing by combining multiple cores, realize flexible switching of optical matrices of different scales by changing the number of cores, and realize interconnection between multiple cores by using optical adapter boards. Figure 1 As shown, the present invention specifically includes n modulator array core particles, m×n optical matrix calculation core particles, m detector array core particles and an optical adapter board for interconnecting the core particles; the matrix block decomposes the large chip in array and matrix mode according to the functional scale and manufacturing process; the active module includes the modulator array core particle and the detector array core particle; the passive module includes the optical matrix calculation core particle; each of the modulator array core particles includes q parallel modulators, each of the detector array core particles includes p parallel detectors, and each of the optical matrix calculation core particles provides a p×q matrix calculation sub-function, including q input ports and p output ports; the input light passes through the n modulator array core particles, is modulated into q signal lights in each of the modulator array core particles, and forms n-channel q-dimensional input vectors X after passing through the n modulator array core particles. j , each channel q-dimensional input vector X j Through 1:m splitting, m copies are made, n channels and q-dimensional input vector X j After replication, m×n q-dimensional vectors are formed, which are input into m×n optical matrix calculation core particles respectively and correspond to the corresponding p×q matrix A ijMultiply them together to get m×n p-dimensional vectors. After the light from n channels is multiplexed through n channels, m p-dimensional output vectors Y are obtained. i , provided to the m detector array core particles for detection in sequence, to obtain the multi-core optical matrix calculation results; the light of the n channels includes orthogonal channels of different wavelengths, orthogonal channels of different polarizations, orthogonal channels of different modes, orthogonal channels of other light wave dimensions, and orthogonal channels of different dimensional combinations; wherein, i = 1, 2, ..., m; j = 1, 2, ..., n.

[0033] like Figure 2 As shown, a schematic diagram of matrix partitioning and calculation principle of a multi-core optical matrix computing architecture is shown. The specific calculation principle has been described in detail in the content of the invention.

[0034] like Figure 3 As shown, a multi-core optical matrix computing architecture and system structure of an example of the present invention includes n modulator array cores, m detector array cores, four optical matrix computing cores and an optical adapter board for interconnecting multiple cores. Preferably, wavelength division multiplexing is selected as different channels. Specifically, the light source uses m lights of different wavelengths, which are respectively coupled into the optical adapter board and then divided into q paths, and then coupled into the modulator array core. The modulator array core is a q-path modulator array, and the n modulator array cores are respectively used to load n q-dimensional vectors, which are combined together to form an N (N = n × q)-dimensional input vector. The N-path modulated optical signals are divided into m by a multi-layer optical adapter board and input into m optical matrix computing cores. The output result of each optical matrix computing core is p-path light of different light intensities, forming a p-dimensional vector. Multiplexing is then achieved through the wavelength division multiplexing device on the silicon nitride adapter board, and finally received by m p-path detector array cores to complete the addition and obtain an M (N = m × p)-dimensional vector output.

[0035] like Figure 4 As shown, a specific multi-core optical matrix computing system of an example of the present invention includes two modulator array cores, two detector array cores, an optical adapter board and four k×k optical matrix computing cores A, B, C, and D, which are used to form a 2k×2k large-scale optical matrix computing system. The light source uses two lights of different wavelengths, which are respectively coupled into the optical adapter board and then divided into k paths, and then coupled into the modulator array core. The modulator array core is a k-path modulator array, and the input 2k-dimensional vector is decomposed into two k-dimensional vectors E and F and loaded by the two modulator array cores respectively. The k-path modulated optical signal is divided into two by a multi-layer silicon nitride adapter board and input into two cores. The calculation results AE (CE) and BF (DF) are multiplexed by a wavelength division multiplexer and finally enter the detector to complete the addition, and two k-dimensional vectors AE+BF and CE+DF are obtained, which together constitute the final 2k-dimensional vector.

[0036] like Figure 5As shown, in the example of the present invention, the connection between multiple core particles adopts a double-layer waveguide cross structure. The optical adapter plate adopts a double-layer waveguide structure, in which black represents the upper silicon nitride waveguide and red represents the lower silicon nitride waveguide. The light intensity of the k-way light passing through the two modulator array core particles is represented by vectors E and F respectively, and then coupled into the lower waveguide and completes beam splitting. After beam splitting, one branch is coupled to the upper waveguide and the other is coupled to the lower waveguide, and they are routed to the two optical computing chips A and C (B and D) respectively. Similarly, the output light AE and BF (CE and DF) of the two computing chips A and B (C and D) also go on the upper and lower waveguides respectively, re-converge and couple to the lower waveguide again. AE (CE) and BF (DF) are multiplexed by the wavelength division multiplexer on the lower waveguide and finally enter the k-way detector array core to complete the addition.

[0037] like Figure 6 As shown in FIG. 1 , the present invention compares the matrix representation functions of different computing architectures of optical matrix computing core particles. The Fast Fourier Transform Architecture (FFTNet) network reduces the number of units required for the k×k cascaded Mach-Zehnder interferometer network architecture from k 2 The comparison of the two structures is shown in the figure. Compared with the traditional triangular network and rectangular network, it effectively reduces the optical path loss and optical phase accumulation error, reduces the input light source power requirement, and reduces the number of units and the number of phase shifter drivers, balancing the contradiction between matrix versatility and complexity, and realizing large-scale optical matrix calculation. At the same time, the error function tr(Re(U aim *U exp H )) / k is used to measure the transfer matrix U of the FFT architecture exp With the target matrix U aim The similarity of U aim is a randomly generated unitary matrix. The comparison between the FFT architecture and the general matrix architecture is shown in the figure. aim *U exp H The closer )) / k is to 1, the smaller the difference between the transmission matrix and the target matrix is. For a unitary matrix, when U exp =U aim When U aim *U exp H =I (unit matrix), that is, tr(Re(U aim *U exp H )) / k=tr(I) / k=1. The choice of specific matrix architecture can be freely adjusted according to the research problem, and the proposed multi-core optical matrix computing acceleration architecture is compatible with various matrix computing implementations.

[0038] like Figure 7As shown, the silicon nitride optical adapter plate used in the example of the present invention includes multiple interlayer couplers, k 1:2 beam splitters and k dual-wavelength wavelength division multiplexers, where the green structure represents the upper silicon nitride waveguide and the white structure represents the lower silicon nitride waveguide. The interlayer coupler adopts an adiabatic gradient tapered structure, where the tip of one layer corresponds to the tail of the other layer. When the waveguide becomes narrower, the light field gradually loses its restraint, forming a super mode between the two layers of waveguides and gradually transitioning to the other layer of waveguide, and vice versa. The double-layer waveguide ensures a certain distance to avoid interlayer crosstalk, while also taking into account the evanescent wave coupling efficiency.

[0039] like Figure 8 As shown, the example of the present invention adopts the structure of silicon-silicon nitride coupler and silicon nitride wavelength division multiplexer. Preferably, the silicon waveguide thickness of the core particle is selected to be 220nm, the silicon nitride waveguide thickness of the optical adapter plate is selected to be 100nm, and the thickness of the silicon dioxide cladding above the silicon core particle and the silicon nitride adapter plate is selected to be 2μm. The core particle is packaged on the adapter plate by cover bonding, and the silicon-silicon nitride coupler uses an adiabatic gradient tapered structure aligned up and down to complete evanescent wave coupling, and the principle is similar to that of the interlayer coupler. The silicon nitride wavelength division multiplexer adopts an asymmetric multimode interference coupler structure, selects the common self-image point of two different wavelengths of light as the position of the beam combining waveguide, and completes wavelength division multiplexing.

[0040] like Fig. 9 As shown, the optical core particles, electrical chips and optical adapter boards in the examples of the present invention are three-dimensionally packaged. The electrical chip is bonded to the optical chip by flip-chip bonding to power the optical core particles, and the optical core particles are then bonded to the optical adapter board by direct bonding. Finally, the optical adapter board is packaged with the PCB board through the TSV process to form a system. The external laser uses methods such as prism / microlens coupling and fiber coupling to achieve low-loss end-face coupling.

[0041] like Fig.10 As shown, the core particles in the example of the present invention are directly bonded to the adapter board, and the multi-core optical matrix computing system and the peripheral circuit are interconnected by silicon through vias. Before bonding, the back thinning process of the core particle wafer is required to reduce warping. In order to achieve high-performance electrical interconnection, a rewiring layer needs to be made on the optical adapter board. The purpose is to fan out the high-density electrodes to the edge blank area to avoid damaging the optical structure on the adapter board when making silicon through vias, and then connect the electrodes to the back of the optical adapter board and the PCB board through the TSV process.

[0042] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-chip optical matrix computing architecture, characterized in that: In the optical computing architecture, a large chip is decomposed into several small core particles by matrix partitioning and separation of active modules and passive modules, specifically including n modulator array core particles, m×n optical matrix computing core particles, m detector array core particles and optical adapter plates for interconnecting the core particles; the matrix partitioning decomposes the large chip in array and matrix mode according to the functional scale and manufacturing process; the active module includes a modulator array core particle and a detector array core particle; the passive module includes an optical matrix computing core particle; each of the modulator array core particles includes q parallel modulators, each of the detector array core particles includes p parallel detectors, and each of the optical matrix computing core particles provides a p×q matrix computing sub-function, including q input ports and p output ports; the input light passes through the n modulator array core particles, is modulated into q signal lights in each of the modulator array core particles, and forms n-channel q-dimensional input vectors X after passing through the n modulator array core particles. j , each channel q-dimensional input vector X j Through 1:m splitting, m copies are made, n channels and q-dimensional input vector X j After replication, m×n q-dimensional vectors are formed, which are input into m×n optical matrix calculation core particles respectively and correspond to the corresponding p×q matrix A ij Multiply them together to get m×n p-dimensional vectors. After the light from n channels is multiplexed through n channels, m p-dimensional output vectors Y are obtained. i , provided to the m detector array core particles for detection in sequence, to obtain the multi-core optical matrix calculation results; the light of the n channels includes orthogonal channels of different wavelengths, orthogonal channels of different polarizations, orthogonal channels of different modes, orthogonal channels of other light wave dimensions, and orthogonal channels of different dimensional combinations; wherein, i = 1, 2, ..., m; j = 1, 2, ..., n.

2. The multi-core optical matrix computing architecture according to claim 1, characterized in that: For large-scale matrix-vector multiplication calculation Y=AX, X is the input N-dimensional vector, Y is the output N-dimensional vector, and A is an M×N matrix. The matrix block idea is used to decompose the M×N matrix A into m×n p×q matrices A ij , where M = m × p, N = n × q, the input N-dimensional vector X is decomposed into n-channel q-dimensional input vector X j , the output M-dimensional vector Y is decomposed into m p-dimensional output vectors Y i ,Right now: Among them, A ij is the decomposed p×q matrix, The result of large-scale matrix-vector multiplication Y=AX can be expressed as: in, Y2, Y3, ..., Y m Same reason.

3. The multi-core optical matrix computing architecture according to claim 1, characterized in that: Each of the modulator array core particles includes q modulators arranged in parallel, and the modulators are micro-ring modulators, micro-disk modulators, photonic crystal microcavity modulators, Mach-Zehnder modulators, electro-absorption modulators, modulators based on two-dimensional materials, or micro-ring and Mach-Zehnder combined structure modulators.

4. The multi-core optical matrix computing architecture according to claim 1, characterized in that: Each of the detector array core particles includes p detectors arranged in parallel, and the detectors are germanium silicon photodetectors, avalanche detectors, III-V group-based photodetectors, or detectors based on two-dimensional materials.

5. The multi-core optical matrix computing architecture according to claim 1, characterized in that: The optical matrix computing core particle is a cascaded Mach-Zehnder interferometer, a microring resonator array, a phase change material synapse array or an on-chip two-dimensional planar diffraction structure; wherein the network type used by the cascaded Mach-Zehnder interferometer is a triangular network, a rectangular network or a non-universal fast Fourier transform FFT network.

6. The multi-chip optical matrix computing architecture according to claim 1, characterized in that The optical adapter board includes a single-layer or multi-layer structure, each layer includes a waveguide array, an interlayer coupler, a 1:m beam splitter, and an n-channel multiplexer, and a multi-layer waveguide is used to reduce the waveguide crossing of the interconnection between core particles; wherein the interlayer coupler uses an evanescent wave coupler to achieve the coupling between the core particle layer and the optical adapter board layer and the coupling between different optical adapter board layers; the 1:m beam splitter uses a micro-nano structure beam splitter including a multi-mode interference coupler to branch the signal light to each optical matrix calculation core particle; the n-channel multiplexer is used to multiplex and add the calculation results of each optical matrix calculation core particle, including a wavelength division multiplexer, a polarization multiplexer, a mode multiplexer, or a multi-dimensional multiplexer that integrates wavelength, polarization, and mode.

7. The multi-core optical matrix computing architecture according to claim 1, characterized in that: The input light enters the n modulator array cores or optical adapter plates in a coupling manner, and the coupling manner is end-face coupling or vertical coupling.

8. The multi-core optical matrix computing architecture according to claim 1, characterized in that: The material platform of the modulator array core particles is silicon, thin-film lithium niobate, electro-optical polymer, III-V group, two-dimensional material, ferroelectric film, and piezoelectric film; the material platform of the optical matrix computing core particles includes silicon, silicon nitride, silicon dioxide, and thin-film lithium niobate; the material platform of the detector array core particles includes epitaxial germanium on silicon, III-V group, and two-dimensional materials; the material platform of the optical adapter plate includes silicon nitride, silicon dioxide, and organic polymer materials.

9. The multi-chip optical matrix computing architecture according to claim 1, characterized in that: The multi-chip optical matrix computing architecture also includes a peripheral circuit module for driving and controlling the multi-chip system; the peripheral circuit module mainly includes two parts: a high-speed signal loading circuit and a low-speed multi-channel control power supply, wherein the high-speed signal loading circuit includes a high-speed programmable logic array FPGA, a high-speed digital-to-analog conversion DAC, a high-speed analog-to-digital conversion ADC, a high-speed driver amplifier Driver, and a high-speed transimpedance amplifier TIA. The high-speed FPGA is used to provide a digital electrical signal corresponding to the data to be calculated and processed, and an analog electrical signal is obtained through a high-speed DAC. After being amplified to a suitable level by a high-speed Driver, it is driven and loaded onto a modulator to obtain an optical signal. After optical matrix calculation, a detection electrical signal is obtained through a detector, appropriately amplified in combination with a high-speed TIA, and then a digital electrical signal is obtained through a high-speed ADC, and finally provided to a high-speed FPGA or a computer for processing; the low-speed multi-channel control power supply mainly includes a microprocessor or a low-speed FPGA, a low-speed multi-channel DAC, and a low-speed power amplifier, which is used to control and adjust the optical chip and each phase shifter of the chip, so as to flexibly configure the coefficients in the matrix of the optical matrix calculation.

10. The multi-chip optical matrix computing architecture according to claim 9, characterized in that: The modulator array core, the detector array core, the optical matrix computing core and the optical adapter board are integrated by direct bonding; the packaging method between the peripheral circuit module and the optical adapter board is 2.5D or 3D advanced packaging, and the electric chip and the optical adapter board are packaged on a ceramic adapter board or a printed circuit board PCB by wire bonding to achieve 2.5D packaging, or the electric chip is directly flip-chip bonded and combined with through-silicon via technology to achieve 3D advanced packaging.

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