A CPU power supply circuit, a power supply method and a main control chip

Abstract

The present invention relates to the technical field of power supply circuit design, and discloses a CPU power supply circuit, a power supply method and a main control chip. The CPU power supply circuit includes a main control chip, a CPU and a power conversion circuit. The main control chip integrates codes of at least two power communication protocols. The main control chip is configured to determine a currently available communication protocol from at least two power communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol. The main control chip is further configured to receive a voltage regulation instruction from the CPU, generate a modulation signal according to the voltage regulation instruction, and send the modulation signal to the power conversion circuit. The power conversion circuit is configured to receive the modulation signal, adjust an externally input voltage according to the modulation signal and output the adjusted voltage to the CPU to supply power to the CPU. This solution realizes compatibility of a power supply chip with multi-platform processors by adjusting the chip software and hardware design, and solves the problems of low design flexibility and high complexity.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply circuit design, and particularly relates to a CPU power supply circuit, a power supply method and a main control chip. Background Art

[0002] Currently, the power supply for a server CPU (Central Processing Unit) needs to use a VRM (Voltage Regulator Module). As Figure 1 shown, compared with the traditional analog power supply scheme, the digital multi-phase power supply scheme has a faster response speed, and the digital multi-phase power supply can adjust power parameters through a digital interface. Therefore, the digital multi-phase power supply has higher flexibility and can adapt to more application scenarios.

[0003] Currently, the requirements for the main control chip by CPUs on different platforms are different, mainly reflected in two aspects. One is software requirements, and the other is hardware requirements. The software requirements are mainly in the power supply communication protocol part. Although CPUs communicate with the main control chip through clock signals (CLK) and data (DATA), different platforms define different specifications for CLK and DATA respectively. Therefore, even the same CLK and DATA waveforms convey different information. For the INTEL platform, the main control chip needs to support the SVID (SVID Power Management Protocol), while the AMD (Advanced Micro Devices) platform requires the main control chip to support the SVI3 protocol, and the Ampere platform requires support for the AVSBUS protocol. Currently, different platforms need to use different main control chips for design and cannot achieve multi-platform compatibility, that is, the platform only supports one power supply communication protocol and cannot meet the requirements of multi-protocol and multi-platform operation. In addition, the current software and hardware design of the main control chip for a single platform also results in high design complexity and low flexibility. Summary of the Invention

[0004] In view of this, the present invention provides a CPU power supply circuit, a power supply method and a main control chip to solve the problems of low design flexibility and poor procurement performance caused by the need to use different power supply chips due to different CPU power supply protocols.

[0005] In a first aspect, the present invention provides a CPU power supply circuit. The CPU power supply circuit includes: a main control chip, a CPU, and a power conversion circuit. Among them, the main control chip integrates codes of at least two power supply communication protocols and is used to provide communication functions of multiple power supply communication protocols for the CPU;

[0006] The master control chip is used to determine the currently available communication protocol from at least two power communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol;

[0007] The master control chip is further used to receive a voltage regulation instruction from the CPU during the communication process, generate a modulation signal according to the voltage regulation instruction, and send the modulation signal to the power conversion circuit;

[0008] The power conversion circuit is used to receive the modulation signal, adjust the external input voltage according to the modulation signal and output it to the CPU to supply power to the CPU.

[0009] The CPU power supply circuit provided in this aspect designs a master control chip with an internal design that can be flexibly adjusted as a code chip and integrates codes of at least two power communication protocols. It can support multiple power communication protocols, determine the currently available communication protocol from multiple power communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol. This design improves the design flexibility and the reuse rate of schematic diagrams for different platforms. By adjusting the chip software and hardware design, a single power chip can be compatible with multi-platform processors, thus solving the problems of low design flexibility and high design complexity caused by the need to use different power chips for different processors.

[0010] Combined with the first aspect, in a possible implementation manner, the master control chip is further used to update the bit identifier corresponding to the currently available communication protocol after determining the currently available communication protocol. The bit identifier has a unique correspondence with the currently available communication protocol and is used to indicate the currently adopted power communication protocol.

[0011] Combined with the first aspect, in another possible implementation manner, the master control chip is connected to the CPU through multiple pins and a switching switch. The multiple pins at least include a first pin and a second pin;

[0012] The master control chip is further used to control the switching switch to conduct the communication link between the first pin and the CPU and disconnect the communication link between the second pin and the CPU. The communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol.

[0013] Combined with the first aspect, in yet another possible implementation manner, the master control chip is further used to transmit a clock signal and a digital signal on the communication link between the first pin and the CPU according to the currently available communication protocol.

[0014] In another possible implementation manner in combination with the first aspect, the CPU power supply circuit further includes a baseboard management controller, and the baseboard management controller is respectively connected to the main control chip and the CPU;

[0015] The baseboard management controller is configured to communicate with the CPU, obtain the CPU type, and transmit the indication information including the CPU type to the main control chip;

[0016] The main control chip is further configured to receive the indication information from the baseboard management controller, determine the CPU type according to the indication information, and after determining the currently available communication protocol according to the CPU type, return a message of the selected power supply communication protocol to the baseboard management controller;

[0017] The baseboard management controller is further configured to receive the selected message and forward it to the CPU.

[0018] In another possible implementation manner in combination with the first aspect, the power conversion circuit includes a voltage input terminal, a voltage output terminal, an enable terminal, and a pulse width modulation terminal; wherein the voltage input terminal is connected to a power supply, the voltage output terminal is connected to the CPU, and the enable terminal and the pulse width modulation terminal are respectively connected to the main control chip;

[0019] The main control chip is further configured to send an enable signal to the enable terminal of the power conversion circuit and send the modulation signal to the pulse width modulation terminal;

[0020] The power conversion circuit is further configured to adjust the voltage according to the enable signal and the modulation signal and output the adjusted voltage to the CPU.

[0021] In another possible implementation manner in combination with the first aspect, the power conversion circuit further includes a third pin and a fourth pin, and both the third pin and the fourth pin are connected to the main control chip;

[0022] The power conversion circuit is further configured to transmit the collected current information of the CPU to the main control chip through the third pin and transmit the collected temperature information of the CPU to the main control chip through the fourth pin;

[0023] The main control chip is further configured to receive and detect whether one or more of the current information and the temperature information are within a preset value range, and in the case of being within the preset value range, feedback an instruction of voltage regulation completion to the CPU.

[0024] Optionally, the at least two power supply communication protocols include at least two of SVID, SVI3, and AVSBUS.

[0025] In a second aspect, the present invention provides a CPU power supply method, which is applied to the CPU power supply circuit described in the foregoing first aspect or any implementation manner of the first aspect. The method includes:

[0026] Obtain the CPU type;

[0027] Determine the currently available communication protocol from at least two power supply communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol;

[0028] During the communication process, receive a voltage regulation instruction from the CPU, generate a modulation signal according to the voltage regulation instruction, and send the modulation signal to a power conversion circuit, which is used to adjust the external input voltage according to the modulation signal and output it to the CPU to supply power to the CPU.

[0029] In combination with the second aspect, in a possible implementation manner, the method further includes: after determining the currently available communication protocol, update the bit identifier corresponding to the currently available communication protocol, and the bit identifier has a unique correspondence with the currently available communication protocol and is used to indicate the currently adopted power supply communication protocol.

[0030] In combination with the second aspect, in another possible implementation manner, the main control chip is connected to the CPU through a plurality of pins and a switching switch. The plurality of pins at least include a first pin and a second pin. The method further includes:

[0031] Control the switching switch to conduct the communication link between the first pin and the CPU and disconnect the communication link between the second pin and the CPU, where the communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol.

[0032] In combination with the second aspect, in another possible implementation manner, the communicating with the CPU according to the currently available communication protocol includes: transmitting a clock signal and a digital signal on the communication link between the first pin and the CPU according to the currently available communication protocol.

[0033] In a third aspect, the present invention further provides a main control chip, which includes: a communication module, a calculation module, and a driving module; wherein, the calculation module is respectively connected to the communication module and the driving module, the communication module is respectively connected to an external baseboard management controller and the CPU, and the driving module is also connected to the CPU;

[0034] Wherein, the communication module integrates codes of at least two power supply communication protocols and is used to provide communication functions of multiple power supply communication protocols for the CPU;

[0035] The communication module is configured to determine a currently available communication protocol from at least two power communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol;

[0036] The computing module is configured to receive a voltage regulation instruction from the CPU during communication, generate a driving instruction according to the voltage regulation instruction, and send the driving instruction to the driving module;

[0037] The driving module is configured to receive the driving instruction, generate a modulation signal, and send the modulation signal to the power conversion circuit, so that the power conversion circuit adjusts an external input voltage according to the modulation signal and outputs it to the CPU to supply power to the CPU.

[0038] In combination with the third aspect, in a possible implementation manner, the communication module further includes a register for storing at least two power communication protocols and bit identifiers corresponding to each power communication protocol.

[0039] In combination with the third aspect, in another possible implementation manner, the communication module further includes a plurality of pins and a switching switch, and the plurality of pins at least include a first pin and a second pin;

[0040] A communication link is established between the first pin and the CPU for communicating with the main control chip according to the currently available communication protocol;

[0041] A communication link is established between the second pin and the CPU for communicating with the main control chip according to another communication protocol, and the other communication protocol is a protocol other than the currently available communication protocol among at least two power communication protocols;

[0042] The switching switch is configured to disconnect or conduct the communication link.

[0043] In a fourth aspect, the present invention further provides a communication module, which includes a receiving unit, a determining unit, and a sending unit. Specifically, the receiving unit is configured to receive indication information including the CPU type sent by a baseboard management controller; the determining unit is configured to determine a currently available communication protocol from at least two power communication protocols according to the CPU type; the sending unit is configured to send a selected message determining the currently available communication protocol to the CPU through the board management controller, so that the CPU communicates with the communication module according to the currently available communication protocol.

[0044] A CPU power supply circuit, a power supply method and a main control chip provided by the present invention adjust the chip software and hardware design to enable a power supply chip to be compatible with multi-platform processors, thereby solving the problems of low design flexibility and high design complexity caused by the need to use different power supply chips for different processors. Specifically, the following beneficial effects are included:

[0045] The main control chip in the present invention adopts a code chip architecture that can be flexibly adjusted and pre-integrates the codes of at least two power communication protocols. This design enables the main control chip to intelligently select the currently optimal power communication protocol from multiple power communication protocols according to the type of CPU, and communicate with the CPU efficiently according to the currently selected power communication protocol. This not only improves the flexibility of communication, but also significantly enhances the compatibility of the circuit with different types of CPUs, realizing the communication transmission of multiple power communication protocols on the main control chip.

[0046] The main control chip of the present invention realizes a fast response to the voltage regulation instruction from the CPU, can accurately parse the voltage regulation instruction, generate an accurate modulation signal accordingly, and send it to the power conversion circuit to adjust the input voltage, so as to provide a suitable output voltage for the CPU. The optimization of this process makes the voltage regulation faster and more accurate, effectively meeting the fine requirements of the CPU for the power supply voltage under different working loads, and improving the performance stability and energy efficiency ratio of the CPU.

[0047] In addition, this method can adjust the output voltage in real time to provide stable and reliable power supply for the CPU. Since the main control chip can intelligently select the optimal communication protocol according to the CPU type and ensure efficient communication with the CPU, this further enhances the response speed and stability of the power supply circuit. At the same time, the support of multiple power communication protocols also increases the adaptability of the circuit in complex environments and improves the reliability of the overall system.

[0048] In addition, usually, power supply chips for SVID, SVI3 and AVSBUS protocols need to use three different models. The present invention uses a power main control chip that is compatible with multiple protocols, and the material model is reduced from 3 to 1, which is beneficial to procurement and preparation of materials and reduces the risk of material stagnation or shortage. Description of the Drawings

[0049] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required to be used in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0050] Figure 1 It is a schematic diagram of a digital multi-phase power supply solution provided by the present invention;

[0051] Figure 2a It is a schematic diagram of the communication between the INTEL platform CPU and the main control chip provided according to an embodiment of the present invention;

[0052] Figure 2b It is a schematic diagram of the communication between the AMD platform CPU and the main control chip provided according to an embodiment of the present invention;

[0053] Figure 3 It is a schematic diagram of a power main control chip integrating multiple protocols provided according to an embodiment of the present invention;

[0054] Figure 4 It is a schematic structural diagram of a CPU power supply circuit provided according to an embodiment of the present invention;

[0055] Figure 5 It is a schematic diagram of software-level compatibility provided according to an embodiment of the present invention;

[0056] Figure 6 It is a schematic diagram of hardware function compatibility provided according to an embodiment of the present invention;

[0057] Figure 7 It is a schematic flow diagram of a CPU power supply method provided according to an embodiment of the present invention;

[0058] Figure 8 It is a structural block diagram of a communication module provided according to an embodiment of the present invention. Detailed implementation manners

[0059] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0060] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0061] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0062] In the different embodiments of the present invention described below, the technical features involved can be combined with each other as long as they do not conflict with each other.

[0063] The technical solution provided by the embodiment of the present invention can be applied to the application scenario powered by CPU (Central Processing Unit, central processing unit). The CPU-powered application scenario generally adopts a digital multi-phase power supply scheme, such as Figure 1 shown, which is a schematic diagram of a digital multi-phase power supply scheme.

[0064] This scheme includes: a CPU, a main control chip, and a power conversion module or a power conversion chip. Since the CPU has high-performance and low-power modes, different working voltages Vout need to be selected in different working scenarios. This voltage requirement is determined by the CPU and transmitted to the main control chip through clock signals and data signals to achieve real-time voltage adjustment.

[0065] Currently, the requirements of CPUs on different platforms for the main control chip are different, which are mainly reflected in two aspects. On the one hand, it is the software requirement, and on the other hand, it is the hardware requirement. Among them, for the software requirement, it is mainly in the power supply communication protocol part, and the power supply communication protocols for different platforms are not compatible with each other. For example Figure 2a shown, on the INTEL (Intel) CPU platform, it is generally recommended to use a chip of model XDPE1***4 as the main control chip, and this active chip can support the SVID (SVID Power Management Protocol, system voltage identification power management protocol) communication of the INTEL CPU.

[0066] Among them, the SVID power management protocol is a communication protocol for power management. It defines the specifications for transmitting and interpreting power management-related information in the system, aiming to achieve power management across suppliers. The SVID protocol helps to improve energy efficiency, reduce power consumption, and simplify the system integration and development process by providing rich functions, high flexibility, and strong scalability. This protocol has a wide range of applications in the field of power management, especially in systems that require efficient and reliable power management.

[0067] On the AMD (Advanced Micro Devices) CPU platform, a chip of model XDPE1***3 is used as the main control chip. As Figure 2b shown, it can support the AMD SVI3 power protocol, and there are also differences in the PIN foot definitions between the two main control chips in addition to the difference in the power protocol.

[0068] Specifically for the SVl3 version, it is a version with certain improvements or upgrades based on the SVID interface. The AMD Serial VID Interface (SVID) is a communication interface between the AMD processor and the power management system, used to implement voltage identification (VID) and power management functions. The SVID interface allows the processor to send its required voltage and current requirements to the power management system, so that the power management system can adjust the power supply parameters accordingly, thereby ensuring the stable operation and efficient energy consumption of the processor.

[0069] In the AMD Ryzen 6000 series processors, SVI3 (System Voltage Interface 3) is an advanced technology used to achieve faster, more accurate, and finer-grained platform-level power or power consumption control. The SVI3 technology realizes more refined management of power control by improving the design of the system voltage interface. It allows the processor to more accurately monitor and control voltage and current changes, thereby optimizing the balance between power consumption and performance. In the field of high-performance computing, the SVI3 technology enables the AMD Ryzen 6000 series processors to achieve better energy efficiency ratios in these scenarios, as well as higher energy efficiency and lower operating costs in the data center environment, and longer battery life.

[0070] Currently, for two types of main control chips, due to different package PIN definitions, different platforms need to use different main control chips in the principle design and cannot achieve multi-platform compatibility. This not only leads to high complexity and low flexibility in the principle design, but also the variety of selected materials is relatively large, which is not conducive to material procurement.

[0071] To solve the above problems, the embodiment of the present invention provides a CPU power supply design scheme that can be compatible with multiple power supply protocols at the same time, that is, integrating the SVID, SVI3, and AVSBUS three power communication protocols in one main control chip and adjusting the chip package design to realize the function of one power main control chip replacing three power main control chips.

[0072] The technical solutions provided by the embodiments of the invention will be described in detail below.

[0073] To meet the design requirements, two aspects of the communication module need to be solved: one is the software level, and the other is the hardware level. In order to enable a single main control chip to be compatible with multiple power communication protocols, improvements need to be made at the software level and the hardware level respectively.

[0074] Among them, the improvements at the software level include: it is necessary to perform compatible designs for the SVID, SVI3, and AVSBUS three power supply protocols, such as Figure 3As shown in the figure, first, when designing the hardware of the main control chip, the chip of the communication module with the ASIC architecture is changed to a chip with the ARM architecture, which is a chip with flexible code adjustment. Because compared with the ASIC architecture chip, the ARM architecture chip can be reprogrammed to flexibly adjust the code program to achieve repeated switching between different protocols. In the past, for the ASIC architecture, generally referring to the hardware structure and organization method of an Application-Specific Integrated Circuit, after a certain power supply protocol is stored in the chip, it cannot be changed anymore, so it can only support a single platform.

[0075] Among them, the ARM architecture, whose full name is Advanced RISC Machine, means Advanced Reduced Instruction Set Computer. It is a processor design solution. ARM architecture chips have been widely used in many fields such as mobile devices, Internet of Things devices, servers, and data centers due to their characteristics of low power consumption, high performance, flexibility, and scalability.

[0076] Then, the three power communication protocols OTP (One Time Programable) are respectively code-compressed to reduce the code space occupied by each protocol. The compressed codes are all implanted into the storage space of the ARM architecture chip for later use, and a two-bit (bit) protocol setting register is defined in the storage space. Among them, the protocol selection register and the communication protocol code are placed in the storage space together, and are specifically used to set which power communication protocol the current power main control chip will use.

[0077] It should be noted that the register and the compressed protocol code can exist side by side. For the storage method, the compressed protocol code can be stored in a part of the storage resources of the communication module, while the register of the communication module is used to store the two-bit protocol relationship. Please refer to Table 1 below for details.

[0078] See Figure 4 , which is a schematic structural diagram of a CPU power supply circuit provided by an embodiment of the present invention. The CPU power supply circuit includes: a main control chip, a CPU, and a power conversion circuit. In addition, the power supply circuit may also include other modules or circuits, such as BMC (Baseboard Management Controller). Among them, the main control chip is a chip with flexible code adjustment and integrates the codes of at least two power communication protocols, and is used to provide communication functions of multiple power communication protocols for the CPU.

[0079] The main control chip is used to determine the currently available communication protocol among at least two power communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol.

[0080] Optionally, at least two power supply communication protocols include at least two of SVID, SVI3, and AVSBUS. Among them, AVSBUS (Adaptive Voltage Scaling Bus) is a high-speed, point-to-point bus mainly used to connect the CPU and the power supply to achieve efficient voltage regulation and power management, and is mainly applied to scenarios that require high performance, low power consumption, and precise power management.

[0081] In addition, AVSBUS is designed to provide a mechanism that enables an ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), or processor to change the voltage of its power supply by sending commands to a POL (Point of Load converter). In addition, AVSBUS also supports reading back the voltage and current of the POL, thereby achieving precise monitoring and management of the power supply subsystem. Through AVSBUS, a digital multi-phase controller can be directly connected to the load and dynamically adjust the voltage level to achieve efficiency savings.

[0082] Specifically, the main control chip is also used to determine the currently available communication protocol among at least two power supply communication protocols according to the CPU type, inform the CPU through the BMC, and communicate with the CPU according to the currently available communication protocol. For example, the previous communication protocol is one of SVID, SVI3, and AVSBUS. Further, the communication module communicates with the CPU through CLK and DATA signals.

[0083] In addition, the main control chip is also used to receive a voltage regulation instruction from the CPU during the communication process, generate a modulation signal according to the voltage regulation instruction, and send the modulation signal to the power conversion circuit.

[0084] The power conversion circuit is used to receive the modulation signal, adjust the external input voltage according to the modulation signal, and output it to the CPU to supply power to the CPU.

[0085] In addition, the above BMC is respectively connected to the main control chip and the CPU; it is used to communicate with the CPU, obtain the CPU type, and transmit the indication information containing the CPU type to the main control chip.

[0086] The main control chip is also used to receive the indication information from the BMC, determine the CPU type according to the indication information, and after determining the currently available communication protocol according to the CPU type, return the message of the selected power supply communication protocol to the BMC.

[0087] The BMC is also used to receive the message from the selection and forward it to the CPU.

[0088] Optionally, the above main control chip includes: a communication module, a calculation module, and a drive module. As Figure 4As shown, the connection relationships are as follows: The communication module is respectively connected to the BMC and the CPU, and the BMC and the CPU are connected through an I2C channel; the computing module is respectively connected to the communication module and the drive module, and the drive module is also connected to the CPU.

[0089] Further, the computing module is used to receive a voltage regulation instruction from the CPU during communication, generate a drive instruction according to the voltage regulation instruction, and send it to the drive module. Further, the computing module is responsible for collecting the current, voltage, and temperature information of the power conversion chip for instruction calculation.

[0090] The drive module is used to receive the drive instruction and generate and output a modulation signal to the power conversion circuit according to the drive instruction.

[0091] In a specific implementation manner of this embodiment, the communication module of the main control chip includes a register, as Figure 5 shown, and at least two power communication protocols and the corresponding bit identifiers for each power communication protocol are stored in the register.

[0092] The protocol setting register sets different digital bits for selecting different communication protocols, and the selection method is shown in Table 1 below. Among them, 00 / 01 / 10 respectively correspond to the SVID / SVI3 / AVSBUS protocols, and 11 represents that no communication protocol is selected.

[0093] Table 1

[0094]

[0095] After the main control chip is designed, the protocol setting register defaults to the "11" state. In the initial state, the power communication protocols recorded in the register are empty, indicating that the chip does not support any power protocol at this time. After the main control chip is soldered to the PCB board, the BMC on the board will work first during operation and detect which platform's CPU solution is used by the CPU on the current board.

[0096] Initialization process: The BMC communicates with the CPU through the I2C channel to detect the CPU type. The CPU will report the currently used platform to the BMC. If the BMC detects that the CPU is of the INTEL platform, the BMC will inform the communication module through the PMBUS channel that the currently used platform of the CPU is INTEL.

[0097] Among them, PMBUS, the full name is Power Management Bus, that is, the power management bus, which is an open standard digital power management protocol. The PMBUS protocol aims to promote communication with power converters or other devices by defining the transmission and physical interfaces and the command language.

[0098] The master control chip is also used to update the bit identifier corresponding to the currently available communication protocol after determining the currently available communication protocol. This bit identifier has a unique correspondence with the currently available communication protocol and is used to indicate the currently adopted power supply communication protocol.

[0099] A specific implementation is that the communication module determines that the power supply communication protocol supported by the current INTEL CPU platform, such as INTEL, is the SVID communication protocol, that is, the currently available communication protocol, according to the currently obtained platform. After determining the currently available communication protocol, the bit identifier of the register is updated from empty to the target bit identifier. The target bit identifier has a unique correspondence with the currently available communication protocol. For example, according to Table 1 above, "11" is updated to "00". Among them, in the SVID communication protocol scenario, the corresponding target bit identifier is "00".

[0100] Such as Figure 4 As shown, after the communication protocol is selected, the master control chip notifies the BMC, and the BMC notifies the CPU. After receiving the completion instruction, the CPU starts communicating with the power supply master control chip.

[0101] Specifically, the BMC communicates with the CPU through the I2C channel, obtains the CPU type, and transmits the indication information containing the CPU type to the communication module of the master control chip through PMBUS; the communication module receives the indication information transmitted from the BMC, determines the currently available communication protocol according to the CPU type included in the indication information, and returns the selected message to the BMC. The BMC receives the selected message sent from the communication module and forwards it to the CPU.

[0102] In a specific implementation of this embodiment, the process of the above power supply master control chip communicating with the CPU includes:

[0103] The master control chip first obtains the compressed code from the storage space, and then decompresses the code to obtain the source code of the SVID protocol, that is, the decompressed file. Specifically, when it is detected that the CPU is an Intel platform, the protocol setting register changes to 00. At this time, the SVID code pre-stored in the storage space will be decompressed and the function adaptation will be completed to achieve normal communication with the CPU.

[0104] The master control chip uses the decompressed source code to generate corresponding DATA or CLK signals, confirms that the path of the SVID protocol is in a conducting state, and then uses the communication module to communicate with the CPU according to the current SVID protocol for CLK and digital signals.

[0105] If the protocol setting fails to be successfully burned, the software will prompt an error. Ensure that the correct communication protocol has been selected for the chip before it is installed on the board to prevent abnormal CPU operation caused by different communication protocols. In this embodiment, the main control chip supports multiple burns and can be flexibly switched between different protocols.

[0106] After solving the software-level problems of the above communication module, it is also necessary to solve the hardware problems. Currently, there are many differences in the pin functions of power controllers on different platforms. In order to enable a single chip to be compatible with multiple platforms, hardware design compatibility also needs to be achieved.

[0107] To achieve this goal, in this embodiment, the different pins are made compatible by designing multifunctional multiplexing pins, that is, one channel can simultaneously be compatible with multiple pin functions. For example, all three power communication protocols need to be interconnected with the CPU through the PIN pins of CLK and DATA to achieve communication. However, if each power protocol designs PIN pins for CLK and DATA, it will result in a larger chip package. And since only one power communication protocol is effective during operation and the rest are not, the extra PINs will also be wasted. Therefore, internal hardware circuits are designed to be compatible with the requirements of CPUs on different platforms, such as Figure 6 As shown, the main control chip is connected to the CPU through multiple pins and a switching switch. Among them, the multiple pins at least include a first pin and a second pin.

[0108] Furthermore, the main control chip is also used to control the switching switch to conduct the communication link between the first pin and the CPU, and disconnect the communication link between the second pin and the CPU. The communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol (such as SVID). The communication link between the second pin and the CPU can be used to transmit data or signals of the SVI3 and AVSBUS protocols. Since the signals of the SVI3 and AVSBUS protocols do not need to be transmitted currently, these links are disconnected through the switching switch, and only the communication link for transmitting the currently required data or signals is conducted.

[0109] In this embodiment, the main control chip can conduct two communication links of the SVID protocol through the control unit, one for transmitting CLK1 and the other for transmitting DATA1, while disconnecting the communication links between the SVI3 and AVSBUS protocols and the CPU.

[0110] In this embodiment, when different power communication protocols are selected, the control unit closes the hardware switches of the corresponding CLK and DATA channels, and disconnects the switches of the remaining communication protocols, so as to achieve the function of replacing 6 PINs with only two multifunctional PINs, thereby saving costs and simplifying the circuit.

[0111] The CPU power supply and voltage regulation process will be described below.

[0112] As Figure 4 shown, the above CPU power supply circuit further includes a power conversion circuit, which includes a voltage input terminal Vout, a voltage output terminal Vin, an enable terminal (enable, EN), and a PWM (Pulse Width Modulation) terminal. In addition, the power conversion circuit may further include more or fewer other pins, such as including a third pin and a fourth pin, and both the third pin and the fourth pin are connected to the main control chip.

[0113] Among them, the voltage input terminal Vin is connected to an external power supply, the voltage output terminal Vout is connected to the CPU, and the enable terminal EN and the PWM terminal are respectively connected to the drive module.

[0114] Optionally, the third pin is the Imon pin, the fourth pin is the Tmon pin, and the third pin and the fourth pin are respectively connected to the calculation module.

[0115] The third pin is used to collect current information and transmit the current information to the calculation module; similarly, the fourth pin can be used to collect the temperature information of the CPU and report the collected temperature information to the calculation module.

[0116] The working process is as follows: The CPU sends a voltage regulation instruction to the communication module through CLK and DATA, and the communication module sends the received voltage regulation instruction to the calculation module.

[0117] After receiving the voltage regulation instruction, the calculation module sets the PWM drive instruction to be executed and sends the drive instruction to the drive module.

[0118] After receiving the drive instruction, the drive module sends an enable signal ENABLE and a PWM signal to the power conversion circuit. After the EN terminal and the PWM terminal of the power conversion circuit respectively receive the enable signal ENABLE and the PWM signal, the output voltage Vout is adjusted and the Vout is output externally. Among them, a part of Vout is used to supply power to the CPU, and the other part returns to the calculation module through sampling to detect whether the voltage reaches the expected set value. If the calculation module detects that the output voltage Vout reaches the set value, the calculation module sends a voltage regulation instruction feedback to the communication module to complete the voltage regulation process.

[0119] Specifically, the drive module is further used to send an enable signal EN to the enable terminal of the power conversion circuit and a PWM drive signal to the PWM terminal. The power conversion circuit is used to adjust the output voltage according to the enable signal ENABLE and the PWM drive signal and transmit the adjusted output voltage to the CPU. Among them, the PWM drive signal is a modulation signal.

[0120] In addition, the power conversion circuit further includes a third pin and a fourth pin, both of which are connected to the computing module. The power conversion circuit is further configured to transmit the collected current information of the CPU to the main control chip through the third pin, and transmit the collected temperature information of the CPU to the main control chip through the fourth pin.

[0121] The main control chip is further configured to receive and detect whether one or more of the current information and the temperature information are within a preset value range, and in the case of being within the preset value range, feedback an instruction of voltage regulation completion to the CPU.

[0122] In this embodiment, the hardware improvement of the main control chip realizes the function of multi-channel and multi-channel switching in the communication module. It should be understood that in addition to the communication module, the PINs with differences in different platforms of the computing module and the driving module can all be designed as hardware multi-functional PINs. Figure 6 For the PIN definition of the multi-protocol power control chip, PINs 1-17 are common to the three platforms and have the same definition. PINs 18-24 are multiplexed in a multi-functional design shown in Table 2 to achieve hardware compatibility among the three platforms. The current chip has been taped out and the feasibility of the solution has been verified through actual tests. See Table 2 for details.

[0123] Table 2

[0124]

[0125] The difference between APWM and BPWM is that a main control chip supports a maximum of two different output voltages, voltage A and voltage B, or it can also output only one voltage. If all 12 channels are used to output voltage A, the expression of the PWM voltage can be APWM1~APWM12. If 6 channels out of 12 channels are used to output voltage A and the other 6 channels are used to output voltage B, then the voltages transmitted by 6 channels are expressed as APWM 1~APWM 6, and the voltages transmitted by the other 6 channels are expressed as BPWM 1~BPWM6.

[0126] Table 2 shows the hardware definitions of the chip and the connection relationships of PIN pin multiplexing when three power communication protocols are selected under three platforms, which are used for hardware implementation of multi-functional multiplexing design. Combined with the above software improvements, the beneficial effect of a power chip being compatible with multi-platform processors is achieved together.

[0127] The master control chip provided in this embodiment is designed in software to adopt a code chip architecture that can be flexibly adjusted, and pre-integrates the codes of at least two power communication protocols, and is selected through a protocol setting register. At the hardware level, three protocols are made hardware-compatible by designing a multi-functional multiplexed PIN. Chip design is carried out according to the theoretical design at the software level and the hardware level, and the feasibility of this solution is verified through back-chip testing, which not only improves the flexibility of communication, but also significantly enhances the compatibility of the circuit with different types of CPUs, and realizes the communication transmission of multiple power communication protocols on the master control chip.

[0128] The present invention realizes a rapid response to the voltage regulation instruction from the CPU, can accurately parse the voltage regulation instruction, and generates an accurate modulation signal accordingly, and sends it to the power conversion circuit to adjust the input voltage, so as to provide a suitable output voltage for the CPU. The optimization of this process makes the voltage regulation faster and more accurate, effectively meeting the fine requirements of the CPU for the power supply voltage under different working loads, and improving the performance stability and energy efficiency ratio of the CPU.

[0129] In addition, this method can adjust the output voltage in real time to provide stable and reliable power supply for the CPU. Since the master control chip can intelligently select the optimal communication protocol according to the CPU type and ensure efficient communication with the CPU, this further enhances the response speed and stability of the power supply circuit. At the same time, the support of multiple power communication protocols also increases the adaptability of the circuit in complex environments and improves the reliability of the overall system.

[0130] In addition, usually, power chips of SVID, SVI3 and AVSBUS protocols need to use three different models. The present invention uses a power master control chip compatible with multiple protocols, and the material model is reduced from 3 to 1, which is conducive to procurement and stock preparation and reduces the risk of material stagnation or out-of-stock.

[0131] An embodiment of a CPU power supply method is provided in an embodiment of the present invention. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0132] In this embodiment, a CPU power supply method is provided, which can be used for the master control chip in the above embodiment. Figure 7 It is a flowchart of the CPU power supply method according to an embodiment of the present invention, and the method includes:

[0133] Step S101: Obtain the CPU type.

[0134] Among them, the CPU type can be obtained by the master control chip according to the indication information containing the CPU type sent by the BMC.

[0135] Step S102: Determine the currently available communication protocol among at least two power supply communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol.

[0136] Step S103: Receive a voltage regulation instruction from the CPU during the communication process, generate a modulation signal according to the voltage regulation instruction, and send the modulation signal to the power conversion circuit.

[0137] The power conversion circuit is used to adjust the external input voltage according to the modulation signal and output it to the CPU to supply power to the CPU.

[0138] In addition, the method of this embodiment further includes: after the CPU receives the selected message, the CPU communicates with the communication module according to the currently available communication protocol.

[0139] In the above step S102, after the main control chip determines the currently available communication protocol, update the bit identifier corresponding to the currently available communication protocol. The bit identifier has a unique correspondence with the currently available communication protocol and is used to indicate the currently adopted power supply communication protocol.

[0140] Among them, the above correspondence can be stored in the register of the communication module. In the initial state, the power supply communication protocol recorded in the register is empty; after determining the currently available communication protocol, update the identifier of the register from empty to the target bit identifier, and the target bit identifier has a unique correspondence with the currently available communication protocol.

[0141] In another possible implementation manner, the main control chip is connected to the CPU through multiple pins and a switching switch. The multiple pins at least include a first pin and a second pin. The method of this embodiment further includes:

[0142] The main control chip controls the switching switch to conduct the communication link between the first pin and the CPU and disconnect the communication link between the second pin and the CPU. Among them, the communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol, and the second pin or other pins are used to establish a communication link of the SVI3 and / or AVSBUS protocol with the CPU.

[0143] Among them, the CPU communicates with the communication module according to the currently available communication protocol, including: transmitting a clock signal and a digital signal on the communication link between the first pin and the CPU according to the currently available communication protocol.

[0144] Specifically, for the detailed process of the above method, refer to the description of the foregoing embodiment, and details are not described herein again.

[0145] In this embodiment, a communication module is further provided. This communication module is used to implement the above-mentioned embodiments and preferred implementation manners, and those that have been described will not be repeated here. As used hereinafter, the term "module" can be a combination of software and / or hardware that can achieve a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0146] This embodiment provides a communication module. As Figure 8 shown, the communication module includes: a receiving unit 810, a determining unit 820, and a transmitting unit 830. In addition, the communication module may further include other more or fewer modules, such as a storage module, etc., and this embodiment does not limit this.

[0147] The receiving unit 810 is configured to receive the indication information including the CPU type sent by the baseboard management controller, and obtain the CPU type according to the indication information.

[0148] The determining unit 820 is configured to determine the currently available communication protocol from at least two power communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol.

[0149] Specifically, the transmitting unit 830 is configured to send the selected message of the currently available communication protocol to the CPU through the BMC, so that the CPU communicates with the communication module according to the currently available communication protocol, and powers the CPU using the computing module and the driving module.

[0150] The further function descriptions of the above-mentioned various modules and units are the same as those in the corresponding above-mentioned embodiments, and will not be repeated here.

[0151] The communication module in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0152] This embodiment of the present invention further provides a main control chip, which has the above-mentioned Figure 4 、 Figure 5 、 Figure 6 and Figure 8 shown communication module.

[0153] Specifically, as Figure 4 shown, the main control chip includes: a communication module, a computing module, and a driving module; wherein, the computing module is respectively connected to the communication module and the driving module, the communication module is respectively connected to the external BMC and the CPU, and the driving module is also connected to the CPU.

[0154] Among them, the communication module is a code chip that can be flexibly adjusted. For example, it is a chip circuit with an ARM architecture, and codes of at least two power communication protocols are pre-implanted in the communication module for providing a multi-power communication function for the computing module. The communication module is used to execute the aforesaid Figure 7 CPU power supply method shown.

[0155] Specifically, the communication module is used to determine the currently available communication protocol among at least two power communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol.

[0156] The computing module is used to receive a voltage regulation instruction from the CPU during the communication process, generate a drive instruction according to the voltage regulation instruction, and send the drive instruction to the drive module.

[0157] The drive module is used to receive the drive instruction, generate a modulation signal, and send the modulation signal to the power conversion circuit, so that the power conversion circuit adjusts the externally input voltage according to the modulation signal and outputs it to the CPU to supply power to the CPU.

[0158] Furthermore, the communication module further includes a register, and the register is used to store at least two power communication protocols and the bit identifier corresponding to each power communication protocol.

[0159] In addition, the communication module provided in this embodiment further includes: a plurality of pins and a switching switch. The plurality of pins at least include a first pin and a second pin. A communication link is established between the first pin and the CPU for communicating with the main control chip according to the currently available communication protocol; a communication link is established between the second pin and the CPU, and this link is used to communicate with the main control chip according to other communication protocols, and the other communication protocols are the protocols other than the currently available communication protocol among at least two power communication protocols. The switching switch is used to disconnect or conduct at least one communication link.

[0160] For the functions of each module, refer to the description in the foregoing embodiment, and details are not described herein again.

[0161] In addition, in this embodiment, the aforesaid CPU may be a central processing unit. Among them, the CPU may further include a hardware chip. The aforesaid hardware chip may be an application specific integrated circuit, a programmable logic device or a combination thereof. The aforesaid programmable logic device may be a complex programmable logic device, a field programmable gate array, a generic array logic or any combination thereof.

[0162] In the communication module, the computing module may also be a processing circuit or a processing module, and may be a complex programmable logic device among programmable logic devices.

[0163] In addition, the communication module further includes a storage module or a storage unit, which may include a program storage area and a data storage area. The program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device and the like. In addition, the storage module or the storage unit may include a high-speed random access memory, and may further include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices.

[0164] In addition, the registers in the communication module may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state drive.

[0165] In addition, the above-mentioned main control chip further includes a plurality of pins or terminals, and at least one communication interface for communicating with other devices or modules.

[0166] An embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and to be stored in a local storage medium, so that the method described herein can be stored as such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware.

[0167] Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiment is implemented.

[0168] Embodiments of the present application may further provide a computer program product, including computer program instructions, which cause a processor to execute the steps in the above method when being run by the processor. Among them, the computer program product can be written in any combination of one or more programming languages to execute the program code for the operations of the embodiments of the present disclosure. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, executed as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0169] The above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them; although the embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A CPU power supply circuit, characterized in that, The CPU power supply circuit includes a main control chip, a CPU, and a power conversion circuit. Among them, the main control chip is connected to the CPU through multiple pins and a switching switch. The power conversion circuit includes a voltage input terminal, a voltage output terminal, an enable terminal, and a pulse width modulation terminal. The voltage input terminal is connected to a power supply, the voltage output terminal is connected to the CPU, and the enable terminal and the pulse width modulation terminal are respectively connected to the main control chip. The main control chip integrates codes of at least two power communication protocols, and is used to provide communication functions of multiple power communication protocols for the CPU. The main control chip is used to determine the currently available communication protocol among at least two power communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol. The main control chip is further used to receive a voltage regulation instruction from the CPU during the communication process, generate a modulation signal according to the voltage regulation instruction, and send the modulation signal to the power conversion circuit. The power conversion circuit is used to receive the modulation signal, adjust the externally input voltage according to the modulation signal, and output it to the CPU to supply power to the CPU.

2. The CPU power supply circuit according to claim 1, wherein The main control chip is further used to update the bit identifier corresponding to the currently available communication protocol after determining the currently available communication protocol. The bit identifier has a unique correspondence with the currently available communication protocol and is used to indicate the currently adopted power communication protocol.

3. The CPU power supply circuit according to claim 1, wherein, The multiple pins at least include a first pin and a second pin. The main control chip is further used to control the switching switch to conduct the communication link between the first pin and the CPU, and disconnect the communication link between the second pin and the CPU. The communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol.

4. The CPU power supply circuit according to claim 3, wherein The main control chip is further used to transmit a clock signal and a digital signal on the communication link between the first pin and the CPU according to the currently available communication protocol.

5. The CPU power supply circuit according to any one of claims 1-4, characterized in that, The CPU power supply circuit further includes a baseboard management controller, and the baseboard management controller is respectively connected to the main control chip and the CPU. The baseboard management controller is used to communicate with the CPU, obtain the CPU type, and transmit the indication information including the CPU type to the main control chip. The main control chip is further used to receive the indication information from the baseboard management controller, determine the CPU type according to the indication information, and after determining the currently available communication protocol according to the CPU type, return a message of the selected power communication protocol to the baseboard management controller. The baseboard management controller is further used to receive the message from the selection and forward it to the CPU.

6. The CPU power supply circuit according to claim 1, wherein The main control chip is further configured to send an enable signal to the enable terminal of the power conversion circuit and send the modulation signal to the pulse width modulation terminal; The power conversion circuit is further configured to adjust the voltage according to the enable signal and the modulation signal and output the adjusted voltage to the CPU.

7. The CPU power supply circuit according to claim 6, wherein The power conversion circuit further includes a third pin and a fourth pin, and both the third pin and the fourth pin are connected to the main control chip; The power conversion circuit is further configured to transmit the collected current information of the CPU to the main control chip through the third pin and transmit the collected temperature information of the CPU to the main control chip through the fourth pin; The main control chip is further configured to receive and detect whether one or more of the current information and the temperature information are within a preset value range, and in the case of being within the preset value range, feedback an instruction indicating that the voltage regulation is completed to the CPU.

8. The CPU power supply circuit according to claim 6, wherein, The at least two power communication protocols include at least two of SVID, SVI3, and AVSBUS.

9. A CPU power supply method, characterized in that, The method is applied to the main control chip according to any one of claims 1 to 8. The main control chip integrates codes of at least two power communication protocols and is used to provide communication functions of multiple power communication protocols for the CPU. The method includes: Obtain the CPU type; Determine the currently available communication protocol from at least two power communication protocols according to the CPU type and communicate with the CPU according to the currently available communication protocol; Receive a voltage regulation instruction from the CPU during the communication process, generate a modulation signal according to the voltage regulation instruction, and send the modulation signal to the power conversion circuit. The power conversion circuit is configured to adjust the external input voltage according to the modulation signal and output it to the CPU to supply power to the CPU.

10. The method according to claim 9, characterized in that, The method further includes: After determining the currently available communication protocol, update the bit identifier corresponding to the currently available communication protocol. The bit identifier has a unique correspondence with the currently available communication protocol and is used to indicate the currently adopted power communication protocol.

11. The method according to claim 9, characterized in that The main control chip is connected to the CPU through a plurality of pins and a switching switch. The plurality of pins at least include a first pin and a second pin. The method further includes: Control the switching switch to conduct the communication link between the first pin and the CPU and disconnect the communication link between the second pin and the CPU. The communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol.

12. The method according to claim 11, wherein The communicating with the CPU according to the currently available communication protocol includes: Transmit a clock signal and a digital signal on the communication link between the first pin and the CPU according to the currently available communication protocol.

13. A main control chip, characterized in that, The main control chip includes: a communication module, a calculation module, and a driving module; wherein, the calculation module is respectively connected to the communication module and the driving module, the communication module is respectively connected to an external baseboard management controller and the CPU, and the driving module is further connected to the CPU; Among them, the communication module integrates codes of at least two power communication protocols, and is used to provide communication functions of multiple power communication protocols for the CPU; The communication module is used to determine the currently available communication protocol among at least two power communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol; The calculation module is used to receive a voltage regulation instruction from the CPU during the communication process, generate a driving instruction according to the voltage regulation instruction, and send the driving instruction to the driving module; The driving module is used to receive the driving instruction, generate a modulation signal, and send the modulation signal to the power conversion circuit, so that the power conversion circuit adjusts the external input voltage according to the modulation signal and outputs it to the CPU to supply power to the CPU.

14. The master control chip according to claim 13, wherein, The communication module further includes a register, and the register is used to store at least two power communication protocols and the bit identifier corresponding to each power communication protocol.

15. The master control chip according to claim 13 or 14, characterized in that, The communication module further includes a plurality of pins and a switching switch, and the plurality of pins at least include a first pin and a second pin; A communication link is established between the first pin and the CPU, and is used to communicate with the main control chip according to the currently available communication protocol; A communication link is established between the second pin and the CPU, and is used to communicate with the main control chip according to other communication protocols, and the other communication protocol is a protocol other than the currently available communication protocol among at least two power communication protocols; The switching switch is used to disconnect or conduct the communication link.

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