Storage device and electronic system

Abstract

The invention discloses a storage device and an electronic system. The storage device comprises a storage controller and N memories, wherein N is a natural number; the storage controller is connected with the N memories, and each memory comprises a reserved space and a storage space for data storage; wherein in the running process of the memory, the memory controller detects whether a fault block exists in the storage space or not, if yes, whether the reserved space has enough unallocated space or not is judged, and if yes, a target space in the reserved space is used for replacing the fault block to serve as a data storage space. According to the invention, a storage scheme with both cost and reliability is provided.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a storage device and an electronic system. Background Art

[0002] With the development of electronic technology, the demand for memory reliability in various electronic products is increasing.

[0003] At present, when various electronic products are used, when it is detected that the memory device is faulty or at the end of its life, a new storage medium is often replaced and the data is moved to the new storage medium so that the electronic product can continue to operate. This results in a large waste of costs and resources. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide a storage device and an electronic system that overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect, a storage device is provided, comprising: A storage controller and N memories, where N is a natural number; The storage controller is connected to the N memories, and the memories include a reserved space and a storage space for data storage; Among them, during the operation of the memory, the storage controller detects whether there is a faulty block in the storage space. If so, it determines whether there is enough unallocated space in the reserved space. If so, the faulty block is replaced with the target space in the reserved space as the data storage space.

[0006] Optionally, if the storage controller detects that there is a faulty block in the storage space but the reserved space does not have sufficient unallocated space, it isolates the faulty block and feeds back storage capacity reduction information to a master control device connected to the storage device, wherein the storage capacity reduction information includes the available storage capacity of the memory after removing the capacity of the faulty block.

[0007] Optionally, the reserved space occupies 1 / 16 to 1 / 8 of the total storage capacity of the memory.

[0008] Optionally, the storage controller obtains the degree of wear of each interval in the memory, and allocates storage addresses of data in the memory according to an inverse correlation between data access frequency and the degree of wear.

[0009] Optionally, the storage device further includes: an open industry standard interconnection interface connected to the storage controller and used for communication between the storage controller and a main control component.

[0010] Optionally, the storage device also includes a cache module, and the storage controller also includes a cache controller, and the cache controller is connected to the cache module; wherein the cache controller synchronizes the data stored in the cache module with the cache data stored in the main control component based on the open industry standard interconnection interface.

[0011] Optionally, the N memories include: dynamic random access memory and non-volatile memory; based on the open industry standard interconnection interface, the main control component accesses the storage device in the order of the cache module, the dynamic random access memory and the non-volatile memory.

[0012] Optionally, the storage controller includes a balancing module; wherein the balancing module is connected to the non-volatile memory to evenly set the storage address of the non-volatile memory according to the usage of the storage area in the non-volatile memory.

[0013] Optionally, in the process of writing write data to the storage device, the write data is first written into the cache module; then the write data is stored in the dynamic random access memory and the non-volatile memory in sequence according to a preset algorithm; in the process of reading read data from the storage device, the cache data in the cache module is first queried, and if a hit is found, the read data is obtained from the cache module; if there is no hit, the data in the dynamic random access memory is queried again, and if a hit is found, the read data is obtained from the dynamic random access memory; if there is still no hit, the data in the non-volatile memory is queried again.

[0014] In a second aspect, an electronic system is provided, comprising: A main control component and a storage device as described in any one of the first aspects; The storage device communicates with the main control component via an open industry standard interconnect interface.

[0015] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages: The storage device and electronic system provided by the embodiment of the present invention are provided with a storage controller connected to N memories, and the memory is also provided with a reserved space and a storage space for data storage. During the operation of the memory, the storage controller is used to check whether there is a faulty block in the storage space. If there is a faulty block and there is enough space in the reserved space, the target space in the reserved space is enabled to replace the faulty block as the data storage space to ensure that the data storage space capacity of the memory is not affected by the faulty block, thereby avoiding the replacement of the memory caused by abnormalities in some storage addresses, and maintaining the reliable use of the storage device, effectively reducing the long-term use cost of the storage device.

[0016] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 The structure of the storage controller in the embodiment of the present invention is shown in FIG. Figure 1 ; Figure 2 The structure of the storage controller in the embodiment of the present invention is shown in FIG. Figure 2 ; Figure 3 Schematic diagram of the structure of an electronic system in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0019] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0020] See also Figure 1, an embodiment of the present application provides a storage device, including: a storage controller 1 and N memories 2, where N is a natural number. The storage controller 1 is connected to the N memories 2, and the memories 2 include reserved space and storage space for data storage. Wherein, during the operation of the memory 2, the storage controller 1 detects whether there is a fault block in its storage space. If so, it determines whether there is enough unallocated space in the reserved space. If so, the fault block is replaced with the target space in the reserved space as the data storage space.

[0021] It should be noted that the memory 2 may be a volatile memory or a non-volatile memory. The N memories 2 may be memories of the same type or memories of different types, which is not limited here.

[0022] The following is a detailed introduction to the structure and operation of the storage device.

[0023] In an optional implementation, the reserved space in the memory 2 may be set to account for 1 / 16 to 1 / 8 of the total storage capacity of the memory 2. This ensures that sufficient replacement space is provided for faulty blocks that occur during use, and also avoids excessive occupation of data storage space.

[0024] In the specific implementation process, the fault block in the storage space can be a damaged address segment space that has a sudden fault during operation, or it can be a failed address segment space that has reached the end of its life. The storage controller 1 detects whether there is a fault block in the storage space by writing and reading each address segment and detecting whether the read data matches the written data. If there is a mismatch exceeding a preset number of times, the address segment space is determined to be a fault block. After determining that there is a fault block, a target space with the same capacity as the fault block is allocated from the reserved space, and the address of the fault block is mapped to the target space, so as to replace the fault block with the target space to provide data storage space, thereby eliminating the need to replace the memory 2 and saving maintenance costs.

[0025] In an optional embodiment, if the storage controller 1 detects that there is a faulty block in the storage space of the memory 2, but there is not enough unallocated space in the reserved space, the faulty block is isolated and storage capacity reduction information is fed back to a main control device (such as a CPU or a motherboard chip) connected to the storage device. The storage capacity reduction information includes the available storage capacity of the memory 2 after removing the capacity of the faulty block.

[0026] Specifically, each time the storage controller 1 detects a faulty block, a target space of corresponding capacity will be allocated from the reserved space to replace the faulty block for data storage, which will result in less and less unallocated space remaining in the reserved space (that is, space in the reserved space that has not yet been allocated as a target space to replace the faulty block). In the case where a faulty block is detected, but there is not enough space in the reserved space to replace the faulty block, the faulty block can be isolated and no longer used, and the remaining space capacity of the memory 2 that can be used to store data after isolating the faulty block is determined, and then the storage capacity reduction information carrying the remaining capacity is fed back to the main control device, so that the main control device can adjust the system address space corresponding to the memory 2 in a timely manner, thereby ensuring that the storage device can continue to be used normally.

[0027] For example, assume that the storage space capacity of memory 2 is 8G, the reserved space is 1G, and the corresponding space capacity is recorded in the master device as 8G. When the storage controller 1 detects a 1G fault block, it allocates 1G of target space from the reserved space to map the address of the fault block, thereby replacing the fault block. When the storage controller subsequently detects a 1G fault block again, the reserved space does not have enough unallocated space, so the fault block is isolated and the remaining capacity of the memory 2 is fed back to the master device as 7G, ​​so that the system address space corresponding to the master device adjuster is 7G to ensure subsequent normal operation.

[0028] In an optional implementation, the storage controller 1 may be configured to obtain the degree of wear of each interval in the memory 2, and allocate the storage address of the data in the memory 2 according to the inverse correlation between the access frequency of the data and the degree of wear.

[0029] Specifically, based on historical access experience and historical access data, it is possible to determine which data is accessed more frequently by the master device, and store the data with higher access frequency in the address space with less wear in the memory 2. Among them, the address space can be allocated according to the predicted access frequency in an inverse relationship with the wear degree when the data is written, or the access frequency of the data already stored in the memory 2 can be monitored, and the storage address can be adjusted regularly or in a triggered manner according to the access frequency to meet the requirement of the inverse correlation between the access frequency and the wear degree. Among them, the wear degree of each address space in the memory 2 can be obtained by counting the cumulative number of accesses to each address space, and the more the number of accesses, the higher the wear degree.

[0030] In an optional embodiment, if Figure 2As shown, the storage controller may also include an open industry standard interconnect interface 3 (Compute Express Link, CXL) interface module, which can be used to connect processors, accelerators, memory buffers, intelligent network interfaces and storage devices, etc. The open industry standard interconnect interface 3 is connected to the storage controller 1, and is used for communication between the storage controller 1 and the main control component 201, and can transmit the access request issued by the main control component 201 to the storage controller 1.

[0031] In an optional embodiment, if Figure 2 As shown, the storage device may further include a cache module 4, and the corresponding storage controller 1 may further include a cache controller 11, which is connected to the cache module 4. The cache controller 11 synchronizes the cache module with the cache data stored in the main control component 201 based on the open industry standard interconnection interface 3.

[0032] Specifically, based on the protocol of the open industry standard interconnection interface 3 (e.g., its .cache protocol), the cache controller 11 manages the cache module 4, and can synchronize the data stored in the cache module 4 with the cache data in the main control component 201. When the main control component 201 is powered off, the data cached at all levels in the main control component 201 will be synchronized and flushed to the cache module 4 of the storage device in a timely manner to avoid data loss.

[0033] In an optional embodiment, if Figure 2 As shown, the N memories 2 connected to the storage controller 1 include: a dynamic random access memory 21 (DRAM) and a non-volatile memory 22 (NVM). Based on the open industry standard interconnection interface 3, the main control component 201 accesses the storage device in the order of the cache module 4, the dynamic random access memory 21, and the non-volatile memory 22. Since the dynamic random access memory 21 has the advantages of low cost and relatively fast access speed, it can effectively balance the cost and access speed as the next-level storage medium of the cache module 4. In addition, the dynamic random access memory 21, as the upper-level cache of the non-volatile memory 22, can also reduce the wear of the non-volatile memory 22 and improve the service life of the entire storage device. The non-volatile memory 22 has a low cost and a large capacity. As the final storage medium, it can effectively balance the data storage capacity and cost. Combining these three, accessing in the order of the cache module 4, the dynamic random access memory 21, and the non-volatile memory 22 can effectively balance the access speed, cost, capacity and service life.

[0034] Specifically, in the process of writing write data to the storage device, the write data is first written into the cache module 4; then the write data is sequentially stored in the dynamic random access memory 21 and the non-volatile memory 22 according to a preset algorithm. The preset algorithm can be that as long as the write data is written into the cache module 4, it is synchronously written into the dynamic random access memory 21 and the non-volatile memory 22 in sequence; or it can be that the write data is written into the cache module 4 and saved as cache data, and the next time there is data written into the cache module 4 and occupies the storage address space of the write data, the data is eliminated and stored in the dynamic random access memory 21, and similarly, when there is subsequent data written into the dynamic random access memory 21 and occupies the storage address space of the write data, the write data is eliminated and stored in the non-volatile memory 22. In this way, not only is the write data saved in the cache module 4 so that it can be quickly hit in the cache module 4 when the data is subsequently read, thereby improving the reading speed, but the write data is also saved in the dynamic random access memory 21 and the non-volatile memory 22 to prevent it from being replaced and updated by subsequent written data in the cache module 4. At the same time, it can also be read in the dynamic random access memory 21 and the non-volatile memory 22, thereby taking into account both access speed and data reliability.

[0035] In the process of reading read data from the storage device, the cache data in the cache module 4 is first queried. If a hit is found, the read data is obtained from the cache module; if no hit is found, the data in the dynamic random access memory 21 is queried. If a hit is found, the read data is obtained from the dynamic random access memory 21; if still no hit is found, the data in the non-volatile memory 22 is queried. If the read data is read from the dynamic random access memory 21 and the non-volatile memory 22, the read data can be returned and stored in the cache module 4 so that the next access can be faster. In this way, by first querying the data in the cache module 4 with a faster reading speed, the speed of data reading can be effectively improved.

[0036] In an optional embodiment, if Figure 2 As shown, the storage controller 1 may also be configured to include a data management module 12. Based on the protocol of the open industry standard interconnect interface 3 (such as its .Cache, .mem and .io protocols), the storage controller 1 can communicate with both volatile and non-volatile memories, wherein the data management module 12 can manage the data storage of the memory 2, and can also be responsible for the interaction of data between each memory 2 and between the memory 2 and the cache module 4, and can also manage the reserved space of the memory 2 (including setting the target space to replace the faulty block) and manage the address during data storage (including allocating the storage address of the data in the memory 2 according to the inverse correlation between the access frequency of the data and the degree of wear).

[0037] In an optional embodiment, if Figure 2As shown, the storage controller 1 may also be configured to include a balancing module 13. The balancing module 13 is connected to the non-volatile memory 22 to evenly set the storage address of the non-volatile memory 22 according to the usage of the storage area in the non-volatile memory 22. Specifically, the balancing module 13 stores a storage address mapping table of the non-volatile memory 22, which represents the mapping relationship between the logical address and the physical address. According to the query of the mapping table, the logical address of the access request can be mapped to the physical address of the non-volatile memory 22. The balancing module 13 records the usage of each physical area in the non-volatile memory 22 to evenly set the storage address mapping table, avoid excessive use of some storage blocks, resulting in consumption of the life of the storage blocks, and try to evenly set the physical address of the data storage to ensure balanced loss of the storage blocks.

[0038] In an optional embodiment, if Figure 2 As shown, the storage controller 1 may also include a memory interface module 14, which is used to connect and access N memories 2. For example, Figure 2 The memory interface module 14 is used to access the storage media of the dynamic random access memory 21 and the non-volatile memory 22 .

[0039] Based on the same inventive concept, the embodiment of the present application also provides an electronic system, such as Figure 3 As shown, including: The main control component 201 and the storage device 301 provided in the aforementioned embodiment.

[0040] The storage device 301 includes: a storage controller and N memories, where N is a natural number; The storage controller is connected to the N memories, and the memories include a reserved space and a storage space for data storage; wherein, during the operation of the memories, the storage controller detects whether there is a fault block in the storage space, and if so, determines whether there is enough unallocated space in the reserved space, and if so, replaces the fault block with a target space in the reserved space as the data storage space; The storage device 301 communicates with the main control component 201 via an open industry standard interconnect interface.

[0041] In an optional embodiment, based on the scalability and multi-port optional mechanism of open industry standard interconnect interface technology, the electronic system can be set up to include multiple main control components 201, and the storage device 301 is communicatively connected to the multiple main control components 201 based on the open industry standard interconnect interface, so that the multiple main control components share the storage device 301.

[0042] Since the storage device 301 included in the electronic system introduced in the embodiment of the present application is exactly the storage device introduced in the embodiment of the present application, the principle and structure of the storage device, and the connection method between the storage device and the main control component 201 have been described in detail above, so they will not be repeated here. Any electronic system including the storage device of the embodiment of the present application belongs to the scope of protection of the present invention.

[0043] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages: The storage device and electronic system provided by the embodiment of the present invention are provided with a storage controller connected to N memories, and the memory is also provided with a reserved space and a storage space for data storage. During the operation of the memory, the storage controller is used to check whether there is a faulty block in the storage space. If there is a faulty block and there is enough space in the reserved space, the target space in the reserved space is enabled to replace the faulty block as the data storage space to ensure that the data storage space capacity of the memory is not affected by the faulty block, thereby avoiding the replacement of the memory caused by abnormalities in some storage addresses, and maintaining the reliable use of the storage device, effectively reducing the long-term use cost of the storage device.

[0044] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the description of the above specific languages ​​is for disclosing the best mode of the present invention.

[0045] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0046] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof.

[0047] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the abstract and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying abstract and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0048] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present invention and to form different embodiments.

[0049] It should be noted that the above embodiments illustrate the present invention rather than limiting it. Any reference symbol between brackets should not be constructed as a limitation of the present invention. The word "comprising" does not exclude the presence of components or steps not listed in the present invention. The word "one" or "an" preceding a component does not exclude the presence of multiple such components. The present invention can be implemented by means of hardware including several different components and by means of appropriately programmed computers. In the embodiments in which several devices are listed, several of these devices can be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Claims

1. A storage device, characterized in that: include: A storage controller and N memories, where N is a natural number; The storage controller is connected to the N memories, and the memories include a reserved space and a storage space for data storage; Among them, during the operation of the memory, the storage controller detects whether there is a faulty block in the storage space. If so, it determines whether there is enough unallocated space in the reserved space. If so, the faulty block is replaced with the target space in the reserved space as the data storage space.

2. The storage device according to claim 1, wherein: If the storage controller detects that there is a faulty block in the storage space but the reserved space does not have sufficient unallocated space, it isolates the faulty block and feeds back storage capacity reduction information to a master control device connected to the storage device, wherein the storage capacity reduction information includes the available storage capacity of the memory after removing the capacity of the faulty block.

3. The storage device according to claim 1, wherein: The reserved space accounts for 1 / 16 to 1 / 8 of the total storage capacity of the memory.

4. The storage device according to claim 1, wherein: The storage controller obtains the degree of wear of each interval in the memory, and allocates a storage address of the data in the memory according to an inverse correlation between the access frequency of the data and the degree of wear.

5. The storage device according to claim 1, wherein: Also includes: An open industry standard interconnection interface is connected to the storage controller and is used for communication between the storage controller and a main control component.

6. The storage device according to any one of claims 1 to 4, characterized in that: The storage device also includes an open industry standard interconnect interface connected to the storage controller and used for communication between the storage controller and the main control component; The storage device further includes a cache module, and the storage controller further includes a cache controller, and the cache controller is connected to the cache module; Wherein, the cache controller synchronizes the data stored in the cache module with the cache data stored in the main control component based on the open industry standard interconnection interface.

7. The storage device according to claim 6, characterized in that: The N memories include: Dynamic random access memory and / or non-volatile memory; Based on the open industry standard interconnection interface, the main control component accesses the storage device in the order of the cache module, the dynamic random access memory, and the non-volatile memory.

8. The storage device according to claim 7, wherein: The storage controller includes a balancing module; The balancing module is connected to the non-volatile memory to evenly set the storage address of the non-volatile memory according to the usage of the storage area in the non-volatile memory.

9. The storage device according to claim 7, wherein: In the process of writing write data to the storage device, the write data is first written into the cache module; and then the write data is sequentially stored into the dynamic random access memory and the non-volatile memory according to a preset algorithm; In the process of reading read data from the storage device, the cache data in the cache module is queried first. If a hit is found, the read data is obtained from the cache module; if no hit is found, the data in the dynamic random access memory is queried again. If a hit is found, the read data is obtained from the dynamic random access memory; if still no hit is found, the data in the non-volatile memory is queried again.

10. An electronic system, characterized in that: include: Main control components and storage devices; The storage device comprises: a storage controller and N memories, where N is a natural number; The storage controller is connected to the N memories, and the memories include a reserved space and a storage space for data storage; wherein, during the operation of the memories, the storage controller detects whether there is a fault block in the storage space, and if so, determines whether there is enough unallocated space in the reserved space, and if so, replaces the fault block with a target space in the reserved space as the data storage space; The storage device communicates with the main control component via an open industry standard interconnect interface.

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