Program detection method and device

Abstract

The invention provides a program detection method and device, which can help a user to quickly complete the check of the program running in a weak memory environment, can improve the detection efficiency of the program, and can be applied to program detection. The method comprises the steps of receiving a program provided by a user, and obtaining a result of the program running in a weak memory environment according to query parameters and the program. Wherein the query parameter is used for indicating the maximum interval for reordering the two operations of the program.

Description

[0001] This application is a divisional application. The application number of the original application is: 202011608587.6, and the original application date is December 29, 2020. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of communications, and in particular to a program detection method and device. Background Art

[0003] The strong memory model and the weakly ordered memory model are two storage models. The strong memory model describes that each instruction implicitly has acquire and release semantics. The acquire semantics can be used to prevent the disorder of read-acquire and any subsequent read and write operations, and the release semantics can be used to prevent the disorder of write-release and any previous read and write operations. That is, the sequence of write operations performed by a core on the memory can be observed by other cores of the central processing unit (CPU) in the same order. The weak memory model describes that within an independent thread, any read and write operations on the memory can be exchanged with other read and write operations without changing the behavior of the thread.

[0004] Due to the lag of the software ecosystem of the weak memory model, programs developed based on the strong memory model platform may experience abnormal phenomena such as program crashes, restarts, or calculation errors after being ported to the weak memory model platform. Therefore, experienced program developers are required to repeatedly test and debug the program to analyze whether abnormalities will occur when the program runs on the weak memory model platform. However, the probability of reproducing the above-mentioned abnormal phenomena such as program crashes, restarts, or calculation errors is low. Due to the limitations of test cases and test environments, the cost of reproducing the problem is high, and the professional ability of testers is very high. Summary of the invention

[0005] The embodiments of the present application provide a program detection method and device, which can help users quickly complete the inspection of programs running on a weak memory model platform, thereby improving the detection efficiency of the program.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a program detection method is provided. The program detection method includes: receiving a program provided by a user, and obtaining a result of the program running in a weak memory environment according to a query parameter and the program. The query parameter is used to indicate a maximum interval between two operations of the program being reordered.

[0008] Based on the program detection method described in the first aspect, the program detection device receives the program provided by the user, and according to the query parameters and the program used to indicate the maximum interval between two operations of the program that are reordered, the result of the program running in a weak memory environment can be obtained. This can help the user quickly complete the inspection of the program running in a weak memory environment, improve the detection efficiency of the program, and has low requirements on the professional ability of the user.

[0009] In a possible design scheme, the above-mentioned obtaining the result of the program running in a weak memory environment based on the query parameters and the program may include: obtaining the result of the program running in a weak memory environment based on the query parameters, the interval between the first operation in the first thread of the program and the second operation in the first thread, and the interval between the third operation in the second thread of the program and the fourth operation in the second thread. Optionally, the first operation and the third operation may be a pair of read and write operations performed on the same variable, the second operation and the fourth operation may be a pair of read and write operations performed on the same variable, the first operation and the second operation may be operations performed on different variables, and the third operation and the fourth operation may be operations performed on different variables. In this way, the user does not need to test the program, which can improve the detection efficiency of the program.

[0010] In one possible design, the program detection method provided in the first aspect may also include: using memory read and write mode query rules to detect the first operation in the first thread of the program, the second operation in the first thread, the third operation in the second thread of the program, and the fourth operation in the second thread to obtain the result of the program running in a weak memory environment.

[0011] Optionally, the memory read / write pattern query rule can be determined based on the query parameters, and the memory read / write pattern query rule can be used to determine whether the first thread and the second thread overlap in time. In this way, if the program meets the memory read / write pattern query rule, the result is wrong, such as the problem of weak memory order; if the memory read / write pattern query rule is not met, the result is correct, such as the result of running correctly on a weak memory model platform, and the user does not need to test the program repeatedly, and can quickly obtain the result of the program running in a weak memory environment.

[0012] Optionally, the memory read-write mode query rule may include a read-read, write-write disorder query rule, and / or a read-write, write-read disorder query rule. In this way, the running result of a program including at least two threads, one thread including a read-read operation and another thread including a write-write operation in a weak memory environment can be checked, and / or the running result of a program including at least two threads, one thread including a read-write operation and another thread including a write-read operation in a weak memory environment can be checked.

[0013] In one possible design, the query parameter may be determined by the user, and the query parameter may include on-chip write operation latency. Optionally, the query parameter may also include cross-NUMA write operation latency and / or cross-NUMA read operation latency. In this way, the memory read / write mode query may be performed according to the query parameter input by the user.

[0014] In a possible design, the program detection method provided in the first aspect may further include: obtaining a value corresponding to a query parameter. The value corresponding to the query parameter may include a value corresponding to an intra-chip write operation delay. Optionally, the value corresponding to the query parameter may also include a value corresponding to a cross-NUMA write operation delay and / or a value corresponding to a cross-NUMA read operation delay.

[0015] Optionally, the weak memory environment may be an operating environment corresponding to an operating device of a non-uniform memory access architecture (NUMA).

[0016] In a possible design, the program detection method provided in the first aspect may further include: providing a result to the user. The result may include a modification suggestion. In this way, the user can manually modify the program according to the modification suggestion, thereby helping the user to quickly locate the location in the program that causes the program error, quickly complete the program modification, and improve the program modification efficiency.

[0017] Optionally, the result may include: correct. Alternatively, the result may include an error and / or a modification suggestion.

[0018] Optionally, the modification suggestion may include location information of the code to be modified, such as code line number and / or program file name, and the modification suggestion may be used by the program detection device to modify the program or by the user to manually modify the program.

[0019] In a possible design, the program detection method provided in the first aspect may further include: in response to the user's confirmation instruction, modifying the program according to the modification suggestion. In this way, the user can be directly helped to complete the modification of the program, further improving the modification efficiency of the program.

[0020] In a second aspect, a program detection device is provided. The program detection device includes: a receiving unit and an acquisition unit. The receiving unit is used to receive a program provided by a user; the acquisition unit is used to obtain a result of the program running in a weak memory environment according to a query parameter and the program. The query parameter is used to indicate the maximum interval between two operations of the program being reordered.

[0021] In a possible design, the acquisition unit is further used to obtain the result of the program running in the weak memory environment according to the query parameter, the interval between the first operation in the first thread of the program and the second operation in the first thread, and the interval between the third operation in the second thread of the program and the fourth operation in the second thread. Optionally, the first operation and the third operation are a pair of read and write operations performed on the same variable, the second operation and the fourth operation are a pair of read and write operations performed on the same variable, the first operation and the second operation are operations performed on different variables, and the third operation and the fourth operation are operations performed on different variables.

[0022] In one possible design, the acquisition unit is also used to adopt memory read and write mode query rules to detect the first operation in the first thread of the program, the second operation in the first thread, the third operation in the second thread of the program, and the fourth operation in the second thread to obtain the result of the program running in a weak memory environment.

[0023] Optionally, the memory read / write pattern query rule may be determined according to a query parameter, and the memory read / write pattern query rule may be used to determine whether the first thread and the second thread overlap in time.

[0024] In a possible design, the memory read-write mode query rule may include a read-read, write-write out-of-order query rule, and / or a read-write, write-read out-of-order query rule.

[0025] In one possible design, the query parameter may be determined by the user, and the query parameter may include on-chip write operation latency. Optionally, the query parameter may also include cross-NUMA write operation latency and / or cross-NUMA read operation latency. In this way, the memory read / write mode query may be performed according to the query parameter input by the user.

[0026] In a possible design, the acquisition unit is further used to acquire a value corresponding to the query parameter. The value corresponding to the query parameter may include a value corresponding to an intra-chip write operation delay. Optionally, the value corresponding to the query parameter may also include a value corresponding to a cross-NUMA write operation delay and / or a value corresponding to a cross-NUMA read operation delay.

[0027] Optionally, the weak memory environment may be an operating environment corresponding to an operating device of a non-uniform memory access architecture NUMA.

[0028] In a possible design, the program detection device described in the second aspect may further include: an output unit. The output unit is used to provide a result to the user. The result may include a modification suggestion.

[0029] Optionally, the result may include: correct. Alternatively, the result may include an error and / or a modification suggestion.

[0030] Optionally, the modification suggestion may include location information of the code to be modified, such as code line number and / or program file name, and the modification suggestion may be used by the program detection device to modify the program or by the user to manually modify the program.

[0031] In a possible design, the acquisition unit is further configured to modify the program according to the modification suggestion in response to a confirmation instruction from the user.

[0032] In one possible design, the program detection device may be placed in a cloud server.

[0033] It should be noted that the receiving unit and the output unit can be provided separately or integrated into one module, namely, a transceiver module. The present application does not specifically limit the specific implementation of the receiving unit and the output unit.

[0034] Optionally, the program detection apparatus described in the second aspect may further include a storage module, wherein the storage module stores a program or an instruction. When the acquisition unit executes the program or the instruction, the program detection apparatus may execute the program detection method described in any possible implementation manner of the first aspect.

[0035] It should be noted that the program detection device described in the second aspect can be a computer device, a server or a cloud server, or it can be a chip (system) or other parts or components that can be set in a computer device, a server or a cloud server, and this application does not limit this.

[0036] In addition, the technical effects of the program detection device described in the second aspect can refer to the technical effects of the program detection method described in the first aspect, and will not be repeated here.

[0037] In a third aspect, a program detection device is provided. The program detection device includes: a processor, the processor is coupled to a memory, and the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory, so that the program detection device performs the program detection method as described in any possible implementation of the first aspect.

[0038] In a possible design, the program detection device described in the third aspect may further include a transceiver. The transceiver may be a transceiver circuit or an input / output port. The transceiver may be used for the program detection device to communicate with other devices.

[0039] In the present application, the program detection device described in the third aspect may be a computer device, a server or a cloud server, or a chip or a chip system disposed inside a computer device, a server or a cloud server.

[0040] In addition, the technical effects of the program detection device described in the third aspect can refer to the technical effects of the program detection method described in any implementation method of the first aspect, and will not be repeated here.

[0041] In a fourth aspect, a chip system is provided, which has a weak memory environment. The chip system includes a processor and an input / output port. The processor is coupled to a memory containing instructions, and is used to control the chip system to implement the processing functions involved in any one of the implementation methods in the first aspect. The input / output port is used to implement the transceiver functions involved in any one of the implementation methods in the first aspect.

[0042] In one possible design, the chip system also includes a memory, which is used to store program instructions and data for implementing the functions involved in the first aspect.

[0043] The chip system may be composed of chips, or may include chips and other discrete devices.

[0044] In a fifth aspect, a computer-readable storage medium is provided, comprising: computer instructions are stored in the computer-readable storage medium; when the computer instructions are executed on a computer, the computer executes the program detection method as described in any possible implementation method of the first aspect.

[0045] In a sixth aspect, a computer program product comprising instructions is provided, including a computer program or instructions, which, when executed on a computer, enables the computer to execute a program detection method as described in any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Schematic diagram of the process of the program detection method provided in the embodiment of the present application Figure 1 ;

[0047] Figure 2 Application diagram of the program detection method provided in the embodiment of the present application Figure 1 ;

[0048] Figure 3 Schematic diagram of the process of the program detection method provided in the embodiment of the present application Figure 2 ;

[0049] Figure 4 A schematic diagram of the structure of the CPU provided in the embodiment of the present application Figure 1;

[0050] Figure 5 Interface diagram of the program detection device provided in the embodiment of the present application Figure 1 ;

[0051] Figure 6 An example diagram of a program provided for an embodiment of the present application;

[0052] Figure 7 Interface diagram of the program detection device provided in the embodiment of the present application Figure 2 ;

[0053] Figure 8 Analysis example of the program provided for the embodiment of the present application Figure 1 ;

[0054] Fig. 9 Analysis example of the program provided for the embodiment of the present application Figure 2 ;

[0055] Fig.10 Application diagram of the program detection method provided in the embodiment of the present application Figure 2 ;

[0056] Fig.11 A schematic diagram of the structure of the program detection device provided in the embodiment of the present application Figure 1 ;

[0057] Fig.12 A schematic diagram of the structure of the program detection device provided in the embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0058] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0059] The present application will present various aspects, embodiments or features around a system that may include multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in conjunction with the figures. In addition, combinations of these schemes may also be used.

[0060] In addition, in the embodiments of the present application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0061] In the embodiments of the present application, "operation instruction" and "operation" may be used interchangeably. It should be noted that when the distinction between them is not emphasized, the meanings they intend to express are the same. "Statement", "program statement" and "code" may be used interchangeably. It should be noted that when the distinction between them is not emphasized, the meanings they intend to express are the same.

[0062] In the description of this application, unless otherwise specified, the meaning of "plurality" refers to two or more. "And / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0063] First, to facilitate understanding, relevant terms and concepts that may be involved in the embodiments of the present application are introduced below.

[0064] (1) Total store ordering (TSO) consistency model

[0065] The TSO consistency model describes that multiple cores in a central processing unit (CPU) have only one global order for memory write operations. The TSO consistency model belongs to a strong memory model.

[0066] The present application embodiment provides a program detection method, which can be used to detect the correctness of a program running on a weak memory model platform, such as the correctness of a program running on an advanced reduced instruction set machine (Advanced RISC Machine, ARM) platform. The program detection method can be used alone or integrated with third-party software. The program detection device provided by the present application embodiment can be a computer device, a server or a cloud server, etc., or it can be a chip or other component with a program detection function applied to a computer device, a server or a cloud server.

[0067] The following will be combined Figure 1-Figure 10 The program detection method provided in the embodiment of the present application is specifically described.

[0068] Figure 1 Schematic diagram of the process of the program detection method provided in the embodiment of the present application Figure 1 The program detection method provided in the embodiment of the present application can be used to check software developed in a compiled language, such as C language or C++ language.

[0069] like Figure 1 As shown, the program detection method includes the following steps:

[0070] S101, receiving a program provided by a user.

[0071] Figure 2 Application diagram of the program detection method provided in the embodiment of the present application Figure 1 .

[0072] like Figure 2 As shown, the program detection device receives a program provided by a user. Taking C / C++ software as an example, the program may be a C / C++ software source code. The program may include one or more threads.

[0073] Optionally, the program detection method provided in the embodiment of the present application may include: using a compiler to convert the program provided by the user into an intermediate representation (IR).

[0074] For example, taking the Clang / LLVM compiler as an example, assuming that the program provided by the user is XXX.c, the program is compiled by the Clang / LLVM compiler to generate intermediate code, for example, clang-emit-llvm-cg XXX.co XXX.bc. Optionally, the intermediate file XXX.bc of the program is analyzed by the program detection device Weakmemcheck.

[0075] Combination Figure 3 (a) or Figure 3 In (b), the program provided by the user is compiled by the compiler to generate an intermediate code IR. The program detection device analyzes the intermediate code, which can realize static analysis of the source code. There is no need to run the program provided by the user, so there is no intrusion on the user's software, which can ensure the security of the user's program and easy operation.

[0076] S102, obtaining a result of the program running in a weak memory environment according to the query parameters and the program.

[0077] Optionally, the weak memory environment is an operating environment corresponding to an operating device of a non-uniform memory access architecture (NUMA).

[0078] Exemplarily, the weak memory environment may be an operating environment of a weak memory model device, or a weak memory model platform, etc.

[0079] Exemplarily, the query parameter is used to indicate the maximum interval between two operations of the program that are reordered. Optionally, the query parameter may include the type of the query parameter and / or the value corresponding to the query parameter.

[0080] In some embodiments, the type of query parameter may include an intra-chip write operation delay. Exemplarily, the intra-chip write operation delay may be used to indicate a maximum interval between reordering of two store instructions in a chip.

[0081] For example, a memory instruction can be used to save data in a register to a memory, and the on-chip write operation latency can be used to detect whether reordering occurs between two or more storage instructions in a NUMA node. Figure 4 Detailed description of .

[0082] Optionally, the type of query parameter may also include cross-NUMA write operation latency and / or cross-NUMA read operation latency. Exemplarily, the cross-NUMA write operation latency may be used to indicate the maximum interval between reordering of two store instructions across NUMA nodes, and the cross-NUMA read operation latency may be used to indicate the maximum interval between reordering of two load instructions across NUMA nodes, wherein the cross-NUMA node instruction refers to an instruction for a NUMA node to access the memory of another NUMA node.

[0083] For example, a load instruction can be used to read data from a memory and put it into a register. The cross-NUMA write operation latency can be used to detect whether reordering will occur between two or more storage instructions between two or more NUMA nodes. The cross-NUMA read operation latency can be used to detect whether reordering will occur between two or more load instructions between two or more NUMA nodes. For cross-NUMA write operation latency and cross-NUMA read operation latency, please refer to the following description. Figure 4 Detailed description of .

[0084] In some embodiments, the value corresponding to the query parameter may include a value corresponding to an on-chip write operation latency.

[0085] Exemplarily, assuming that the value corresponding to the on-chip write operation delay is set to 8, the maximum interval between two storage instructions that are reordered is 8 memory operation instructions. That is, if the interval between two storage instructions is less than or equal to 8 memory operation instructions, it is considered that the two storage instructions will be reordered; if the interval between two storage instructions is greater than 8 memory operation instructions, it is considered that the two storage instructions will not be reordered. The memory operation instructions may include: store instructions and / or load instructions.

[0086] Optionally, the numerical value corresponding to the query parameter may also include a value corresponding to a cross-NUMA write operation delay and / or a value corresponding to a cross-NUMA read operation delay.

[0087] For example, assuming that the value corresponding to the cross-NUMA write operation delay is set to 8, the maximum interval between two storage instructions for reordering is 8 memory operation instructions. In other words, if the interval between two storage instructions is less than or equal to 8 memory operation instructions, it is considered that the two storage instructions will be reordered; if the interval between two storage instructions is greater than 8 memory operation instructions, it is considered that the two storage instructions will not be reordered.

[0088] Similarly, assuming that the value corresponding to the cross-NUMA read operation latency is set to 8, the maximum interval between two load instructions for reordering is 8 memory operation instructions. In other words, if the interval between two load instructions is less than or equal to 8 memory operation instructions, it is considered that the two load instructions will not be reordered; if the interval between two load instructions exceeds 8 memory operation instructions, it is considered that the two load instructions will not be reordered.

[0089] Optionally, the type of the query parameter may include an intra-chip read operation delay, and the value corresponding to the query parameter may include a value corresponding to the intra-chip read operation delay. Exemplarily, the intra-chip read operation delay may be used to indicate the maximum interval between two load instructions that are reordered, and the intra-chip read operation delay may be used to detect whether reordering will occur between two or more load instructions in a NUMA node. The specific implementation of the intra-chip read operation delay is similar to the above-mentioned intra-chip write operation delay, and will not be repeated here.

[0090] It should be noted that, taking the example of a program including memory operation instruction 1 and memory operation instruction 2, reordering may refer to a change in the execution order of memory operation instruction 1 and memory operation instruction 2. For example, the order recorded in the code of the program file is that memory operation instruction 1 is executed before memory operation instruction 2. If the program is run in a weak memory environment, due to the characteristics of the weak memory environment, memory operation instruction 2 is executed first and then memory operation instruction 1.

[0091] In some embodiments, a memory read / write mode query may be performed based on query parameters. The query parameters are used to describe the memory read / write delays of different cores of the CPU hardware on-chip and off-chip, and to construct a memory read / write mode query rule.

[0092] Optionally, the query parameter may be determined according to the structure of the CPU.

[0093] Figure 4 A schematic diagram of the structure of the CPU provided in the embodiment of the present application Figure 1 .

[0094] like Figure 4As shown, the CPU includes two memories, memory 0 (memory0) and memory 1 (memory1), and the two memories correspond to cores and caches respectively. Memory0 corresponds to core0, core1, cache cache0 and cache1, and there is a corresponding storage cache (Store Buffer) between core core0 and cache cache0, and there is a corresponding storage cache (Store Buffer) between core core1 and cache cache1. Memory1 corresponds to core2, core3, cache2, and cache3, and there is a corresponding storage cache (Store Buffer) between core core2 and cache cache2, and there is a corresponding storage cache (Store Buffer) between core core3 and cache cache3. Optionally, there is a cross-NUMA load cache (NUMA Load Buffer) and / or a cross-NUMA storage cache (NUMA Store Buffer) between memory 0 (memory0) and memory 1 (memory1). For example, core0 and core1 can read memory1 through the cross-NUMA mount cache, and core0 and core1 can write to memory1 through the cross-NUMA storage cache. Similarly, core2 and core3 can read memory0 through the cross-NUMA mount cache, and core2 and core3 can write to memory0 through the cross-NUMA storage cache.

[0095] Combination Figure 4 , the architecture including memory0, core0, core1, cache0 and cache1, and the corresponding Store Buffer can be called NUMA node 0, and the read operation of core0 or core1 inside NUMA node 0 to the memory (memory0) or cache (cache0 and cache1, and the corresponding Store Buffer) inside NUMA node 0 is called an intra-chip read operation. For example, the read operation of core0 to memory0 is called an intra-chip read operation. The write operation of core0 or core1 inside NUMA node 0 to the memory (memory0) or cache (cache0 and cache1, and the corresponding Store Buffer) inside NUMA node 0 is called an intra-chip write operation. For example, the write operation of core0 to memory0 is called an intra-chip write operation.

[0096] Similarly, the architecture including memory1, core2, core3, cache2, cache3, and the corresponding Store Buffer can be called NUMA node 1, and the read operation of core2 or core3 inside NUMA node 1 to the memory (memory1) or cache (cache2, cache3, and the corresponding Store Buffer) inside NUMA node 1 is called an intra-chip read operation. For example, the read operation of core2 to memory1 is called an intra-chip read operation. The write operation of core2 or core3 inside NUMA node 1 to the memory (memory1) or cache (cache2, cache3, and the corresponding Store Buffer) inside NUMA node 1 is called an intra-chip write operation. For example, the write operation of core2 to memory1 is called an intra-chip write operation.

[0097] Exemplarily, the memory operation between NUMA node 0 and NUMA node 1 is referred to as a cross-NUMA memory operation, and the memory operation includes a read operation and / or a write operation. For example, the read operation of core0 in NUMA node 0 on memory1 in NUMA node 1 is referred to as a cross-NUMA read operation, and the write operation of core0 in NUMA node 0 on memory1 in NUMA node 1 is referred to as a cross-NUMA write operation. Similarly, the read operation of core2 in NUMA node 1 on memory0 in NUMA node 0 is referred to as a cross-NUMA read operation, and the write operation of core2 in NUMA node 1 on memory0 in NUMA node 0 is referred to as a cross-NUMA write operation, which are not listed here one by one.

[0098] For example, in combination Figure 4 , if the CPU includes a storage cache (Store Buffer), it can be determined to use the on-chip write operation delay and / or the value corresponding to the on-chip write operation delay. If the CPU includes a cross-NUMA load cache (NUMA Load Buffer), it can be determined to use the cross-NUMA write operation delay and / or the value corresponding to the cross-NUMA write operation delay. If the CPU includes a cross-NUMA storage cache (NUMA Store Buffer), it can be determined to use the cross-NUMA read operation delay and / or the value corresponding to the cross-NUMA read operation delay. Optionally, if the CPU includes a load cache (Load Buffer), it can be determined to use the on-chip read operation delay and / or the value corresponding to the on-chip read operation delay. Among them, there can be a corresponding load cache (LoadBuffer) between core core0 and cache cache0. Similarly, there can be corresponding load caches ( Figure 4 not shown).

[0099] In some embodiments, the query parameters may be determined by a program detection device.

[0100] Exemplarily, the program detection apparatus may determine the type of query parameter, for example, using intra-chip write operation delay, or using cross-NUMA write operation delay and / or cross-NUMA read operation delay.

[0101] Exemplarily, the program detection device may determine a value corresponding to the query parameter. For example, the program detection device obtains the value corresponding to the query parameter according to the test set measurement, such as the program detection device may determine a value corresponding to the intra-chip write operation delay, and may also determine a value corresponding to the cross-NUMA write operation delay and / or a value corresponding to the cross-NUMA read operation delay.

[0102] In some embodiments, the query parameters may be user-determined.

[0103] Combination Figure 2 ,The program detection device can analyze the program according to the query parameters determined by the user, and obtain the result that the program is running in a weak memory environment.

[0104] Optionally, the user can determine the type of query parameter.

[0105] Exemplarily, the user may input query parameters in the display interface of the program detection device. Figure 5 Interface diagram of the program detection device provided in the embodiment of the present application Figure 1 . Combined Figure 5 In (a), the user can enter the instruction corresponding to the query parameter in the area for inputting query parameters on the display interface. For example, the instruction StoreBuffer corresponding to the intra-chip write operation delay can be entered. Optionally, the instruction NUMAStoreSize corresponding to the cross-NUMA write operation delay and / or the instruction NUMALoadSize corresponding to the cross-NUMA read operation delay can also be entered.

[0106] Alternatively, illustratively, the display interface of the program detection device may include a selection box for on-chip write operation delay, and may also include a selection box for cross-NUMA write operation delay and / or a selection box for cross-NUMA read operation delay. Exemplarily, the user may determine the type of query parameter to be used by checking the selection box corresponding to the type of query parameter. Figure 5 In (b), the user can check the box corresponding to the intra-chip write operation delay to determine the use of intra-chip write operation delay. Similarly, the user can check the box corresponding to the cross-NUMA write operation delay to determine the use of cross-NUMA write operation delay. If the cross-NUMA read operation delay is not used, the check box corresponding to the cross-NUMA read operation delay can be left unchanged.

[0107] Optionally, the user may determine a value corresponding to the query parameter.

[0108] Combination Figure 5 (a) or Figure 5 In (b), the user can enter a corresponding value in the area for inputting a numerical value corresponding to the type of each query parameter. For example, the user can enter 8 in the area for inputting a numerical value corresponding to intra-chip write operation delay. Similarly, 8 can be entered in the area for inputting a numerical value corresponding to cross-NUMA write operation delay, and 8 can be entered in the area for inputting a numerical value corresponding to cross-NUMA read operation delay.

[0109] It should be noted that the above is only an example provided by the embodiment of the present application, and the embodiment of the present application does not limit how the query parameter is determined. For example, the type of the query parameter may be determined by the program detection device, and the value corresponding to the query parameter may be determined by the user. Alternatively, the type of the query parameter is determined by the user, and the value of the query parameter is determined by the program detection device. Alternatively, after the program detection device determines the type of the query parameter and / or the value corresponding to the query parameter, the user can modify the type of the query parameter and / or the value corresponding to the query parameter.

[0110] In a possible design, the program detection method provided in the embodiment of the present application may also include: obtaining a numerical value corresponding to the query parameter.

[0111] Optionally, the numerical value corresponding to the query parameter may be preset, and / or the numerical value corresponding to the query parameter may be provided by the user through an input numerical value area corresponding to the type of the query parameter in the display interface.

[0112] In one possible design, the above S102 may include: obtaining the result of the program running in a weak memory environment based on query parameters, the interval between the first operation in the first thread of the program and the second operation in the first thread, and the interval between the third operation in the second thread of the program and the fourth operation in the second thread.

[0113] Optionally, the first operation and the third operation may be a pair of read and write operations performed on the same variable, the second operation and the fourth operation may be a pair of read and write operations performed on the same variable, the first operation and the second operation may be operations performed on different variables, and the third operation and the fourth operation may be operations performed on different variables. For example, the variable may be a shared variable. A pair of operations may be: the first operation is a read operation on the first variable, and the third operation is a write operation on the first variable; or, the first operation is a write operation on the first variable, and the third operation is a read operation on the first variable. Similarly, the second operation is a read operation on the second variable, and the fourth operation is a write operation on the second variable; or, the second operation is a write operation on the second variable, and the fourth operation is a read operation on the second variable. The first variable may include a global variable, a shared variable, etc., and the second variable may include a global variable, a shared variable, etc.

[0114] Figure 6 An example diagram of a program provided in an embodiment of the present application.

[0115] like Figure 6 As shown, the program includes the first thread thread1 in line 14 and the second thread thread2 in line 21. The interval between the write operation on the variable population in thread1 (line 17) and the write operation on the variable syn_flag in thread1 (line 18) can be calculated. The interval between the read operation on the variable syn_flag in thread2 (line 23) and the read operation on the variable population in thread2 (line 24) can be calculated. The result of the program running in a weak memory environment is obtained based on the query parameters and the two intervals.

[0116] In one possible design, the program detection method provided in the embodiment of the present application may also include: using memory read and write mode query rules to detect the first operation in the first thread of the program, the second operation in the first thread, the third operation in the second thread of the program, and the fourth operation in the second thread to obtain the result of the program running in a weak memory environment.

[0117] For example, the specific implementations of the first operation, the second operation, the third operation, and the fourth operation may refer to the above-mentioned specific implementations, which will not be described in detail here.

[0118] Optionally, the memory read / write pattern query rule may be determined according to a query parameter, and the memory read / write pattern query rule may be used to determine whether the first thread and the second thread overlap in time.

[0119] Combination Figure 6 , you can use the memory read and write mode to query the rule pair Figure 6Thread 1 and thread 2 in the program shown are tested to obtain the result that the program runs in a weak memory environment.

[0120] Exemplarily, the memory read-write mode query rule may include a read-read, write-write out-of-order query rule, and / or a read-write, write-read out-of-order query rule.

[0121] Exemplarily, the read-read, write-write out-of-order query rule may include one or more of the following conditions: the first operation instruction and the second operation instruction are two adjacent operation instructions in the first thread, the first operation instruction is a write operation instruction for the first variable, the second operation instruction is a write operation instruction for the second variable, the third operation instruction and the fourth operation instruction are two adjacent operation instructions in the second thread, the third operation instruction is a read operation instruction for the first variable, and the fourth operation instruction is a read operation instruction for the second variable; the first operation instruction and the third operation instruction are in a competitive relationship, and the second operation instruction and the fourth operation instruction are in a competitive relationship; the interval between the first operation instruction and the second operation instruction is less than the sum of the value corresponding to the intra-chip write operation delay and the value corresponding to the cross-NUMA write operation delay; and the interval between the third operation instruction and the fourth operation instruction is less than the value corresponding to the cross-NUMA read operation delay. In this way, the read-read, write-write out-of-order query rule can be used to check the running results of a program including at least two threads, one thread including a read-read operation and the other thread including a write-write operation in a weak memory environment.

[0122] Exemplarily, the read-write and write-read out-of-order query rules may include one or more of the following conditions: the fifth operation instruction and the sixth operation instruction are two adjacent operation instructions in the first thread, the fifth operation instruction is a write operation instruction for the third variable, and the sixth operation instruction is a read operation instruction for the fourth variable, and the seventh operation instruction and the eighth operation instruction are two adjacent operation instructions in the second thread, the seventh operation instruction is a read operation instruction for the third variable, and the eighth operation instruction is a write operation instruction for the fourth variable; the fifth operation instruction and the seventh operation instruction are in a competing relationship, and the sixth operation instruction and the eighth operation instruction are in a competing relationship; the interval between the fifth operation instruction and the sixth operation instruction is smaller than the sum of the value corresponding to the on-chip write operation delay, the value corresponding to the cross-NUMA write operation delay, and the value corresponding to the cross-NUMA read operation delay, and the interval between the third operation instruction and the eighth operation instruction is smaller than the sum of the value corresponding to the on-chip write operation delay, the value corresponding to the cross-NUMA write operation delay, and the value corresponding to the cross-NUMA read operation delay. In this way, read-write and write-read out-of-order query rules may be used to check the running results of a program including at least two threads, one thread including read-write operations and the other thread including write-read operations in a weak memory environment.

[0123] Specifically, the competition relationship may be that the execution order of the two operation instructions may affect the execution result. The third variable may include a global variable, a shared variable, etc., and the fourth variable may include a global variable, a shared variable, etc.

[0124] Program statements that satisfy the above memory read / write pattern query rules may be determined as dangerous statements that may cause incorrect results due to disordered instructions in a weak memory environment.

[0125] In this way, if the program meets the memory read-write mode query rules, the result is wrong, such as it is easy to produce weak memory order problems; if it does not meet the memory read-write mode query rules, the result is correct. If the result is correct when running on a weak memory model platform, the user does not need to test the program repeatedly, and can quickly obtain the result of the program running in a weak memory environment.

[0126] In a possible design, the program detection method provided in the embodiment of the present application may further include: providing a result to the user. Optionally, the result may include: correct. Alternatively, the result may include an error and / or a modification suggestion.

[0127] For example, a correct answer can indicate that the program can run correctly in a weak memory environment, and an error can indicate that the program will crash, exit, or have errors in program calculation results when running in a weak memory environment. The modification suggestion can include the location information of the code that needs to be modified, such as the code line number and / or the program file name. The modification suggestion can be used by the program detection device to modify the program or by the user to manually modify the program so that the program runs correctly in a weak memory environment. In this way, the user can quickly locate the location in the program that causes the program error, quickly complete the program modification, and improve the efficiency of program modification.

[0128] Optionally, if the result is correct, the test result can be displayed to the user through the display interface. If the result is wrong, the test result can be displayed to the user through the display interface, and / or modification suggestions can be displayed.

[0129] Figure 7 Interface diagram of the program detection device provided in the embodiment of the present application Figure 2 .like Figure 7 As shown, if the result is an error, the result can be displayed as an error, the corresponding program file name, and the code line number of the error statement, etc. on the display interface.

[0130] In one possible design, the program detection method provided in the embodiment of the present application may also include: in response to a confirmation instruction of the user, modifying the program according to the modification suggestion.

[0131] Combination Figure 7, the user selects the area to be repaired in the display interface, and the program detection device can modify the program according to the modification suggestion in response to the user's confirmation instruction. Alternatively, after the user selects the area not to be repaired in the display interface, the program can be manually modified according to the modification suggestion. In this way, the user can be directly helped to complete the modification of the program, further improving the efficiency of program modification.

[0132] based on Figure 1 The program detection method described above is a program detection device that receives a program provided by a user and can obtain the result of the program running in a weak memory environment based on query parameters and the program. This can help the user quickly complete the inspection of the program running in a weak memory environment, improve the detection efficiency of the program, and has low requirements on the user's professional ability.

[0133] In some embodiments, in combination Figure 3 (a) or Figure 3 In (b), the program checking method provided in the embodiment of the present application may further include the following steps 1 to 8. The following is an example of a program including a first thread and a second thread.

[0134] Step 1: Analyze the alias relationship of all variables in the multiple variables included in the program.

[0135] Combination Figure 6 and Figure 8 ,analyze Figure 6 The alias relationship of all variables in the program shown in Figure 8 The alias relationships shown are {Beijing.Population Alias ​​my_city->population}, and {Beijing.sync_flag Alias ​​my_city->sync_flag}.

[0136] Step 2: Perform variable dependency analysis on the program.

[0137] Exemplarily, the function relationship and variable dependency in the program provided by the user are analyzed, and the related thread relationship diagram and function call relationship diagram are constructed. The multithreading related application programming interface (API) used in the program is analyzed, and a thread data structure based on thread call context and function call context is constructed to distinguish the contexts of different thread operations and analyze variable dependencies. Among them, the multithreading related API may include thread related functions, such as pthread_create, pthread_mutex_lock, etc.

[0138] Combination Figure 6 and Figure 8 ,right Figure 6The program shown in the figure performs variable dependency analysis and obtains the following Figure 8 The main function main (including its functions and instructions), the first thread thread1 (including its functions and instructions) and the second thread thread2 (including its functions and instructions) are shown.

[0139] In this way, by decomposing the program, the function call context of the first thread and the function call context of the second thread can be sorted out, and a thread analysis method based on the thread call context and the function call context can be implemented.

[0140] Step three, analyze the first variable in the program.

[0141] Exemplarily, one or more first variables in the program are analyzed, and the thread call context and function call context accessed by each of the one or more first variables are distinguished. The first variable may be a variable included in both the first thread and the second thread, and the first variable may include a shared variable, a global variable, etc. In this way, a shared variable access point identification method based on a thread call context and a function call context may be implemented. Exemplarily, the search for shared variables may be completed based on an alias analysis algorithm to improve efficiency, and context coding technology may be used to analyze shared variables in the program to improve calculation accuracy.

[0142] Combination Figure 6 and Figure 8 ,right Figure 6 The program shown in the figure performs shared variable analysis and obtains the following Figure 8 The variable search results shown are my_city->population: {line 17, 24, 31}, my_city->sync_flag: {line 18, 23, 30}.

[0143] Step 4: Analyze the lock variables in the program.

[0144] Exemplarily, whether any statement in the program uses a lock variable is analyzed. One or more mutex lock variables used by both the first thread and the second thread are analyzed, and the thread call context and function call context of each of the one or more mutex lock variables are distinguished. Context encoding technology can be used to analyze the lock variables in the program to improve calculation accuracy.

[0145] Combination Figure 6 and Figure 8 ,right Figure 6 The program shown performs lock variable analysis, because Figure 6 The program shown does not include a lock variable, so Figure 8 The analysis results for lock variables are not included.

[0146] Step five: analyzing the possibility of parallel occurrence of the basic blocks of the program including the first variable.

[0147] Exemplarily, a static vector time algorithm can be used to analyze the possibility of parallel occurrence (may happen in parallel, MHP) of each statement in each basic block (BB) of the program including the first variable. A vector timestamp is constructed for the basic block of the program including the read operation or the write operation of the first variable, and the relative logical time of the execution of this basic block of the program in the program or the thread is simulated, so that a parallel analysis method based on the thread call context and the function call context of the whole program can be implemented with the basic block of the program as the granularity.

[0148] Combination Figure 6 and Figure 8 ,right Figure 6 The MHP analysis was performed using the procedure shown in the figure. Figure 8 The vector timestamp construction result of the first thread thread1 and the vector timestamp construction result of the second thread thread2 are shown. The statement execution time of thread1 and the statement execution time of thread2 overlap, and the statements of thread1 and thread2 may be executed concurrently.

[0149] Fig. 9 Analysis example of the program provided for the embodiment of the present application Figure 2 . Fig. 9 For Figure 6 The analysis results of the program shown (such as the file name weekConsistency.c).

[0150] like Fig. 9 As shown, Note 1: ST means Static Thread. Note 2: We precisely record the call string of each variable. Note 3: In the call string types such as A(b)->C(d), A represents the caller, and b represents the call instruction. Note 4: A(b)->C means that A calls C by instruction b.

[0151] Use the above steps for five pairs Figure 6 By analyzing the program shown (e.g., the file name is weekConsistency.c), the following information can be obtained: the group includes: the write operation of the global variable population is in thread1 (line 17 in the source code weekConsistency.c), and the read operation of the global variable population is in thread2 (line 24 in the source code weekConsistency.c); the group includes: the write operation of the global variable syrn_flag is in thread1 (line 18 in the source code weekConsistency.c), and the read operation of the global variable syrn_flag is in thread2 (line 23 in the source code weekConsistency.c). Among them, the time interval between the statement on line 17 of thread1 and the statement on line 18 of thread1, and the time interval between the statement on line 23 of thread2 and the statement on line 24 of thread2 overlap, and the statements of thread1 and thread2 may be executed concurrently.

[0152] It should be noted that the above steps 3 to 5 are methods for analyzing the inside of a single thread, and the above steps 3 to 5 can be performed on the first thread and the second thread included in the program respectively. The present application does not limit the specific implementation method. For example, the above steps 3 to 5 can be performed on the first thread first, and then on the second thread. Alternatively, after performing the above step 3 on the first thread, the above step 3 is performed on the second thread. Similarly, after performing the above step 4 on the first thread, the above step 4 is performed on the second thread.

[0153] It should be noted that the present embodiment does not limit the order of the above steps 3 to 5. Figure 3 In (b), step 3, step 4 and step 5 may be in a parallel relationship, and the execution order of step 3, step 4 and step 5 does not affect the corresponding execution results of each step.

[0154] Step six, query the memory read and write mode of the program.

[0155] Regarding the specific implementation method of step six, you can refer to the above-mentioned memory read and write mode query rules to detect the first operation in the first thread of the program, the second operation in the first thread, the third operation in the second thread of the program, and the fourth operation in the second thread to obtain a specific description of the result of the program running in a weak memory environment, which will not be repeated here.

[0156] For example, in combination Figure 3In (b), according to the results of the above steps 3 to 5, the statements in the program can be queried to obtain a first statement, where the first statement includes read and write operations on the same variable, and the read and write operations of the variable are not write-protected, and the read and write operations of the variable may be executed concurrently by the first thread and the second thread at the same time, and the read and write operations of the variable may constitute a competitive relationship.

[0157] Combination Figure 6 and Figure 8 ,right Figure 6 The program shown performs memory read and write mode query. Figure 6 The program shown does not contain any dangerous statements, so Figure 8 The results shown in can include correct.

[0158] Step 7: Get the result of the program running in a weak memory environment.

[0159] Exemplarily, the first statement is marked as a dangerous statement, which may also be referred to as a dangerous code, and a modification suggestion may be determined based on the dangerous code and the operation type included in the dangerous code. The modification suggestion may include the code line number and / or program file name of the dangerous code, and the operation type may include a write operation or a read operation.

[0160] Step 8: Provide the results to the user.

[0161] Optionally, the result may include: correct. Alternatively, the result may include an error and / or a modification suggestion. The specific implementation of S706 may refer to the above related description, which will not be repeated here.

[0162] Optionally, the font color of the dangerous code may be converted to a color different from the font color of other codes in the program, and displayed to the user through a display interface.

[0163] Fig.10 Application diagram of the program detection method provided in the embodiment of the present application Figure 2 .like Fig.10 As shown, assuming that the program A provided by the user is a program running on a strong memory model platform, the program detection device provided in the embodiment of the present application uses the program detection method provided in the embodiment of the present application to detect program A, and the result obtained is an error. The user manually or the program detection device automatically modifies program A, such as by inserting a memory shielding instruction to fix the existing problem. After being compiled by the compiler, the obtained program A' can run correctly on a weak memory model platform, which can improve the efficiency of program detection and modification.

[0164] based on Figure 3 (a) or Figure 3The program detection method shown in (b) can statically analyze the read and write operations and relative timing relationships of global variables in the program provided by the user, determine whether there will be problems when the program runs in a weak memory environment, obtain the location of the problematic code, and help users perform automatic or manual repairs, thereby improving the detection and repair efficiency of the program.

[0165] Combination of the above Figure 1-Figure 10 The program detection method provided in the embodiment of the present application is described in detail. Figure 11-Figure 12 The program detection device provided in the embodiment of the present application is described in detail.

[0166] Fig.11 This is a schematic diagram of the structure of the program detection device provided in the embodiment of the present application. Figure 1 The program detection device can be used to perform Figure 1 The function of the program detection device in the program detection method shown in FIG. Fig.11 Only the main components of the program detection device are shown.

[0167] like Fig.11 As shown, the program detection device 1100 includes: a receiving unit 1101 and an acquisition unit 1102. The receiving unit 1101 is used to receive a program provided by a user. The acquisition unit 1102 is used to obtain the result of the program running in a weak memory environment according to a query parameter and the program. The query parameter is used to indicate the maximum interval between two operations of the program being reordered.

[0168] In a possible design, the acquisition unit 1102 is further used to obtain the result of the program running in the weak memory environment according to the query parameter, the interval between the first operation in the first thread of the program and the second operation in the first thread, and the interval between the third operation in the second thread of the program and the fourth operation in the second thread. Optionally, the first operation and the third operation are a pair of read and write operations performed on the same variable, the second operation and the fourth operation are a pair of read and write operations performed on the same variable, the first operation and the second operation are operations performed on different variables, and the third operation and the fourth operation are operations performed on different variables.

[0169] In one possible design, the acquisition unit 1102 is also used to adopt memory read and write mode query rules to detect the first operation in the first thread of the program, the second operation in the first thread, the third operation in the second thread of the program, and the fourth operation in the second thread to obtain the result of the program running in a weak memory environment.

[0170] Optionally, the memory read / write pattern query rule may be determined according to a query parameter, and the memory read / write pattern query rule may be used to determine whether the first thread and the second thread overlap in time.

[0171] In a possible design, the memory read-write mode query rule may include a read-read, write-write out-of-order query rule, and / or a read-write, write-read out-of-order query rule.

[0172] In one possible design, the query parameter may be determined by a user, and the query parameter may include an on-chip write operation delay.

[0173] Optionally, the query parameter may further include a cross-NUMA write operation delay and / or a cross-NUMA read operation delay. In this way, a memory read / write mode query may be performed according to the query parameter input by the user.

[0174] In a possible design, the acquisition unit 1102 is further configured to acquire a value corresponding to the query parameter, wherein the value corresponding to the query parameter may include a value corresponding to an on-chip write operation delay.

[0175] Optionally, the numerical value corresponding to the query parameter may also include a value corresponding to a cross-NUMA write operation delay and / or a value corresponding to a cross-NUMA read operation delay.

[0176] Optionally, the weak memory environment may be an operating environment corresponding to an operating device of a non-uniform memory access architecture NUMA.

[0177] In a possible design, the program detection device 1100 may further include: an output unit 1103. The output unit 1103 is used to provide a result to the user, wherein the result may include a modification suggestion.

[0178] Optionally, the result may include: correct. Alternatively, the result may include an error and / or a modification suggestion.

[0179] Optionally, the modification suggestion may include location information of the code to be modified, such as code line number and / or program file name, and the modification suggestion may be used by the program detection device to modify the program or by the user to manually modify the program.

[0180] In a possible design, the acquisition unit 1102 is further configured to modify the program according to the modification suggestion in response to a confirmation instruction from the user.

[0181] In one possible design, the program detection device 1100 may be placed in a cloud server.

[0182] It should be noted that the receiving unit 1101 and the output unit 1103 can be separately provided or integrated into one module, namely, a transceiver module ( Fig.11 The present application does not specifically limit the specific implementation of the receiving unit 1101 and the output unit 1103.

[0183] Optionally, the program detection device 1100 may further include a storage module ( Fig.11 When the acquisition unit 1102 executes the program or instruction, the program detection device 1100 can execute Figure 1 The function of the program detection device in the program detection method shown.

[0184] It should be noted that the program detection device 1100 can be a computer device, a server or a cloud server, or it can be a chip (system) or other parts or components that can be set in a computer device, a server or a cloud server, and this application does not limit this.

[0185] also, Fig.11 The technical effect of the program detection device 1100 shown can be referred to Figure 1 The technical effects of the program detection method shown will not be repeated here.

[0186] Fig.12 This is a schematic diagram of the structure of the program detection device provided in the embodiment of the present application. Figure 2 The program detection device may be a computer device, a server or a cloud server, or a chip (system) or other parts or components that can be set in a computer device, a server or a cloud server, and this application does not limit this.

[0187] like Fig.12 As shown, the program detection device 1200 may include a processor 1201. Optionally, the program detection device 1200 may also include a memory 1202 and a transceiver 1203. The processor 1201 is coupled with the memory 1202 and the transceiver 1203, such as being connected via a communication bus.

[0188] Combine the following Fig.12 The various components of the program detection device 1200 are specifically introduced:

[0189] The processor 1201 is the control center of the program detection device 1200, and can be a processor or a general term for multiple processing elements. For example, the processor 1201 is one or more central processing units (CPUs), or can be an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application, such as one or more microprocessors (digital signal processors, DSPs), or one or more field programmable gate arrays (FPGAs).

[0190] The processor 1201 may execute various functions of the program detection device 1200 by running or executing software programs stored in the memory 1202 and calling data stored in the memory 1202 .

[0191] In a specific implementation, as an embodiment, the processor 1201 may include one or more CPUs, such as Fig.12 CPU0 and CPU1 are shown in the figure.

[0192] In a specific implementation, as an embodiment, the program detection device 1200 may also include multiple processors, such as Fig.12 1 and 1204. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0193] The memory 1202 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compressed optical disc, a laser disc, an optical disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1202 may be integrated with the processor 1201, or may exist independently, and may be accessed through the input / output port ( Fig.12 ) is coupled to the processor 1201, which is not specifically limited in the embodiment of the present application.

[0194] The memory 1202 is used to store the software program for executing the solution of the present application, and the execution is controlled by the processor 1201. The above specific implementation can refer to the above method embodiment, which will not be repeated here.

[0195] The transceiver 1203 is used for communication with other devices. In addition, the transceiver 1203 may include a receiver and a transmitter ( Fig.12 The receiver is used to implement the receiving function, and the transmitter is used to implement the sending function. The transceiver 1203 can be integrated with the processor 1201, or can exist independently, and can be detected by the program 1200 through the input / output port ( Fig.12 ) is coupled to the processor 1201, which is not specifically limited in the embodiment of the present application.

[0196] It should be noted that Fig.12 The structure of the program detection device 1200 shown in the figure does not constitute a limitation on the program detection device. The actual program detection device may include more or fewer components than those shown in the figure, or combine certain components, or arrange the components differently.

[0197] The embodiment of the present application provides a chip system, which includes a processor and an input / output port, wherein the processor is used to implement the processing function involved in the above method embodiment, and the input / output port is used to implement the transceiver function involved in the above method embodiment.

[0198] In one possible design, the chip system also includes a memory, which is used to store program instructions and data for implementing the functions involved in the above method embodiments.

[0199] The chip system may be composed of chips, or may include chips and other discrete devices.

[0200] An embodiment of the present application provides a computer-readable storage medium, including: the computer-readable storage medium stores computer instructions; when the computer instructions are executed on a computer, the computer executes the program detection method described in the above method embodiment.

[0201] An embodiment of the present application provides a computer program product including instructions, including a computer program or instructions. When the computer program or instructions are executed on a computer, the computer is caused to execute the program detection method described in the above method embodiment.

[0202] It should be understood that the processor in the embodiments of the present application may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0203] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0204] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0205] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0206] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0207] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0208] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0209] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0210] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0211] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0212] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0213] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0214] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A program detection method, characterized in that: include: receiving a program, wherein the program is provided by a user; According to the query parameter and the program, a result of the program running in a weak memory environment is obtained; wherein the query parameter is used to indicate a maximum interval between two operations of the program being reordered.

2. The program detection method according to claim 1, characterized in that: The obtaining, according to the query parameters and the program, a result of the program running in a weak memory environment, includes: A result of the program running in the weak memory environment is obtained according to the query parameter, an interval between a first operation in a first thread of the program and a second operation in the first thread, and an interval between a third operation in a second thread of the program and a fourth operation in the second thread; wherein the first operation and the third operation are a pair of read and write operations performed on the same variable, the second operation and the fourth operation are a pair of read and write operations performed on the same variable, the first operation and the second operation are operations performed on different variables, and the third operation and the fourth operation are operations performed on different variables.

3. The program detection method according to claim 2, characterized in that: Also includes: Using memory read and write mode query rules, a first operation in a first thread of the program, a second operation in the first thread, a third operation in a second thread of the program, and a fourth operation in the second thread are detected to obtain a result of the program running in the weak memory environment.

4. The program detection method according to claim 3, characterized in that: The memory read / write mode query rule is determined according to the query parameter, and the memory read / write mode query rule is used to determine whether the first thread and the second thread overlap in time.

5. The program detection method according to any one of claims 1 to 4, characterized in that: The query parameter is determined by the user, and the query parameter includes an on-chip write operation delay.

6. The program detection method according to any one of claims 1 to 5, characterized in that: The weak memory environment is an operating environment corresponding to an operating device of a non-uniform memory access architecture NUMA.

7. The program detection method according to any one of claims 1 to 6, characterized in that: Also includes: The results are provided to the user, wherein the results include modification suggestions.

8. The program detection method according to claim 7, characterized in that: Also includes: In response to a determination instruction from the user, the program is modified according to the modification suggestion.

9. A program detection device, characterized in that: include: A receiving unit, used for receiving a program, wherein the program is provided by a user; The acquisition unit is used to obtain the result of the program running in a weak memory environment according to the query parameter and the program; wherein the query parameter is used to indicate the maximum interval between two operations of the program being reordered.

10. The program detection device according to claim 9, characterized in that: The acquisition unit is further used to obtain a result of the program running in the weak memory environment according to the query parameter, an interval between a first operation in a first thread of the program and a second operation in the first thread, and an interval between a third operation in a second thread of the program and a fourth operation in the second thread; wherein the first operation and the third operation are a pair of read and write operations performed on the same variable, the second operation and the fourth operation are a pair of read and write operations performed on the same variable, the first operation and the second operation are operations performed on different variables, and the third operation and the fourth operation are operations performed on different variables.

11. The program detection device according to claim 9, characterized in that: The acquisition unit is also used to adopt memory read and write mode query rules to detect the first operation in the first thread of the program, the second operation in the first thread, the third operation in the second thread of the program, and the fourth operation in the second thread to obtain the result of the program running in the weak memory environment.

12. The program detection device according to claim 11, characterized in that: The memory read / write mode query rule is determined according to the query parameter, and the memory read / write mode query rule is used to determine whether the first thread and the second thread overlap in time.

13. The program detection device according to any one of claims 9 to 12, characterized in that: The query parameter is determined by the user, and the query parameter includes an on-chip write operation delay.

14. The program detection device according to any one of claims 9 to 13, characterized in that: The weak memory environment is an operating environment corresponding to an operating device of a non-uniform memory access architecture NUMA.

15. The program detection device according to any one of claims 9 to 14, characterized in that: Also includes: Output unit; wherein, The output unit is used to provide the result to the user; wherein the result includes modification suggestions.

16. The program detection device according to claim 15, characterized in that: The acquisition unit is further configured to modify the program according to the modification suggestion in response to a confirmation instruction of the user.

17. The program detection device according to any one of claims 9 to 16, characterized in that: The program detection device is placed in the cloud server.

18. A program detection device, characterized in that: The apparatus includes: a processor coupled to a memory; The memory is used to store computer programs; The processor is configured to execute the computer program stored in the memory, so that the device executes the program detection method according to any one of claims 1 to 8.

19. A computer program product, characterized in that The computer program product comprises: a computer program code, and when the computer program code is run on a computer, the computer is enabled to execute the program detection method according to any one of claims 1 to 8.

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