Communication interface circuit, chip and electronic equipment

Abstract

The invention discloses a communication interface circuit, a chip and an electronic device, the communication interface circuit comprises a data processing module and a distribution output module, the data processing module is used for extracting valid data in to-be-transmitted data according to byte information, and packaging the valid data to obtain a coded data frame; and the distribution output module is used for distributing the coded data frame to each effective output channel according to the byte information, a preset distribution byte number and channel configuration information received across the clock domain, and controlling each effective output channel to output corresponding distribution data. According to the communication interface circuit, the to-be-transmitted data of any byte can be sent, the application scene of a communication protocol is expanded, resources are saved, and the circuit cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a communication interface circuit, chip and electronic equipment. Background Art

[0002] Aurora is a serial transmission protocol, specifically a scalable lightweight link layer protocol for moving data between point-to-point serial links. It can provide a transparent interface for the physical layer, allowing proprietary protocols or industry standard protocols to easily use high-speed transceivers, using fewer logical resources, but providing low latency, high bandwidth and a highly configurable feature set. Based on the above features, Aurora is widely used in high-speed serial communications.

[0003] The core features of conventional Aurora designs are the data frame structure, code type and encoding, clock compensation, error detection and multi-channel serial output of data of specific bytes. The circuit structure designed based on this can only be applied to the transmission of data of specific byte length.

[0004] In the related art, corresponding Aurora modules are generated according to the bytes to be sent to achieve the transmission of data of different byte lengths, but this also leads to serious waste of resources. Summary of the invention

[0005] In view of the above problems, the present application provides a communication interface circuit, chip and electronic device to solve the above technical problems.

[0006] In a first aspect, the present application provides a communication interface circuit, the communication interface circuit comprising a data processing module and a distribution output module;

[0007] A data processing module, used to extract valid data from the data to be transmitted according to the byte information, and encapsulate the valid data to obtain a coded data frame, wherein the byte information is used to represent the number of valid bytes of the data to be transmitted;

[0008] The allocation output module is connected to the data processing module and is used to allocate the encoded data frame to each valid output channel according to the byte information, the preset allocated byte number and the channel configuration information, and control each valid output channel to output the corresponding allocated data to send the data to be transmitted; wherein the channel configuration information carries the channel number of the valid output channel for sending the data to be transmitted, and the preset allocated byte number is used to represent the number of bytes of the encoded data frame allocated to each valid output channel each time.

[0009] The communication interface circuit allocates the encoded data frames corresponding to the data to be transmitted to the corresponding valid output channels for output according to the byte information, the preset number of allocated bytes and the number of channels of the valid output channels carried by the channel configuration information. It can realize the sending of data to be transmitted of any byte, expand the application scenarios of the communication protocol, save resources and reduce circuit costs.

[0010] In a second aspect, the present application also provides a chip, comprising a chip body and the above-mentioned communication interface circuit arranged in the chip body.

[0011] In a third aspect, the present application also provides an electronic device, including a device body and a communication interface circuit or chip as described above, which is arranged in the device body.

[0012] The communication interface circuit provided by the present application extracts valid data from the data to be transmitted according to byte information through a data processing module and encapsulates it to obtain a coded data frame. The output allocation module allocates the coded data frame to the corresponding valid output channel for output according to the byte information, the preset number of allocated bytes and the number of channels of the valid output channel carried by the channel configuration information. It can be used to send data of any byte to be transmitted, that is, the communication interface circuit of the present application can be applicable to the sending of data of any byte to be transmitted. Compared with the related art of generating different communication protocol modules for different byte lengths, it saves resources, greatly expands the application scenarios of the communication protocol and reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 It is a schematic diagram of an application scenario of the communication interface circuit provided in an embodiment of the present application;

[0015] Figure 2 is a structural schematic diagram of a communication interface circuit provided in an embodiment of the present application;

[0016] Figure 3 It is a structural schematic diagram of a data processing module provided in an embodiment of the present application;

[0017] Figure 4 It is a structural diagram of a distribution output module provided in an embodiment of the present application;

[0018] Figure 5 It is a schematic diagram of an allocation process of a coded data frame provided in an embodiment of the present application;

[0019] Figure 6 It is a structural diagram of a data allocation control unit provided in an embodiment of the present application;

[0020] Figure 7 is a structural schematic diagram of a sampling output unit provided in an embodiment of the present application;

[0021] Figure 8 is another structural schematic diagram of the sampling output unit provided in the embodiment of the present application;

[0022] Fig. 9 It is a schematic diagram of a working principle of a sampling output unit provided in an embodiment of the present application;

[0023] Fig.10 It is another structural schematic diagram of the sampling output unit provided in the embodiment of the present application;

[0024] Fig.11 It is a structural schematic diagram of a double-edge serial output subunit provided in an embodiment of the present application;

[0025] Fig.12 is another structural schematic diagram of the communication interface circuit provided in the embodiment of the present application;

[0026] Fig.13 It is a structural diagram of a receiving synchronization module provided in an embodiment of the present application;

[0027] Fig.14 It is another structural schematic diagram of the communication interface circuit provided in the embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0029] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0030] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0031] Moreover, the terms "comprises", "comprising" or any other variation thereof are intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of more restrictions, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the element.

[0032] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0033] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0034] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0035] Before introducing the communication interface circuit, chip and electronic device of the present application, the relevant background information of the embodiments of the present application is first introduced.

[0036] Currently, Aurora has been widely used in high-speed serial communications because it can provide a transparent interface for the physical layer, allowing proprietary protocols or industry-standard protocols to easily use high-speed transceivers, using fewer logic resources but providing low latency, high bandwidth and a highly configurable feature set.

[0037] However, the core features of conventional Aurora designs lie in the data frame structure, code type and encoding, clock compensation, error detection and multi-channel serial output of data of specific bytes. Therefore, the circuit structure designed based on this can only be applied to the transmission of data of specific byte length.

[0038] However, in some practical applications, the number of data bytes that the system needs to send is variable. In view of this situation, the related art generates Aurora protocol modules in different situations according to the bytes to be sent to send data of different bytes, thus causing serious waste of resources.

[0039] Based on this, the embodiments of the present application provide a communication interface circuit, a chip and an electronic device, which are described in detail below.

[0040] See also Figure 1 , Figure 1 It is a schematic diagram of an application scenario of the communication interface circuit provided in an embodiment of the present application. The communication interface circuit 10 can be set in a chip to send the data to be transmitted from the data source 20 to the data receiving end 30 to realize data transmission.

[0041] It is understandable that in some other application scenarios, the communication interface circuit 10 can also be externally mounted on the chip and respectively connected to the data receiving end 30 and the data source 20 on the chip, so that the data to be transmitted from the data source 20 can also be transmitted to the data receiving end 30.

[0042] The communication interface circuit 10 can implement data transmission based on any existing communication protocol, including but not limited to the Aurora protocol, which can be specifically determined according to the actual application scenario and is not limited here.

[0043] Those skilled in the art will understand that Figure 1 The application environment shown in is only an application scenario adapted to the solution of the present application and does not constitute a limitation on the application scenario of the solution of the present application. The communication interface circuit 10 of the present application or the chip integrating the communication interface circuit 10 can be used in application scenarios such as communication, audio amplifier, power supply equipment, and automobiles, and is not specifically limited here.

[0044] First, the present application embodiment provides a communication interface circuit. Figure 2 , Figure 2 It is a structural diagram of a communication interface circuit provided in an embodiment of the present application. The communication interface circuit 10 may include a data processing module 100 and a distribution output module 200.

[0045] The data processing module 100 can be used to extract valid data from the data to be transmitted according to the byte information, and encapsulate the valid data to obtain a coded data frame, wherein the byte information can be used to represent the number of valid bytes of the data to be transmitted.

[0046] The allocation output module 200 can be used to allocate the encoded data frame to each valid output channel according to the byte information, the preset allocated byte number and the channel configuration information, and control each valid output channel to output the corresponding allocated data to send the data to be transmitted; wherein the channel configuration information carries the channel number of the valid output channel for sending the data to be transmitted, and the preset allocated byte number is used to represent the number of bytes of the encoded data frame allocated to each valid output channel each time.

[0047] Since the byte information represents the number of valid bytes of the data to be transmitted, the data processing module 100 can extract the valid data in the data to be transmitted according to the byte information, and then encapsulate the valid data based on the corresponding communication protocol to obtain a coded data frame.

[0048] The communication protocols applicable to the embodiments of the present application include, but are not limited to, the Aurora protocol, the Modbus protocol, etc., which can be determined according to the actual application scenario and are not limited here. It is understandable that with the development of communication technology, updating and improving the current communication protocol or newly formulated communication protocols are also applicable, that is, the communication protocols mentioned in the embodiments of the present application are not limited to the existing communication protocols.

[0049] In the embodiment of the present application, the data processing module 100 performs encapsulation processing on the valid data, which may be to format and encode the extracted valid data based on a determined communication protocol.

[0050] like Figure 3 As shown, as an example, the data processing module 100 may include a data cache level 1 unit 110, a byte cache level 1 unit 120, a data extraction unit 130, a formatting unit 140 and an encoding unit 150, wherein the data cache level 1 unit 110 stores data to be transmitted, the byte cache level 1 unit 120 stores byte information, and the data extraction unit 130 obtains byte information from the byte cache level 1 unit 120, thereby extracting valid data from the data to be transmitted stored in the data cache level 1 unit 110 according to the byte information, and sending the extracted valid data to the formatting unit 140 for formatting processing, and then sending the formatted data to the encoding unit 150 for encoding, so as to obtain a final encoded data frame.

[0051] The data cache first-level unit 110 and the byte cache first-level unit 120 can both be implemented using a cache; the formatting unit 140 formats the valid data, specifically, it can be to add start bits, supplementary bits, stop bits and the like to the valid data according to the provisions of the communication protocol to form a data format that meets the requirements of the communication protocol. It can be understood that the number of bytes of the valid data can be determined according to the actual application scenario. Therefore, for valid data with different numbers of bytes, the start bits, supplementary bits, and stop bits added during the formatting process may be different; the encoding unit 150 can use an encoder corresponding to the communication protocol. For example, if the communication protocol is the Aurora protocol, the encoding unit 150 can use an 8b / 10b encoder, and the 8b / 10b encoder can convert 8-bit input data into 10-bit output data to form an encoded data frame.

[0052] Please continue reading Figure 2 The allocation output module 200 may also receive channel configuration information configured by the user. Since the channel configuration information carries the number of valid output channels for sending the aforementioned data to be transmitted, the allocation output module 200 may determine the valid output channels for sending the data to be transmitted from the received channel configuration information. In this embodiment, the communication interface circuit 10 may be configured with multiple output channels, for example Figure 2 The first output channel LANE 1, the second output channel LANE 2, the Nth output channel LANE N, etc. are shown in the figure, where N is a value greater than 2. According to the channel configuration information, it can be determined which output channels of the N output channels are valid output channels for sending the data to be transmitted this time. For example, if the first valid output channel and the second valid output channel are configured as valid output channels, data transmission is realized through the first valid output channel and the second valid output channel.

[0053] After determining the effective output channel, the output allocation module 200 can allocate the encapsulated encoded data frames to each effective output channel in sequence according to the byte information and the number of bytes allocated to each effective output channel each time, that is, the preset number of allocated bytes, and control each effective output channel to output the corresponding allocated data, thereby realizing the sending of any byte of data to be transmitted.

[0054] The communication interface circuit 10 provided in the embodiment of the present application extracts valid data from the data to be transmitted according to byte information through the data processing module 100 and encapsulates it to obtain a coded data frame. The allocation output module 200 allocates the coded data frame to the corresponding valid output channel for output according to the byte information, the preset number of allocated bytes and the number of channels of the valid output channel carried by the channel configuration information. It can be used to send data to be transmitted of any byte, that is, the communication interface circuit 10 of the present application can be applicable to the sending of data to be transmitted of any byte. Compared with the related art that generates different communication protocol modules for different byte lengths, it saves resources, greatly expands the application scenarios of the communication protocol, and reduces costs.

[0055] Next, continue to Figure 2 The modules shown and the specific implementation methods that may be used in practical applications are described in detail.

[0056] like Figure 4 As shown, in some embodiments of the present application, the allocation output module 200 may include a data allocation control unit 210, a sampling output unit 220, and a cache unit corresponding to each valid output channel, and the bit width of each cache unit is obtained according to a preset number of allocated bytes; the data allocation control unit 210 can be used to perform a division operation on the byte information and the total number of bytes allocated in a single time, and round up the operation result to obtain the total number of allocations, and control the allocation of the encoded data frame to the cache unit of each valid output channel one by one based on the total number of allocations, and the number of bytes allocated to each cache unit each time is equal to the preset number of allocated bytes; wherein the total number of bytes allocated in a single time is the product of the preset number of allocated bytes and the number of channels of the valid output channel; the sampling output unit 220 can be connected to each cache unit, and is used to sample the current allocation data stored in each cache unit, and after outputting the sampled data to the corresponding valid output channel, trigger the data allocation control unit 210 to perform the next data allocation to update the current allocation data in each cache unit.

[0057] Assuming that the valid output channels in the embodiment of the present application are the first valid output channel and the second valid output channel, the data allocation control unit 210 can control the encoded data frame to be successively allocated to the first cache unit corresponding to the first valid output channel and the second cache unit corresponding to the second valid output channel, and then the sampling output unit 220 samples the current allocated data stored in the first cache unit and the second cache unit respectively, and outputs them to the first valid output channel and the second valid output channel accordingly. When the current allocated data in the first cache unit and the second cache unit are sent, the data allocation control unit 210 is triggered to allocate the remaining data in the encoded data frame to the first cache unit and the second cache unit again, update the current allocated data in the first cache sub-unit and the second cache sub-unit, and perform the next sampling output.

[0058] See also Figure 5 As an example, the coded data frame includes 10 valid bytes (D1D2D3D4D5D6D7D8D9D10), and the preset number of allocated bytes is 2 bytes, then the bit width of the cache unit is set to 20 bits. During the first data allocation, the data allocation control unit 210 controls the two bytes D1D2, totaling 20 bits of data, to be allocated to the first cache unit, and the two bytes D3D4, totaling 20 bits of data, to be allocated to the second cache unit. After the sampling output unit 220 outputs the corresponding samples of D1D2 and D3D4 to the first valid output channel and the second valid output channel, the data allocation control unit 210 is triggered to perform the second data allocation, and the control The two bytes of D5D6 totaling 20 bits of data are allocated to the first cache unit, and the two bytes of D7D8 totaling 20 bits of data are allocated to the second cache unit. After the sampling output unit 220 outputs the corresponding samples of D5D6 and D7D8 to the first effective output channel and the second effective output channel, it triggers the data allocation control unit 210 again to perform the third data allocation, and controls the two bytes of D9D10 totaling 20 bits of data to be allocated to the first cache unit. Since the encoded data frame has a total of 10 bytes and 100 bits of data that have been allocated, during the third data allocation, 20 bits of data "0" are added to the second cache unit to complete the data allocation.

[0059] Similarly, if there are three valid output channels, during the first data allocation, the data allocation control unit 210 controls the two bytes of D1D2, totaling 20 bits of data, to be allocated to the first cache unit, the two bytes of D3D4, totaling 20 bits of data, to be allocated to the second cache unit, and the two bytes of D5D6, totaling 20 bits of data, to be allocated to the third cache unit. After the sampling output unit 220 outputs the corresponding samples of D1D2, D3D4, and D5D6 to the first valid output channel, the second valid output channel, and the third valid output channel, the data allocation control unit 210 is triggered to perform the second data allocation, controlling the two bytes of D7D8, totaling 20 bits of data, to be allocated to the first cache unit, the two bytes of D9D10, totaling 20 bits of data, to be allocated to the second cache unit, and filling the third cache unit with 20 bits of data "0", thereby completing the data allocation.

[0060] It can be seen that the total number of allocations of the data allocation control unit 210 can be calculated based on the byte information, the preset number of allocated bytes and the number of channels of the valid output channels. The specific calculation is: the total number of bytes allocated in a single time is obtained by multiplying the preset number of allocated bytes and the number of channels of the valid output channels, and then the total number of bytes allocated in a single time is used as the divisor and the valid number of bytes of the data to be transmitted is used as the dividend for division operation, and the operation result is rounded up to obtain the total number of allocations.

[0061] In this embodiment, rounding up the calculation result can be understood as: when the total number of bytes allocated in a single time and the number of valid bytes cannot be divided evenly and there is a remainder, add 1 to the current quotient. For example, 10 divided by 3 cannot be divided evenly and there is a remainder. Rounding up the calculation result is to add 1 to the quotient of 3, and the final result is 4.

[0062] It can be understood that the number of valid bytes of data to be transmitted, the preset number of allocated bytes, and the number of channels of valid output channels can all be selected according to actual application scenarios and are not limited here.

[0063] like Figure 6 As shown, in some embodiments of the present application, the data allocation control unit 210 may include an allocation counter 2101 and an allocation control subunit 2102; the allocation counter 2101 can store the total number of allocations, and is used to count in response to an allocation instruction or a trigger signal from the sampling output unit 220, and send a trigger allocation signal to the allocation control subunit 2102 until the current count value is greater than the total number of allocations, and stops sending the trigger allocation signal; the allocation control subunit 2102 can be used to control the allocation of encoded data frames to the cache units of each valid output channel in response to the trigger allocation signal.

[0064] In an embodiment of the present application, the allocation instruction may be an instruction signal issued by the main chip or other unit modules, and the allocation counter 2101 may start counting from the initial value in response to the allocation instruction, and simultaneously issue a trigger allocation signal to the allocation control subunit 2102 to trigger the allocation control subunit 2102 to perform the first data allocation; when the sampling output unit 220 outputs the current allocated data sample in the cache unit to the corresponding valid output channel, the sampling output unit 220 issues a trigger signal to the allocation counter 2101 to trigger the allocation counter 2101 to update the current count value, and at the same time issues a trigger allocation signal to the allocation control subunit 2102 again to trigger the allocation control subunit 2102 to perform the next data allocation, until the current count value is greater than the total number of allocations, it can be considered that all byte data of the encoded data frame have been allocated, so the allocation counter 2101 stops issuing the trigger allocation signal, and the allocation control subunit 2102 stops data allocation.

[0065] For example, assuming that the total number of allocations is 2, the allocation counter 2101 starts counting from the initial value 0 in response to the allocation instruction. At this time, the current count value 1 is less than the total number of allocations 2, and a trigger allocation signal is sent to the allocation control subunit 2102 to trigger the allocation control subunit 2102 to perform the first data allocation; when the sampling output unit 220 outputs the current allocation data sample in the cache unit to the corresponding valid output channel, the sampling output unit 220 sends a trigger signal to the allocation counter 2101, triggering the allocation counter 2101 to update the current count value 1 to 2, and the current count value 2 is equal to the total number of allocations 2, then a trigger allocation signal is sent again. The sampling output unit 220 sends a trigger signal to the allocation control subunit 2102 to trigger the allocation control subunit 2102 to perform a second data allocation; when the sampling output unit 220 samples and outputs the current allocated data in the cache unit to the corresponding valid output channel again, the sampling output unit 220 sends a trigger signal to the allocation counter 2101 again, triggering the allocation counter 2101 to update the current count value 2 to 3. At this time, the current count value 3 is greater than the total allocation times 2, so it can be determined that all byte data of the encoded data frame have been allocated. At this time, the allocation counter 2101 no longer sends a trigger allocation signal, and the allocation control subunit 2102 stops data allocation.

[0066] like Figure 7 As shown, in some embodiments of the present application, the sampling output unit 220 may include an edge counter 2201, which can be connected to each cache unit respectively, for counting in response to the rising edge or falling edge of the clock signal, and sampling and outputting the current allocated data stored in each cache unit bit by bit to the corresponding valid output channel based on the count value, and triggering the data allocation control unit 210 to perform the next data allocation when the count value is greater than a preset first count threshold; wherein the preset first count threshold is obtained according to the bit width of the cache unit.

[0067] In the embodiment of the present application, the edge counter 2201 can be a rising edge counter, which triggers counting at each rising edge of the clock signal, uses the count value as an index value to sample the current allocated data in each cache unit bit by bit, and outputs it to the corresponding valid output channel. If the bit width of the cache unit is 20 bits, and the rising edge counter starts counting from 0, the first counting threshold can be set to 19, that is, when the first rising edge of the clock signal arrives, the count value of the rising edge counter is 0, at which time the first bit data0 of the current allocated data in the first cache unit is sampled and output to the first valid output channel, and the first bit data0 of the current allocated data in the second cache unit is sampled and output to the second valid output channel; when the second rising edge of the clock signal arrives, the count value of the rising edge counter is updated to 1, at which time the second bit data1 of the current allocated data in the first cache unit is sampled and output to the first valid output channel, and the second bit data1 of the current allocated data in the second cache unit is sampled and output to the first valid output channel. a1 is sampled and output to the second valid output channel; and so on, until the twentieth rising edge of the clock signal arrives, the count value of the rising edge counter is updated to 19, at this time the twentieth bit data19 of the currently allocated data in the first cache unit is sampled and output to the first valid output channel, and the twentieth bit data19 of the currently allocated data in the second cache unit is sampled and output to the second valid output channel, completing the sampling and output of the currently allocated data in the first cache unit and the second cache unit. When the twenty-first rising edge of the clock signal arrives, since the count value is updated to 20 which is greater than the first count threshold 19, the edge counter 2201 sends a trigger signal to trigger the data allocation control unit 210 to perform the next data allocation.

[0068] Similarly, in some other embodiments, the edge counter 2201 may also be a falling edge counter, and the working principle of the falling edge counter is the same as that of the rising edge counter. For details, please refer to the description of the rising edge counter in the above embodiment, which will not be repeated here.

[0069] In order to improve the data output efficiency, such as Figure 8As shown, in some embodiments of the present application, the sampling output unit 220 may include a first rising edge counter 2202, a first falling edge counter 2203 and an adder 2204, the output end Q of the first rising edge counter 2202 and the output end Q of the first falling edge counter 2203 are respectively connected to the input end of the adder 2204, and the output end of the adder 2204 is connected to each cache unit; the first rising edge counter 2202 can be used to count in response to the rising edge of the clock signal clk, and output the rising edge count value to the adder 2204; the first falling edge counter 2203 can be used to count in response to the falling edge of the clock signal clk, and output the falling edge count value to the adder 2204; the adder 2204 can be used to obtain a multiplication index value according to the rising edge count value and the falling edge count value, and based on the multiplication index value, the current allocated data stored in each cache unit is sampled bit by bit and output to the corresponding valid output channel.

[0070] The first rising edge counter 2202 can also be used to trigger the data allocation control unit 210 to perform the next data allocation when the rising edge count value is greater than a preset second count threshold, wherein the preset second count threshold is obtained according to the bit width of the cache unit; or, the first falling edge counter 2203 can also be used to trigger the data allocation control unit 210 to perform the next data allocation when the falling edge count value is greater than a preset third count threshold, wherein the preset third count threshold is obtained according to the bit width of the cache unit.

[0071] In the embodiment of the present application, by performing double-edge triggered sampling in response to the clock signal clk by the first rising edge counter 2202 and the first falling edge counter 2203, the current allocated data in the cache unit can be output at a double frequency, thereby improving data output efficiency.

[0072] For details, please refer to Fig. 9, the first rising edge counter 2202 starts counting from 0 in response to the rising edge of the clock signal clk, and the first falling edge counter 2203 starts counting from 0 in response to the falling edge of the clock signal clk. During the counting process, the adder 2204 adds the rising edge count value and the falling edge count value to obtain the frequency multiplication index value corresponding to each clock edge. For example, at the initialization, based on the frequency multiplication index value 0, the first bit data0 in the current allocated data is sampled and output to the corresponding valid channel. When the first rising edge arrives, the frequency multiplication index value 1 is obtained, and the second bit data1 in the allocated data is sampled and output to the corresponding valid channel. When the first falling edge arrives, the frequency multiplication index value 2 is obtained, and the allocated The third bit data2 in the data is sampled and output to the corresponding valid channel; and so on, when the ninth falling edge arrives, the multiplication index value 18 is obtained, and the nineteenth bit data18 in the allocated data is sampled and output to the corresponding valid channel. When the tenth rising edge arrives, the multiplication index value 19 is obtained, and the twentieth bit data19 in the allocated data is sampled and output to the corresponding valid channel, thereby completing the multiplication output of the current allocated data in the cache unit. When the tenth falling edge or the eleventh rising edge of the clock signal arrives, since the output of the current allocated data has been completed, the data allocation control unit 210 is triggered to perform the next data allocation and update the current allocated data stored in the cache unit.

[0073] It can be understood that the preset second counting threshold corresponding to the first rising edge counter 2202 and the preset third counting threshold corresponding to the first falling edge counter 2203 can both be obtained according to the bit width of the cache unit. Specifically, due to the double-edge triggered sampling, the preset second counting threshold and the preset third counting threshold are both related to half of the bit width of the cache unit.

[0074] For example, if the bit width of the cache unit is 20, and the rising edge of the clock signal clk arrives earlier than the falling edge, the preset second counting threshold may be 20 / 2=10, and the preset third counting threshold may be 20 / 2-1=9. In other words, if the data allocation control unit 210 is triggered to perform the next data allocation by the first rising edge counter 2202, when the rising edge count value of the first rising edge counter 2202 is greater than 10, the first rising edge counter 2202 sends a trigger signal to the data allocation control unit 210; if the data allocation control unit 210 is triggered to perform the next data allocation by the first falling edge counter 2203, when the rising edge count value of the first falling edge counter 2202 is greater than 9, the first falling edge counter 2202 sends a trigger signal to the data allocation control unit 210.

[0075] In an embodiment of the present application, the frequency doubling output of the current allocated data in each cache unit is realized through the first rising edge counter 2202, the first falling edge counter 2203 and the adder, and the output process is monitored by the first rising edge counter 2202 or the first falling edge counter 2203. When the current allocated data is sent, the data allocation control unit 210 is triggered to control the allocation of data to each cache unit again, thereby ensuring the integrity and reliability of the output data and improving the output efficiency.

[0076] In some embodiments of the present application, in order to improve the output stability, before the basis of the above embodiments, as Fig.10 As shown, the sampling output unit 220 may also include double-edge serial output sub-units corresponding to each cache unit one by one, the input end of each double-edge serial output sub-unit is connected to the output end of the corresponding cache unit, and the output end is connected to the corresponding effective output channel; each double-edge serial output sub-unit can be used to output the sampling data output by the corresponding cache unit based on the multiplication index value bit by bit in series to the corresponding effective output channel.

[0077] like Fig.11 As shown, the double-edge serial output subunit may include a first XOR gate XOR1, a second XOR gate XOR2, a third XOR gate XOR3, a second rising edge counter 2205 and a second falling edge counter 2206; the first input end of the first XOR gate XOR1 and the second input end of the second XOR gate XOR2 are respectively connected to the output end of the corresponding cache unit, the second input end of the first XOR gate XOR1 is connected to the output end Q of the second falling edge counter 2206, the output end of the first XOR gate XOR1 is connected to the input end D of the second rising edge counter 2205, the output end Q of the second rising edge counter 2205 is connected to the first input end of the second XOR gate XOR2, the output end of the second XOR gate XOR2 is connected to the input end D of the second falling edge counter 2206, the first input end of the third XOR gate XOR3 is connected to the output end Q of the second rising edge counter 2205, the second input end of the third XOR gate XOR3 is connected to the output end Q of the second falling edge counter 2206, and the output end of the third XOR gate XOR3 is connected to the corresponding valid output channel.

[0078] In the embodiment of the present application, a double-edge serial output sub-unit is configured for each effective output channel to send the data output by the cache unit at a double frequency, thereby achieving stable double-frequency serial output of the data of each effective output channel, further expanding the scope of application of the circuit.

[0079] like Fig.12As shown, in some embodiments of the present application, the communication interface circuit 10 may further include a receiving synchronization module 300, which may be used to transmit the data and byte information to be transmitted to the data processing module after cross-clock domain processing when the data and byte information to be transmitted are not synchronized with the clock of the data processing module 100.

[0080] If the data and byte information to be transmitted are not synchronized with the clock of the data processing module 100, that is, they are located in different clock domains, data loss may occur, and even normal communication may not be possible. To avoid this situation, in an embodiment of the present application, the data and byte information to be transmitted are processed across clock domains by receiving the synchronization module 300.

[0081] The receiving synchronization module 300 and the data processing module 100 are located in different clock domains, that is, the receiving synchronization module 300 and the data processing module 100 operate at different clock frequencies. In order to ensure the integrity of the data, after receiving the data to be transmitted and the byte information, the receiving synchronization module 300 can perform cross-clock domain processing on the data to be transmitted and the byte information respectively, and then transmit the data to be transmitted and the byte information after the cross-clock domain processing to the data processing module 100, so as to ensure that the data to be transmitted and the byte information can be completely received by the data processing module 100.

[0082] like Fig.13 As shown, in some embodiments of the present application, the receiving synchronization module 300 may include a data receiving unit 310 and a byte receiving unit 320, the data receiving unit 310 is correspondingly connected to an asynchronous data cache unit 330, and the byte receiving unit 320 is correspondingly connected to an asynchronous byte cache unit 340. The data receiving unit 310 may be used to receive data to be transmitted, and write the data to be transmitted into the asynchronous data cache unit 330 based on a first clock frequency; wherein the first clock frequency is the working clock frequency of the receiving synchronization module 300. The byte receiving unit 320 may be used to receive byte information, and write the byte information into the asynchronous byte cache unit 340 based on the first clock frequency. The asynchronous data cache unit 330 may be used to transmit the data to be transmitted to the data processing module 100 based on a second clock frequency; wherein the second clock frequency is the working clock frequency of the data processing module 100. The asynchronous byte cache unit 340 may be used to transmit the byte information to the data processing module 100 based on the second clock frequency.

[0083] In the embodiment of the present application, both the asynchronous data cache unit 330 and the asynchronous byte cache unit 340 can adopt a first-in first-out queue (FIFO). Specifically, the corresponding asynchronous data cache unit 330 can be established according to the maximum bit width of the data that can be sent in the scenario, and the corresponding asynchronous byte cache unit 340 can be established according to the maximum bit width of the byte.

[0084] The asynchronous data cache unit 330 can receive the data to be transmitted from the data receiving unit 310 operating at the first clock frequency, and transmit the data to be transmitted to the data processing module 100 based on the second clock frequency of the data processing module 100; similarly, the asynchronous byte cache unit 340 can receive the byte information, that is, the number of valid bytes, from the byte receiving unit 320 operating at the first clock frequency, and transmit the valid number of bytes to the data processing module 100 based on the second clock frequency of the data processing module 100, thereby realizing cross-clock domain transmission of the data to be transmitted and the byte information.

[0085] It can be understood that if the channel configuration information is not synchronized with the clock of the data processing module 100, the channel configuration information can also be output to the data processing module 100 after cross-clock domain processing. The principle of the cross-clock domain processing can refer to the description of the cross-clock domain processing of the transmitted data and byte information in the aforementioned embodiment, which will not be repeated here.

[0086] It is understandable that in some other application scenarios, asynchronous dual-port RAM, Gray code conversion, etc. can also be used to implement cross-clock domain processing, which can be determined according to the actual application scenario and is not limited here.

[0087] like Fig.14 As shown, Fig.14 1 is another structural diagram of the communication interface circuit 10 provided in the embodiment of the present application. The relevant contents of each unit module in the communication interface circuit 10 correspond to the above one by one. Those skilled in the art can clearly understand that for the convenience and simplicity of description, Fig.14 The specific working process of the communication interface circuit 10 and its corresponding unit modules described in the present invention can be referred to as follows Figures 2 to 13 The description of the communication interface circuit in any embodiment will not be repeated here in detail.

[0088] Based on the above embodiments, the present application also provides a chip, which may include a chip body and a Figures 1 to 14 Corresponding to the communication interface circuit in any embodiment.

[0089] The chip may be an integrated circuit (IC), or microcircuit, microchip, or chip. The chip may be, but is not limited to, a system on chip (SOC) or a system in package (SIP) chip.

[0090] Since the chip is provided with the communication interface circuit of the above-mentioned embodiment, it has all the beneficial effects of the communication interface circuit in any of the above-mentioned embodiments, which will not be described in detail here.

[0091] The embodiment of the present application also provides an electronic device, which may include a device body and a communication interface circuit or chip as described above provided in the device body. The electronic device may be, but is not limited to, a display device, a car central control screen, a car, a smart wearable device, a mobile terminal, or a smart home device.

[0092] Among them, display devices include but are not limited to conference tablets and commercial display screens. Smart wearable devices include but are not limited to smart watches, smart bracelets, and cervical massagers. Mobile terminals include but are not limited to smartphones, laptops, tablets, and point of sales terminals (POS). Smart home devices include but are not limited to smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0093] Since the electronic device is provided with the communication interface circuit of the above embodiment, it has all the beneficial effects of the communication interface circuit in any of the above embodiments, which will not be described in detail here.

[0094] The above are only preferred embodiments of the present application and are not intended to limit the present application in any form. Although the present application has been disclosed as a preferred embodiment as above, it is not intended to limit the present application. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A communication interface circuit, characterized in that: include: A data processing module, used to extract valid data from the data to be transmitted according to the byte information, and encapsulate the valid data to obtain a coded data frame; wherein the byte information is used to represent the number of valid bytes of the data to be transmitted; An allocation output module, connected to the data processing module, is used to allocate the encoded data frame to each valid output channel according to the byte information, the preset allocation byte number and the channel configuration information, and control each valid output channel to output the corresponding allocation data to send the data to be transmitted; The channel configuration information carries the channel number of the valid output channel for sending the data to be transmitted, and the preset number of allocated bytes is used to represent the number of bytes of the encoded data frame allocated to each of the valid output channels each time.

2. The communication interface circuit according to claim 1, characterized in that: The distribution output module includes a data distribution control unit, a sampling output unit, and a cache unit corresponding to each of the valid output channels, and the bit width of each of the cache units is obtained according to the preset number of allocated bytes; The data allocation control unit is used to perform a division operation on the byte information and the total number of bytes allocated in a single allocation, and round up the operation result to obtain the total number of allocations, and control the allocation of the encoded data frame to the cache unit of each valid output channel one by one based on the total number of allocations, and the number of bytes allocated to each cache unit each time is equal to the preset number of allocated bytes; wherein the total number of bytes allocated in a single allocation is the product of the preset number of allocated bytes and the number of channels of the valid output channels; The sampling output unit is connected to each of the cache units, and is used to sample the current allocation data stored in each of the cache units. After outputting the sampled data to the corresponding valid output channel, the data allocation control unit is triggered to perform the next data allocation to update the current allocation data in each of the cache units.

3. The communication interface circuit according to claim 2, characterized in that: The data distribution control unit includes a distribution counter and a distribution control subunit; The distribution counter stores the total distribution times, is used to count in response to a distribution instruction or a trigger signal from the sampling output unit, and sends a trigger distribution signal to the distribution control subunit until the current count value is greater than the total distribution times, and stops sending the trigger distribution signal; The allocation control subunit is used to control the sequential allocation of the encoded data frames to the buffer units of each of the valid output channels in response to the trigger allocation signal.

4. The communication interface circuit according to claim 2, characterized in that: The sampling output unit includes an edge counter, which is respectively connected to each of the cache units and is used to count in response to the rising edge or falling edge of the clock signal, and sample and output the current allocated data stored in each of the cache units bit by bit to the corresponding valid output channel based on the count value, and trigger the data allocation control unit to perform the next data allocation when the count value is greater than a preset first count threshold; wherein the preset first count threshold is obtained according to the bit width of the cache unit.

5. The communication interface circuit according to claim 2, characterized in that: The sampling output unit comprises a first rising edge counter, a first falling edge counter and an adder, wherein the output end of the first rising edge counter and the output end of the first falling edge counter are respectively connected to the input end of the adder, and the output end of the adder is connected to each of the cache units; The first rising edge counter is used for counting in response to the rising edge of the clock signal and outputting the rising edge count value to the adder; The first falling edge counter is used for counting in response to the falling edge of the clock signal and outputting the falling edge count value to the adder; The adder is used to obtain a frequency multiplication index value according to the rising edge count value and the falling edge count value, and sample and output the current allocation data stored in each cache unit bit by bit to the corresponding valid output channel based on the frequency multiplication index value; The first rising edge counter is also used to trigger the data allocation control unit to perform the next data allocation when the rising edge count value is greater than a preset second count threshold, wherein the preset second count threshold is obtained according to the bit width of the cache unit; or, the first falling edge counter is also used to trigger the data allocation control unit to perform the next data allocation when the falling edge count value is greater than a preset third count threshold, wherein the preset third count threshold is obtained according to the bit width of the cache unit.

6. The communication interface circuit according to claim 5, characterized in that: The sampling output unit further includes a double-edge serial output subunit corresponding to each of the cache units, the input end of the double-edge serial output subunit is connected to the output end of the corresponding cache unit, and the output end of the double-edge serial output subunit is connected to the corresponding effective output channel; The double-edge serial output sub-unit is used to serially output the sampled data output by the cache unit based on the frequency multiplication index value to the effective output channel bit by bit.

7. The communication interface circuit according to any one of claims 1 to 6, characterized in that: The communication interface circuit also includes a receiving synchronization module; The receiving synchronization module is used to transmit the data to be transmitted and the byte information to the data processing module after cross-clock domain processing when the data to be transmitted and the byte information are not synchronized with the clock of the data processing module.

8. The communication interface circuit according to claim 7, characterized in that: The receiving synchronization module comprises a data receiving unit and a byte receiving unit, the data receiving unit is correspondingly connected to an asynchronous data buffer unit, and the byte receiving unit is correspondingly connected to an asynchronous byte buffer unit; The data receiving unit is used to receive the data to be transmitted, and write the data to be transmitted into the asynchronous data cache unit based on a first clock frequency; wherein the first clock frequency is the working clock frequency of the receiving synchronization module; The byte receiving unit is used to receive the byte information and write the byte information into the asynchronous byte buffer unit based on the first clock frequency; The asynchronous data cache unit is used to transmit the data to be transmitted to the data processing module based on a second clock frequency; wherein the second clock frequency is the working clock frequency of the data processing module; The asynchronous byte cache unit is used to transmit the byte information to the data processing module based on the second clock frequency.

9. A chip, characterized in that: The invention comprises a chip body and a communication interface circuit as claimed in any one of claims 1 to 8 arranged on the chip body.

10. An electronic device, characterized in that: The device comprises a device body and a communication interface circuit as described in any one of claims 1 to 8 or a chip as described in claim 9, which is arranged on the device body.

Images