AXI bus interconnection matrix system

Abstract

The invention provides an AXI bus interconnection matrix system, which belongs to the field of digital chip design, and comprises m master device interfaces, n slave device interfaces, a configuration module, a decoding module, an arbitration module and a cache module. According to the embodiment of the invention, a channel-level processing mode is provided, an address channel and a data channel are independent, and an arbitration strategy is configured through the register block, so that access limitation modifiability and flexible soft configuration between the AXI bus interconnection matrix master device and the AXI bus interconnection matrix slave device can be realized, and the purpose of access modifiability is achieved; the application scene range of chip information security and function security is effectively expanded, the read-write operation transmission efficiency of the chip is improved, and then the chip performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of digital chip design, and in particular to an AXI bus interconnection matrix system. Background Art

[0002] In the related technologies, as the scale of integrated circuit chips increases day by day, the functions and complexity of chips are improved, and the requirements for the processing speed performance of SOC (System on Chip) chips are getting higher and higher. As the central bridge connecting various modules, the internal bus of the chip has an important impact on the performance of the SOC system, especially in systems with multiple master devices and multiple slave devices. AXI (Advanced eXtensible Interface) is an on-chip bus for high performance, high bandwidth, and low latency in the AMBA (Advanced Microcontroller Bus Architecture) bus system proposed by ARM.

[0003] AXI is essentially a master-slave point-to-point interface protocol. The AXI protocol does not specify the specific implementation method of the bus interconnection matrix module. In the process of SOC chip design and implementation, designers need to design the bus interconnection matrix according to their needs or purchase ARM's interconnection matrix IP. In related technologies, either an independent arbitration method for read and write address channels is used, but the independence between address channels and data channels cannot be fully utilized, which will limit the bus transmission performance and fail to realize the advance transmission function of AXI; or a multi-level cascade method is used, but the interface conversion will consume clock cycles and increase transmission delay, which cannot meet the design requirements of high-performance SOC.

[0004] With respect to the above-mentioned problems existing in the related technologies, no efficient and accurate solutions have been found yet. Summary of the invention

[0005] The invention provides an AXI bus interconnection matrix system to solve the technical problems in related technologies.

[0006] According to one embodiment of the present invention, an AXI bus interconnection matrix system is provided, comprising: m master device interfaces, n slave device interfaces, a configuration module, a decoding module, an arbitration module, and a cache module, wherein the master device interface is used to connect to a master device of a system on chip (SOC), and the master device initiates a read / write operation to the slave device using the bus interconnection matrix system through the master device interface; the slave device interface is used to connect to a slave device of the SOC, and the slave device responds to the read / write operation using the bus interconnection matrix system through the slave device interface; the configuration module is used to configure the connectivity relationship between the master device interface and the slave device interface, and to configure the arbitration strategy of the arbitration module using a register group; the decoding module is used to decode the address information sent by the master device and determine the corresponding slave device interface for access application; the arbitration module, each channel of each slave device interface corresponds to an independent arbitrator, and is used to perform arbitration selection according to the arbitration strategy when receiving application selection signals of multiple master device channels; the cache module is used to cache data for channel-level transmission tasks of the address channel and data channel of the master device during the access operation.

[0007] Furthermore, each master device interface is configured with the following independent channels: write address channel, write data channel, write reply channel, read address channel, and read data channel; each slave device interface is configured with the following independent channels: write address channel, write data channel, write reply channel, read address channel, and read data channel; wherein the channel restrictions of the master device interface are interconnected with the same type of channels of the slave device interface.

[0008] Further, the configuration module includes: an interface configuration submodule, which is used to freely configure the connectivity between each master device interface and the slave device interface, and freely configure the restricted access between each master device interface and the slave device interface; a channel configuration submodule, which is used to freely configure the connectivity between each type of channel of each master device interface and the slave device interface, and freely configure the restricted access between each type of channel of each master device interface and the slave device interface; an arbitration configuration submodule, which is used to configure the arbitration mechanism of the arbitrator of each slave device interface, and configure the arbitration priority for different signals.

[0009] Furthermore, the interface configuration submodule is configured with an interface register group, the interface register group includes n registers, each register corresponds to a slave device, each register has m bits, each bit number corresponds to a master device, and the configurable value of each bit number includes: a first flag bit and a second flag bit, wherein the first flag bit is used to represent free access with the corresponding master device, and the second flag bit is used to represent access restrictions with the corresponding master device.

[0010] Furthermore, the channel configuration submodule is configured with a channel register group, which includes n registers, each register corresponding to a slave device; each register has 5 channel registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel, respectively, each channel register has m bits, each bit number corresponds to a master device, and the configurable value of each bit number includes: a third flag bit and a fourth flag bit, wherein the third flag bit is used to represent free access with the corresponding master device, and the fourth flag bit is used to represent access restriction with the corresponding master device.

[0011] Furthermore, the arbitration configuration submodule is configured with an arbitration register group, including n register groups, each register group corresponds to a slave device; each register group has 5 channel arbitration registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel respectively; each channel arbitration register has k bits, and each bit number corresponds to an arbitration mechanism.

[0012] Furthermore, k=4, and the four arbitration mechanisms are: fixed priority, round-robin priority, combined priority, and adaptive priority, wherein the adaptive priority is used to indicate that the priority order of the corresponding master device is adjusted in real time according to the frequency of the master device applying for arbitration within a fixed time period.

[0013] Furthermore, the arbitration configuration submodule is configured with a channel priority register group, each register group corresponds to a slave device; each register group has 5 channel priority registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel respectively; each channel priority register has m bits, which are used to store a sequence of length m, each element of the sequence corresponds to a master device, and the order of the m elements in the sequence corresponds to the arbitration priority order of the m master devices.

[0014] Furthermore, the arbitration module configures the following channel arbiters for each slave device interface: a write address channel arbiter, a read address channel arbiter, a write data channel arbiter, a read data channel arbiter, and a write reply channel arbiter.

[0015] Furthermore, the cache information of the transmission task includes the following fields: cache information category, master device interface number, slave device interface number, cache task code, wherein the cache information category is used to indicate the channel type, and the cache task code is used to indicate the task identifier of the transmission task initiated by the master device to the slave device.

[0016] Furthermore, the channel-level transmission tasks include: a read address channel transmission task, a read data channel transmission task, a write address channel transmission task, and a write data channel transmission task.

[0017] Furthermore, the master device includes a central processing unit (CPU) and a direct memory access (DMA) device, and the slave device includes a static random access memory (SRAM) controller, a flash memory controller, and an advanced high performance peripheral bus (AXI-to-AHB) bridge.

[0018] According to another aspect of an embodiment of the present application, a storage medium is further provided, which includes a stored program, and the above steps are executed when the program is run.

[0019] According to another aspect of an embodiment of the present application, there is also provided an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; wherein: the memory is used to store computer programs; and the processor is used to execute the steps in the above method by running the program stored in the memory.

[0020] The embodiment of the present application also provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute the steps in the above method.

[0021] Beneficial effects of the present invention:

[0022] 1. The AXI bus interconnection matrix system of the present invention provides a register configuration method for interface configuration and channel configuration of the AXI bus interconnection matrix. Compared with the hardened circuit configuration method of the prior art, it can realize flexible soft configuration of the modifiable access restrictions between master and slave devices of the AXI bus interconnection matrix, achieve the purpose of modifiable access, and effectively expand the application scenario scope of chip information security and functional safety.

[0023] 2. The AXI bus interconnection matrix system of the present invention provides a register configuration method for configuring the arbitration mechanism of the AXI bus interconnection matrix. The arbitration mechanism can be flexibly and softly configured to change the arbitration mechanism according to the register configuration. Compared with the hardened circuit configuration method of the prior art, it is more flexible and provides the possibility of changing the arbitration method after chip tape-out.

[0024] 3. The AXI bus interconnection matrix system of the present invention provides a channel-level task cache method. Compared with the entire burst transmission transaction cache or transmission data cache in the prior art, it occupies less storage resources of the interconnection matrix, is more efficient, and is accurate to each channel, giving full play to the advantages of independence between AXI bus channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0026] Figure 1 is a schematic diagram of an AXI bus interconnection matrix system according to an embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a configuration module in an embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of the structure of an arbitration module in an embodiment of the present invention;

[0029] Figure 4 It is an arbitration flow chart of the arbitration module in the embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] Example 1

[0033] As used below, the term "module" may be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0034] In this embodiment, an AXI bus interconnection matrix system is provided. Figure 1 is a schematic diagram of an AXI bus interconnection matrix system according to an embodiment of the present invention. Figure 1As shown, the process includes: m master device interfaces 10, n slave device interfaces 11, a configuration module 12, a decoding module 13, an arbitration module 14, and a cache module 15, wherein:

[0035] The master device of this embodiment includes a central processing unit (CPU), a direct memory access (DMA) device, and the slave device includes a static random access memory (SRAM) controller, a flash memory controller, and an advanced high-performance peripheral bus (AXI-to-AHB) bridge. Both m and n are positive integers greater than 0.

[0036] A master device interface 10 is used to connect to a master device of a system on chip SOC, and the master device initiates a read / write operation to a slave device through the master device interface using a bus interconnection matrix system;

[0037] A slave device interface 11, used to connect a slave device of the SOC, the slave device responds to a read / write operation using a bus interconnection matrix system through the slave device interface;

[0038] The master device interface is connected to an external master device, the slave device interface is connected to an external slave device, the master device initiates a read / write operation to the slave device using a bus interconnection matrix through the master device interface, and the slave device responds to the read / write operation using the bus interconnection matrix through the slave device interface.

[0039] Each master / slave interface has five independent channels, namely, write address channel (AW), write data channel (W), write reply channel (B), read address channel (AR), and read data channel (R); a channel of the master interface can only be connected to the same channel of the slave.

[0040] Due to AXI protocol restrictions, the number of master devices and slave devices, m and n, can be configured to be less than or equal to 16.

[0041] A configuration module 12, used to configure the connectivity relationship between the master device interface and the slave device interface, and to configure the arbitration strategy of the arbitration module using a register group;

[0042] A decoding module 13, used to decode the address information sent by the master device and determine the slave device interface corresponding to the access request;

[0043] When the master device initiates an access request (read / write operation) to the slave device, it carries the address information of the slave device to which access is requested.

[0044] The decoding module is connected to the read address channel and write address channel of the master-slave device interface, and includes two parts: read address decoding and write address decoding. During decoding, according to the slave device storage address table, the decoding module decodes the address information sent by the master device and obtains the slave device corresponding to the address information, that is, the slave device requested to access by the master device. The slave device storage address table is used to record the address space range of all slave devices. The address table is adjusted according to the interface configuration and channel configuration results to implement read and write access restrictions between master and slave devices. The decoding module sends the decoding result to the arbitrator of the slave device for arbitration.

[0045] The arbitration module 14, each channel of each slave device interface corresponds to an independent arbitrator, which is used to perform arbitration gating according to the arbitration strategy when receiving application gating signals from multiple master device channels;

[0046] The cache module 15 is used to cache data for channel-level transmission tasks of the address channel and data channel of the master device during the access operation.

[0047] Through the above system, a channel-level processing method is provided. The address channel and the data channel are independent. By configuring the arbitration strategy through the register group, the flexible soft configuration of the modifiable access restrictions between the master and slave devices of the AXI bus interconnection matrix can be realized, so as to achieve the purpose of modifiable access, effectively expand the application scenario scope of chip information security and functional safety, improve the transmission efficiency of the chip's read and write operations, and thus improve the chip performance.

[0048] In one implementation of this embodiment, each master device interface is configured with the following independent channels: a write address channel, a write data channel, a write reply channel, a read address channel, and a read data channel; each slave device interface is configured with the following independent channels: a write address channel, a write data channel, a write reply channel, a read address channel, and a read data channel; wherein the channel restrictions of the master device interface are interconnected with the same type of channels of the slave device interface.

[0049] For example, the write address channel of the master device interface can only be interconnected with the write address channel of the slave device interface, and cannot be interconnected with the write data channel, write reply channel, read address channel, and read data channel of the slave device interface.

[0050] In this embodiment, the configuration module includes: an interface configuration submodule, which is used to freely configure the connectivity between each master device interface and the slave device interface, and freely configure the restricted access between each master device interface and the slave device interface; a channel configuration submodule, which is used to freely configure the connectivity between each type of channel of each master device interface and the slave device interface, and freely configure the restricted access between each type of channel of each master device interface and the slave device interface; an arbitration configuration submodule, which is used to configure the arbitration mechanism of the arbitrator of each slave device interface, and configure the arbitration priority for different signals.

[0051] In the system of this embodiment, the configuration module includes three parts: interface configuration, channel configuration, and arbitration mechanism configuration. Interface configuration: used to freely configure the connectivity between all master device interfaces and slave device interfaces, restrict certain master device interfaces from accessing certain slave device interfaces, and cooperate with the decoding module to realize the free change from the fully connected matrix to the sparsely connected matrix, so as to achieve the effect of physical isolation between certain master and slave devices. Channel configuration: used to freely configure the connectivity between a certain type of channels of all master device interfaces and slave device interfaces, restrict the connectivity between certain master device interface channels and slave device interface channels, and cooperate with the decoding module to realize the read-only or write-only operation function between certain master and slave devices, so as to achieve the security access needs between certain master and slave devices. Arbitration configuration: used to configure the arbitration mechanism of the arbitrator of all slave devices, and configure the arbitration priority mechanism according to the different situations of each slave device. The arbitrators of each channel of the slave device are independent, which can realize that the master device channel priorities corresponding to the read and write channels of the same slave device are different, so as to achieve the purpose of precise control.

[0052] In one example, the interface configuration submodule is configured with an interface register group, which includes n registers, each register corresponds to a slave device, each register has m bits, each bit number corresponds to a master device, and the configurable value of each bit number includes: a first flag bit and a second flag bit, wherein the first flag bit is used to represent free access with the corresponding master device, and the second flag bit is used to represent access restrictions with the corresponding master device.

[0053] The interface configuration submodule determines which slave devices the master device can access, and cooperates with the decoding module to achieve physical isolation between the master device and some slave devices; the interface configuration is achieved by configuring the interface register group IREG, which contains n registers ireg1, ireg2…iregn, corresponding to slave device 1, slave device 2…slave device n respectively; each ireg register has m bits {i1, i2,…im}, corresponding to master device 1, master device 2…master device m respectively; the accessibility between the master device and the slave device is set by configuring the value of the register.

[0054] For example, the first bit i1 of the interface register ireg1 is configured to be 1 and the second bit i2 is configured to be 0, which means that the master device 1 can access the slave device 1, but the master device 2 cannot access the slave device 1, and the configuration of other interface registers is similar.

[0055] In an example, the channel configuration submodule is configured with a channel register group, which includes n registers, each register corresponding to a slave device; each register has 5 channel registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel, respectively, each channel register has m bits, each bit number corresponds to a master device, and the configurable value of each bit number includes: a third flag bit and a fourth flag bit, wherein the third flag bit is used to represent free access with the corresponding master device, and the fourth flag bit is used to represent access restrictions with the corresponding master device.

[0056] The channel configuration submodule determines whether the read and write channels of the master device and the slave devices can be interconnected based on the interface configuration, so as to realize the master device's read-only access, write-only access or both read and write access to certain slave devices. The read channel includes the read address channel AR and the read data channel R, and the write channel includes the write address channel AW, the write data channel W and the write reply channel B. The channel configuration is realized by configuring the channel register group CREG. The channel register group CREG contains n register groups creg1, creg2...cregn, corresponding to slave device 1, slave device 2...slave device n respectively. Each creg register group has 5 channel registers ar, r, aw, w, b, corresponding to the read address channel, read data channel, write address channel, write data channel and write reply channel respectively. Each channel register has m bits {c1, c2,...cm}, corresponding to master device 1, master device 2...master device m respectively. The readability and writability between the master device and the slave device are set by configuring the value of the channel register.

[0057] For example, to set the master device 1 to be only readable but not writable to the slave device 1 and the master device 2 to be only writable but not readable to the slave device 1, the following configuration is made: configure the first bit c1 of the channel register ceg1.ar to be 1 and the second bit c2 to be 0, the first bit c1 of the channel register ceg1.r to be 1 and the second bit c2 to be 0, the first bit c1 of the channel register ceg1.aw to be 0 and the second bit c2 to be 1, the first bit c1 of the channel register ceg1.w to be 0 and the second bit c2 to be 1, the first bit c1 of the channel register ceg1.b to be 0 and the second bit c2 to be 1, and the channel register configurations for other read and write restriction scenarios between the master and slave devices can be deduced accordingly.

[0058] Figure 2It is a schematic diagram of a configuration module in an embodiment of the present invention, including an interface configuration register group IREG (ireg1-iregn), a channel configuration register group CREG (creg1-cregn), an arbitration configuration register group AREG (areg1-aregn), and an arbitration priority configuration register PREG (preg1-pregn).

[0059] In an example, the arbitration configuration submodule is configured with an arbitration register group, which includes n register groups, each register group corresponds to a slave device; each register group has 5 channel arbitration registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel; each channel arbitration register has k bits, and each bit number corresponds to an arbitration mechanism.

[0060] In one example, k=4, and the four arbitration mechanisms are: fixed priority, round-robin priority, combined priority, and adaptive priority, where the adaptive priority is used to indicate that the priority order of the corresponding master device is adjusted in real time according to the frequency of the master device applying for arbitration within a fixed time period.

[0061] In the above example, the arbitration mechanism of the arbitrator includes four modes, namely, fixed priority, cyclic priority, combined priority, and adaptive priority. The fixed priority is that all master devices are sorted in a fixed order, and the master device in the front order has a high priority and is given priority when applying for arbitration; the cyclic priority is that all master devices are in a cyclic order, and the master device that applies for selection and passes arbitration in the current round has the lowest priority in the next round of arbitration, and the priority order of the master devices in the initial state is arranged according to the initial set master device order; the group priority is that all master devices are divided into multiple priority groups, each group is sorted in a fixed order, and arbitration is performed between groups in a fixed priority manner. The master devices in each group have the same priority, and arbitration is performed within the group in a cyclic priority manner; the adaptive priority is to adjust the priority order of the master devices in real time according to the frequency of master devices applying for arbitration within a fixed time period, and the master device with a high frequency has a high priority. The priority order is adjusted once after each time period, and the priority order of the master devices in the initial state is arranged according to the initial set master device order.

[0062] In an example, the arbitration configuration submodule is configured with a channel priority register group, each register group corresponds to a slave device; each register group has 5 channel priority registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel, respectively; each channel priority register has m bits for storing a sequence of length m, each element of the sequence corresponds to a master device, and the order of the m elements in the sequence corresponds to the arbitration priority order of the m master devices.

[0063] The arbitration configuration submodule configures the arbitration mechanism of the arbitrators of all slave devices, and configures the arbitration priority mechanism according to the different situations of each slave device corresponding to the master device. The configuration is divided into two parts. The first part is to configure the arbitration mechanism of each arbitrator, that is, to select one of the four arbitration mechanisms such as fixed priority, round-robin priority, combined priority, and adaptive priority; the second part is to configure the priority order of each arbitrator corresponding to the master device, that is, to determine the priority of all master devices that have the authority to access the slave device. The arbitrators of each channel of the slave device are independent, which can realize different master device channel priorities corresponding to the read and write channels of the same slave device, so as to achieve the purpose of precise control. The configuration of the channel arbitrator arbitration mechanism is achieved by configuring the arbitration register group AREG. The arbitration register group AREG contains n register groups areg1, areg2...aregn, corresponding to slave device 1, slave device 2...slave device n respectively; each areg register group has 5 channel arbitration registers ar, r, aw, w, b, corresponding to the read address channel, read data channel, write address channel, write data channel, write reply channel respectively; each channel arbitration register has 4 bits {a1, a2,...a4}, corresponding to four arbitration mechanisms such as fixed priority, round-robin priority, combined priority, and adaptive priority respectively; the arbitration mechanism of the channel arbitrator is set by configuring the value of the channel arbitration register. For example, if the arbitration mechanism of the read address channel arbitrator of slave device 1 is set to round-robin priority, the third bit a3 of the areg1.ar register is configured to be 1, and the remaining bits are all 0. The arbitration mechanism configuration of other slave device channel arbitrators can be deduced in the same way. The master device priority order corresponding to the channel arbiter is realized by configuring the channel priority register group PREG. The channel priority register group PREG contains n register groups preg1, preg2...pregn, corresponding to slave device 1, slave device 2...slave device n respectively; each preg register group has 5 channel priority registers ar, r, aw, w, b, corresponding to the read address channel, read data channel, write address channel, write data channel, write reply channel respectively; each channel priority register has m bits, and p1, p2,...pm correspond to master device 1, master device 2...master device m respectively; by configuring p1, p2 , …pm in the priority register to set the arbitration priority order of master device access. For example, preg1.ar={p2,p1,…pm} means that the arbitration priority order of master device access corresponding to the write address channel of slave device 1 is p2,p1,…pm, that is, master device 2 has the highest priority, master device 1 has the second highest priority, …master device m has the lowest priority; the configuration of the arbitration priority order of master device access of other slave device channels can be deduced in the same way. The arbitration priority order is used to configure the order of master devices with fixed priority, as well as the initial order of master devices with cyclic priority, combined priority and adaptive priority mechanism.

[0064] The arbitration module is equipped with an independent arbitrator for each channel of each slave device interface, which can realize independent arbitration of each channel connection request. The arbitrator of a slave device channel only allows one master device channel of the same type to communicate with the slave device channel at a certain time. Each arbitrator determines the master device channel with the right to participate in arbitration based on the configuration module interface configuration and channel configuration results. Each arbitrator determines the arbitration priority order of the master device channel with the right to participate in arbitration based on the results of the configuration module arbitration configuration. When the arbitrator of the slave device channel receives the application selection signal from the master device channel, it performs arbitration selection according to the priority order.

[0065] The arbitrator performs arbitration based on the arbitration mechanism pre-configured by the configuration module, including four modes: fixed priority, round-robin priority, combined priority, and adaptive priority.

[0066] In one implementation of this embodiment, the arbitration module configures the following channel arbiters for each slave device interface: a write address channel arbiter, a read address channel arbiter, a write data channel arbiter, a read data channel arbiter, and a write reply channel arbiter.

[0067] Figure 3 FIG. 1 is a schematic diagram of the structure of the arbitration module in an embodiment of the present invention. Figure 3 As shown, as an embodiment of the present invention, an arbitration module structure of an AXI bus interconnection matrix is ​​provided, in which the arbitration module is equipped with an independent arbitrator for each channel of each slave device interface, that is, each slave device has a write address channel AW arbitrator, a read address channel AR arbitrator, a write data channel W arbitrator, a read data channel R arbitrator, and a write reply channel B arbitrator, which can realize independent arbitration of each channel connection request.

[0068] Figure 4 This is an arbitration flow chart of the arbitration module in an embodiment of the present invention, which provides an arbitration method flow of an AXI bus interconnection matrix. The arbitrator of a slave device channel only allows one master device channel to communicate with the slave device channel at a certain time. The arbitration process steps of the channel arbitrator are as follows:

[0069] S41, when multiple master devices simultaneously initiate use requests to a slave device channel, the slave device channel arbitrator starts arbitration;

[0070] S42, the channel arbitrator determines the master device channel with the right to participate in arbitration according to the configuration module interface configuration and the channel configuration result;

[0071] S43, the channel arbitrator determines the arbitration mechanism and the arbitration priority order of the master device channels with the right to participate in the arbitration according to the result of the arbitration configuration of the configuration module;

[0072] S44, the channel arbitrator performs arbitration according to the arbitration mechanism and arbitration priority order, determines the master device with priority, and the arbitration ends.

[0073] The cache module of this embodiment is used for channel-level transmission task cache of the read / write address channel and the read / write data channel of the master device during the read / write operation.

[0074] In the system of this embodiment, the cache information of the transmission task includes the following fields: cache information category, master device interface number, slave device interface number, cache task code, wherein the cache information category is used to indicate the channel type, and the cache task code is used to indicate the task identifier of the transmission task initiated by the master device to the slave device.

[0075] The transmission task cache information includes the cache information category (read address, write address, read data, write data), the master device interface number (which master device initiated the read and write operation), the slave device interface number (the slave device object of the read and write operation), and the cache task code (used to distinguish multiple task caches initiated by a master device to the same slave device).

[0076] Optionally, the channel-level transmission tasks include: a read address channel transmission task, a read data channel transmission task, a write address channel transmission task, and a write data channel transmission task.

[0077] When the master device performs advance transmission, out-of-order transmission, or the arbitration application fails during the read and write operations, the transmission task cache for the read and write operations is required. During the read operation, there is a read address channel transmission task cache and a read data channel transmission task cache; during the write operation, there is a write address channel transmission task cache and a write data channel transmission task cache; since the write reply channel is for the reply of the entire burst transmission transaction, the channel occupancy time is short and there is no need for transmission task cache. The transmission task cache information includes the cache information category (read address, write address, read data, write data), the master device interface number (which master device initiated the read and write operation), the slave device interface number (the slave device object of the read and write operation), and the cache task code (used to distinguish multiple task caches initiated by a master device to the same slave device).

[0078] The cache module of this embodiment only caches the transmission task, rather than the data required to be transmitted by the transmission task, so the amount of cached information is relatively small, and the cache module occupies little storage resources.

[0079] Compared with the entire burst transfer transaction cache or transfer data cache of the prior art, the channel-level task cache method proposed in this embodiment occupies less storage resources of the interconnection matrix, is more efficient, and is accurate to each channel, giving full play to the advantages of independence between AXI bus channels.

[0080] This embodiment provides a register configuration method for the interface configuration and channel configuration of the AXI bus interconnect matrix. Compared with the hardened circuit configuration method of the prior art, it can realize the flexible soft configuration of the access restriction modifiability between the master and slave devices of the AXI bus interconnect matrix, achieve the purpose of modifiability of access, and effectively expand the scope of application scenarios of chip information security and functional safety. This embodiment provides a register configuration method for the arbitration mechanism configuration of the AXI bus interconnect matrix. The flexible soft configuration of the arbitration mechanism can change the arbitration mechanism according to the register configuration. Compared with the hardened circuit configuration method of the prior art, it provides the possibility of changing the arbitration method after chip tape-out.

[0081] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0082] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0083] In the embodiments provided in the present application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0084] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0085] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0086] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0087] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. An AXI bus interconnection matrix system, characterized in that: include: m master device interfaces, n slave device interfaces, a configuration module, a decoding module, an arbitration module, and a cache module, wherein: A master device interface is used to connect to a master device of a system on chip SOC. The master device initiates a read / write operation to a slave device through the master device interface using a bus interconnection matrix system. A slave device interface, used to connect a slave device of the SOC, the slave device responding to a read / write operation using a bus interconnection matrix system through the slave device interface; A configuration module, used to configure the connectivity relationship between the master device interface and the slave device interface, and to configure the arbitration strategy of the arbitration module using a register group; A decoding module, used to decode the address information sent by the master device and determine the slave device interface corresponding to the access request; The arbitration module has an independent arbitrator corresponding to each channel of each slave device interface, which is used to perform arbitration selection according to the arbitration strategy when receiving the application selection signals of multiple master device channels; The cache module is used to cache data for channel-level transmission tasks of the address channel and data channel of the master device during the access operation.

2. The system according to claim 1, characterized in that Each master device interface is configured with the following independent channels: write address channel, write data channel, write reply channel, read address channel, and read data channel; each slave device interface is configured with the following independent channels: write address channel, write data channel, write reply channel, read address channel, and read data channel; among which, the channel limits of the master device interface are interconnected with the same channels of the slave device interface.

3. The system according to claim 1, characterized in that The configuration module includes: An interface configuration submodule, used to freely configure the connectivity between each master device interface and the slave device interface, and freely configure the restricted access between each master device interface and the slave device interface; A channel configuration submodule, used to freely configure connectivity between each type of channel of each master device interface and slave device interface, and freely configure restricted access between each type of channel of each master device interface and slave device interface; The arbitration configuration submodule is used to configure the arbitration mechanism of the arbitrator of each slave device interface and configure the arbitration priority for different signals.

4. The system according to claim 3, characterized in that The interface configuration submodule is configured with an interface register group, which includes n registers, each register corresponds to a slave device, each register has m bits, each bit number corresponds to a master device, and the configurable value of each bit number includes: a first flag bit and a second flag bit, wherein the first flag bit is used to represent the freedom of access between the corresponding master device and the second flag bit is used to represent the access restriction between the corresponding master device.

5. The system according to claim 3, characterized in that The channel configuration submodule is configured with a channel register group, which includes n registers, each register corresponds to a slave device; each register has 5 channel registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel, respectively, each channel register has m bits, each bit number corresponds to a master device, and the configurable value of each bit number includes: a third flag bit and a fourth flag bit, wherein the third flag bit is used to represent the freedom of access between the corresponding master device, and the fourth flag bit is used to represent the access restriction between the corresponding master device.

6. The system according to claim 3, characterized in that The arbitration configuration submodule is configured with an arbitration register group, including n register groups, each register group corresponds to a slave device; each register group has 5 channel arbitration registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel respectively; each channel arbitration register has k bits, and each bit number corresponds to an arbitration mechanism.

7. The system according to claim 6, characterized in that k=4, the four arbitration mechanisms are: fixed priority, round-robin priority, combined priority, and adaptive priority, wherein the adaptive priority is used to indicate that the priority order of the corresponding master device is adjusted in real time according to the frequency of the master device applying for arbitration within a fixed time period.

8. The system according to claim 3, characterized in that The arbitration configuration submodule is configured with a channel priority register group, each register group corresponds to a slave device; each register group has 5 channel priority registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel respectively; each channel priority register has m bits, which are used to store a sequence of length m, each element of the sequence corresponds to a master device, and the order of the m elements in the sequence corresponds to the arbitration priority order of the m master devices.

9. The system according to claim 1, characterized in that The arbitration module configures the following channel arbiters for each slave device interface: a write address channel arbiter, a read address channel arbiter, a write data channel arbiter, a read data channel arbiter, and a write reply channel arbiter.

10. The system according to claim 1, characterized in that The cache information of the transmission task includes the following fields: cache information category, master device interface number, slave device interface number, cache task code, wherein the cache information category is used to indicate the channel type, and the cache task code is used to indicate the task identifier of the transmission task initiated by the master device to the slave device.

11. The system according to claim 1, characterized in that The channel-level transmission tasks include: a read address channel transmission task, a read data channel transmission task, a write address channel transmission task, and a write data channel transmission task.

12. The system according to any one of claims 1 to 11, characterized in that: The master device includes a central processing unit (CPU) and a direct memory access (DMA) device, and the slave device includes a static random access memory (SRAM) controller, a flash memory controller, and an advanced high performance peripheral bus (AXI-to-AHB) bridge.

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