A design unit placement method and related equipment

Abstract

The present application discloses a method for placing a design unit and related equipment, comprising: generating a placement area according to design input parameters of a target integrated circuit; placing the boundary unit at the boundary of the placement area according to the definition of the boundary unit in a library exchange format file, and dividing the placement area into a plurality of placement grids; placing all standard units and all macro units in each placement grid according to a target optimization function, and inserting units for power consumption optimization and units for timing optimization into corresponding positions in the placement grid; evaluating each placement grid according to a wiring pre-evaluation function to obtain an evaluation result corresponding to each placement grid, and if the evaluation result does not meet a preset requirement, optimizing the evaluation result until the evaluation result meets the preset requirement; after the optimization is completed, if there is a blank area in the placement area, inserting a filler unit in the blank area.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and more specifically, to a method for placing a design unit and related equipment. Background Art

[0002] As integrated circuit design enters the FinFET process node, transistors present a three-dimensional structure and their complexity increases significantly. Under this circumstance, the placement algorithm of traditional mature processes encounters a series of severe challenges.

[0003] On the one hand, the placement of design units needs to deal with a large number of design rule checks (DRCs), variable 3D track grids, and reasonable allocation of wiring resources below the M3 metal level, while solving problems such as 3D wiring congestion and ensuring DRC compliance.

[0004] On the other hand, if the placement method of mature processes is still used in the FinFET process to carry out automatic placement of design units, the result is often that DRC violations cannot be completely eliminated and the chip design area cannot be minimized. This will cause the generated layout data format (Graphic Data System, GDS) file for manufacturing to be unmanufacturable or lose cost advantages, which will cause irreparable and significant losses to the entire chip design process. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In a first aspect, the present application proposes a method for placing a design unit, comprising:

[0007] generating a placement area according to design input parameters of a target integrated circuit;

[0008] According to the definition of the boundary cell in the library exchange format file, the boundary cell is placed at the boundary of the placement area, and the placement area is divided into a plurality of placement grids;

[0009] Placing all standard cells and all macro cells in each of the placement grids according to the target optimization function, and inserting cells for power consumption optimization and cells for timing optimization into corresponding positions in the placement grids;

[0010] According to the wiring pre-evaluation function, each of the placement grids is evaluated to obtain an evaluation result corresponding to each of the placement grids, and if the evaluation result does not meet the preset requirements, the evaluation result is optimized until the evaluation result meets the preset requirements;

[0011] After the optimization is completed, if there is a blank area in the placement area, a filling unit is inserted into the blank area.

[0012] In a feasible implementation, all standard cells and all macro cells are placed in each of the placement grids according to the target optimization function, including: placing each of the standard cells and each of the macro cells at any coordinate point in the placement area, and re-placing all of the standard cells and all of the macro cells according to the target optimization function until the cell density in each of the placement grids reaches a preset threshold; wherein the input of the target optimization function is the semi-perimeter line length, and the output of the target optimization function is the placement coordinates of each of the standard cells and each of the macro cells in the placement area.

[0013] In a feasible implementation, the method further includes: generating a three-dimensional linear track grid according to the library exchange format file; normalizing the placement coordinates of each of the standard cells and each of the macro cells according to the coordinates in the three-dimensional linear track grid, so that the longitudinal coordinates of each of the standard cells and each of the macro cells are the same as the longitudinal coordinates of the corresponding horizontal coordinates in the three-dimensional linear track grid; if multiple cells are placed on the same placement coordinate, moving the redundant cells, so that only one cell is placed on the same placement coordinate, and the multiple cells are multiple standard cells or multiple macro cells or simultaneously include at least one standard cell and at least one macro cell.

[0014] In a feasible implementation, if multiple units are placed on the same placement coordinate, the redundant units are moved so that only one unit is placed on the same placement coordinate, including: if multiple units are placed on the same placement coordinate, a target coordinate position is determined in the placement area, and the moving distance between the target coordinate position and the placement coordinate is the smallest; the redundant units are moved to the target coordinate position so that only one unit is placed on the same placement coordinate.

[0015] In a feasible implementation, the method further includes: normalizing the position coordinates of the unit for power consumption optimization in the placement grid according to the coordinates in the three-dimensional linear track grid so that the vertical coordinate in the position coordinates of the unit for power consumption optimization is the same as the vertical coordinate of the corresponding horizontal coordinate in the three-dimensional linear track grid; if a plurality of units for power consumption optimization are placed at the same position coordinates, moving the redundant units for power consumption optimization so that only one unit for power consumption optimization is placed at the same position coordinates.

[0016] In a feasible implementation, the method further includes: normalizing the position coordinates of the unit for timing optimization in the placement grid according to the coordinates in the three-dimensional linear track grid so that the vertical coordinate in the position coordinates of the unit for timing optimization is the same as the vertical coordinate of the corresponding horizontal coordinate in the three-dimensional linear track grid; if multiple units for timing optimization are placed at the same position coordinates, moving the redundant units for timing optimization so that only one unit for timing optimization is placed at the same position coordinates.

[0017] In a feasible implementation, each of the placement grids is evaluated according to a routing pre-evaluation function to obtain an evaluation result corresponding to each of the placement grids, including: evaluating each of the placement grids according to the routing pre-evaluation function to obtain an evaluation value corresponding to each of the placement grids output by the routing pre-evaluation function, wherein the input of the routing pre-evaluation function is the semi-perimeter line length, cell density-related parameters within the placement grid, and routing congestion estimation-related parameters; constructing a three-dimensional solution surface according to the evaluation value corresponding to each of the placement grids and the number of each of the placement grids within the placement area, and using the curvature of the three-dimensional solution surface and the evaluation value corresponding to each of the placement grids as the evaluation result corresponding to each of the placement grids.

[0018] In a feasible implementation, the evaluation result is optimized until the evaluation result meets the preset requirements, including: adjusting the positions of all the standard cells, all the macro cells, cells for power consumption optimization, and cells for timing optimization within the placement grid until the curvature of the three-dimensional solution surface is zero and the evaluation value corresponding to each of the placement grids is the minimum.

[0019] In a second aspect, the present application proposes a placement device for a design unit, comprising:

[0020] A generating unit configured to generate a placement area according to design input parameters of a target integrated circuit;

[0021] A first placement unit is configured to place the boundary unit at the boundary of the placement area according to the definition of the boundary unit in the library exchange format file, and divide the placement area into a plurality of placement grids;

[0022] A second placement unit is configured to place all standard cells and all macro cells in each of the placement grids according to a target optimization function, and insert cells for power consumption optimization and cells for timing optimization into corresponding positions in the placement grids;

[0023] An evaluation unit is configured to evaluate each of the placement grids according to a wiring pre-evaluation function to obtain an evaluation result corresponding to each of the placement grids, and if the evaluation result does not meet a preset requirement, optimize the evaluation result until the evaluation result meets the preset requirement;

[0024] The inserting unit is configured to insert a filling unit into the blank area if there is a blank area in the placement area after the optimization is completed.

[0025] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of a method for placing a design unit as described in any one of the first aspects above when executing the computer program stored in the memory.

[0026] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method for placing the design unit of any one of the first aspects is implemented.

[0027] In summary, the design unit placement method and related equipment proposed in this application accurately generate placement areas based on design input parameters, properly place boundary cells and divide placement grids according to boundary cell definitions in library exchange format files, build an orderly layout, improve layout space utilization, reduce cost increases caused by layout confusion, enhance manufacturability, and ensure a smooth chip manufacturing process. With the help of target optimization functions, standard cells and macro cells are reasonably placed, and power consumption and timing optimization units are inserted at corresponding locations to resolve design rule checking and three-dimensional wiring congestion problems, finely control chip power consumption and timing to optimize performance, consolidate layout rationality and compliance, reduce DRC violation rate, and improve chip design success rate and stability. Use wiring pre-evaluation functions to evaluate and optimize, avoid DRC violation difficulties and design area redundancy problems, improve manufacturability, reduce manufacturing correction costs, ensure efficient and smooth chip design process, improve design quality and efficiency, meet FinFET process design requirements, and provide strong support for integrated circuit research and development and manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0029] Figure 1 A schematic diagram of an exemplary system used in an embodiment of the present application.

[0030] Figure 2 A schematic diagram of the process of placing a design unit provided in an embodiment of the present application.

[0031] Figure 3 A schematic diagram of the process of placing a design unit provided in an embodiment of the present application.

[0032] Figure 4 A schematic diagram of the process of placing a design unit provided in an embodiment of the present application.

[0033] Figure 5 A schematic diagram of the process of placing a design unit provided in an embodiment of the present application.

[0034] Figure 6 A schematic diagram of the structure of a placement device for a design unit provided in an embodiment of the present application.

[0035] Figure 7 A schematic diagram of a standard unit generating electronic device structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0037] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0038] It should be noted that the terms used in the specification and claims of this application and the above-mentioned drawings are only used to describe the embodiments and are not intended to limit the scope of this application. It should be understood that the terms "include", "comprises", "having", etc., when used in this article, specify the existence of the stated features, wholes, steps, operations, elements, components and / or their groups, but do not exclude the existence or addition of one or more of other features, wholes, steps, operations, elements, components and / or their groups.

[0039] It will be further understood that, although the terms "first", "second", "third", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present invention, the first element may be referred to as the second element. Similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0041] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0042] It should be understood that, in the present application, “at least one (item)” means one or more, and “more than one” means two or more.

[0043] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0044] Integrated Circuit (IC) is a microelectronic device that uses a specific process to integrate transistors, resistors, capacitors, inductors and other components and wiring on a small semiconductor chip or dielectric substrate and encapsulates it in a tube shell. It can realize circuit functions and has the characteristics of miniaturization, high performance and low power consumption. It can be classified according to function, integration level, manufacturing process, etc.

[0045] FinFET process: FinFET process is an advanced semiconductor manufacturing process. FinFET (Fin Field-Effect Transistor) refers to fin field-effect transistors. In this process, a raised fin-shaped structure is manufactured on the substrate as the channel of the transistor, and the gate surrounds the three sides of the fin. This unique three-dimensional structure can more effectively control the current in the channel, reduce leakage, and significantly improve device performance and integration. It is widely used in advanced processes and is one of the key process technologies for achieving smaller size, higher performance, and lower power consumption in modern integrated circuit manufacturing.

[0046] Standard Cell: Standard Cell (STDCell) refers to a basic unit module with certain logical functions that has been pre-designed, optimized and exists in a specific layout form, such as AND gate, OR gate, NOT gate, trigger, etc. These standard cells have fixed sizes and electrical characteristics, and they are widely used in very large-scale integrated circuit (VLSI) design. Designers can select appropriate cells from the existing standard cell library according to the functional requirements of the circuit, and combine and connect them according to certain rules, so as to quickly build a complex integrated circuit system.

[0047] Macrocell: Macrocell is a concept widely used in integrated circuit design and programmable logic device (PLD) design. It is a relatively large, pre-designed functional unit that can be used as a whole in a higher-level design, thereby simplifying the complex circuit design process.

[0048] Figure 1 A schematic diagram of an implementation environment in which the technical solution of the embodiments of the present application can be applied is shown.

[0049] like Figure 1 As shown, the implementation environment includes one or more terminal devices 101, 102, 103, a network 104 and a server 105. The network 104 is used to provide a medium for a communication link between the terminal devices 101, 102, 103 and the server 105.

[0050] The network 104 may be any suitable combination of one or more wired and / or wireless networks. For example, the network 104 may include any one or more of the following: the Internet, an intranet, a wide area network (WAN), a local area network (LAN), a wireless network, a digital subscriber line (DSL) network, a frame relay network, an asynchronous transfer mode (ATM) network, a virtual private network (VPN), and / or any other suitable communication network.

[0051] Optionally, the server 105 is an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. Optionally, the terminal devices 101, 102, and 103 can be smart phones, tablet computers, laptops, desktop computers, smart speakers, smart watches, etc., but are not limited to these.

[0052] Those skilled in the art will appreciate that the number of the terminal devices may be more or less. For example, the terminal device may be only one, or the terminal devices may be dozens or hundreds, or more. The embodiment of the present application does not limit the number and type of terminal devices.

[0053] The placement method of the design unit provided in the embodiment of the present application is generally executed by the server 105, and accordingly, the placement device of the design unit is generally set in the server 105. It can be understood that the placement method of the design unit can also be executed by the terminal devices 101, 102, and 103, and accordingly, the placement device of the design unit is set in the terminal devices 101, 102, and 103.

[0054] It should be noted that Figure 1 The schematic diagram of the scenario for applying the method for placing the design unit shown is merely an example. The application of the method for placing the design unit and the scenario described in the embodiment of the present application are intended to more clearly illustrate the technical solution of the embodiment of the present application, and do not constitute a limitation on the technical solution provided in the embodiment of the present application. A person of ordinary skill in the art can appreciate that with the evolution of the application of information methods and the emergence of new business scenarios, the technical solution provided in the embodiment of the present application is equally applicable to similar technical problems.

[0055] It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0056] Figure 2 A flowchart of a method for placing a design unit according to an embodiment of the present application is shown. The method for placing a design unit can be executed by a terminal device, which can be Figure 1 The terminal devices 101, 102, 103 shown in FIG. 1 , of course, the placement method of the design unit can also be executed by the server, for example, Figure 1 Refer to the server 105 shown in Figure 2 As shown, the placement methods of the design unit include:

[0057] Step S110, generating a placement area according to design input parameters of the target integrated circuit;

[0058] Step S120, placing the boundary cells at the boundaries of the placement area according to the definition of the boundary cells in the library exchange format file, and dividing the placement area into a plurality of placement grids;

[0059] Step S130, placing all standard cells and all macro cells in each placement grid according to the target optimization function, and inserting cells for power consumption optimization and cells for timing optimization into corresponding positions in the placement grid;

[0060] Step S140: evaluate each placement grid according to the wiring pre-evaluation function to obtain an evaluation result corresponding to each placement grid. If the evaluation result does not meet the preset requirements, optimize the evaluation result until the evaluation result meets the preset requirements.

[0061] Step S150: After the optimization is completed, if there is a blank area in the placement area, a filling unit is inserted into the blank area.

[0062] These steps are described in detail below.

[0063] In step S110 , a placement area is generated according to design input parameters of a target integrated circuit.

[0064] Specifically, the target integrated circuit refers to an integrated circuit chip that is expected to be designed with specific functions, performance, and application scenarios. The design input parameters are a series of data information that are determined before the integrated circuit design work is carried out, which play a key guiding and constraining role in the design. The design input parameters here can be Core width and Core height, where Core width refers to the width of the core part of the chip, which describes the size of the core area of ​​the chip in the horizontal direction; Core height represents the height of the core part of the chip, that is, the size measurement of the core area of ​​the chip in the vertical direction. These two parameters are critical to determining the physical range of the chip core.

[0065] The placement area refers to a specific physical range on the integrated circuit design layout that is specially demarcated for placing various design units. In this embodiment, the placement area for placing various design units can be determined based on two key parameters: core width and core height.

[0066] In step S120, according to the definition of the boundary cell in the library exchange format file, the boundary cell is placed at the boundary of the placement area, and the placement area is divided into a plurality of placement grids.

[0067] In the integrated circuit chip design process, there is a specially planned placement area, and this placement area has its boundary range. The Library Exchange Format (LEF) file plays an important role here, and it has a clear definition of the boundary cells. According to such definition requirements, these boundary cells can be accurately placed at the boundary position of the placement area determined in step S110, so as to improve the layout of the chip design layout, achieve purposes such as optimizing signal integrity and improving chip electrical performance, and ensure that the entire chip design complies with the corresponding rules and subsequent production and manufacturing requirements.

[0068] It needs to be explained that the boundary cells can include TapCell (Tapping Cell) and EndCap (End-of-Row Cap Cell). TapCell is mainly used to provide good power and ground (VDD and VSS) connections in chip design. EndCap is mainly used to optimize the electrical performance at the end of the row or column of the chip layout. In the LEF file, there are many clear definitions for boundary cells such as TapCell and EndCap. As for TapCell, the connection position and method of its power (VDD) and ground (VSS) pins and the parameters of the corresponding connections will be defined, its physical dimensions such as width, height and spacing requirements with adjacent cells will be specified, and its internal transistor size, active area conditions, parasitic parameters and other process-related contents at different process nodes will be clarified; and for EndCap, its specific electrical structure and method for achieving isolation and protection functions will be explained, such as how to control edge effects, etc., and its physical dimensions such as length, width, height and spacing with adjacent cells will be limited. At the same time, the specific requirements for process compatibility such as its internal structure and manufacturing steps at specific process nodes will be clarified. These definitions are intended to ensure that they can accurately play their specific functions and roles in chip design and manufacturing.

[0069] In the design layout of the integrated circuit chip, after the boundary unit is placed at the boundary of the placement area, in order to facilitate the subsequent placement and wiring of the design unit in a more orderly and regular manner, a grid division method will be adopted to handle this placement area. Specifically, the entire placement area is divided into N grids in both the vertical and horizontal directions according to the principle of average, and the overall N×N placement grid system is formed. For example, if N is 10, it means that 10 grids are evenly divided in the horizontal and vertical directions, and a total of 100 small placement grids are obtained.

[0070] Each placement grid mentioned here has a certain capacity, that is, each such small grid can place a certain number (n) of wire tracks. The wire track can be simply understood as a "track" for the subsequent layout of various signal lines, power lines and other lines, just like a pre-planned placement channel for wires. The number of wire tracks that each placement grid can accommodate is limited to n. Through such a clear setting, the layout direction and quantity scale of the lines in the entire chip layout can be better planned, making the wiring work in the chip design process more standardized and organized, and also helping to improve the efficiency of the entire chip design and ensure the rationality of the design, so that it meets the requirements of chip functions and performance.

[0071] In step S130 , all standard cells and all macro cells are placed in each placement grid according to the target optimization function, and cells for power consumption optimization and cells for timing optimization are inserted into corresponding positions in the placement grid.

[0072] Standard cells are usually small circuit modules with basic logical functions and relatively uniform size specifications, such as common AND gates, OR gates, NOT gates and other logic gate circuit units; macro cells are larger and more complex modules, such as the computing units and storage modules in processors. They work together in chip design to achieve overall functional requirements.

[0073] In this embodiment, the standard cells and macro cells can be accurately placed in the divided placement grid by coordinate pairing assignment according to the target optimization function in an iterative manner. That is to say, each cell will correspond to a specific coordinate position (coordinates in a certain placement grid), just like marking the specific longitude and latitude coordinates of each object on the map, so that each cell has a clear and unique position on the chip layout, which is convenient for further design work such as subsequent circuit connection. Iteration means that a process will be repeated many times, and adjustments and optimizations will be made continuously until the desired effect is achieved. Here, the operation of placing standard cells and macro cells in corresponding positions is performed many times.

[0074] The objective optimization function can be in the form of a multi-objective optimization function, Softmax, exponential function, gradient function, and other functions. Here, taking the multi-objective optimization function as an example, the operation scheme for pairing and assigning values ​​according to the objective optimization function is described in detail. In the first step, the optimization objectives can be clearly defined, such as minimizing chip area, minimizing power consumption, and maximizing performance. Then, weights are assigned to each objective. Assume that the weight of chip area is w1, the weight of power consumption is w2, and the weight of performance is w3, and w1+w2+w3=1. The size of these weights reflects the relative importance of different objectives in the optimization process. For example, for a low-power chip design with extremely high power consumption requirements, the value of w2 may be set relatively large. In the second step, for each combination of a cell (STD Cell or Macro Cell) and a placement grid (i.e., each possible placement scheme), the value of the objective optimization function F1 is calculated. Assuming that for a certain placement scheme, the calculated chip area is A, the power consumption is P, and the performance is Q (the performance here can be measured by indicators such as signal delay), then the value of F1 can be expressed as F1=w1×A+w2×P+w3×Q. The third step is to traverse all possible unit-placement grid combinations and calculate their F1 values. Then select the combination with the smallest (if the goal is to minimize) or largest (if the goal is to maximize) F1 value as the optimal placement solution. Once the optimal placement solution is determined, the unit is placed in the corresponding placement grid and the coordinates (x, y) of the placement grid are assigned to the unit to complete the pairing assignment.

[0075] After all standard cells and all macro cells are placed in each placement grid, cells for power consumption optimization and cells for timing optimization may be further inserted into corresponding positions in the placement grid.

[0076] Specifically, according to the unified power constraint file (UPF), various power-related units (Power cells) such as shifters, retention registers, and isolation cells can be automatically selected from the technology database (TechDatabase) and inserted into the corresponding positions that meet the requirements to control chip power consumption and ensure the stability of circuit functions. According to the timing constraint file (Synopsys DesignConstraints, SDC), buffer cells can be automatically selected from the technology database (TechDatabase) and inserted into the corresponding positions that meet the requirements to meet the timing requirements of chip design.

[0077] To further explain, for the units used for power optimization, the design tool can first parse the Power constraint file UPF to obtain power constraint details such as power consumption limits of each module and power management strategies. Then, select Power cells in TechDatabase: for Shifter, select low power consumption and timing based on data processing requirements; RetentionRegister is selected based on data retention time and read and write power consumption requirements; Isolation Cell is selected based on isolation requirements and power consumption conditions. Finally, the insertion point is determined according to the UPF power consumption strategy and circuit function, such as Shifter is placed in the data path, Retention Register is placed at the key register end, and Isolation Cell is placed in the power domain or between easily interfered modules. The design tool then completes the insertion according to the layout rules with an automated script or algorithm, and connects the pins and peripheral circuits. For the units for timing optimization, the Buffer Cell can be inserted into the corresponding position according to the Clock Tree Synthesis (CTS) algorithm. Specifically, first, extract information such as clock frequency, waveform, and timing path delay from the SDC file. Then, plan the clock tree structure based on the chip layout and the distribution of synchronous components, and simulate and calculate its delay and skew. Next, where the clock signal path is long or the strength needs to be enhanced, select the appropriate Buffer Cell according to TechDatabase to insert it, so that its input is connected to the previous stage clock line and its output is connected to the next stage or register clock pin, while considering the layout and connection. Finally, verify the clock tree performance. If the timing constraints are not met, adjust the Buffer Cell type, quantity or position. After multiple iterations, a compliant clock tree is built.

[0078] In some embodiments of the present application, the method of placing all standard cells and all macro cells in each placement grid according to the target optimization function can specifically include: first, placing each standard cell and each macro cell at any coordinate point in the placement area; then, according to the target optimization function, re-placing all standard cells and all macro cells until the cell density in each placement grid reaches a preset threshold; wherein the input of the target optimization function is the semi-perimeter line length, and the output of the target optimization function is the placement coordinates of each standard cell and each macro cell in the placement area.

[0079] Specifically, this includes the initial placement operation and the re-placement based on the target optimization function. Among them, the first step is to perform a relatively random initial placement. This means that at the beginning, not too many optimization factors are considered, but all these units are simply randomly placed in the previously delineated chip design placement area. Each unit first occupies a coordinate position, just like placing various parts randomly in a site where things are ready to be built, in preparation for subsequent fine-tuning. Next, these standard units and macro units that have been preliminarily placed should be re-layouted and placed according to the target optimization function. This target optimization function plays a key guiding role here, and its purpose is to make the layout of the entire chip more reasonable and efficient.

[0080] Specifically, in the process of continuous re-placement, the cell density in each placement grid must reach the preset threshold. As mentioned earlier, the placement area of ​​the chip is divided into placement grids, and the cell density refers to the number of standard cells and macro cells placed in each placement grid. The preset threshold is a reasonable cell quantity standard that is pre-set at the beginning of the design based on multiple factors such as the chip's function, performance, and manufacturing process. For example, it is stipulated that a maximum of 5 cells can be placed in a certain placement grid.

[0081] By continuously adjusting the placement of cells according to the target optimization function, the number of cells in each placement grid is balanced so that it gradually approaches the preset reasonable density standard. This helps to achieve efficient use of the chip layout space, avoiding situations where some areas are too crowded and some areas are too empty. It also has a positive impact on subsequent wiring and other operations, ensuring the overall performance and manufacturability of the chip.

[0082] In this embodiment, relocation based on the target optimization function is achieved through the input and output of the target optimization function. Specifically, the input of the target optimization function is the half-perimeter wire length. The half-perimeter wire length (HPWL) is a commonly used measurement indicator in chip design layout. It mainly reflects the length of the wiring by calculating the half-perimeter of the rectangle surrounded by the wires around a unit or a group of units. In simple terms, it is a quantitative parameter of the line length when the unit is connected to the periphery. For example, the wires around a unit form a rectangle with a length of 10 and a width of 8, then its half-perimeter wire length is (10 + 8) ÷ 2 = 9. The target optimization function will use this half-perimeter wire length as an important reference data to comprehensively evaluate the impact of the current unit placement position on the wiring length and the rationality of the overall layout.

[0083] After a series of calculations and evaluations, the target optimization function will eventually determine where each standard cell and macro cell should be placed in the entire placement area, that is, output their corresponding coordinate positions (such as coordinates (x, y)). This will guide these cells from the initial random placement state to gradually adjust to the final placement position that meets the optimization requirements, completing the optimization process of the layout link in chip design, and laying a good foundation for subsequent further circuit connection, physical implementation and other steps.

[0084] In step S140, each placement grid is evaluated according to the wiring pre-evaluation function to obtain an evaluation result corresponding to each placement grid. If the evaluation result does not meet the preset requirements, the evaluation result is optimized until the evaluation result meets the preset requirements.

[0085] In integrated circuit design, the wiring pre-evaluation function plays a key role. It is a tool that measures the chip placement grid based on specific rules and algorithms. For each placement grid that has been divided, this function will be used to analyze its relevant characteristics. For example, many factors will be considered, such as the number and type of circuit units placed in the placement grid, the complexity of the connection lines of these units, and the estimated required wiring space. By comprehensively considering these aspects, the evaluation result corresponding to each placement grid is obtained. This result can intuitively reflect the situation that the placement grid may face in the subsequent wiring link, such as whether it is easy to route, whether the routing will be too crowded, etc.

[0086] Once the evaluation results of each placement grid are obtained, they must be compared with the preset requirements. The preset requirements are the wiring-related standards determined at the beginning of chip design based on factors such as the overall function, performance, and manufacturing process of the chip. For example, it is stipulated that the wiring congestion level in each placement grid cannot exceed a certain value, and the signal transmission delay must be controlled within a certain range. If the evaluation results of a placement grid do not meet these preset requirements, it means that there is a problem with the wiring of the grid and it needs to be optimized.

[0087] The optimization process is not achieved overnight, but is a continuous process. The evaluation results will be improved by adjusting the layout of cells in the placement grid, changing the route planning of the lines, or adopting some special routing strategies. Then the routing pre-evaluation function is used for evaluation again, and this operation is repeated until the evaluation results corresponding to each placement grid can meet the preset requirements. Only in this way can the subsequent actual routing work be carried out smoothly and the overall chip design can meet the expected functional and performance standards.

[0088] In step S150, after the optimization is completed, if there is a blank area in the placement area, a filling unit is inserted into the blank area.

[0089] In the integrated circuit design layout, after a series of placement operations on standard cells, macro cells, cells for power optimization, and cells for timing optimization, there are often some unoccupied spaces, which are the so-called "blank placement areas". If these blank areas are not properly handled, they may have an adverse effect on the performance and manufacturing process of the chip, such as affecting the physical stability of the chip or causing abnormal signal transmission, so they need to be reasonably utilized and filled.

[0090] TechDatabase plays an important role here, storing detailed information about FillerCell. FillerCell is a special cell used to fill blank areas, with different sizes, electrical characteristics, physical structures and other properties. The database will clearly record the specific specifications of each FillerCell, such as the width and height of a FillerCell, its power consumption, the degree of impact on the signal, and its performance under different process steps. This information provides comprehensive data support for the subsequent selection of the appropriate FillerCell.

[0091] In order to select the most suitable ones for filling the blank area from many types of FillerCells, a variety of optimization algorithms can be used, such as dynamic optimization, simulated annealing, numerical analysis, genetic algorithm, large language model (LLM), etc.

[0092] The dynamic optimization algorithm will dynamically adjust and select the appropriate size of FillerCell for filling according to the real-time status of the blank area and some current dynamic changing factors of the entire chip design, such as the impact of the placed cells on the surrounding blank areas, the different filling requirements at different locations, etc., and seek the optimal filling solution in the ever-changing process to achieve efficient use of the blank area.

[0093] The simulated annealing algorithm simulates the solid annealing process in physics. When selecting FillerCell filling, it allows a certain probability to accept some choices that may not be optimal temporarily but help to jump out of the local optimal solution. Through the continuous "cooling down" (adjusting the selection strategy) process, the global optimal filling method is gradually found to avoid falling into the local optimum and missing the overall better filling effect. It is like finding the lowest point in a complex terrain to place an object. This is the way to find the most suitable way to fill the blank area.

[0094] The numerical analysis algorithm will analyze and calculate the relevant numerical parameters of various FillerCells (such as size values, electrical parameter values, etc.) and establish a mathematical model to evaluate the advantages and disadvantages of different filling schemes. For example, based on the area value of the blank area and the electrical parameter values ​​of the surrounding circuits, the numerical results of the impact of different sizes of FillerCell filling on the overall circuit performance are calculated, and then the optimal filling scheme is selected.

[0095] The genetic algorithm regards different FillerCell filling schemes as "individuals" that form a "population". By simulating operations such as selection, crossover, and mutation in biological genetics, good filling schemes (excellent "genes") can be inherited and combined for optimization. After many generations of "evolution", the FillerCell filling scheme that can best adapt to the blank area is finally selected. Just like organisms evolve the characteristics that are most adaptable to the environment, here we get the most suitable filling method for the blank area.

[0096] LLM can use its powerful language understanding and logical reasoning capabilities to conduct a comprehensive analysis of the overall requirements of chip design, the characteristics of the blank area, and various information of FillerCell. Based on a large amount of text knowledge and pre-trained rules, it can give reasonable suggestions on what size FillerCell to choose to fill the blank area, and help find the optimal filling strategy.

[0097] After the FillerCell filling of the blank placement area is completed using the optimization algorithm, the final result, which includes the layout of the filled layout, the specific location of each FillerCell and related properties, needs to be saved in the design database (DesignDatabase). In this way, when further analyzing, verifying or manufacturing the chip, the relevant filling result information can be easily retrieved from this database to ensure the continuity of the entire chip design process and the traceability of the data, providing a complete and accurate data foundation for the chip to smoothly move from design to manufacturing.

[0098] Based on the technical solution provided in the above embodiment, the placement area is accurately generated based on the design input parameters, and the boundary units are properly placed in strict accordance with the definition of the boundary units in the library exchange format file, and then the placement area is scientifically divided into multiple placement grids. In this way, an orderly layout architecture is constructed, which significantly improves the utilization efficiency of the layout space. By avoiding the disorder of the layout, the cost increase caused by unreasonable layout is effectively reduced, and at the same time, the manufacturability of the layout is effectively enhanced, laying a solid foundation for the smooth advancement of the chip manufacturing process.

[0099] With the help of the target optimization function, the standard cells and macro cells are reasonably laid out, and the cells for power optimization and timing optimization are accurately inserted at the appropriate positions. This process effectively resolves a large number of complex design rule checks and thorny problems such as three-dimensional wiring congestion under the FinFET process. From the perspective of performance optimization, fine-grained control of chip power consumption and timing is achieved, significantly improving the overall performance of the chip. In terms of layout characteristics, the rationality and compliance of the layout are further consolidated, and the probability of design rule check (DRC) violations is greatly reduced, thereby significantly improving the success rate and stability of chip design.

[0100] Use the wiring pre-evaluation function to carry out comprehensive evaluation and in-depth optimization. This rigorous optimization process completely avoids the drawbacks of the traditional process that DRC violations are difficult to eradicate and the chip design area is too redundant. From the perspective of manufacturability, it directly improves the manufacturability level of the layout and reduces the cost of repeated manufacturing processes and corrections due to design defects. From the perspective of the design process, it effectively guarantees the efficient and smooth operation of the chip design process, and comprehensively improves the quality level and operational efficiency of chip design, so that it can accurately meet the stringent requirements and complex needs of integrated circuit design under the FinFET process, and provides a solid technical support and guarantee mechanism for the research and development and manufacturing of high-performance, high-quality integrated circuits.

[0101] In some embodiments of the present application, after all standard cells and all macro cells are placed in each placement grid according to the target optimization function, a normalization operation may be performed on all standard cells and all macro cells, such as Figure 3 As shown, it may specifically include steps S310 to S330, which are described in detail as follows:

[0102] Step S310: Generate a three-dimensional linear track grid according to the library exchange format file.

[0103] Library exchange format files (usually such as LEF files, etc.) are extremely critical information carriers in integrated circuit design. They cover many detailed contents about the physical characteristics of circuit units and wiring rules. For example, it will clearly describe the relevant parameters of different metal layers (such as the M1 metal layer and its corresponding Width and Pitch rules), and will also specify the physical properties such as the shape, size, and pin position of various units, providing standard specifications for the layout and wiring of the entire chip layout. It is an important basis for subsequent design work, which is equivalent to drawing a detailed "design blueprint" for building the integrated circuit layout.

[0104] Since integrated circuits are multi-layer stacked three-dimensional structures with multi-layer metal wiring and stacked units with different functions, the wire track grid is constructed in three-dimensional space based on the wiring rules of each metal layer (from the bottom M1 to the top metal layers) and the layout rules of each functional layer in the library exchange format file. This three-dimensional wire track grid generated based on the library exchange format file ensures that the entire design process follows a unified standard that meets process requirements, avoids various design violations and signal transmission problems caused by arbitrary layout and wiring, helps to improve the quality of chip design, and ensures that the final generated chip layout can be smoothly put into the manufacturing production link.

[0105] Step S320 , normalizing the placement coordinates of each standard cell and each macro cell according to the coordinates in the three-dimensional track grid, so that the ordinate of each standard cell and each macro cell is the same as the ordinate of the corresponding abscissa in the three-dimensional track grid.

[0106] The three-dimensional linear track grid constructs a standard spatial reference framework for the placement of various types of units, with a clear coordinate system. As important components of the chip layout, standard cells and macro cells may have different and irregular placement coordinates. The purpose of normalization is to make the placement of these units more orderly and unified, so that they can better fit the established layout framework of the three-dimensional linear track grid. Specifically, it is necessary to achieve that the vertical coordinate of each standard cell and the vertical coordinate of each macro cell are consistent with the vertical coordinate of the corresponding horizontal coordinate position in the three-dimensional linear track grid, so that the vertical positions of all cells can be aligned according to a unified standard, so that the entire layout is more regular and regular, which is convenient for subsequent wiring, signal transmission and other related operations.

[0107] Specifically, it is necessary to check the existing placement coordinates of each standard unit and macro unit according to the coordinate system set by the three-dimensional linear track grid. Then, for the horizontal coordinate of each unit, find the corresponding horizontal coordinate position in the three-dimensional linear track grid, and then adjust the vertical coordinate of the unit to the vertical coordinate value of the corresponding horizontal coordinate position. For example, if the original horizontal coordinate of a standard unit corresponds to a horizontal coordinate position in the three-dimensional linear track grid, and its vertical coordinate does not match it, through this normalization operation, the vertical coordinate of the standard unit will be modified to the vertical coordinate of the corresponding horizontal coordinate position in the three-dimensional linear track grid, and the macro unit is operated in the same way. In this way, the vertical position of each unit is standardized and unified according to the coordinate rules of the three-dimensional linear track grid, eliminating the chaotic vertical coordinate differences that may have existed.

[0108] This normalization operation is of great significance for integrated circuit layout design. On the one hand, it makes the layout more neat and orderly, and the entire layout structure is clearer from a visual point of view, which is convenient for designers to view, analyze, and further adjust and optimize the layout. On the other hand, in terms of actual circuit function realization, the regular unit vertical coordinate can better ensure the accurate and efficient transmission of signals along the vertical direction between different units, reduce signal interference and delay caused by uneven unit positions, and also help to produce and process chips more accurately according to the design layout in the manufacturing process, thereby improving the success rate of chip manufacturing and the quality of the final chip product.

[0109] Step S330: If multiple units are placed on the same placement coordinate, move the redundant units so that only one unit is placed on the same placement coordinate. The multiple units are multiple standard units or multiple macro units or include at least one standard unit and at least one macro unit.

[0110] In integrated circuit layout design, each cell (including standard cells and macro cells) has its corresponding placement coordinates to determine their positions in the entire layout space. However, sometimes there is a situation where multiple cells are placed on the same placement coordinate, which may be caused by various arrangements or misoperations during the design process. However, from the perspective of the rationality of the layout and the smoothness of subsequent operations (such as wiring, signal processing, etc.), it is usually required to place only one cell on the same placement coordinate. Therefore, when there is a situation where multiple cells are placed on the same coordinate, corresponding measures need to be taken to adjust.

[0111] Once multiple cells are found at the same placement coordinate, no matter whether these cells are multiple standard cells, multiple macro cells, or a mixture of at least one standard cell and at least one macro cell, the redundant cells must be moved. For example, if three standard cells are placed at a certain coordinate point at the same time, it is necessary to select two of them and move them to other suitable and free coordinate positions based on the layout planning of the entire layout, the distribution of surrounding cells, and wiring resources, to ensure that only one cell is left at the coordinate position where there were originally multiple cells. The purpose of this is to ensure that each coordinate position has a clear and unique corresponding cell, to avoid layout confusion caused by multiple cells being squeezed together, and to affect subsequent circuit function implementation and layout-related operations.

[0112] In some embodiments of the present application, Figure 4 As shown, step S330 may specifically include steps S410 to S420, which are specifically described as follows:

[0113] Step S410: If multiple units are placed on the same placement coordinate, a target coordinate position is determined in the placement area, and a moving distance between the target coordinate position and the placement coordinate is the smallest.

[0114] In integrated circuit layout design, each unit has its corresponding placement coordinates to determine its specific position in the layout. However, sometimes multiple units are placed on the same placement coordinate, which does not meet the ideal layout specifications and is likely to cause a series of subsequent problems such as complex wiring and signal interference, so the redundant units need to be relocated. The purpose of determining the target coordinate position is to solve this problem. The core goal is to find a target coordinate position in the entire placement area, and the moving distance between the target coordinate position and the placement coordinate where multiple units appear is minimized. The moving distance here can be ΔHPWL (Half-Perimeter Wire Length). ΔHPWL is often used to measure the impact of unit layout on wiring length and other aspects. Minimizing it helps optimize the layout wiring and overall performance.

[0115] When multiple cells are found on the same placement coordinate, it is necessary to start searching and evaluating in the placement area. It will traverse the many available free coordinate positions in the placement area, and for each potential target coordinate position, calculate the ΔHPWL between it and the placement coordinate where multiple cells exist. This calculation usually involves a comprehensive consideration of factors such as the wiring length that may be affected by the change in cell layout, and calculates the specific value according to the corresponding algorithm or rule. Then, by comparing the ΔHPWL values ​​corresponding to different target coordinate positions, the coordinate position with the smallest value is selected and determined as the final target coordinate position, which is the most suitable place to move the redundant cells. This can minimize the impact on the wiring and the rationality of the overall layout when adjusting the cell layout.

[0116] From the perspective of layout, selecting the target coordinate position with the smallest moving distance ΔHPWL can maintain the compactness and rationality of the original layout to the greatest extent, avoid large-area layout structure changes caused by unit movement, and reduce unnecessary waste of wiring resources and the resulting increase in wiring complexity. From the perspective of circuit performance, a smaller ΔHPWL means that the path length of signal transmission changes relatively little, which helps to reduce signal delays, reduce power consumption, and ensure the efficiency and stability of signal transmission within the chip, thereby improving the performance and working reliability of the entire chip.

[0117] Step S420: Move the redundant units to the target coordinate position so that only one unit is placed at the same placement coordinate.

[0118] After the target coordinate position is selected, the redundant cells can be moved from the originally crowded placement coordinates to the selected target coordinate position, thereby achieving an ideal layout state where only one cell remains at the same placement coordinate. This helps to optimize the layout structure, reduce signal interference, reduce wiring complexity, and improve the overall performance and reliability of the chip.

[0119] In some embodiments of the present application, after inserting the unit for power consumption optimization into the corresponding position in the placement grid, a normalization operation on the unit for power consumption optimization may be performed, which may specifically include: first, the position coordinates of the unit for power consumption optimization in the placement grid may be normalized according to the coordinates in the three-dimensional linear track grid, so that the vertical coordinate in the position coordinates of the unit for power consumption optimization is the same as the vertical coordinate of the corresponding horizontal coordinate in the three-dimensional linear track grid; then, if multiple units for power consumption optimization are placed at the same position coordinates, the redundant units for power consumption optimization are moved, so that only one unit for power consumption optimization is placed at the same position coordinates. The normalization operation here is the same as Figure 3 The normalization operation in the illustrated embodiment is similar and will not be described in detail here.

[0120] In some embodiments of the present application, after the unit for timing optimization is inserted into the corresponding position in the placement grid, a normalization operation of the unit for timing optimization can also be performed, which can specifically include: first, the position coordinates of the unit for timing optimization in the placement grid can be normalized according to the coordinates in the three-dimensional linear track grid, so that the vertical coordinate in the position coordinates of the unit for timing optimization is the same as the vertical coordinate of the corresponding horizontal coordinate in the three-dimensional linear track grid; then, if multiple units for timing optimization are placed at the same position coordinates, the redundant units for timing optimization are moved so that only one unit for timing optimization is placed at the same position coordinates. The normalization operation here is the same as Figure 3 The normalization operation in the illustrated embodiment is similar and will not be described in detail here.

[0121] In some embodiments of the present application, Figure 5 As shown, the step of evaluating each placement grid in step S140 may specifically include steps S510 to S520, which are described in detail as follows:

[0122] Step S510, evaluate each placement grid according to the routing pre-evaluation function to obtain an evaluation value corresponding to each placement grid output by the routing pre-evaluation function, wherein the input of the routing pre-evaluation function is the semi-perimeter line length, cell density related parameters in the placement grid, and routing congestion estimation related parameters.

[0123] In order to scientifically and comprehensively evaluate the routing status of each placement grid, a routing pre-evaluation function can be established. This function is like an accurate "ruler" that aims to consider the situations that each placement grid may face in subsequent routing from multiple dimensions, thereby providing designers with a clear reference to make targeted optimization decisions for different placement grids and ensure the rationality and efficiency of the entire chip layout routing work.

[0124] There are many optional function forms for the wiring pre-evaluation function, such as multi-objective optimization function, Softmax, exponential function, gradient function, etc. Different function forms have their own characteristics and applicable scenarios. For example, the multi-objective optimization function can take into account multiple different evaluation goals at the same time, and comprehensively weigh various factors to give an evaluation result, which is very suitable for wiring, which involves considering multiple key factors; the Softmax function can normalize data of different dimensions, so that the weight of the influence of each input parameter on the result can be more reasonably reflected; the exponential function has an advantage in reflecting the nonlinear change trend of certain parameters on wiring; the gradient function can analyze the gradient of parameter changes and gain insight into the sensitivity of wiring conditions to parameter changes.

[0125] The input of the routing pre-evaluation function can be HPWL, parameters related to the cell density in the placement grid, and parameters related to routing congestion estimation. Among them, HPWL reflects the approximate length of the connection required when routing in the unit placement grid. The length of the connection is closely related to the distance of signal transmission and the degree of occupation of routing resources. It is an important indicator for measuring the complexity and resource requirements of routing. For example, a larger HPWL value means that the line may be longer during routing, requiring more routing space and more reasonable layout planning to avoid problems such as signal delay.

[0126] The parameters related to the density of cells in the unit placement grid include the number of cell pins, the number of cells, the cell pin area, and the calculation of the pin shape characteristics of the FinFET process cell. Cell density reflects the density of the cell distribution in the placement grid, and its related parameters characterize this characteristic from different angles. A large number of cell pins means that there are more lines that need to be connected, which has a greater impact on the complexity of wiring; a large number of cells directly indicates that the density of the cells is high, and the wiring space will be relatively tight; the size of the cell pin area affects the space occupation and connection relationship with the surrounding area during wiring; and the unique cell pin shape characteristics under the FinFET process will also change the direction and difficulty of wiring. Combining these factors can comprehensively evaluate the wiring pressure based on the cell situation in the grid.

[0127] The parameters related to the estimation of wiring congestion in a unit placement grid specifically include the number of multi-level horizontal track grids in the FinFET process, the number of multi-level vertical track grids in the FinFET process, the number of pins, the number of obstacles, the number of PDNs (power distribution networks), etc. The number of multi-level track grids under the FinFET process determines the basic framework and space resources of the wiring. The number of horizontal and vertical track grids affects the layout direction and scalability of the line; the number of pins, as mentioned above, is related to the complexity of the line connection; the number of obstacles reflects the number of factors that may hinder the normal wiring, such as some special fixed structures that will limit the wiring path; the number of PDNs is related to the distribution of power lines, and their number and layout will affect the rationality of the overall wiring and whether it is easy to have line congestion. Combining these parameters can effectively estimate the degree of wiring congestion that may occur in the future in the placement grid.

[0128] Based on the above rich and critical input parameters, the routing pre-evaluation function will output the corresponding evaluation value for each placement grid. This evaluation value is a comprehensive quantitative reflection of the routing situation of the placement grid. It can intuitively show whether a certain placement grid is relatively easy and reasonable in routing, or faces great difficulties and challenges. For example, a higher evaluation value often means that the placement grid may encounter problems such as too dense lines, tight routing space, and easy congestion during routing, prompting designers to pay attention and take corresponding optimization measures, such as adjusting the unit layout, optimizing the track grid, etc.; while a lower evaluation value means that the placement grid is relatively smooth in routing, and the routing resources are relatively matched with the demand, without too much additional adjustment intervention. Through such an evaluation value, designers can reasonably optimize each placement grid in a targeted manner to ensure that the entire chip layout can ultimately achieve high-quality routing effects and guarantee the normal function and performance of the chip.

[0129] Step S520, construct a three-dimensional solution surface according to the evaluation value corresponding to each placement grid and the number of each placement grid in the placement area, and use the curvature of the three-dimensional solution surface and the evaluation value corresponding to each placement grid as the evaluation result corresponding to each placement grid.

[0130] The evaluation value corresponding to each placement grid is obtained through the wiring pre-evaluation function. At the same time, each placement grid has a corresponding number in the placement area. These two become the key elements for constructing a three-dimensional solution surface. The number of the placement grid can be regarded as the coordinate position on the plane, and the evaluation value is equivalent to the "height" value corresponding to this coordinate position. Based on this correspondence, just like shaping the terrain according to the different altitudes (evaluation values) of each location (placement grid) on a two-dimensional map (placement area plane), this information is integrated to construct a three-dimensional solution surface, so as to more intuitively and comprehensively present the comprehensive situation of each placement grid in terms of wiring and their relationship with each other.

[0131] After the three-dimensional solution surface is constructed, its curvature becomes an important characteristic indicator. The curvature of the surface reflects the degree of bending of the surface at different positions. In this context, it can reflect the changing trend and correlation characteristics of the wiring evaluation between the placed grids. For example, an area with a large curvature means that the evaluation value of the corresponding placed grid changes more drastically locally, which may indicate that there are obvious differences in the wiring conditions around these grids, or that the wiring difficulty has changed significantly from one grid to the adjacent grid; while an area with a small curvature indicates that the evaluation value of the placed grid is relatively stable, and the surrounding grids are relatively similar in terms of wiring, with little change. By analyzing the curvature, we can grasp the complexity and changing rules of the wiring conditions in the entire placement area as a whole.

[0132] Finally, the curvature of the three-dimensional solution surface and the evaluation value corresponding to each placement grid obtained previously are taken together as the evaluation result corresponding to each placement grid. This is done because a single evaluation value can only reflect the routing difficulty of the grid itself, and combined with the curvature of the surface, it can further consider its relationship with the surrounding grids and the change trend, making the evaluation result more comprehensive and three-dimensional. Based on such comprehensive evaluation results, designers can more accurately understand the actual status of each placement grid in the entire layout wiring, so as to take targeted optimization measures, such as focusing on grids with large curvature changes and high evaluation values ​​and adjusting their unit layout, optimizing wiring schemes, etc., to ensure that the entire chip layout wiring work is completed smoothly and efficiently.

[0133] In some embodiments of the present application, the evaluation results are optimized until the evaluation results meet preset requirements, which may specifically include adjusting the positions of all standard cells, all macro cells, cells for power consumption optimization, and cells for timing optimization within the placement grid until the curvature of the three-dimensional solution surface is zero and the evaluation value corresponding to each placement grid is the minimum.

[0134] After obtaining the evaluation results corresponding to each placement grid, if the evaluation results do not meet the preset requirements, the evaluation results need to be optimized until they meet the preset requirements. The preset requirements here are clearly to make the curvature of the three-dimensional solution surface zero, and to minimize the evaluation value corresponding to each placement grid. The reason for setting such a goal is that the curvature of zero means that the wiring conditions in the entire placement area change smoothly and evenly between the grids, without obvious differences or mutations, and the minimum evaluation value means that the wiring difficulty of each grid itself is in the optimal state, which can ensure that the wiring of the entire chip layout is the most reasonable and efficient, and the overall performance can also reach a good level.

[0135] In order to achieve the above optimization goals, the main method is to adjust the positions of various units placed in the grid, such as all standard units, all macro units, and units used for power optimization and timing optimization. This position adjustment is not done randomly, but is achieved with the help of some advanced and effective optimization algorithms. For example, the simulated annealing algorithm simulates the solid annealing process, and gradually approaches the optimal solution by continuously accepting or discarding some solutions in the search space, which helps to find a solution that makes the evaluation result better among many possible unit position combinations; the genetic algorithm draws on the inheritance and mutation mechanisms in biological evolution, and screens, crosses, and mutates different "populations" of unit positions, and continuously evolves position configurations that are more in line with the optimization goals; numerical analysis uses mathematical calculations and analysis to accurately explore the optimal position; the conjugate gradient algorithm uses the gradient information of the function to efficiently find the descent direction, and promotes the unit position to adjust in the direction that can reduce the evaluation value and change the surface curvature; there is also LLM (the related ideas of large language models may be used to analyze and process some complex layout logic and rule constraints, etc.), these algorithms start from different angles and provide powerful tools and methods for the reasonable adjustment of unit positions.

[0136] Continue to use these algorithms to adjust the unit position and continuously optimize the evaluation results until the curvature of the three-dimensional solution surface is zero and the evaluation value corresponding to each placement grid is the minimum preset requirement, which is of great significance to the entire integrated circuit layout design. It can maximize the optimization of the wiring situation in the layout, reduce wiring congestion, reduce signal transmission delay, and improve the power consumption and timing performance of the chip, so that the chip can run more stably and efficiently after subsequent manufacturing and production. At the same time, it also ensures that the entire chip design from layout layout to wiring planning is in a high-quality and expected state, which improves the success rate of chip design and the competitiveness of the product.

[0137] In a second aspect, the present application also proposes a placement device for a design unit, such as Figure 6As shown, it includes: a generating unit 601 , a first placing unit 602 , a second placing unit 603 , an evaluating unit 604 and an inserting unit 605 .

[0138] Among them, the generation unit 601 is configured to generate a placement area according to the design input parameters of the target integrated circuit; the first placement unit 602 is configured to place the boundary cell at the boundary of the placement area according to the definition of the boundary cell in the library exchange format file, and divide the placement area into multiple placement grids; the second placement unit 603 is configured to place all standard cells and all macro cells in each of the placement grids according to the target optimization function, and insert the cells for power consumption optimization and the cells for timing optimization into the corresponding positions in the placement grids; the evaluation unit 604 is configured to evaluate each of the placement grids according to the wiring pre-evaluation function to obtain the evaluation result corresponding to each of the placement grids, and if the evaluation result does not meet the preset requirements, optimize the evaluation result until the evaluation result meets the preset requirements; the insertion unit 605 is configured to insert a filling cell in the blank area if there is a blank area in the placement area after the optimization is completed.

[0139] In some embodiments of the present application, the second placement unit 603 is further configured to place each of the standard cells and each of the macro cells at any coordinate point within the placement area; according to the target optimization function, all of the standard cells and all of the macro cells are re-placed until the cell density within each of the placement grids reaches a preset threshold; wherein the input of the target optimization function is the semi-perimeter line length, and the output of the target optimization function is the placement coordinates of each of the standard cells and each of the macro cells within the placement area.

[0140] In some embodiments of the present application, the device also includes a normalization unit, which is configured to generate a three-dimensional linear track grid according to the library exchange format file; normalize the placement coordinates of each of the standard cells and each of the macro cells according to the coordinates in the three-dimensional linear track grid, so that the longitudinal coordinates of each of the standard cells and each of the macro cells are the same as the longitudinal coordinates of the corresponding horizontal coordinates in the three-dimensional linear track grid; if multiple cells are placed on the same placement coordinate, the redundant cells are moved so that only one cell is placed on the same placement coordinate, and the multiple cells are multiple standard cells or multiple macro cells or simultaneously include at least one standard cell and at least one macro cell.

[0141] In some embodiments of the present application, the normalization unit is further configured as: if a plurality of the units are placed on the same placement coordinate, then a target coordinate position is determined within the placement area, and a moving distance between the target coordinate position and the placement coordinate is minimized; and the redundant units are moved to the target coordinate position so that only one unit is placed on the same placement coordinate.

[0142] In some embodiments of the present application, the normalization unit is further configured to: perform normalization operation on the position coordinates of the unit for power consumption optimization in the placement grid according to the coordinates in the three-dimensional linear track grid, so that the vertical coordinate in the position coordinates of the unit for power consumption optimization is the same as the vertical coordinate of the corresponding horizontal coordinate in the three-dimensional linear track grid; if multiple units for power consumption optimization are placed at the same position coordinates, the redundant units for power consumption optimization are moved so that only one unit for power consumption optimization is placed at the same position coordinates.

[0143] In some embodiments of the present application, the normalization unit is further configured to: perform normalization operation on the position coordinates of the unit for timing optimization in the placement grid according to the coordinates in the three-dimensional linear track grid, so that the vertical coordinate in the position coordinates of the unit for timing optimization is the same as the vertical coordinate of the corresponding horizontal coordinate in the three-dimensional linear track grid; if multiple units for timing optimization are placed at the same position coordinates, move the redundant units for timing optimization so that only one unit for timing optimization is placed at the same position coordinates.

[0144] In some embodiments of the present application, the evaluation unit 604 is further configured to: evaluate each of the placement grids according to the routing pre-evaluation function to obtain an evaluation value corresponding to each of the placement grids output by the routing pre-evaluation function, wherein the input of the routing pre-evaluation function is the semi-perimeter line length, cell density-related parameters within the placement grid, and routing congestion estimation-related parameters; construct a three-dimensional solution surface according to the evaluation value corresponding to each of the placement grids and the number of each of the placement grids in the placement area, and use the curvature of the three-dimensional solution surface and the evaluation value corresponding to each of the placement grids as the evaluation results corresponding to each of the placement grids.

[0145] In some embodiments of the present application, the evaluation unit 604 is further configured to: adjust the positions of all the standard cells, all the macro cells, cells for power consumption optimization, and cells for timing optimization within the placement grid until the curvature of the three-dimensional solution surface is zero and the evaluation value corresponding to each of the placement grids is the minimum.

[0146] like Figure 7As shown, an embodiment of the present application also provides an electronic device 700, including a memory 710, a processor 720, and a computer program 711 stored in the memory 710 and executable on the processor, and when the processor 720 executes the computer program 711, the steps of any method of placing the above-mentioned design unit are implemented.

[0147] Since the electronic device introduced in this embodiment is a device used to implement a placement device of a design unit in the embodiment of the present application, based on the method introduced in the embodiment of the present application, technical personnel in this field can understand the specific implementation mode of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by technical personnel in this field to implement the method in the embodiment of the present application is within the scope of protection of this application.

[0148] In the specific implementation process, when the computer program 711 is executed by the processor, it can achieve Figures 2 to 5 Any implementation manner in the corresponding embodiments.

[0149] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0150] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0151] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0152] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0153] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0154] An embodiment of the present application also provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the process of placing the design unit in the corresponding embodiment.

[0155] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0156] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0157] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0158] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0159] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0160] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0161] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for placing a design unit, characterized in that: include: generating a placement area according to design input parameters of a target integrated circuit; According to the definition of the boundary cell in the library exchange format file, the boundary cell is placed at the boundary of the placement area, and the placement area is divided into a plurality of placement grids; Placing all standard cells and all macro cells in each of the placement grids according to the target optimization function, and inserting cells for power consumption optimization and cells for timing optimization into corresponding positions in the placement grids; According to the wiring pre-evaluation function, each of the placement grids is evaluated to obtain an evaluation result corresponding to each of the placement grids, and if the evaluation result does not meet the preset requirements, the evaluation result is optimized until the evaluation result meets the preset requirements; After the optimization is completed, if there is a blank area in the placement area, a filling unit is inserted in the blank area; Placing all the standard cells and all the macro cells in each of the placement grids according to the target optimization function includes: placing each of the standard cells and each of the macro cells at any coordinate point in the placement area; re-placing all of the standard cells and all of the macro cells according to the target optimization function until the cell density in each of the placement grids reaches a preset threshold; wherein the input of the target optimization function is the semi-perimeter line length, and the output of the target optimization function is the placement coordinates of each of the standard cells and each of the macro cells in the placement area; The method of evaluating each of the placement grids according to the wiring pre-evaluation function to obtain an evaluation result corresponding to each of the placement grids includes: evaluating each of the placement grids according to the wiring pre-evaluation function to obtain an evaluation value corresponding to each of the placement grids output by the wiring pre-evaluation function, wherein the input of the wiring pre-evaluation function is the semi-perimeter line length, cell density-related parameters within the placement grid, and wiring congestion estimation-related parameters; constructing a three-dimensional solution surface according to the evaluation value corresponding to each of the placement grids and the number of each of the placement grids within the placement area, and using the curvature of the three-dimensional solution surface and the evaluation value corresponding to each of the placement grids as the evaluation result corresponding to each of the placement grids.

2. The method according to claim 1, characterized in that The method further comprises: Generate a three-dimensional linear track grid according to the library exchange format file; Normalizing the placement coordinates of each of the standard cells and each of the macro cells according to the coordinates in the three-dimensional linear track grid, so that the ordinate of each of the standard cells and the ordinate of each of the macro cells are the same as the ordinate of the corresponding abscissa in the three-dimensional linear track grid; If multiple units are placed on the same placement coordinate, the redundant units are moved so that only one unit is placed on the same placement coordinate. The multiple units are multiple standard units, or multiple macro units, or simultaneously include at least one standard unit and at least one macro unit.

3. The method according to claim 2, characterized in that If a plurality of units are placed on the same placement coordinate, the redundant units are moved so that only one unit is placed on the same placement coordinate, including: If a plurality of the units are placed on the same placement coordinate, a target coordinate position is determined in the placement area, and a moving distance between the target coordinate position and the placement coordinate is the smallest; The redundant units are moved to the target coordinate positions so that only one unit is placed at the same placement coordinate.

4. The method according to claim 2, characterized in that: The method further comprises: Normalizing the position coordinates of the unit for power optimization in the placement grid according to the coordinates in the three-dimensional linear track grid, so that the ordinate in the position coordinates of the unit for power optimization is the same as the ordinate of the corresponding abscissa in the three-dimensional linear track grid; If a plurality of the units for optimizing power consumption are placed at the same position coordinates, the redundant units for optimizing power consumption are moved so that only one unit for optimizing power consumption is placed at the same position coordinates.

5. The method according to claim 2, characterized in that: The method further comprises: Normalizing the position coordinates of the unit for timing optimization in the placement grid according to the coordinates in the three-dimensional linear track grid, so that the ordinate in the position coordinates of the unit for timing optimization is the same as the ordinate of the corresponding abscissa in the three-dimensional linear track grid; If a plurality of the units for timing optimization are placed at the same position coordinates, the redundant units for timing optimization are moved so that only one unit for timing optimization is placed at the same position coordinates.

6. The method according to claim 1, characterized in that Optimizing the evaluation result until the evaluation result meets the preset requirements includes: The positions of all the standard cells, all the macro cells, cells for power consumption optimization, and cells for timing optimization in the placement grid are adjusted until the curvature of the three-dimensional solution surface is zero and the evaluation value corresponding to each of the placement grids is the minimum.

7. A device for placing a design unit, characterized in that: include: A generating unit configured to generate a placement area according to design input parameters of a target integrated circuit; A first placement unit is configured to place the boundary unit at the boundary of the placement area according to the definition of the boundary unit in the library exchange format file, and divide the placement area into a plurality of placement grids; A second placement unit is configured to place all standard cells and all macro cells in each of the placement grids according to a target optimization function, and insert cells for power consumption optimization and cells for timing optimization into corresponding positions in the placement grids; An evaluation unit is configured to evaluate each of the placement grids according to a wiring pre-evaluation function to obtain an evaluation result corresponding to each of the placement grids, and if the evaluation result does not meet a preset requirement, optimize the evaluation result until the evaluation result meets the preset requirement; an inserting unit configured to insert a filling unit into the blank area if there is a blank area in the placement area after the optimization is completed; Placing all the standard cells and all the macro cells in each of the placement grids according to the target optimization function includes: placing each of the standard cells and each of the macro cells at any coordinate point in the placement area; re-placing all of the standard cells and all of the macro cells according to the target optimization function until the cell density in each of the placement grids reaches a preset threshold; wherein the input of the target optimization function is the semi-perimeter line length, and the output of the target optimization function is the placement coordinates of each of the standard cells and each of the macro cells in the placement area; The method of evaluating each of the placement grids according to the wiring pre-evaluation function to obtain an evaluation result corresponding to each of the placement grids includes: evaluating each of the placement grids according to the wiring pre-evaluation function to obtain an evaluation value corresponding to each of the placement grids output by the wiring pre-evaluation function, wherein the input of the wiring pre-evaluation function is the semi-perimeter line length, cell density-related parameters within the placement grid, and wiring congestion estimation-related parameters; constructing a three-dimensional solution surface according to the evaluation value corresponding to each of the placement grids and the number of each of the placement grids within the placement area, and using the curvature of the three-dimensional solution surface and the evaluation value corresponding to each of the placement grids as the evaluation result corresponding to each of the placement grids.

8. An electronic device, comprising: A memory and a processor, wherein the processor is used to implement the steps of the method for placing a design unit as described in any one of claims 1 to 6 when executing a computer program stored in the memory.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for placing a design unit according to any one of claims 1 to 6 are implemented.

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