Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, the display panel and the display device comprise a shift register circuit located in a display area and a plurality of first signal lines electrically connected with the shift register circuit, the first signal lines extend along a first direction and are arranged along a second direction, the first direction intersects with the second direction; the display panel further comprises an electrostatic protection circuit arranged in the display area, the electrostatic protection circuit is located on the side, facing the edge of the display panel, of the end of the first signal line in the first direction, and the end of the first signal line is electrically connected with the electrostatic protection circuit. According to the display panel, the shifting register circuit and the electrostatic protection circuit are arranged in the display area, the narrow-frame or frameless design of a display product can be achieved, in addition, the end of the first signal line is electrically connected with the electrostatic protection circuit, and the antistatic performance of the display panel can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] The effect of static electricity in the environment will have an adverse effect on the display effect of display products. Therefore, how to improve the anti-static ability of display products is one of the technical problems that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device, aiming to improve the anti-static ability of the product.

[0005] In a first aspect, the present disclosure provides a display panel, comprising a shift register circuit located in a display area and a plurality of first signal lines connected to the shift register circuit, the first signal lines extending along a first direction and arranged along a second direction, the first direction and the second direction intersecting;

[0006] The display panel further includes an electrostatic protection circuit disposed in the display area. Along the first direction, the electrostatic protection circuit is located at a side of the end of the first signal line facing the edge of the display panel, and the end of the first signal line is electrically connected to the electrostatic protection circuit.

[0007] In a second aspect, based on the same inventive concept, the present disclosure provides a display device, including the display panel provided in the first aspect of the present disclosure.

[0008] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0009] In the display panel provided by the present disclosure, the shift register circuit is arranged in the display area, and the control signal is provided to the first signal line through the shift register circuit located in the display area. At the same time, the electrostatic protection circuit is also arranged in the display area, and the shift register circuit and the electrostatic protection circuit will no longer occupy the non-display area space of the display panel. In this way, the non-display area can be not arranged in the display panel, or only the non-display area with a smaller width can be arranged, so as to realize the borderless or extremely narrow border design of the display panel. When the display panel with a borderless structure is spliced ​​to form a large-sized display panel, it is conducive to weakening the splicing seam, and it is more conducive to improving the display effect of the large-sized display panel. When the shift register circuit is arranged in the display area, in order to simplify the connection between the shift register and the first signal line and reduce the winding, the connection point of the first signal line with the shift register circuit will be located in the non-end area of ​​the first signal line. At this time, if the ends of the first signal line located at both ends along the first direction are floating, when there is static electricity in the subsequent process or use of the display panel, the static electricity will be able to act on the pixel driving circuit through the end of the first signal line, affecting the display effect of the display panel, and even possibly damaging the related circuit structure. To this end, the present invention introduces an electrostatic protection circuit in the display area, and electrically connects the end of the first signal line to the electrostatic protection circuit. When the display panel is subjected to static electricity, the static electricity will be able to be discharged through the electrostatic protection circuit to avoid affecting the display effect and circuit of the display panel, thereby helping to improve the overall anti-static ability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0012] Figure 1 Shown is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0013] Figure 2 Shown is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure;

[0014] Figure 3 Shown is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0015] Figure 4FIG. 1 is a connection diagram of a shift register circuit, a first signal line, a light emitting element, and a pixel driving circuit in an embodiment of the present disclosure;

[0016] Figure 5 Shown is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0017] Figure 6 FIG. 2 is another connection diagram of the shift register circuit, the first signal line, the light emitting element and the pixel driving circuit in the embodiment of the present disclosure;

[0018] Figure 7 Shown is a schematic diagram in which the first signal line is not connected to the electrostatic protection circuit;

[0019] Figure 8 FIG. 2 is another connection diagram of the shift register circuit, the first signal line, the light emitting element and the pixel driving circuit in the embodiment of the present disclosure;

[0020] Fig. 9 Shown is a circuit schematic diagram of a first protection circuit and a second protection circuit;

[0021] Fig.10 FIG. 1 is a schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0022] Fig.11 Shown with Fig.10 A corresponding timing diagram;

[0023] Fig.12 Shown is a schematic diagram of a connection between a first signal line corresponding to a pixel driving circuit and an electrostatic protection circuit;

[0024] Fig.13 The figure shows a schematic diagram of an arrangement of the first protection circuit and the second protection circuit in the display panel;

[0025] Fig.14 Shown is another schematic diagram of arrangement of the first protection circuit and the second protection circuit in the display panel;

[0026] Fig.15 Shown is another schematic diagram of arrangement of the first protection circuit and the second protection circuit in the display panel;

[0027] Fig.16 Shown is another schematic diagram of arrangement of the first protection circuit and the second protection circuit in the display panel;

[0028] Fig.17 Shown is another schematic diagram of arrangement of the first protection circuit and the second protection circuit in the display panel;

[0029] Fig.18 Shown is a circuit layout diagram of a display panel provided by the present disclosure;

[0030] Fig.19 Shown is a schematic diagram of a connection between an electrostatic protection circuit and a first voltage line and a second voltage line;

[0031] Fig. 20 Shown with Fig.19 A structural schematic diagram of a corresponding electrostatic protection circuit;

[0032] Fig.21 Shown is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0035] Figure 1 FIG. 1 is a schematic diagram of a planar structure of a display panel provided by the present disclosure. Please refer to FIG. Figure 1 The present disclosure provides a display panel 100, including a shift register circuit 20 located in a display area AA and a plurality of first signal lines 10 connected to the shift register circuit 20, wherein the first signal lines 10 extend along a first direction D1 and are arranged along a second direction D2, and the first direction D1 intersects with the second direction D2; the display panel 100 also includes an electrostatic protection circuit 30 disposed in the display area AA, wherein along the first direction D1, the electrostatic protection circuit 30 is located at a side of an end of the first signal line 10 facing an edge B of the display panel, and the end of the first signal line 10 is electrically connected to the electrostatic protection circuit 30.

[0036] Figure 1The rectangular display panel is used as an example for illustration, and the actual shape of the display panel is not limited. In some other embodiments of the present disclosure, the display panel can also be embodied in any other feasible shape such as a circle, a rounded rectangle, etc. Optionally, the display panel provided in this embodiment can be a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc. This type of display panel has the advantages of high brightness, low power consumption, and easy splicing, and is widely used in display products. The connection relationship of the light-emitting element in the display panel can be appropriately referred to Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure. The light emitting element LD is electrically connected to a pixel driving circuit 40 in the display panel. It should be noted that: Figure 2 Only one film layer structure of the display panel is illustrated, and the actual number and size of the film layers are not limited. In some other embodiments of the present disclosure, the display panel can also be embodied as an organic light-emitting display panel, and the corresponding light-emitting element is an organic light-emitting element (such as OLED), which is not specifically limited in the present disclosure. It should be noted that in order to clearly illustrate the relative position relationship between the shift register circuit 20, the first signal line 10 and the electrostatic protection circuit 30, Figure 1 Other structures of the display panel such as the light emitting element LD are not shown, and the pixel driving circuit 40 is only illustrated in a rectangular structure, and the number and arrangement of the pixel driving circuit 40 are not limited. Figure 1 The position of the shift register circuit 20 in the display area is only for illustration, and an example is given in which a group of shift register circuits 20 are introduced into the display panel and the shift register circuit 20 is arranged in the middle area of ​​the display area AA, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the shift register circuit 20 may also be arranged at other positions in the display area, for example, please refer to Figure 3 , Figure 3 Shown is another schematic diagram of the planar structure of the display panel provided by the embodiment of the present disclosure. This embodiment is explained by taking the introduction of two groups of shift register circuits 20 in the display panel, and the two groups of shift register circuits 20 are respectively arranged in the left and right half-screen areas of the display panel as an example. The method of providing control signals to the first signal line 10 by the two groups of shift register circuits 20 is beneficial to improving the transmission efficiency and transmission reliability of the control signal.

[0037] Figure 4The figure shows a connection diagram of the shift register circuit 20, the first signal line 10, the light emitting element LD and the pixel driving circuit 40 in the embodiment of the present disclosure, wherein the pixel driving circuit 40 is electrically connected to the light emitting element LD for driving the light emitting element LD to emit light, the first signal line 10 is electrically connected to the pixel driving circuit 40, and the control signal generated by the shift register circuit is transmitted to the pixel driving circuit 40 through the first signal line 10 to control the operation of the pixel driving circuit 40. For the specific structure of the pixel driving circuit 40, please refer to the relevant technology, and the present disclosure does not specifically limit this. The specific structure of the pixel driving circuit 40 will be illustrated in the subsequent embodiments. Optionally, the shift register circuit 20 includes a plurality of cascaded shift register units 21, the shift register units 21 are arranged along the second direction D2, the output end of the shift register unit is connected to the first signal line 10, and the control signal is provided to the pixel driving circuit 40 through the first signal line 10, and the control signal includes, for example, a reset signal, a scan signal, a light emitting control signal, etc.

[0038] It should also be noted that Figure 1 , Figure 3 and Figure 4 The shift register circuit 20, the first signal line 10 and the electrostatic protection circuit 30 are only for illustration, and the number and position of the shift register circuit 20, the first signal line 10 and the electrostatic protection circuit 30 actually included in the display panel are not specifically limited. The specific structure of the electrostatic protection circuit 30 will be described in subsequent embodiments. Figure 1 , Figure 3 and Figure 4 The shift register circuit 20 is only taken as an example to be located between pixel columns, and the present disclosure is not limited to this. In some other embodiments of the present disclosure, the shift register circuit 20 may also be arranged between adjacent pixel rows. For example, please refer to Figure 5 and Figure 6 , Figure 5 Shown is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure; Figure 6 FIG. 1 is another connection diagram of the shift register circuit, the first signal line, the light emitting element and the pixel driving circuit in the embodiment of the present disclosure. It should be noted that: Figure 5 and Figure 6 The figure shows a scheme in which the shift register circuit 20 and the pixel driving circuit 40 overlap along the second direction, but the present disclosure is not limited to this. In some other embodiments of the present disclosure, along the second direction, the shift register circuit 20 and the pixel driving circuit 40 may not overlap or partially overlap.

[0039] Please combine Figures 1 to 6In the display panel provided by the present disclosure, the shift register circuit 20 is arranged in the display area AA, and the control signal is provided to the first signal line 10 through the shift register circuit 20 located in the display area AA. At the same time, the electrostatic protection circuit 30 is also arranged in the display area AA. The shift register circuit 20 and the electrostatic protection circuit 30 will no longer occupy the non-display area space of the display panel 100. In this way, the non-display area may not be set in the display panel, or only a non-display area with a smaller width may be set, which is conducive to realizing a borderless or extremely narrow border design of the display panel. When the display panels with a borderless structure are spliced ​​to form a large-size display panel, it is conducive to weakening the splicing seam, which is more conducive to improving the display effect of the large-size display panel. Figure 7 FIG. 1 is a schematic diagram showing that the first signal line 10 is not connected to the electrostatic protection circuit 30. Figure 7 When the shift register circuit 20 is set in the display area, in order to simplify the connection between the shift register and the first signal line 10 and reduce winding, the connection point between the first signal line 10 and the shift register circuit 20 will be located in the non-end area of ​​the first signal line 10. At this time, the ends DB of the first signal line 10 located at both ends along the first direction D1 will float. If there is static electricity in the subsequent display panel manufacturing process or use, the static electricity will be able to act on the pixel driving circuit 40 through the ends DB of the first signal line 10, affecting the display effect of the display panel and even possibly damaging the related circuit structure. For this purpose, please refer to Figure 1 , Figure 3 and Figure 4 The present disclosure introduces an electrostatic protection circuit 30 in the display area, and electrically connects the end of the first signal line 10 to the electrostatic protection circuit 30. When the display panel 100 is subjected to static electricity, the static electricity can be discharged through the electrostatic protection circuit 30 to avoid affecting the display effect of the display panel and the circuit in the display panel, thereby helping to improve the overall anti-static ability of the display panel.

[0040] Figure 8 Shown is another connection schematic diagram of the shift register circuit 20, the first signal line 10, the light-emitting element LD and the pixel driving circuit 40 in an embodiment of the present disclosure. In an optional implementation of the present disclosure, the electrostatic protection circuit 30 includes a first protection circuit 31 and a second protection circuit 32, and the first protection circuit 31 and the second protection circuit 32 are connected to different signals.

[0041] Taking the display panel provided in the present disclosure as an inorganic light emitting diode display panel as an example, the pixel driving circuit 40 connected to the light emitting element LD may include a pulse width modulation circuit 120 and a pulse amplitude modulation circuit 110, and the pulse width modulation circuit 120 and the pulse amplitude modulation circuit 110 are respectively connected to different first signal lines 10, Figure 8Only the example of the pulse width modulation circuit 120 being connected to a first signal line 10 and the pulse amplitude modulation circuit 110 being connected to a first signal line 10 is used for illustration, but the number of first signal lines 10 to which the pulse width modulation circuit 120 and the pulse amplitude modulation circuit 110 are respectively connected is not limited. In this embodiment, the electrostatic protection circuit 30 includes a first protection circuit 31 and a second protection circuit 32, wherein the first protection circuit 31 can be electrically connected to the end of the first signal line 10 corresponding to the pulse width modulation circuit 120, and the second protection circuit 32 can be electrically connected to the end of the first signal line 10 corresponding to the pulse amplitude modulation circuit 110, that is, the pulse width modulation circuit 120 and the pulse amplitude modulation circuit 110 correspond to different electrostatic protection circuits 30, respectively. In this embodiment, the first protection circuit 31 and the second protection circuit 32 are connected to different signals, which can be regarded as the first protection circuit 31 and the second protection circuit 32 are connected to different voltage lines, and the signal transmitted on the voltage line connected to the first protection circuit 31 is different from the signal transmitted on the voltage line connected to the second protection circuit 32. In this way, electrostatic protection circuits 30 corresponding to different voltage domains can be introduced into the pulse amplitude modulation circuit 110 and the pulse width modulation circuit 120 in the pixel driving circuit 40, respectively, to perform electrostatic protection on the pulse width modulation circuit 120 and the pulse amplitude modulation circuit 110, which is beneficial to improving the overall anti-static ability of the display panel.

[0042] Please continue to refer to Figure 8 In an optional embodiment of the present disclosure, the first protection circuit 31 and the second protection circuit 32 respectively include a first signal terminal S01 and a second signal terminal S02; the first signal terminal S01 of the first protection circuit 31 is configured to receive a first high voltage, and the second signal terminal S02 of the first protection circuit is configured to receive a first low voltage; the first signal terminal S01 of the second protection circuit 32 is configured to receive a second high voltage, and the second signal terminal S02 of the second protection circuit 32 is configured to receive a second low voltage; wherein the first high voltage is not equal to the second high voltage, and / or the first low voltage is not equal to the second low voltage.

[0043] Specifically, the first signal terminal S01 of the first protection circuit 31 and the second protection circuit 32 is used to receive a high voltage signal, and the second signal terminal S02 is used to receive a low voltage signal. Optionally, the first signal terminal S01 and the second signal terminal S02 are respectively connected to different voltage lines, which can be regarded as electrostatic release lines. When high voltage static electricity is generated on the first signal line 10, the first signal line 10 can release the high voltage static electricity to the voltage line connected to the first signal terminal S01 through the electrostatic protection circuit 30 connected thereto. When low voltage static electricity is generated on the first signal line 10, the first signal line 10 can release the low voltage static electricity to the voltage line connected to the second signal terminal S02 through the electrostatic protection circuit 30 connected thereto. In this embodiment, the first signal terminal S01 and the second signal terminal S02 of the electrostatic protection circuit 30 are respectively connected to the high voltage signal and the low voltage signal, which is conducive to the release of the high voltage static electricity signal and the low voltage static electricity signal. In addition, for the first protection circuit 31 and the second protection circuit 32, the two are connected to different signals, which may specifically include the following three situations: the first situation is that the first high voltage connected to the first signal terminal S01 of the first protection circuit 31 is different from the second high voltage connected to the first signal terminal S01 of the second protection circuit 32, and the first low voltage connected to the second signal terminal S02 of the first protection circuit 31 is the same as the second low voltage connected to the second signal terminal S02 of the second protection circuit 32. The second situation is that the first high voltage connected to the first signal terminal S01 of the first protection circuit 31 is the same as the second high voltage connected to the first signal terminal S01 of the second protection circuit 32, and the first low voltage connected to the second signal terminal S02 of the first protection circuit 31 is different from the second low voltage connected to the second signal terminal S02 of the second protection circuit 32. The third situation is that the first high voltage connected to the first signal terminal S01 of the first protection circuit 31 is different from the second high voltage connected to the first signal terminal S01 of the second protection circuit 32, and the first low voltage connected to the second signal terminal S02 of the first protection circuit 31 is different from the second low voltage connected to the second signal terminal S02 of the second protection circuit 32. In this way, the different voltage domain requirements of the pulse width modulation circuit 120 and the pulse amplitude modulation circuit 110 in the pixel driving circuit 40 can be matched, and the overall electrostatic discharge effect of the display panel can be improved.

[0044] Please continue to refer to Figure 8 In an optional embodiment of the present disclosure, the voltage value of the first high voltage corresponding to the first signal terminal S01 of the first protection circuit 31 is V11, the voltage value of the first low voltage corresponding to the second signal terminal S02 of the first protection circuit 31 is V01, the voltage value of the second high voltage corresponding to the first signal terminal S01 of the second protection circuit 32 is V12, and the voltage value of the second low voltage corresponding to the second signal terminal S02 of the second protection circuit 32 is V02, wherein V11-V01=V12-V02.

[0045] When V11-V01=V12-V02 is set, it is equivalent to setting the voltage difference between the first high voltage and the first low voltage corresponding to the first protection circuit 31 to be the same as the voltage difference between the second high voltage and the second low voltage corresponding to the second protection circuit 32. For example, V11=8V, V01=-7V, and the difference between the two is 15V; V12=3V, V02=-12V, and the difference between the two is also 15V. When the voltage difference corresponding to the first protection circuit 31 and the voltage difference corresponding to the second protection circuit 32 are set to be the same, it is helpful to simplify the design difficulty of the voltage signal in the display panel. It should be noted that the values ​​of V11, V01, V12 and V02 in this embodiment are only examples, and the actual voltage values ​​are not limited. The above voltage values ​​can be flexibly set according to actual circuit requirements.

[0046] In the above embodiment, the voltage difference between the high and low voltages corresponding to the first protection circuit 31 and the voltage difference between the high and low voltages corresponding to the second protection circuit 32 are set to be the same. In an optional embodiment of the present disclosure, the two can also be designed to be different. Specifically, the voltage value of the first high voltage corresponding to the first signal terminal S01 of the first protection circuit 31 is V11, the voltage value of the first low voltage corresponding to the second signal terminal S02 of the first protection circuit 31 is V01, the voltage value of the second high voltage corresponding to the first signal terminal S01 of the second protection circuit 32 is V12, and the voltage value of the second low voltage corresponding to the second signal terminal S02 of the second protection circuit 32 is V02, wherein V11-V01≠V12-V02. When the difference between the high voltage and the low voltage corresponding to the first protection circuit 31 is set to be different from the difference between the high voltage and the low voltage corresponding to the second protection circuit 32, a pixel driving circuit with a corresponding voltage difference requirement can be matched, and the reliable release of static electricity can also be achieved, which is conducive to improving the antistatic performance of the display panel.

[0047] In an optional implementation of the present disclosure, the voltage value of the first high voltage is V11, the voltage value of the first low voltage is V01, the voltage value of the second high voltage is V12, the voltage value of the second low voltage is V02, V11>V12>0, V02<V01<0.

[0048] In the embodiment of the present disclosure, the first high voltage and the first low voltage corresponding to the first protection circuit 31 are relative to the voltage of 0V, and the second high voltage and the second low voltage corresponding to the second protection circuit 32 are also relative to the voltage of 0V. Specifically, in the present disclosure, the first high voltage received by the first protection circuit 31 and the second high voltage received by the second protection circuit 32 are both positive voltages, and the first low voltage received by the first protection circuit 31 and the second low voltage received by the second protection circuit 32 are both negative voltages, that is, a voltage greater than 0V can be regarded as a high voltage, and a voltage less than 0V can be regarded as a low voltage. In this way, whether there is a positive voltage static electricity acting on the display panel or a negative voltage static electricity acting on the display panel, it can be released through the static electricity protection circuit 30, thereby improving the all-round anti-static performance of the display panel.

[0049] Please refer to Figure 8 In an optional embodiment of the present disclosure, the display area includes a light-emitting element LD and a pixel driving circuit 40 connected to the light-emitting element LD, the pixel driving circuit 40 includes a pulse width modulation circuit and a pulse amplitude modulation circuit, the first signal line 10 includes a first type of signal line 01 and a second type of signal line 02, the first type of signal line 01 is electrically connected to the pulse width modulation circuit, and the second type of signal line 02 is electrically connected to the pulse amplitude modulation circuit; the end of the first type of signal line 01 is electrically connected to the first protection circuit 31, and the end of the second type of signal line 02 is electrically connected to the second protection circuit 32.

[0050] In the pixel driving circuit 40, the pulse amplitude modulation circuit 110 can be used to control the amplitude of the driving current, and the pulse width modulation circuit 120 can be used to adjust the pulse width of the driving current applied to the light-emitting element LD. The pulse width modulation circuit 120 is used to adjust the pulse width of the voltage applied to the light-emitting element LD, that is, the pulse width modulation circuit 120 adjusts the actual emission period of the driving current applied to the light-emitting element LD; at the same time, the driving current applied to the light-emitting element LD can be maintained at a constant level to adjust the grayscale or brightness displayed by the light-emitting element LD, rather than adjusting the grayscale or brightness displayed by the light-emitting element LD by adjusting the magnitude of the driving current applied to the light-emitting element LD. Therefore, the pulse amplitude modulation circuit can provide a driving current to the light-emitting element LD so that the light-emitting element LD is driven with the best luminous efficiency, and adjust the grayscale or brightness displayed by the light-emitting element LD by adjusting the light-emitting duty cycle of the light-emitting element LD (that is, the emission period of the light-emitting element LD) through the pulse width modulation circuit 120.

[0051] Please continue to refer to Figure 8In this embodiment, the first signal line 10 includes a first type signal line 01 connected to the pulse width modulation circuit 120 and a second type signal line 02 connected to the pulse amplitude modulation circuit 110. The first type signal line 01 is used to provide a signal to the pulse width modulation circuit 120, such as a scan signal, a frequency sweep signal, a light control signal, a reset signal, etc., and the second type signal line 02 is used to provide a signal to the pulse amplitude modulation circuit 110, such as a scan signal, a light control signal, a reset signal, etc. In the present disclosure, the end of the first type signal line 01 is electrically connected to the first protection circuit 31, and the end of the second type signal line 02 is electrically connected to the second protection circuit 32. When static electricity is generated on the first type signal line 01, this part of the static electricity can be released through the first protection circuit 31; when static electricity is generated on the second type signal line 02, this part of the static electricity can be released through the second protection circuit 32. Therefore, the introduction of the first protection circuit 31 and the second protection circuit 32 can be targeted to perform static electricity protection on the pulse width modulation circuit and the pulse amplitude modulation circuit in the pixel driving circuit 40, respectively, which is conducive to improving the overall anti-static performance of the display panel.

[0052] The specific structure of the electrostatic protection circuit is described below. Fig. 9 FIG. 1 is a schematic diagram of a circuit of the first protection circuit 31 and the second protection circuit 32. Fig. 9 In an optional embodiment of the present disclosure, the first protection circuit 31 includes a first transistor T1 and a second transistor T2, the gate and the first electrode of the first transistor T1 are electrically connected to the end of the first type signal line 01, and the second electrode of the first transistor T1 receives a first high voltage; the gate and the first electrode of the second transistor T2 receive a first low voltage, and the second electrode of the second transistor T2 is electrically connected to the end of the first type signal line 01. The second protection circuit 32 includes a third transistor T3 and a fourth transistor T4, the gate and the first electrode of the third transistor T3 receive a second high voltage, and the second electrode of the third transistor T3 is electrically connected to the end of the second type signal line 02; the gate and the first electrode of the fourth transistor T4 receive a second low voltage, and the second electrode of the fourth transistor T4 is electrically connected to the end of the second type signal line 02.

[0053] It should be noted that Fig. 9 Only the structure and arrangement of one first protection circuit 31 and one second protection circuit 32 are illustrated. The structures of other first protection circuits 31 and second protection circuits 32 can be referred to. Fig. 9. The first protection circuit 31 and the second protection circuit 32 include two transistors respectively. In the first protection circuit 31, the gate and the first electrode of the first transistor T1 are connected to the first type signal line 01, and the second electrode of the first transistor T1 is connected to the voltage line 51 for receiving the first high voltage; the gate and the first electrode of the second transistor T2 are connected to the voltage line 53 for receiving the first low voltage, and the second electrode of the second transistor T2 is electrically connected to the first type signal line 01. Among them, the first transistor T1 and the second transistor T2 are transistors of the same type. This embodiment is described by taking the first transistor T1 and the second transistor T2 as N-type transistors as an example. When the first type signal line 01 generates high voltage static electricity, the second transistor T2 is turned off, the first transistor T1 is turned on, and the high voltage static electricity will be released through the voltage line 51. When the first type signal line 01 generates low voltage static electricity, the second transistor T2 is turned on, the first transistor T1 is turned off, and the low voltage static electricity will be released through the voltage line 53. In this way, the first protection circuit 31 is used to realize the function of electrostatic protection for the first type signal line 01 and the corresponding circuit.

[0054] In the second protection circuit 32, the gate and the first electrode of the third transistor T3 are electrically connected to the second type signal line 02, and the second electrode of the third transistor T3 is connected to the voltage line 52 for receiving the second high voltage; the gate and the first electrode of the fourth transistor T4 are connected to the voltage line 54 for receiving the second low voltage, and the second electrode of the fourth transistor T4 is electrically connected to the second type signal line 02. Among them, the third transistor T3 and the fourth transistor T4 are transistors of the same type, and this embodiment is described by taking the third transistor T3 and the fourth transistor T4 as N-type transistors as an example. It should be noted that the first protection circuit 31 and the second protection circuit 32 can correspond to four different voltage lines. When the second type signal line 02 generates high voltage static electricity, the fourth transistor T4 is turned off, the third transistor T3 is turned on, and the high voltage static electricity will be released through the voltage line 52. When the second type signal line 02 generates low voltage static electricity, the fourth transistor T4 is turned on, the third transistor T3 is turned off, and the low voltage static electricity will be released through the voltage line 54. In this way, the second protection circuit 32 is used to realize the function of electrostatic protection for the second type signal line 02 and the corresponding circuit.

[0055] In this embodiment, the first high voltage is different from the second high voltage, and / or the first low voltage is different from the second low voltage, that is, the first protection circuit 31 corresponding to the first type of signal line 01 connected to the pulse width modulation circuit and the second protection circuit 32 corresponding to the second type of signal line 02 connected to the pulse amplitude modulation circuit are connected to different voltage signals respectively, which can achieve reliable conduction of static electricity and meet the different voltage domain requirements of the pulse width modulation circuit and the pulse amplitude modulation circuit.

[0056] Fig.10FIG. 4 is a schematic diagram of a pixel driving circuit 40 provided in an embodiment of the present disclosure. Figures 8 to 10 In an optional embodiment of the present disclosure, the pixel driving circuit 40 includes a first scan line SM1, a first light-emitting control signal line PWM_EM, a first reset signal line VREF1 and a frequency sweeping signal line SWEEP electrically connected to the pulse width modulation circuit 120, and a second scan line SM2, a second light-emitting control signal line PAM_EM and a second reset signal line VREF2 electrically connected to the pulse amplitude modulation circuit 110; the first type of signal line 01 mentioned in the embodiment of the present disclosure includes at least one of the first scan line SM1, the first light-emitting control signal line PWM_EM, the first reset signal line VREF1 and the frequency sweeping signal line SWEEP, and the second type of signal line 02 includes at least one of the second scan line SM2, the second light-emitting control signal line PAM_EM and the second reset signal line VREF2. In this embodiment, the first protection circuit 31 is electrically connected to the first type of signal line 01 corresponding to the pulse width modulation circuit 120, and the second protection circuit 32 is electrically connected to the second type of signal line 02 corresponding to the pulse amplitude modulation circuit 110. It should be noted that the power signal line VDD_PWM electrically connected to the pulse width modulation circuit 120 and the power signal line VDD_PAM electrically connected to the pulse amplitude modulation circuit are usually mesh structures, so there is no floating signal terminal, and therefore the power signal lines VDD_PWM and VDD_PAM do not need to be electrically connected to the electrostatic protection circuit 30.

[0057] The signals transmitted by the first type signal line 01 and the second type signal line 02 will be described below in conjunction with the specific structure of the pixel driving circuit 40 .

[0058] Fig.11 Shown with Fig.10 For a corresponding timing diagram, please refer to Fig.10 and Fig.11 In the present disclosure, the pixel driving circuit 40 includes a pulse amplitude modulation circuit 110 and a pulse width modulation circuit 120, the pulse amplitude modulation circuit 110 is configured to control the amplitude of the driving current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit 120 is configured to control the pulse width of the driving current.

[0059] It should be noted that Fig.10 The pixel driving circuit 40 shown is for illustration only. The present disclosure does not limit the actual structure of the pixel circuit. In some other embodiments of the present disclosure, any other feasible pixel circuit structure may be adopted. In the pixel driving circuit 40, the pulse width modulation circuit 120 is electrically connected to the pulse amplitude modulation circuit 110, and the pulse amplitude modulation circuit 110 is used to be electrically connected to the light emitting element LD.

[0060] Please continue to refer to Fig.10 and Fig.11 Optionally, the pulse amplitude modulation circuit 110 and the pulse width modulation circuit 120 both include an initialization unit 111 / 121, a data writing unit 112 / 122, a threshold compensation unit 113 / 123, a light emitting control unit 114 / 124, a storage capacitor C1 / C2 and a driving transistor Dr_PAM / Dr_PWM (wherein the pulse amplitude modulation circuit 110 includes an initialization unit 111, a data writing unit 112, a threshold compensation unit 113, a light emitting control unit 114, a storage capacitor C1 and a driving transistor Dr_PAM; the pulse width modulation circuit 120 includes an initialization unit 121, The data writing unit 122, the threshold compensation unit 123, the light emitting control unit 124, the storage capacitor C2 and the driving transistor Dr_PWM), the initialization unit 111 / 121 is electrically connected between the initialization signal terminal VREF1 / VREF2 and the first node N11 / N12, the initialization signal terminal VREF1 / VREF2 is connected to the reset signal line VREF1 / VREF2 (the signal terminal and the signal provided by the signal terminal are represented by the same character here), the control terminal of the initialization unit 121 is connected to the first scanning line PWM_S1, and the control terminal of the initialization unit 111 is connected to the second scanning line PAM_S1. In the initialization stage t1, the first scanning line PWM_S1 and the second scanning line PAM_S1 control the initialization unit 121 / 111 to be turned on respectively, and the initialization unit 111 / 121 is used to provide the initialization signal of the initialization signal terminal VREF1 / VREF2 to the first node N11 / N12 (the value of the initialization signal provided by the initialization signal terminal of the pulse amplitude modulation circuit 110 and the value of the initialization signal provided by the initialization signal terminal of the pulse width modulation circuit 120 may be the same or different).

[0061] The data writing unit 112 / 122 is electrically connected between the data signal terminal DATA_PAM / DATA_PWM and the first electrode of the driving transistor Dr_PAM / Dr_PWM, the control terminal of the data writing unit 112 is connected to the second scan line PAM_S2, the control terminal of the data writing unit 111 is connected to the first scan line PWM_S2, the first scan line PWM_S2 and the second scan line PAM_S2 are used to control the data writing unit 122 and the data writing unit 112 to be turned on respectively in the data writing stage. The gate of the driving transistor Dr_PAM / Dr_PWM and the first electrode plate of the storage capacitor C1 / C2 are electrically connected to the first node N11 / N12; the data writing unit 112 / 122 is used to provide the data voltage signal of the data signal terminal DATA_PAM / DATA_PWM to the first node N11 / N12 through the driving transistor Dr_PAM / Dr_PWM in the data writing stage t2. The threshold compensation unit 113 / 123 is electrically connected between the second electrode of the driving transistor Dr_PAM / Dr_PWM and the first node N11 / N12, the control end of the threshold compensation unit 113 is connected to the second scan line PAM_S2, the control end of the threshold compensation unit 123 is connected to the first scan line PWM_S2, and the threshold compensation unit 113 / 123 is used to compensate the threshold voltage of the driving transistor Dr_PAM / Dr_PWM to the first node N11 / N12. It should be noted that in the embodiment of the present disclosure, the scan lines corresponding to the pulse width modulation circuit 120 are collectively referred to as the first scan lines SM1, and the scan lines corresponding to the pulse amplitude modulation circuit 110 are collectively referred to as the second scan lines SM2. In fact, there are multiple first scan lines SM1 connected to the pulse width modulation circuit 120, such as the scan lines PWM_S1 and PWM_S2. The first scan lines with the same reference numerals transmit the same scan signals, and the first scan lines with different reference numerals transmit different scan signals. Similarly, there are multiple second scan lines SM2 connected to the pulse amplitude modulation circuit 110, such as scan lines PAM_S1 and PAM_S2. Second scan lines with the same reference numerals transmit the same scan signals, and second scan lines with different reference numerals transmit different scan signals.

[0062] In the pulse width modulation circuit 120, the second electrode plate of the storage capacitor C2 is electrically connected to the sweep signal terminal SWEEP, and the sweep signal terminal SWEEP is electrically connected to the sweep signal line SWEEP (the signal terminal and the signal provided by the signal terminal are represented by the same characters here), and receives the sweep signal. The light-emitting control unit 124 is electrically connected between the first power supply terminal VDD_PWM and the first node N11 in the pulse amplitude modulation circuit 110; the control terminal of the light-emitting control unit 124 is connected to the first light-emitting control signal line PWM_EM, which is used to transmit the light-emitting control signal to the light-emitting control unit 124. The light-emitting control unit 124 is used to control the driving transistor Dr_PWM to generate a driving pulse in the light-emitting stage t3; the first power supply terminal VDD_PWM receives the first power supply voltage signal VDD_PWM (the signal terminal and the signal provided by the signal terminal are represented by the same characters here), and the data signal terminal DATA_PWM receives the pulse width modulated data voltage DATA_PWM (the signal terminal and the signal provided by the signal terminal are represented by the same characters here).

[0063] In the pulse amplitude modulation circuit 110, the second electrode plate of the storage capacitor C1 is electrically connected to the power signal terminal VDD_PAM, and the power signal terminal VDD_PAM receives the second power voltage signal VDD_PAM (the signal terminal and the signal provided by the signal terminal are represented by the same characters). The light-emitting control unit 114 is electrically connected between the power signal terminal VDD_PAM and the light-emitting element LD, and the control terminal of the light-emitting control unit 114 is connected to the second light-emitting control signal line PAM_EM, which is used to transmit the light-emitting control signal to the light-emitting control unit 114. The light-emitting control unit 114 is used to control the driving transistor Dr_PAM to generate a driving current to flow into the light-emitting element LD in the light-emitting stage, so as to drive the light-emitting element LD to emit light, and the data signal terminal DATA_PAM receives the pulse amplitude modulation data voltage DATA_PAM (the signal terminal and the signal provided by the signal terminal are represented by the same characters).

[0064] In this embodiment, the output end of the pulse width modulation circuit 120 is electrically connected to the first node N11 of the pulse amplitude modulation circuit 110, and is used to provide a control signal to the first node N11. Since the first node N11 is electrically connected to the gate of the driving transistor Dr_PAM, it is equivalent to providing a control signal to the gate of the driving transistor Dr_PAM. In the pulse width modulation circuit 120, when the voltage difference between the gate and the source of the driving transistor Dr_PWM is greater than the threshold voltage of the driving transistor Dr_PWM, the driving transistor Dr_PWM is in a cut-off state. At this time, the pulse width modulation circuit 120 does not provide a control signal to the first node N11 of the pulse amplitude modulation circuit 110, and the driving transistor Dr_PAM in the pulse amplitude modulation circuit 110 provides a driving current to the light emitting element LD according to the pulse amplitude modulation data voltage DATA_PAM. As the voltage of the sweep signal SWEEP changes, the gate potential of the driving transistor Dr_PWM changes synchronously until the voltage difference between the gate and the source of the driving transistor Dr_PWM is less than or equal to the threshold voltage of the driving transistor Dr_PWM. The driving transistor Dr_PWM is turned on, and the driving transistor Dr_PWM transmits the first power supply voltage signal VDD_PWM of the first power supply terminal VDD_PWM as a cut-off voltage to the first node N11 of the pulse amplitude modulation circuit 110, so that the driving transistor Dr_PAM in the pulse amplitude modulation circuit 110 is cut off, thereby stopping providing the driving current to the light emitting element LD.

[0065] It should be noted that Fig.10 In the embodiment, the output terminal of the pulse width modulation circuit 120 is directly connected to the gate of the driving transistor Dr_PAM in the pulse amplitude modulation circuit 110. Fig.10 The pixel driving circuit 40 shown is for illustration only. The present disclosure does not limit the actual structure of the pixel driving circuit 40. In some other embodiments of the present disclosure, any other feasible pixel driving circuit 40 structure may be adopted. For example, in some other embodiments of the present disclosure, the output end of the pulse width modulation circuit 120 may also be connected to the gate of the driving transistor in the pulse amplitude modulation circuit 110 through a connecting capacitor. For another example, the pulse amplitude modulation circuit 110 may also include a control transistor, which is connected between the driving transistor Dr_PAM and the light emitting element LD, and the output end of the pulse width modulation circuit 120 may be connected to the gate of the control transistor.

[0066] Fig.12 FIG. 1 is a schematic diagram showing a connection between the first signal line 10 corresponding to the pixel driving circuit 40 and the electrostatic protection circuit 30. Fig.12 The specific structures of the first protection circuit 31 and the second protection circuit 32 can be referred to Fig. 9 , Fig.12The specific structure of the pulse width modulation circuit and the pulse amplitude modulation circuit can be referred to Fig.10 , please refer to Fig.12 , and combined with Fig. 9 and Fig.10 In an optional embodiment of the present disclosure, the first protection circuit 31 includes a first sub-circuit 311 and a second sub-circuit 312, the first sub-circuit 311 is connected to the first reset signal line VREF1, and the second sub-circuit 312 is connected to at least one of the first scanning line PWM_S1 / PWM_S2, the first light-emitting control signal line PWM_EM and the sweep signal line SWEEP; the channel width of the first transistor T1 in the first sub-circuit 311 is W11, and the channel width of the second transistor T2 is W12; the channel width of the first transistor T1 in the second sub-circuit 312 is W21, and the channel width of the second transistor T2 is W22, wherein W11<W21, and / or, W12<W22.

[0067] For the first reset signal line VREF1, the reset signal it provides is applicable to the pulse width modulation circuit 120 corresponding to each pixel driving circuit 40 in the display panel, that is, the reset signal provided by the first reset signal line VREF1 is a global signal. If the width of the transistor in the electrostatic protection circuit 30 connected to the first reset signal line VREF1 is too large, the corresponding leakage will also be large, affecting the reset reliability. Therefore, this embodiment distinguishes the first protection circuit 31 connected to the first reset signal line VREF1 from the first protection circuit 31 connected to other first-class signal lines 01, wherein, among the first-class signal lines 01 connected to the pulse width modulation circuit 120, the first protection circuit 31 connected to the first reset signal line VREF1 is a first sub-circuit 311, and the first protection circuit 31 connected to other first-class signal lines 01 (such as the first scanning line PWM_S1 / PWM_S2, the first light-emitting control signal line PWM_EM, and the sweeping signal line SWEEP) is a second sub-circuit 312. The channel widths of the first transistor T1 and the second transistor T2 in the first subcircuit 311 and the second subcircuit 312 can be set in the following three situations: the first situation is that W11<W21, W12=W22; the second situation is that W12<W22, W11=W21; the third situation is that W12<W21 and W12<W22. That is, the channel width of at least one transistor in the first subcircuit 311 is smaller than the channel width of the transistor in the second subcircuit 312. Setting the size of the transistor in the first subcircuit 311 smaller is conducive to reducing the leakage of the first reset signal line VREF1 through the first subcircuit 311, and improving the reset reliability of the pulse width modulation circuit 120 in the pixel driving circuit 40.

[0068] When the size of the transistor in the first sub-circuit 311 connected to the first reset signal line VREF1 is set to be smaller, in an optional embodiment of the present disclosure, the channel widths of the first transistor T1 and the second transistor T2 are the same in the plurality of second sub-circuits 312. In this way, the first transistor T1 and the second transistor T2 in the second sub-circuit 312 can be manufactured using the same size standard, and there is no need to perform differentiated designs on the first transistor T1 and the second transistor T2 in different second sub-circuits 312, which is conducive to simplifying the manufacturing process of the display panel and improving the production efficiency of the display panel.

[0069] Please refer to Fig.12 , Fig. 9 and Fig.10 In an optional embodiment of the present disclosure, the second protection circuit 32 includes a third sub-circuit 323 and a fourth sub-circuit 324, the third sub-circuit 323 is connected to the second reset signal line VREF2, and the fourth sub-circuit 324 is connected to at least one of the second scan line PAM_S1 / PAM_S2 and the second light emitting control signal line PAM_EM; the channel width of the third transistor T3 in the third sub-circuit 323 is W13, and the channel width of the fourth transistor T4 is W14; the channel width of the third transistor T3 in the fourth sub-circuit 324 is W23, and the channel width of the fourth transistor T4 is W24, wherein W13<W23, and / or, W14<W24.

[0070] For the second reset signal line VREF2, the reset signal it provides is suitable for the pulse amplitude modulation circuit 110 corresponding to each pixel driving circuit 40 in the display panel, that is, the reset signal provided by the second reset signal line VREF2 is a global signal. If the width of the transistor in the electrostatic protection circuit 30 connected to the second reset signal line VREF2 is too large, the corresponding leakage will also be large, affecting the reset reliability. Therefore, this embodiment distinguishes the second protection circuit 32 connected to the second reset signal line VREF2 from the second protection circuit 32 connected to other second-type signal lines 02, wherein, among the second-type signal lines 02 connected to the pulse amplitude modulation circuit, the first protection circuit 31 connected to the second reset signal line VREF2 is the third sub-circuit 323, and the second protection circuit 32 connected to other second-type signal lines 02 (such as the second scanning line PAM_S1 / PAM_S2, the second light-emitting control signal line PAM_EM) is the fourth sub-circuit 324. The channel widths of the third transistor T3 and the fourth transistor T4 in the third sub-circuit 323 and the fourth sub-circuit 324 can be set in the following three situations: the first situation is that W13<W23, W14=W24; the second situation is that W13<W23, W14=W24; the third situation is that W13<W23 and W14<W24. In other words, the channel width of at least one transistor in the third sub-circuit 323 is smaller than the channel width of the transistor in the fourth sub-circuit 324. Setting the size of the transistor in the third sub-circuit 323 to be smaller is conducive to reducing the leakage of the second reset signal line VREF2 through the third sub-circuit 323, and improving the reset reliability of the pulse amplitude modulation circuit in the pixel driving circuit 40.

[0071] When the size of the transistor in the third subcircuit 323 connected to the second reset signal line VREF2 is set to be smaller, in an optional embodiment of the present disclosure, the channel widths of the third transistor T3 and the fourth transistor T4 are the same in the plurality of fourth subcircuits 324. In this way, the third transistor T3 and the fourth transistor T4 in the fourth subcircuit 324 can be manufactured using the same size standard, and there is no need to perform differentiated designs on the third transistor T3 and the fourth transistor T4 in different fourth subcircuits 324, which is conducive to simplifying the manufacturing process of the display panel and improving the production efficiency of the display panel.

[0072] Please refer to Fig.12 , Fig. 9 and Fig.10In an optional embodiment of the present disclosure, the first protection circuit 31 includes a first sub-circuit 311 and a second sub-circuit 312, the first sub-circuit 311 is connected to the first reset signal line VREF1, and the second sub-circuit 312 is connected to at least one of the first scan line PWM_S1 / PWM_S2, the first light-emitting control signal line PWM_EM and the sweep signal line SWEEP; the second protection circuit 32 includes a third sub-circuit 323 and a fourth sub-circuit 324, the third sub-circuit 323 is connected to the second reset signal line VREF2, and the fourth sub-circuit 324 is connected to at least one of the second scan line PAM_S1 / PAM_S2 and the second light-emitting control signal line PAM_EM; the channel width of the transistor in the first sub-circuit 311 is the same as the channel width of the transistor in the third sub-circuit 323.

[0073] In this embodiment, the first reset signal line VREF1 is connected to the pulse width modulation circuit 120, and the second reset signal line VREF2 is connected to the pulse amplitude modulation circuit 110. To avoid electrostatic interference, the end of the first reset signal line VREF1 is electrically connected to the first sub-circuit 311, the end of the second reset signal line VREF2 is electrically connected to the third sub-circuit 323, the end of the other first-type signal line 01 corresponding to the pulse width modulation circuit 120 is electrically connected to the second sub-circuit 312, and the end of the other second-type signal line 02 corresponding to the pulse amplitude modulation circuit 110 is electrically connected to the fourth sub-circuit 324. In this embodiment, the size of the transistors in the first sub-circuit 311 and the third sub-circuit 323 is set to be small, specifically W11<W21, and / or, W12<W22; W13<W23, and / or, W14<W24, to avoid excessive leakage on the first reset signal line VREF1 and the second reset signal line VREF2, which affects the reset effect. At the same time, in this embodiment, the channel width of the transistor in the first subcircuit 311 is set to be the same as the channel width of the transistor in the third subcircuit 323. Specifically, the channel width W11 of the first transistor T1 in the first subcircuit 311 is the same as the channel width W13 of the third transistor T3 in the third subcircuit 323, and the channel width W12 of the second transistor T2 in the first subcircuit 311 is the same as the channel width W14 of the fourth transistor T4 in the third subcircuit 323. In this way, the first subcircuit 311 and the third subcircuit 323 can be manufactured using the same size standard and process, which is conducive to simplifying the manufacturing process of the display panel and improving production efficiency. Optionally, the sizes of the two transistors in the first subcircuit 311 and the two transistors in the third subcircuit 323 can be reduced, and W11=W12=W13=W14, which is more conducive to simplifying the manufacturing process of the first subcircuit 311 and the third subcircuit 323.

[0074] Please continue to refer to Fig. 9 , Fig.10 and Fig.12 In an optional embodiment of the present disclosure, the channel widths of the transistors in the second subcircuit 312 and the fourth subcircuit 324 are the same. In this way, there is no need to distinguish the sizes of the transistors in the second subcircuit 312 and the fourth subcircuit 324, and the transistors in the second subcircuit 312 and the fourth subcircuit 324 can be manufactured using the same size standard, which is conducive to simplifying the manufacturing process of the second subcircuit 312 and the fourth subcircuit 324, and is also conducive to improving the production efficiency of the display panel.

[0075] Fig.13 FIG. 1 is a schematic diagram showing an arrangement of the first protection circuit 31 and the second protection circuit 32 in the display panel. Fig.14 FIG. 1 is another schematic diagram of an arrangement of the first protection circuit 31 and the second protection circuit 32 in the display panel. In an optional implementation of the present disclosure, please refer to FIG. Fig.13 , along the first direction D1, the first protection circuit 31 and the second protection circuit 32 are located on one side of the first signal line 10; or, please refer to Fig.14 , along the first direction D1, the first protection circuit 31 is located at a first side of the first signal line 10, and the second protection circuit 32 is located at a second side of the first signal line 10, wherein the first side and the second side are arranged opposite to each other.

[0076] Fig.13 and Fig.14 The illustrated embodiment shows two arrangements of the first protection circuit 31 and the second protection circuit 32 in the display panel. Fig.13 In the illustrated embodiment, the first protection circuit 31 and the second protection circuit 32 are located on one side of the first signal line 10 along the first direction D1. This embodiment is described by taking the first protection circuit 31 and the second protection circuit 32 as being located on the left side of the first signal line 10 as an example, but is not limited thereto. In some other embodiments of the present disclosure, the first protection circuit 31 and the second protection circuit 32 may also be located on the right side of the first signal line 10. When static electricity is generated on the first signal line 10, the static electricity may be released through the first protection circuit 31 or the second protection circuit 32. Fig.14 In the illustrated embodiment, the first protection circuit 31 and the second protection circuit 32 are respectively located on different sides of the first signal line 10 along the first direction D1, wherein the first protection circuit 31 is located on the first side of the first signal line 10, and the second protection circuit 32 is located on the second side of the first signal line 10. When static electricity is generated on the first signal line 10, it can also be released through the first protection circuit 31 or the second protection circuit 32. Fig.13 and Fig.14 The solutions shown are all beneficial to the discharge of static electricity and to improving the antistatic performance of the display panel.

[0077] Fig.15 FIG. 1 is another schematic diagram showing another arrangement of the first protection circuit 31 and the second protection circuit 32 in the display panel. Fig.15 In an optional embodiment of the present disclosure, an electrostatic protection circuit 30 is disposed on a first side and a second side of the first signal line 10 along a first direction D1, wherein the first side and the second side are disposed opposite to each other.

[0078] This embodiment shows a solution in which a first protection circuit 31 and a second protection circuit 32 are provided on a first side of a first signal line 10 along a first direction D1, and a first protection circuit 31 and a second protection circuit 32 are also provided on a second side of the first signal line 10 along the first direction D1, wherein the first protection circuit 31 and the second protection circuit 32 corresponding to the pixel driving circuit 40 of odd rows are located on the first side of the first signal line 10, and the first protection circuit 31 and the second protection circuit 32 corresponding to the pixel driving circuit 40 of even rows are located on the second side of the first signal line 10. When static electricity is generated on the first signal line 10, the static electricity can be released through the first protection circuit 31 or the second protection circuit 32, which is also beneficial to improving the static electricity release capability of the display panel.

[0079] The above embodiment shows a scheme in which one end of the first signal line 10 is connected to the electrostatic protection circuit 30. In some other embodiments of the present disclosure, both ends of the first signal line 10 can be electrically connected to the electrostatic protection circuit 30. For example, please refer to Fig.16 , Fig.16 The figure shows another arrangement diagram of the first protection circuit 31 and the second protection circuit 32 in the display panel. In an optional embodiment of the present disclosure, two opposite ends of the first signal line 10 along the first direction D1 are respectively electrically connected to the electrostatic protection circuit 30. In this way, both ends of the first signal line 10 will not float. When static electricity is generated in the first signal line 10, the static electricity can be released through the two electrostatic protection circuits 30 connected to the first signal line 10, which is conducive to improving the static electricity release efficiency and reducing the action time of static electricity on the display panel, thereby being more conducive to improving the overall anti-static ability of the display panel.

[0080] Fig.17 FIG. 1 is another schematic diagram showing another arrangement of the first protection circuit 31 and the second protection circuit 32 in the display panel. Fig.17In an optional embodiment of the present disclosure, the electrostatic protection circuit 30 includes a first circuit group Z1 and a second circuit group Z2, the first circuit group Z1 includes a plurality of first protection circuits 31, the second circuit group Z2 includes a plurality of second protection circuits 32, the plurality of first protection circuits 31 are arranged along the second direction D2, and the plurality of second protection circuits 32 are arranged along the second direction D2; on the same side of the first signal line 10 along the first direction D1, the first circuit group Z1 and the second circuit group Z2 are alternately arranged; along the second direction D2, the spacing between two adjacent first protection circuits 31 in the first circuit group Z1 is S1, the spacing between two adjacent second protection circuits 32 in the second circuit group Z2 is S2, and the spacing between adjacent first circuit groups Z1 and second circuit groups Z2 is S0, S0>S1, and / or, S0>S2.

[0081] In this embodiment, along the second direction D2, the spacing S0 between adjacent first circuit group Z1 and second circuit group Z2 refers to the spacing distance between the first protection circuit 31 and the second protection circuit 32 that are closest to each other in the adjacent first circuit group Z1 and the second circuit group Z2. In this embodiment, the spacing S0 between the first circuit group Z1 and the second circuit group Z2 is set to be larger, so that it is larger than at least one of the spacing S1 between adjacent first circuits in the first circuit group Z1 and the spacing S2 between adjacent second circuits in the second circuit group Z2, so as to reasonably match the position of the first signal line led out from the pulse width modulation circuit 120 and the pulse amplitude modulation circuit 110, and simplify the connection between the electrostatic protection circuit and the first signal line.

[0082] Please refer to the appropriate Fig.17 In an optional embodiment of the present disclosure, along the first direction D1, the spacing S1 between adjacent first protection circuits 31 in the first circuit group Z1 and the spacing S2 between adjacent second protection circuits 32 in the second circuit group Z2 satisfy the relationship: S1 = S2. In this way, it is equivalent to arranging the first protection circuits 31 in the first circuit group Z1 and the second protection circuits 32 in the second circuit group Z2 at equal intervals, which is conducive to simplifying the arrangement complexity of the first protection circuits 31 and the second protection circuits 32, and simplifying the layout structure of the electrostatic protection circuit 30 in the display panel.

[0083] Fig.18 FIG. 1 is a circuit layout diagram of a display panel provided by the present disclosure. It should be noted that: Fig.18Only part of the film layers in the display panel are illustrated, and the entire film layer structure in the display panel is not shown. The relative position relationship of the first circuit group Z1, the second circuit group Z2, the pixel driving circuit 40, the anode pad P01 of the light-emitting element LD and other structures are illustrated, and the arrangement of the voltage lines 51 / 52 / 53 / 54 connected to the electrostatic protection circuit 30, the trigger signal line VSR_STV connected to the shift register circuit, and the data line DATA_PWM and the power line VDD_PWM corresponding to the pulse width modulation circuit 120 are illustrated, and the actual arrangement of these signal lines is not limited. Optionally, these signal lines are arranged in the same layer. Please combine Figure 2 and Fig.18 In an optional embodiment of the present disclosure, the electrostatic protection circuit 30 overlaps with the light emitting element LD in a direction perpendicular to the plane where the light emitting surface of the display panel is located. It should be noted that, Fig.18 Only the anode pad P01 for binding the light emitting element LD is shown, and the light emitting element LD is not shown. The relative position relationship between the light emitting element LD and the anode pad P01 can be referred to. Figure 2 , the electrode of the light-emitting element LD is bound to the anode pad P01 and the cathode pad P02. When the anode pad P01 overlaps with the electrostatic protection circuit 30, the light-emitting element LD also overlaps with the electrostatic protection circuit 30. In the actual production process, the electrode of the light-emitting element LD can be bound to the anode pad P01 and the cathode pad P02 by bonding. After the light-emitting element LD is bound to the anode pad P01 and the cathode pad P02, the light-emitting element LD will overlap with the electrostatic protection circuit 30 in a direction perpendicular to the plane where the display panel is located, and part of the electrostatic protection circuit 30 will be located below the light-emitting chip of the light-emitting element LD. In this way, the effective space in the display panel is fully utilized, and the space utilization rate of the display panel is improved.

[0084] Fig.19 FIG. 1 is a schematic diagram showing a connection between the electrostatic protection circuit 30 and the first voltage line and the second voltage line. Fig. 20 Shown with Fig.19 For a schematic diagram of the corresponding electrostatic protection circuit, please refer to Fig.19 and Fig. 20In an optional embodiment of the present disclosure, the display panel also includes a pixel driving circuit 40, and along the first direction D1, the pixel driving circuit 40 is located on a side of the electrostatic protection circuit 30 away from the edge of the display panel; the display area includes a first voltage line and a second voltage line, the first signal terminal S01 of the electrostatic protection circuit 30 is electrically connected to the first voltage line 051, and the second signal terminal S02 of the electrostatic protection circuit 30 is electrically connected to the second voltage line 052; along the first direction D1, the first voltage line 051 and the second voltage line 052 are located on both sides of the electrostatic protection circuit 30, and the first voltage line 051 is located between the electrostatic protection circuit 30 and the pixel driving circuit 40.

[0085] Please refer to Fig.19 and Fig. 20In the present disclosure, the electrostatic protection circuit 30 includes a first protection circuit 31 and a second protection circuit 32. The first protection circuit 31 is used to be electrically connected to the end of the first type signal line 01 connected to the pulse width modulation circuit 120, and the second protection circuit 32 is used to be electrically connected to the end of the second type signal line 02 connected to the pulse amplitude modulation circuit 110. The first protection circuit 31 includes a first transistor T1 and a second transistor T2, and the second protection circuit 32 includes a third transistor T3 and a fourth transistor T4. In the first protection circuit 31, optionally, the first transistor T1 and the second transistor T2 are arranged along the first direction D1, and the gate and the first electrode of the first transistor T1 are connected to the first direction D2. The second electrode of the second transistor T2 is electrically connected to the end of the first type signal line 01, the second electrode of the first transistor T1 is connected to the first voltage line 051, and receives a high voltage, and the gate and the first electrode of the second transistor T2 are connected to the second voltage line 052, and receive a low voltage; in the second protection circuit 32, optionally, the third transistor T3 and the fourth transistor T4 are arranged along the first direction D1, the gate and the first electrode of the third transistor T3, and the second electrode of the fourth transistor T4 are connected to the end of the second type signal line 02, the second electrode of the third transistor T3 is connected to the first voltage line 051, and receives a high voltage, and the gate and the first electrode of the fourth transistor T4 are connected to the second voltage line 052, and receive a low voltage. It can be seen that in the first protection circuit 31 and the second protection circuit 32, the second electrode of the first transistor T1 and the second electrode of the third transistor T3 are connected to the first voltage line. When the first voltage line is set on the same side of the first transistor T1 and the third transistor T3 along the first direction D1, it is beneficial to simplify the connection of the first voltage line 051; the gate and the first electrode of the second transistor T2 and the gate and the first electrode of the fourth transistor T4 are connected to the second voltage line 052. When the second voltage line 052 is set on the same side of the second transistor T2 and the fourth transistor T4 along the first direction D1, it is beneficial to simplify the connection of the second voltage line 052. Therefore, when the second transistor T2 in the first protection circuit 31 is set between the first transistor T1 and the edge of the display panel, and the fourth transistor T4 in the second protection circuit 32 is set between the third transistor T3 and the edge of the display panel, the first voltage line 051 and the second voltage line 052 are respectively set on both sides of the electrostatic protection circuit 30 along the first direction D1, and the first voltage line 051 is set close to the first transistor T1 and the third transistor T3, and the second voltage line 052 is set close to the second transistor T2 and the fourth transistor T4. In other words, the first voltage line 051 is set between the electrostatic protection circuit 30 and the pixel driving circuit 40, and the second voltage line 052 is set between the electrostatic protection circuit 30 and the edge of the display panel, which is conducive to simplifying the connection between the first transistor T1 and the third transistor T3 and the first voltage line 051, and is conducive to simplifying the connection between the second transistor T2 and the fourth transistor T4 and the second voltage line 052, thereby helping to simplify the overall wiring complexity of the display panel.

[0086] It should be noted that when the positions of the first transistor T1 and the second transistor T2 in the first protection circuit 31 are interchanged, and the positions of the third transistor T3 and the fourth transistor T4 in the second protection circuit 32 are interchanged, the positions of the first voltage line 051 and the second voltage line 052 are also interchanged accordingly. At this time, the second voltage line 052 will be located between the electrostatic protection circuit 30 and the pixel driving circuit 40, which can also simplify the connection between the first transistor T1 and the third transistor T3 and the first voltage line 051, and simplify the connection between the second transistor T2 and the fourth transistor T4 and the second voltage line 052.

[0087] Please refer to Figure 8 and Fig. 9 In an optional embodiment of the present disclosure, the electrostatic protection circuit 30 includes a first protection circuit 31 and a second protection circuit 32, the pixel driving circuit 40 includes a pulse width modulation circuit 120 and a pulse amplitude modulation circuit 110, the first signal line 10 includes a first type of signal line 01 and a second type of signal line 02, the first type of signal line 01 is electrically connected to the pulse width modulation circuit 120, and the second type of signal line 02 is electrically connected to the pulse amplitude modulation circuit 110; the end of the first type of signal line 01 is electrically connected to the first protection circuit 31, and the end of the second type of signal line 02 is electrically connected to the second protection circuit 32;

[0088] The first voltage line includes a first sub-line 51 and a second sub-line 52, the second voltage line includes a third sub-line 53 and a fourth sub-line 54, the first signal terminal S01 and the second signal terminal S02 of the first protection circuit 31 are electrically connected to the first sub-line 51 and the third sub-line 53, respectively, and the first signal terminal S01 and the second signal terminal S02 of the second protection circuit 32 are electrically connected to the second sub-line 52 and the fourth sub-line 54, respectively;

[0089] Along the first direction D1 , the first sub-line 51 is located between the electrostatic protection circuit 30 and the second sub-line 52 , and the third sub-line 53 is located between the electrostatic protection circuit 30 and the fourth sub-line 54 .

[0090] Please continue to refer to Figure 8 and Fig. 9This embodiment shows a scheme in which the first protection circuit 31 and the second protection circuit 32 are connected to different signals, and voltage lines are respectively set for the first protection circuit 31 and the second protection circuit 32, wherein the first voltage line includes a first sub-line 51 and a second sub-line 52 that are insulated from each other, and the second voltage line includes a third sub-line 53 and a fourth sub-line 54 that are insulated from each other, and the first signal terminal S01 of the first protection circuit 31 is connected to the first sub-line 51 to obtain a first high voltage, and the second signal terminal S02 of the first protection circuit 31 is connected to the third sub-line 53 to obtain a first low voltage; the first signal terminal S01 of the second protection circuit 32 is connected to the second sub-line 52 to obtain a second high voltage, and the second signal terminal S02 of the second protection circuit 32 is connected to the fourth sub-line 54 to obtain a second low voltage, wherein the first high voltage is different from the second high voltage, and / or the first low voltage is different from the second low voltage. In this embodiment, the first sub-line 51 and the second sub-line 52 are located on one side of the electrostatic protection circuit 30 along the first direction D1, and the third sub-line 53 and the fourth sub-line 54 are located on the other side of the electrostatic protection circuit 30 along the first direction D1, and the first sub-line 51 and the third sub-line 53 are closer to the electrostatic protection circuit 30, that is, the first sub-line 51 is located on the side of the second sub-line 52 facing the electrostatic protection circuit 30, and the third sub-line 53 is located on the side of the fourth sub-line 54 facing the electrostatic protection circuit 30. In this way, the first protection circuit 31 can be directly connected to the first sub-line 51 and the third sub-line 53, which is conducive to reducing the difficulty of connecting the first protection circuit 31 with the first sub-line 51 and the third sub-line 53. When the second protection circuit 32 is connected to the second sub-line 52 and the fourth sub-line 54, it can be connected by a cross-line method. In this embodiment, the arrangement of each transistor in the first protection circuit 31 and the second protection circuit 32 can refer to Fig.18 The embodiments shown are described, and the repeated parts are not repeated here.

[0091] It should be noted that in some other embodiments of the present disclosure, Fig.19 The positions of the first sub-line 51 and the second sub-line 52 are interchanged, and the positions of the third sub-line 53 and the fourth sub-line 54 are interchanged, so that the second protection circuit 32 can be directly connected to the second sub-line 52 and the fourth sub-line 54, which is beneficial to reduce the difficulty of connecting the second protection circuit 32 with the second sub-line 52 and the fourth sub-line 54. The first protection circuit 31 can be connected to the first sub-line 51 and the third sub-line 53 by means of a cross-line.

[0092] Please continue to refer to Fig.19 and Fig. 20In an optional embodiment of the present disclosure, the electrostatic protection circuit 30 includes a first protection circuit 31 and a second protection circuit 32, the pixel driving circuit 40 includes a pulse width modulation circuit 120 and a pulse amplitude modulation circuit 110, and the first signal line 10 includes a first type of signal line 01 and a second type of signal line 02, the first type of signal line 01 is electrically connected to the pulse width modulation circuit 120, and the second type of signal line 02 is electrically connected to the pulse amplitude modulation circuit 110; the end of the first type of signal line 01 is electrically connected to the first protection circuit 31, and the end of the second type of signal line 02 is electrically connected to the second protection circuit 32; the first signal terminal S01 of the first protection circuit 31 and the first signal terminal S01 of the second protection circuit 32 are connected to the first voltage line 051, and the second signal terminal S02 of the first protection circuit 31 and the second signal terminal S02 of the second protection circuit 32 are connected to the second voltage line 052.

[0093] Fig.19 and Fig. 20 The illustrated embodiment shows a scheme in which the first protection circuit 31 and the second protection circuit 32 are connected to the same signal, that is, the first transistor T1 in the first protection circuit 31 and the third transistor T3 in the second protection circuit 32 are connected to the same first voltage line 051, and the second transistor T2 in the first protection circuit 31 and the fourth transistor T4 in the second protection circuit 32 are connected to the same second voltage line 052. This arrangement does not require the introduction of different voltage lines for the first protection circuit 31 and the second protection circuit 32, respectively. The first protection circuit 31 and the second protection circuit 32 can share a set of voltage lines, which is conducive to reducing the number of voltage lines corresponding to the electrostatic protection circuit 30 and simplifying the wiring complexity. It should be noted that the arrangement of the transistors in the first protection circuit 31 and the second protection circuit 32 and the arrangement of the first voltage line 051 and the second voltage line 052 can be the content of the aforementioned embodiment, and will not be repeated in this embodiment.

[0094] Please refer to Figure 2 and Fig.18 In an optional embodiment of the present disclosure, the display area includes a light-emitting element LD and a pixel driving circuit 40 connected to the light-emitting element LD, and the electrostatic protection circuit 30 and the pixel driving circuit 40 do not overlap along a direction perpendicular to the plane where the display panel is located.

[0095] When the electrostatic protection circuit 30 is introduced into the display panel provided in the present disclosure, in order to realize the electrical connection between the electrostatic protection circuit 30 and the end of the first signal line 10, the electrostatic protection circuit 30 is arranged along the first direction D1 on the side of the edge of the display panel in the area where the pixel driving circuit 40 is located, so as to avoid the overlap of the electrostatic protection circuit 30 and the pixel driving circuit 40 in the direction perpendicular to the plane where the display panel is located, which is beneficial to avoid the problem of signal crosstalk between the electrostatic protection circuit 30 and the pixel driving circuit 40, and is beneficial to improving the working reliability of the display panel.

[0096] Please continue to refer to Fig.12 and Fig.18 In an optional embodiment of the present disclosure, the electrostatic protection circuit 30 overlaps with the pixel driving circuit 40 along the first direction D1. That is to say, when the electrostatic protection circuit 30 is introduced into the display panel, the electrostatic protection circuit 30 is arranged on one side or both sides of the pixel driving circuit 40 along the first direction D1, that is to say, along the first direction D1, the area where the electrostatic protection circuit 30 is located overlaps with the area where the pixel driving circuit 40 is located. Since the pixel driving circuit 40 is electrically connected to the first signal line 10 extending along the first direction D1, and the electrostatic protection circuit 30 is electrically connected to the end of the first signal line 10, therefore, setting the electrostatic protection circuit 30 to overlap with the pixel driving circuit 40 along the first direction D1 is conducive to simplifying the winding of the first signal line 10 when connecting with the electrostatic protection circuit 30, thereby helping to simplify the overall wiring complexity of the display panel.

[0097] Please continue to refer to Fig.12 and Fig.18 In an optional embodiment of the present disclosure, the electrostatic protection circuit 30 includes a first protection circuit 31 and a second protection circuit 32, the pixel driving circuit 40 includes a pulse width modulation circuit 120 and a pulse amplitude modulation circuit 110, the first protection circuit 31 is connected to the first signal line 10 corresponding to the pulse width modulation circuit 120, and the second protection circuit 32 is connected to the first signal line 10 corresponding to the pulse amplitude modulation circuit 110; along the first direction D1, the first protection circuit 31 overlaps with the pulse width modulation circuit, and the second protection circuit 32 overlaps with the pulse amplitude modulation circuit.

[0098] When the electrostatic protection circuit 30 is introduced into the display panel, the electrostatic protection circuit 30 is divided into a first protection circuit 31 connected to the first signal line 10 corresponding to the pulse width modulation circuit 120, and a second protection circuit 32 connected to the first signal line 10 corresponding to the pulse amplitude modulation circuit 110. Optionally, in the pixel driving circuit 40, the pulse width modulation circuit 120 and the pulse amplitude modulation circuit 110 are arranged along the second direction D2 to Fig.17 and Fig.18For example, the pulse width modulation circuit 120 is above the pulse amplitude modulation circuit 110, so that the first type signal line 01 connected to the pulse width modulation circuit 120 will also be located above the second type signal line 02 connected to the pulse amplitude modulation circuit 110. In this embodiment, along the first direction D1, the first protection circuit 31 is set to overlap with the pulse width modulation circuit 120, and the second protection circuit 32 overlaps with the pulse amplitude modulation circuit 110. In this way, when the first protection circuit 31 is electrically connected to the first type signal line 01, the first type signal line 01 can be electrically connected to the first protection circuit 31 without a large amount of winding or crossing the line. Similarly, when the second protection circuit 32 is electrically connected to the second type signal line 02, the second type signal line 02 can be electrically connected to the second protection circuit 32 without a large amount of winding or crossing the line. Therefore, it is helpful to simplify the connection between the first signal line 10 and the electrostatic protection circuit 30 and the overall wiring difficulty of the display panel.

[0099] Please refer to Figure 2 Combined with Fig.18 In an optional embodiment of the present disclosure, the display panel includes a flat layer JY1 and a power wiring layer M0 located on the side of the flat layer JY1 facing the light emitting surface of the display panel, and the power line VEE in the power wiring layer M0 includes a plurality of first openings K1, and the first openings K1 overlap with the electrostatic protection circuit 30 along a direction perpendicular to the plane where the light emitting surface of the display panel is located.

[0100] The flat layer JY1 in the display panel is made of organic insulating material. After the organic material is subjected to a high-temperature process, some water vapor and other substances will be volatilized. If a large piece of metal is covered on the organic insulating material, the volatile substances of the organic insulating material are usually unable to penetrate the dense metal layer, for example, the power wiring layer M0, thereby causing the surface of the power wiring VEE in individual areas to bulge, causing defects. Therefore, the present disclosure sets a plurality of first openings K1 on the power line VEE in the power wiring layer M0. When the organic insulating material generates volatile substances, the volatile substances can be volatilized through the first openings K1, thereby avoiding the problem of bulging of the power line VEE caused by the difficulty of volatilization of the volatile substances. In this embodiment, the first opening K1 on the power line overlaps with the electrostatic protection circuit 30 in a direction perpendicular to the plane where the light-emitting surface of the display panel is located, thereby facilitating the reduction of crosstalk between the electrostatic protection circuit 30 and the power signal on the power line, thereby facilitating the improvement of the working reliability of the electrostatic protection circuit 30 in the display panel and the signal stability on the power line.

[0101] Please combine Figure 2 , Figure 8 , Fig.17 , Fig.18 and Fig.19In an optional embodiment of the present disclosure, the display area includes a light-emitting element LD and a pixel driving circuit 40 connected to the light-emitting element LD, the pixel driving circuit 40 includes a pulse width modulation circuit 120 and a pulse amplitude modulation circuit 110, the first signal line 10 includes a first type of signal line 01 and a second type of signal line 02, the first type of signal line 01 is electrically connected to the pulse width modulation circuit 120, and the second type of signal line 02 is electrically connected to the pulse amplitude modulation circuit 110; the electrostatic protection circuit 30 includes a first protection circuit 31 and a second protection circuit 32, the first type of signal line 01 is electrically connected to the pulse width modulation circuit 120, and the second type of signal line 02 is electrically connected to the pulse amplitude modulation circuit 110; The end of the second type signal line 01 is electrically connected to the first protection circuit 31, and the end of the second type signal line 02 is electrically connected to the second protection circuit 32; the protection circuit includes a first circuit group Z1 and a second circuit group Z2, the first circuit group Z1 includes multiple first protection circuits 31, and the second circuit group Z2 includes multiple second protection circuits 32; the display panel includes an anode pad P01 and a cathode pad P02 connected to the light-emitting element LD, the anode pad P01 overlaps with the second protection circuit 32 in the second circuit group Z2, and overlaps with part of the first protection circuit 31 in the first circuit group Z1.

[0102] In the present disclosure, in the area where the electrostatic protection circuit 30 is set, the first circuit group Z1 and the second circuit group Z2 are alternately arranged along the second direction D2, the first protection circuit 31 in the first circuit group Z1 is used to be electrically connected to the first type of signal line 01 corresponding to the pulse width modulation circuit 120, and the second protection circuit 32 in the second circuit group Z2 is used to be electrically connected to the second type of signal line 02 corresponding to the pulse amplitude modulation circuit 110, so as to realize the conduction of static electricity. In order to make full use of the space of the display panel, the light-emitting element LD can also be set in the area where the electrostatic protection circuit 30 is set, for example, the anode pad P01 and the cathode pad P02 electrically connected to the light-emitting element LD are set above the transistors corresponding to the first protection circuit 31 and the second protection circuit 32, that is, set on the film layer above the electrostatic protection circuit 30, so that the electrostatic protection circuit 30 and the light-emitting element LD do not interfere with each other in the setting space. At this time, along the direction perpendicular to the plane where the light emitting surface of the display panel is located, the anode pad P01 of the light emitting element LD overlaps with the second protection circuit 32 in the second circuit group Z2, and overlaps with part of the first protection circuit 31 in the first circuit group Z1. In this embodiment, along the first direction D1, the first circuit group Z1 is located above the second circuit group Z2, which is equivalent to arranging the light emitting element LD in the middle area and the lower area of ​​the area where the electrostatic protection circuit 30 is located, thereby realizing rational use of the space in the display panel.

[0103] It should be noted that in order to simplify the film layer setting on the display panel, the anode pad P01, the cathode pad P02 and the negative power line VEE in the display panel can be set in the same film layer. To avoid short circuit, a gap can be formed by digging holes, for example, a gap for insulation is formed between the anode pad P01 and the cathode pad P02, and a gap for insulation is formed between the cathode pad P02 and the power line.

[0104] Please continue to refer to Figure 2 and Fig.18 In an optional embodiment of the present disclosure, both the cathode pad P02 and the anode pad P01 have openings, and the opening of the anode pad P01 overlaps with the electrostatic protection circuit 30 along a direction perpendicular to the plane where the light emitting surface of the display panel is located.

[0105] When the anode pad P01 and the cathode pad P02 are arranged above the flat layer JY1 in the display panel, openings are formed on the anode pad P01 and the cathode pad P02. When the organic material in the flat layer JY1 produces volatile substances, the volatile substances can volatilize through the above openings, thereby avoiding the problem of bulging of the anode pad P01 and the cathode pad P02 due to the difficulty of volatilizing the volatile substances. In addition, in this embodiment, the opening of the anode pad P01 is overlapped with the electrostatic protection circuit 30, which is conducive to reducing the interference of the electrostatic protection circuit 30 on the signal on the anode pad P01, and improving the light-emitting stability and accuracy of the light-emitting element LD.

[0106] Based on the same inventive concept, the present disclosure also provides a display device, Fig.21 FIG. 2 is a schematic diagram of a structure of a display device 200 provided in an embodiment of the present disclosure. Fig.21 , the display device 200 includes the display panel in any of the above embodiments. The display device 200 provided in the embodiment of the present disclosure may be any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a laptop computer, an e-book, or a television. The display device 200 provided in the embodiment of the present disclosure has the beneficial effects of the display panel provided in the embodiment of the present disclosure. For details, please refer to the specific description of the display panel in the above embodiments, which will not be repeated in this embodiment.

[0107] Understandably, Fig.21 Only a rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of the present disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and the present disclosure does not specifically limit this.

[0108] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0109] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: It includes a shift register circuit located in a display area and a plurality of first signal lines connected to the shift register circuit, wherein the first signal lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect; The display panel also includes an electrostatic protection circuit arranged in the display area. Along the first direction, the electrostatic protection circuit is located on the side of the end of the first signal line facing the edge of the display panel, and the end of the first signal line is electrically connected to the electrostatic protection circuit.

2. The display panel according to claim 1, characterized in that: The electrostatic protection circuit includes a first protection circuit and a second protection circuit, and the first protection circuit and the second protection circuit are connected to different signals.

3. The display panel according to claim 2, characterized in that: The first protection circuit and the second protection circuit include a first signal terminal and a second signal terminal respectively; The first signal terminal of the first protection circuit is configured to receive a first high voltage, and the second signal terminal of the first protection circuit is configured to receive a first low voltage; The first signal terminal of the second protection circuit is configured to receive a second high voltage, and the second signal terminal of the second protection circuit is configured to receive a second low voltage; wherein the first high voltage is not equal to the second high voltage, and / or the first low voltage is not equal to the second low voltage.

4. The display panel according to claim 3, characterized in that: The voltage value of the first high voltage is V11, the voltage value of the first low voltage is V01, the voltage value of the second high voltage is V12, and the voltage value of the second low voltage is V02, wherein V11-V01=V12-V02.

5. The display panel according to claim 3, characterized in that: The voltage value of the first high voltage is V11, the voltage value of the first low voltage is V01, the voltage value of the second high voltage is V12, and the voltage value of the second low voltage is V02, wherein V11-V01≠V12-V02.

6. The display panel according to claim 3, characterized in that: The voltage value of the first high voltage is V11, the voltage value of the first low voltage is V01, the voltage value of the second high voltage is V12, the voltage value of the second low voltage is V02, V11>V12>0, V02<V01<0.

7. The display panel according to claim 2, characterized in that: The display area includes a light-emitting element and a pixel driving circuit connected to the light-emitting element, the pixel driving circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, the first signal line includes a first type of signal line and a second type of signal line, the first type of signal line is electrically connected to the pulse width modulation circuit, and the second type of signal line is electrically connected to the pulse amplitude modulation circuit; An end of the first-type signal line is electrically connected to the first protection circuit, and an end of the second-type signal line is electrically connected to the second protection circuit.

8. The display panel according to claim 7, characterized in that: The first protection circuit includes a first transistor and a second transistor, the gate and the first electrode of the first transistor are electrically connected to the end of the first type signal line, and the second electrode of the first transistor receives a first high voltage; the gate and the first electrode of the second transistor receive a first low voltage, and the second electrode of the second transistor is electrically connected to the end of the first type signal line; The second protection circuit includes a third transistor and a fourth transistor, the gate and the first electrode of the third transistor are electrically connected to the end of the second type of signal line, the second electrode of the third transistor receives a second high voltage; the gate and the first electrode of the fourth transistor receive a second low voltage; the second electrode of the fourth transistor is electrically connected to the end of the second type of signal line.

9. The display panel according to claim 8, characterized in that: The pixel driving circuit includes a first scanning line, a first light emitting control signal line, a first reset signal line and a frequency sweeping signal line electrically connected to the pulse width modulation circuit, and a second scanning line, a second light emitting control signal line and a second reset signal line electrically connected to the pulse amplitude modulation circuit; The first type of signal line includes at least one of the first scan line, the first light-emitting control signal line, the first reset signal line and the frequency scanning signal line, and the second type of signal line includes at least one of the second scan line, the second light-emitting control signal line and the second reset signal line.

10. The display panel according to claim 9, characterized in that: The first protection circuit includes a first subcircuit and a second subcircuit, the first subcircuit is connected to the first reset signal line, and the second subcircuit is connected to at least one of the first scan line, the first light emission control signal line, and the frequency sweep signal line; The channel width of the first transistor in the first sub-circuit is W11, and the channel width of the second transistor is W12; the channel width of the first transistor in the second sub-circuit is W21, and the channel width of the second transistor is W22, wherein W11<W21, and / or W12<W22.

11. The display panel according to claim 10, characterized in that: In the plurality of second sub-circuits, the channel widths of the first transistors and the second transistors are the same.

12. The display panel according to claim 9, characterized in that: The second protection circuit includes a third subcircuit and a fourth subcircuit, the third subcircuit is connected to the second reset signal line, and the fourth subcircuit is connected to at least one of the second scan line and the second light emitting control signal line; The channel width of the third transistor in the third sub-circuit is W13, and the channel width of the fourth transistor is W14; the channel width of the third transistor in the fourth sub-circuit is W23, and the channel width of the fourth transistor is W24, wherein W13<W23, and / or W14<W24.

13. The display panel according to claim 12, characterized in that: In the plurality of fourth sub-circuits, the channel widths of the third transistors and the fourth transistors are the same.

14. The display panel according to claim 9, characterized in that: The first protection circuit includes a first sub-circuit and a second sub-circuit, the first sub-circuit is connected to the first reset signal line, and the second sub-circuit is connected to at least one of the first scan line, the first light-emitting control signal line and the frequency scanning signal line; the second protection circuit includes a third sub-circuit and a fourth sub-circuit, the third sub-circuit is connected to the second reset signal line, and the fourth sub-circuit is connected to at least one of the second scan line and the second light-emitting control signal line; the channel width of the transistor in the first sub-circuit is the same as the channel width of the transistor in the third sub-circuit.

15. The display panel according to claim 14, characterized in that: The channel widths of the transistors in the second sub-circuit and the fourth sub-circuit are the same.

16. The display panel according to claim 2, characterized in that: Along the first direction, the first protection circuit and the second protection circuit are located on one side of the first signal line; or, along the first direction, the first protection circuit is located on a first side of the first signal line, and the second protection circuit is located on a second side of the first signal line, wherein the first side and the second side are arranged opposite to each other.

17. The display panel according to claim 1, characterized in that: The electrostatic protection circuit is disposed on a first side and a second side of the first signal line along the first direction, wherein the first side and the second side are disposed opposite to each other.

18. The display panel according to claim 1, characterized in that: Two opposite ends of the first signal line along the first direction are electrically connected to the electrostatic protection circuit.

19. The display panel according to claim 2, characterized in that: The electrostatic protection circuit includes a first circuit group and a second circuit group, the first circuit group includes a plurality of first protection circuits, the second circuit group includes a plurality of second protection circuits, the plurality of first protection circuits are arranged along the second direction, and the plurality of second protection circuits are arranged along the second direction; on the same side of the first signal line along the first direction, the first circuit group and the second circuit group are alternately arranged; Along the second direction, the spacing between two adjacent first protection circuits in the first circuit group is S1, the spacing between two adjacent second protection circuits in the second circuit group is S2, and the spacing between adjacent first circuit groups and second circuit groups is S0, S0>S1, and / or, S0>S2.

20. The display panel according to claim 19, characterized in that: S1=S2.

21. The display panel according to claim 1, characterized in that: The display panel further includes a pixel driving circuit, and along the first direction, the display panel is located on a side of the edge of the electrostatic protection circuit away from the pixel driving circuit; The display area includes a first voltage line and a second voltage line, the first signal end of the electrostatic protection circuit is electrically connected to the first voltage line, and the second signal end of the electrostatic protection circuit is electrically connected to the second voltage line; Along the first direction, the first voltage line and the second voltage line are located at two sides of the electrostatic protection circuit, and the first voltage line is located between the electrostatic protection circuit and the pixel driving circuit.

22. The display panel according to claim 21, characterized in that: The electrostatic protection circuit includes a first protection circuit and a second protection circuit, the pixel driving circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, the first signal line includes a first type of signal line and a second type of signal line, the first type of signal line is electrically connected to the pulse width modulation circuit, and the second type of signal line is electrically connected to the pulse amplitude modulation circuit; the end of the first type of signal line is electrically connected to the first protection circuit, and the end of the second type of signal line is electrically connected to the second protection circuit; The first voltage line includes a first sub-line and a second sub-line, the second voltage line includes a third sub-line and a fourth sub-line, the first signal terminal and the second signal terminal of the first protection circuit are electrically connected to the first sub-line and the third sub-line respectively, and the first signal terminal and the second signal terminal of the second protection circuit are electrically connected to the second sub-line and the fourth sub-line respectively; Along the first direction, the first sub-line is located between the electrostatic protection circuit and the second sub-line, and the third sub-line is located between the electrostatic protection circuit and the fourth sub-line.

23. The display panel according to claim 21, characterized in that: The electrostatic protection circuit includes a first protection circuit and a second protection circuit, the pixel driving circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, the first signal line includes a first type of signal line and a second type of signal line, the first type of signal line is electrically connected to the pulse width modulation circuit, and the second type of signal line is electrically connected to the pulse amplitude modulation circuit; the end of the first type of signal line is electrically connected to the first protection circuit, and the end of the second type of signal line is electrically connected to the second protection circuit; The first signal end of the first protection circuit and the first signal end of the second protection circuit are connected to the first voltage line, and the second signal end of the first protection circuit and the second signal end of the second protection circuit are connected to the second voltage line.

24. The display panel according to claim 1, characterized in that: The display area includes a light-emitting element and a pixel driving circuit connected to the light-emitting element. Along a direction perpendicular to the plane where the display panel is located, the electrostatic protection circuit and the pixel driving circuit do not overlap.

25. The display panel according to claim 24, characterized in that: Along the first direction, the electrostatic protection circuit overlaps with the pixel driving circuit.

26. The display panel according to claim 25, characterized in that: The electrostatic protection circuit includes a first protection circuit and a second protection circuit, the pixel driving circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, the first protection circuit is connected to the first signal line corresponding to the pulse width modulation circuit, and the second protection circuit is connected to the first signal line corresponding to the pulse amplitude modulation circuit; Along the first direction, the first protection circuit overlaps with the pulse width modulation circuit, and the second protection circuit overlaps with the pulse amplitude modulation circuit.

27. The display panel according to claim 24, characterized in that: Along a direction perpendicular to a plane where a light emitting surface of the display panel is located, the electrostatic protection circuit overlaps with the light emitting element.

28. The display panel according to claim 1, characterized in that: The display panel includes a flat layer and a power wiring layer located on the side of the flat layer facing the light emitting surface of the display panel, the power line in the power wiring layer includes a plurality of first openings, and the first openings overlap with the electrostatic protection circuit along a direction perpendicular to the plane where the light emitting surface of the display panel is located.

29. The display panel according to claim 1, characterized in that: The display area includes a light-emitting element and a pixel driving circuit connected to the light-emitting element, the pixel driving circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, the first signal line includes a first type of signal line and a second type of signal line, the first type of signal line is electrically connected to the pulse width modulation circuit, and the second type of signal line is electrically connected to the pulse amplitude modulation circuit; the electrostatic protection circuit includes a first protection circuit and a second protection circuit, the end of the first type of signal line is electrically connected to the first protection circuit, and the end of the second type of signal line is electrically connected to the second protection circuit; the protection circuit includes a first circuit group and a second circuit group, the first circuit group includes a plurality of the first protection circuits, and the second circuit group includes a plurality of the second protection circuits; The display panel includes an anode pad and a cathode pad connected to the light emitting element, and the anode pad overlaps with both of the second protection circuits in the second circuit group and overlaps with a portion of the first protection circuits in the first circuit group.

30. The display panel according to claim 29, characterized in that: The cathode pad and the anode pad both have an opening, and along a direction perpendicular to the plane where the light emitting surface of the display panel is located, the opening of the anode pad overlaps with the electrostatic protection circuit.

31. A display device, characterized in that: The display panel comprises any one of claims 1 to 30.

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