Memory device supporting word line hold operation and operating method thereof

Abstract

The invention relates to a memory device supporting word line holding operation and an operating method thereof. The memory device includes: a memory cell array; and a controller configured to: perform program cycles until a program operation of selecting a memory cell succeeds, each program cycle including a voltage application operation, a word line holding operation, and a verify operation; applying a hold pass voltage having a level higher than a ground voltage to each of a first word line having a program state and a second word line having an erase state during a word line hold operation, the first word line and the second word line belonging to unselected word lines among the plurality of word lines; during a verify operation, a verify pass voltage having a higher level than the hold pass voltage is applied to K word lines belonging to the first word line and the second word lines, and the hold pass voltage is applied to the remaining word lines other than the K word lines among the second word lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0097993, filed on Jul. 27, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments relate to a memory device, and more particularly, to a memory device supporting a word line holding operation and an operating method thereof. Background Art

[0004] A memory system is a storage device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. The memory system may be a volatile memory device or a non-volatile memory device. A volatile memory device is a memory device in which the data stored therein is lost when its power supply is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. A non-volatile memory device is a memory device in which the data stored therein is retained even when its power supply is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. The flash memory may be a NOR-type flash memory or a NAND-type flash memory.

[0005] A cell of a nonvolatile memory device is an element on which electrical programming / erasing operations can be performed. When electrons are moved by a strong electric field applied to a thin oxide film of a cell, a nonvolatile memory device can perform programming and erasing operations on a cell by changing the threshold voltage of the cell.

[0006] A programming operation of a plurality of memory cells included in a nonvolatile memory device may be performed by an incremental step pulse programming (ISPP) algorithm, the ISPP algorithm being used to change the threshold voltage of a memory cell selected as a programming target while applying a programming pulse with a gradually increasing voltage to a word line to which the memory cell selected as a programming target is connected. In addition, after applying the programming pulse, a verification operation of checking whether the threshold voltage level of the memory cell selected as a programming target has reached a target voltage level may be performed. In this case, the verification operation may be repeated together with the voltage application operation by the ISPP algorithm.

[0007] Furthermore, in the voltage application operation, the difference between the potential level of the programming voltage applied to the word line selected as the programming target and the potential level of the programming pass voltage applied to the word line not selected as the programming target may be large. Therefore, even after the moment when the voltage application operation has been completed, the potential level of the word line selected as the programming target and the potential level of the word line not selected as the programming target may be in a state where the potential levels have a certain degree of difference. The verification operation performed in this state will likely cause an error. Summary of the invention

[0008] Various embodiments of the present disclosure are directed to providing a memory device and an operating method thereof, the memory device being capable of performing a program operation by repeating a program loop in which a word line holding operation is added between a voltage applying operation and a verification operation.

[0009] In addition, embodiments of the present disclosure may provide a memory device and an operating method of the memory device, which memory device is capable of adjusting the voltage level applied to word lines that are not selected as programming targets between a word line hold operation and a verification operation included in a programming loop based on the state of the word lines that are not selected as programming targets (i.e., whether the unselected word lines are physically adjacent to the programming word lines or the erase word lines / selection word lines).

[0010] Problems to be solved by the present disclosure are not limited to the above-mentioned problems, and other unmentioned problems will be clearly understood by those skilled in the art from the following description.

[0011] In one aspect of an embodiment of the present disclosure, a memory device may include: a memory cell array including a plurality of cell strings connected between a plurality of bit lines and a common source line and a plurality of word lines connected to the plurality of cell strings; and a controller configured to: execute a programming loop until a programming operation for a selected memory cell corresponding to a selected word line and a selected cell string is successful, each programming loop including a voltage application operation, a word line holding operation, and a verification operation; during the word line holding operation, a holding pass voltage having a level higher than a ground voltage is applied to each of a first word line having a programming state and a second word line having an erased state, the first word line and the second word line being unselected word lines among a plurality of word lines; during the verification operation, a verification pass voltage having a level higher than the holding pass voltage is applied to K word lines belonging to the first word line and the second word line, and the holding pass voltage is applied to the remaining word lines among the second word lines except the K word lines, where K may be an integer equal to or greater than 0.

[0012] In one aspect of an embodiment of the present disclosure, a method for operating a memory device, the memory device including a plurality of cell strings connected between a plurality of bit lines and a common source line and a plurality of word lines connected to the plurality of cell strings, the method for operating may include: performing a programming loop until a programming operation of a selected memory cell corresponding to a selected word line and a selected cell string is successful, each programming loop including a voltage application operation, a word line holding operation, and a verification operation; classifying a plurality of word lines into selected word lines and unselected word lines, and classifying the unselected word lines into a first word line having a programmed state and a second word line having an erased state; during a word line holding operation, applying a hold pass voltage to each of a first word line and a second word line, and applying a hold voltage having a level higher than or equal to the hold pass voltage to the selected word line; and during a verification operation, applying a verification voltage to the selected word line, applying a verification pass voltage having a level higher than the hold pass voltage to K word lines belonging to the first word line and the second word line, and applying the hold pass voltage to the remaining word lines among the second word lines except the K word lines, wherein K may be an integer equal to or greater than 0.

[0013] According to the prior art, when a programming operation is performed on a memory cell connected to a word line selected as a programming target by repeating a voltage application operation, a holding operation, and a verification operation, the voltage level applied to the word line not selected as the programming target can be adjusted between the holding operation and the verification operation according to the state of the unselected word line (i.e., whether the unselected word line is physically adjacent to the programming word line or the erase word line / selection word line).

[0014] Therefore, in the process of performing the retention operation, unnecessary power consumption can be reduced by optimizing the change of the voltage level applied to the word line that is not selected as the program target. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a diagram for describing a memory device according to an embodiment of the present disclosure.

[0016] Figure 2 It is used to describe the embodiments according to the present disclosure. Figure 1 Schematic diagram of a programming operation of a memory device disclosed in FIG.

[0017] Figure 3 It is used to describe the embodiments according to the present disclosure. Figure 1 Schematic diagram of a controller among components of a memory device disclosed in .

[0018] FIG. 4A to FIG. 4C It is used to describe the embodiments according to the present disclosure. Figure 1 and Figure 2 Schematic diagram of a program loop included in a program operation of a memory device disclosed in FIG.

[0019] Figure 5 It is used to describe the embodiments according to the present disclosure. Figure 1 and Figure 2 A diagram of a sequence of programming operations of a memory device disclosed in FIG. DETAILED DESCRIPTION

[0020] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any disclosed embodiment.

[0021] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “optional embodiments,” etc.) are intended to indicate that any of these features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0022] In this disclosure, the terms "comprising", "including", "includes" and "comprising" are open ended. As used in the appended claims, these terms specify the presence of the elements stated and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components (e.g., interface units, circuits, etc.).

[0023] In the present disclosure, various units, circuits, or other components may be described or stated as being "configured to" perform one or more tasks. In this context, "configured to" is used to represent a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even if the block / unit / circuit / component is not currently running (e.g., not turned on or activated), it can be said that the specified block / unit / circuit / component is configured to perform a task. Blocks / units / circuit / components used with the "configured to" language include hardware, such as circuits, memories storing program instructions that can be run to implement operations, etc. In addition, "configured to" can include general structures (e.g., general circuits) manipulated by software and / or firmware (e.g., FPGAs or general processors running software) to operate in a manner that can perform the relevant tasks. "Configured to" can also include making a manufacturing process (e.g., a semiconductor manufacturing facility) suitable for manufacturing devices (e.g., integrated circuits) that implement or perform one or more tasks.

[0024] As used in this disclosure, the term "circuit" or "logic" refers to all of the following: (a) pure hardware circuit implementations (e.g., implementations of analog and / or digital circuits only), and (b) combinations of circuits and software (and / or firmware), such as (as applicable to): (i) a combination of processors or (ii) portions of processors / software (including digital signal processors), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions; and (c) circuits that require software or firmware to operate even if the software or firmware is not physically present (e.g., a microprocessor or a portion of a microprocessor). This definition of "circuit" or "logic" applies to all uses of the term in this application (including any claims). As another example, as used in this application, the term "circuit" or "logic" also covers implementations of only a processor (or multiple processors) or a portion of a processor and its (or their) accompanying software and / or firmware. For example, if applicable to a particular claim element, the term "circuit" or "logic" also covers integrated circuits of storage devices.

[0025] As used herein, the terms "first", "second", "third", etc. are used as labels for nouns preceding these terms, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms "first" and "second" do not necessarily mean that the first value must be written before the second value. In addition, although these terms can be used to identify various elements in this article, these elements are not limited by these terms. These terms are used to distinguish one element from another element, otherwise they would have the same or similar names. For example, a first circuit can be distinguished from a second circuit.

[0026] In addition, the term "based on" is used to describe one or more factors that affect the determination. The term does not exclude other factors that may affect the determination. That is, the determination may be based only on those factors or at least in part on those factors. For example, the phrase "determine A based on B." Although in this case, B is a factor that affects the determination of A, such a phrase does not exclude that the determination of A is also based on C. In other cases, A may be determined based only on B.

[0027] Herein, an item of data, a data item, a data entry, or an entry of data may be a bit sequence. For example, a data item may include file contents, a portion of a file, a page in a memory, an object in an object-oriented program, a digital message, a digital scanned image, a portion of a video or audio signal, or any other entity that may be represented by a bit sequence. According to an embodiment, a data item may include a discrete object. According to another embodiment, a data item may include an information unit within a transmission packet between two different components.

[0028] Figure 1is a diagram for describing a memory device 150 according to an embodiment of the present disclosure.

[0029] Figure 2 It is used to describe the embodiments according to the present disclosure. Figure 1 Schematic diagram of a programming operation of the memory device 150 disclosed in FIG.

[0030] Reference Figure 1 , the memory device 150 may include a memory cell array 201 and a controller 202 .

[0031] The memory cell array 201 may include a plurality of memory blocks. In addition, each memory block may include a plurality of pages, and each page may include a plurality of memory cells.

[0032] A storage block can be understood as a group of nonvolatile memory cells from which data is removed together by an erase operation. From a logical point of view, each storage block may include pages in which nonvolatile memory cells are grouped, such as pages that store data together during a programming operation or output data together during a read operation. For example, a storage block may include multiple pages. A page may include multiple nonvolatile memory cells.

[0033] From a physical perspective different from a logical perspective such as a program operation or a read operation, one memory block may include a plurality of word lines. One word line may include a plurality of nonvolatile memory cells.

[0034] In this case, according to the number of bits that can be stored or expressed in a nonvolatile memory cell, a word line can correspond to at least one page. For example, when a nonvolatile memory cell is a single-layer cell (SLC) storing one data bit, a word line can correspond to one page. When a nonvolatile memory cell is a double-layer cell (DLC) storing two data bits, a word line can correspond to two pages. When a nonvolatile memory cell is a triple-layer cell (TLC) storing three data bits, a word line can correspond to three pages. When a nonvolatile memory cell is a quad-layer cell (QLC) storing four data bits, a word line can correspond to four pages. In this way, when a nonvolatile memory cell is a multi-layer cell storing five or more data bits, a word line can correspond to five or more pages.

[0035] More specifically, each memory block may include a 3D structure. For example, each memory block may include a plurality of memory cells stacked on a substrate. Thus, each memory block may be arranged along the +X direction, the +Y direction, and the +Z direction.

[0036] That is, each memory block may include a plurality of memory cells connected among a plurality of word lines WL<1:n> arranged in the Z direction, a plurality of bit lines BL<1:m> arranged in the X direction, and a plurality of cell strings CS<1:2><1:m> arranged in the Y direction.

[0037] Herein, each of the cell strings CS<1:2><1:m> may include at least one source select transistor SST, first to nth memory cells MC<1:n>, and at least one drain select transistor DST.

[0038] Herein, each of the selection transistors SST and DST and the memory cells MC<1:n> may have a similar structure. According to an embodiment of the present disclosure, each of the selection transistors SST and DST and the memory cells MC<1:n> may include a channel layer, a tunnel dielectric layer, a charge storage layer, and a blocking dielectric layer. According to another embodiment of the present disclosure, a column for providing a channel layer may be provided in each cell string. According to yet another embodiment of the present disclosure, a column for providing at least one of a channel layer, a tunnel dielectric layer, a charge storage layer, and a blocking dielectric layer may be provided to each cell string.

[0039] The source selection transistor SST included in each of the cell strings CS<1:2><1:m> may be coupled between the common source line CSL and the memory cells MC<1:n>.

[0040] According to an embodiment of the present disclosure, source selection transistors of cell strings arranged in the same row may be connected to a source selection line extending in the row direction, and source selection transistors of cell strings arranged in different rows may be connected to different source selection lines. In the accompanying drawings, source selection transistors of cell strings CS1<1:m> in the first row may be connected to a first source selection line SSL1. In addition, source selection transistors of cell strings CS2<1:m> in the second row may be connected to a second source selection line SSL2.

[0041] According to another embodiment of the present disclosure, unlike those shown in the drawings, source selection transistors of cell strings CS1<1:m> and CS2<1:m> may be commonly coupled to one source selection line.

[0042] First to nth memory cells MC<1:n> included in each of the cell strings CS<1:2><1:m> may be coupled between a source select transistor SST and a drain select transistor DST.

[0043] The drain selection transistor DST included in each of the cell strings CS<1:2> <1:m> may be coupled between the corresponding bit line and the memory cell MC<1:n>. The cell strings arranged in the row direction may be coupled to the drain selection line extending in the row direction. The drain selection transistor of the cell string CS1<1:m> in the first row may be coupled to the first drain selection line DSL1. The drain selection transistor of the cell string CS2<1:m> in the second row may be coupled to the second drain selection line DSL2.

[0044] Cell strings arranged in a column direction may be coupled to bit lines extending in the column direction. In the drawing, cell strings CS11' and CS21' in a first column may be coupled to a first bit line BL1. Cell strings CS1m' and CS2m' in an mth column may be coupled to an mth bit line BLm.

[0045] Memory cells connected to word lines in cell strings arranged along the row direction may form one physical page. For example, memory cells connected to the first word line WL1 among cell strings CS1<1:m> of the first row may form one physical page. For another example, memory cells connected to the first word line WL1 among cell strings CS2<1:m> of the second row may form another physical page. Cell strings arranged along a row direction may be selected by selecting one of drain select lines DSL1 and DSL2. One physical page among the selected cell strings may be selected by selecting one of word lines WL<1:n>.

[0046] According to an embodiment of the present disclosure, at least one of the first to nth memory cells MC<1:n> may be used as a dummy memory cell. For example, at least one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cell MC<1:n>. In addition, at least one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cell MC<1:n>. When more dummy memory cells are provided, the size of the memory block may increase although the operational reliability of the memory block is improved. When fewer memory cells are provided, the operational reliability of the memory block may deteriorate although the size of the memory block is reduced.

[0047] In order to effectively control at least one or more dummy memory cells, each dummy memory cell may have a required threshold voltage. A programming operation may be performed on all or some dummy memory cells before or after an erase operation is performed on a storage block. When an erase operation is performed after a programming operation, each dummy memory cell may have a required threshold voltage by controlling the voltage applied to a dummy word line connected to the dummy memory cell.

[0048] The controller 202 may control a program operation for programming data in a selected area of ​​the memory cell array 201. The controller 202 may perform a program operation on a selected memory cell (referred to as a "selected cell") connected between a word line (referred to as a "selected word line") selected as a programming target among a plurality of word lines WL<1:n>, a plurality of bit lines BL<1:m>, and a selected string (referred to as a "selected string") selected among memory cell strings CS<1:2><1:m>. Herein, the selected cell may have one of a plurality of programming states through a program operation.

[0049] According to an embodiment of the present disclosure, a single-layer cell SLC storing one data bit may have two programming states distinguished based on one threshold voltage level. A multi-layer cell MLC storing two data bits may have four programming states distinguished based on three threshold voltage levels. A three-layer cell TLC storing three data bits may have eight programming states distinguished based on seven threshold voltage levels. A four-layer cell QLC storing four data bits may have 16 programming states distinguished based on 15 threshold voltage levels.

[0050] Reference Figure 2 as well as Figure 1 The programming operation may include a plurality of programming loops PL1 to PL7. The controller 202 may program the programming unit to have one programming state among a plurality of programming states by executing the plurality of programming loops PL1 to PL7 one by one in a predetermined order until the programming operation is completed (see Figure 1 Herein, if the program operation is not successful within a predetermined number of program loops, the controller 202 may determine that the program operation has failed.

[0051] According to an embodiment of the present disclosure, Figure 2 In the embodiment, at the time when the seventh program loop PL7 among the program loops PL1 to PL7 is completed, the program operation is successfully performed. Figure 2 In the embodiment, when the seventh program loop PL7 among the program loops PL1 to PL7 is completed, the program cells have the target program states.

[0052] In this case, each of the programming loops PL1 to PL7 may include a voltage application operation VIO for changing a threshold voltage level of a selected cell by applying each of the programming voltages PGM<1:7> to a selected word line, a word line holding operation HD for preventing an increase in a difference between levels of the word lines WL<1:n>, and a verification operation VER for verifying a programming state of a selected cell by applying each of the verification voltages VRY<1:7> corresponding to a target level to a selected word line.

[0053] Whenever each of the programming loops PL1 to PL7 is executed, the potential level of the programming pulse may be increased. When each of the programming loops PL1 to PL7 is executed, the programming operation may increase the level of the programming voltage according to an incremental step pulse programming (ISPP) method. In this case, the number of times the programming voltage used in each of the programming loops PL1 to PL7 is applied, the level of the programming voltage, and the length of time for applying the programming voltage may be determined in different forms.

[0054] In addition, the controller 202 may classify word lines that are not selected as programming targets among the word lines WL<1:n> (hereinafter referred to as “unselected word lines”) into first word lines having a programming state and second word lines having an erase state (see Figure 1 That is, the controller 202 may classify the unselected word lines into the first word line and the second word line based on the set programming sequence of the word lines WL<1:n>.

[0055] According to an embodiment, the controller 202 may perform a programming operation on the word lines WL<1:n> in a sequence starting from the 1st word line WL1 and ending at the nth word line WLn. In one example, it should be noted that programming may be performed on one word line at a time. Therefore, in such an example, the programming operation may be performed in the following manner: the memory cells connected to the 1st word line WL1 are completely programmed to have a desired programming state, and then the memory cells connected to the 2nd word line WL2 are completely programmed to have a desired programming state. In this sequence, if the 10th word line is selected as the selection word line, the controller 202 may classify the 1st to 9th word lines having a state in which programming of the 1st to 9th word lines has been completed as the first word line, and may classify the 11th to nth word lines having an erased state in which programming of the 11th to nth word lines has not yet been started as the second word line.

[0056] According to another embodiment, the controller 202 may perform a programming operation on the word lines WL<1:n> according to a sequence starting from the nth word line WLn and ending at the 1st word line WL1. In one example, it should be noted that programming may be performed on one word line at a time. Therefore, in such an example, the programming operation may be performed in the following manner: the memory cells connected to the nth word line WLn are fully programmed to have a desired programming state, and then the memory cells connected to the n-1th word line WLn-1 are fully programmed to have a desired programming state. In this sequence, if the 10th word line is selected as the selection word line, the controller 202 may classify the nth to 11th word lines having a state in which programming of the nth to 11th word lines has been completed as the first word line, and may classify the 9th to 1st word lines having an erased state in which programming of the 9th to 1st word lines has not yet started as the second word line.

[0057] Furthermore, in the word line hold operation HD included in each of the program loops PL1 to PL7, the controller 202 may apply a hold voltage HDV to a selected word line, may apply a hold pass voltage HDVP to a first word line, and may apply a hold pass voltage HDVP to a second word line (see Figure 1 In this case, the controller 202 may set the level of the hold voltage HDV to be equal to or higher than the level of the hold pass voltage HDVP.

[0058] Furthermore, in the verification operation VER included in each of the program loops PL1 to PL7, the controller 202 may apply a verification voltage VRY to a selection word line, may apply a verification pass voltage VRYP to K word lines belonging to the first word line and the second word line, and may apply a hold pass voltage HDVP to the remaining word lines except the K word lines belonging to the second word line (see Figure 1 In this case, K may be an integer equal to or greater than 0. In this case, the controller 202 may set the level of the hold pass voltage HDVP to a level lower than the level of the verify pass voltage VRYP.

[0059] According to an embodiment, when K is 0, in the verification operation VER included in each of the programming loops PL1 to PL7, the controller 202 may apply a verification voltage VRY to the selection word line, may apply a verification pass voltage VRYP to the first word line, and may apply a hold pass voltage HDVP to the second word line. That is, this may mean that when K is set to 0, in the verification operation VER included in each of the programming loops PL1 to PL7, the hold pass voltage HDVP is applied to all the second word lines.

[0060] According to another embodiment, when K is 1, in the verification operation VER included in each of the programming loops PL1 to PL7, the controller 202 may apply a verification voltage VRY to a selection word line, may apply a verification pass voltage VRYP to a word line belonging to the first word line and the second word line, and may apply a hold pass voltage HDVP to the remaining word lines belonging to the second word line except the word line.

[0061] In addition, the controller 202 may classify a set number of word lines belonging to the second word line and physically adjacent to the selection word line into K word lines. In this case, the term "physically adjacent" to the selection word line may indicate a state in which no physical word line exists between the word line and the selection word line. For example, if K is 1 and the 10th word line is selected as the selection word line, the word line physically adjacent to the 10th word line may be represented as the 9th or 11th word line. As another example, if K is 2 and the 10th word line is selected as the selection word line, the word line physically adjacent to the 10th word line may be represented as the 8th and 9th word lines or the 11th and 12th word lines.

[0062] For reference, the relationship between the voltage levels used in the word line hold operation HD and the verification operation VER included in each of the program loops PL1 to PL7 can be arranged as follows. First, the level of the hold voltage HDV can be higher than or equal to the level of the hold pass voltage HDVP. In addition, the level of the verification pass voltage VRYP can be higher than the level of the hold pass voltage HDVP.

[0063] Figure 3 It is used to describe the embodiments according to the present disclosure. Figure 1 Schematic diagram of a controller among components of a memory device disclosed in .

[0064] Reference Figure 3 , the memory device 150 may include a memory cell array 201 and a controller 202. The controller 202 may include a control circuit (or peripheral circuit) 309 and a control logic 304. The control circuit 309 may include a page buffer circuit 302, a checker 303, a data input / output circuit 305, a voltage generator 306, and an address decoder 307.

[0065] The memory cell array 201 may include a plurality of memory blocks MEMORY BLOCK<1:6>. The memory blocks MEMORY BLOCK<1:6> may be connected to the control circuit 309 through row lines DSL<1:2>, WL<1:n>, SSL<1:2>, and bit lines BL1 to BLm. Each of the memory blocks MEMORY BLOCK<1:6> may include a plurality of memory cells. Each of the memory blocks MEMORY BLOCK<1:6> may be formed to have a three-dimensional structure. That is, each of the memory blocks MEMORY BLOCK<1:6> may include a plurality of memory cells arranged to have a reference Figure 1 A plurality of memory cells in a three-dimensional structure along +X direction, +Y direction and +Z direction are described.

[0066] The row lines DSL<1:2>, WL<1:n>, SSL<1:2> may include at least one source select line (SSL1, SSL2), a plurality of word lines (WL<1:n>), and at least one drain select line (DSL1, DSL2).

[0067] The control logic 304 may be connected to the address decoder 307 , the voltage generator 306 , the page buffer circuit 302 , the data input / output circuit 305 , and the checker 303 included in the control circuit 309 .

[0068] The control logic unit 304 may control the control circuit 309 by generating a plurality of signals in response to the command CMD and the address ADDR. For example, the control logic 304 may generate a generation control signal OP_SIG, a transfer control signal VTR, a read and write control signal PBSIGNALS, a detection reference signal VRYBIT, and an input / output control signal I / O_CON in response to the command CMD and the address ADDR. The control logic 304 may output the operation signal OP_SIG to the voltage generator 306, may output the transfer control signal VTR to the address decoder 307, may output the read and write control signal PBSIGNALS to the page buffer circuit 302, may output the detection reference signal VRYBIT to the checker 303, and may output the input / output control signal I / O_CON to the data input / output circuit 305. In addition, the control logic 304 may determine whether a verification operation or a read operation included in a program operation is passed or failed in response to a pass signal PASS or a fail signal FAIL outputted by the checker 303.

[0069] The control circuit 309 may be configured to perform a programming operation, a reading operation, or an erasing operation on a selected area of ​​the memory cell array 201. The control circuit 309 may drive the memory cell array 201. For example, the control circuit 309 may apply various operating voltages to the row lines DSL<1:2>, WL<1:n>, SSL<1:2>, and the bit lines BL1 to BLm, or discharge the applied voltages. The control circuit 309 may perform a programming operation on the programming unit in response to the control of the control logic 304. Specifically, the control circuit 309 may adjust the voltage levels applied to the row lines DSL<1:2>, WL<1:n>, and SSL<1:2>, and the bit lines BL1 to BLm in response to the transfer control signal VTR generated by the control logic 304.

[0070] The voltage generator 306 in the control circuit 309 may be configured to generate a plurality of operation voltages Vop by using an external power supply voltage. The voltage generator 306 may operate in response to the control of the control logic 304 .

[0071] In an embodiment, the voltage generator 306 may regulate an external supply voltage and generate an internal supply voltage.

[0072] In an embodiment, the voltage generator 306 may generate a plurality of operating voltages Vop by utilizing an external power supply voltage or an internal power supply voltage.

[0073] The voltage generator 306 may include a plurality of pumping capacitors receiving an internal power supply voltage to generate a plurality of operating voltages Vop having various voltage levels, and generate the plurality of operating voltages Vop by selectively activating the plurality of pumping capacitors in response to the control of the control logic 304 .

[0074] The generated operating voltage Vop may be provided to the memory cell array 201 by the address decoder 307. For example, the voltage generator 306 may adjust a level and a supply time of each operating voltage Vop in response to the operation signal OP_SIG.

[0075] According to an embodiment, the voltage generator 306 may generate the program voltages PGM<1:7> (see Figure 2), a programming pass voltage VPGM, a verification voltage VRY, a verification pass voltage VRYP, a hold voltage HDV, a hold pass voltage HDVP, a read voltage, and an erase voltage as an operation voltage VOP, and the generated operation voltage VOP may be provided to the address decoder 307. For example, after the programming operation starts, the voltage generator 306 may generate a programming voltage PGM<1:7>, a programming pass voltage VPGM, a verification voltage VRY, a verification pass voltage VRYP, a hold voltage HDV, and a hold pass voltage HDVP as an operation voltage VOP in response to the generation control signal OP_SIG, and the generated operation voltage VOP may be provided to the address decoder 307. In this case, the programming voltage PGM<1:7> may be a voltage supplied to a selected word line in a voltage application operation VIO. In addition, the programming pass voltage VPGM may be a voltage supplied to an unselected word line in a voltage application operation VIO. In addition, the verification voltage VRY may be a voltage supplied to a selected word line in a verification operation VER. In addition, the verification pass voltage VRYP may be a voltage supplied to K word lines belonging to the first word line and the second word line in the verification operation VER. In addition, the hold pass voltage HDVP may be a voltage supplied to unselected word lines in the word line hold operation HD and applied to the remaining word lines except for K word lines belonging to the second word line in the verification operation VER. In addition, the hold voltage HDV may be a voltage supplied to the selected word line in the word line hold operation HD. The voltage generator 306 may adjust the time of supplying the operation voltage VOP in response to the generation of the control signal OP_SIG. For example, the voltage generator 306 may adjust the time of outputting each of the programming voltage PGM<1:7>, the programming pass voltage VPGM, the verification voltage VRY, the verification pass voltage VRYP, the hold voltage HDV, and the hold pass voltage HDVP in response to the generation of the control signal OP_SIG, and may output each voltage based on the adjusted time.

[0076] The address decoder 307 of the control circuit 309 may be connected to the memory cell array 201 through one or more source selection lines SSL<1:2>, word lines WL<1:n>, and one or more drain selection lines DSL<1:2>. In addition, the address decoder 307 may be configured to operate in response to a transfer control signal VTR generated by the control logic 304. In addition, the address decoder 307 may select at least one memory block among the memory blocks MEMORY BLOCK<1:6> in response to the transfer control signal VTR received from the control logic 304, may classify at least one word line among the word lines included in the selected memory block into a selected word line and an unselected word line, and may classify the unselected word line into a first word line and a second word line. In addition, the address decoder 307 may transfer one of a hold voltage HDV and a verification voltage VRY to the selected word line in response to the transfer control signal VTR. In addition, the address decoder 307 may transfer one of a hold pass voltage HDVP and a verification pass voltage VRYP to K word lines belonging to the first word line and the second word line in response to the transfer control signal VTR. In addition, the address decoder 307 may transmit the hold pass voltage HDVP to the remaining word lines except for the K word lines belonging to the second word line in response to the transfer control signal VTR. In addition, the address decoder 307 may transmit a voltage (e.g., source selection voltage VSSL or ground voltage VSS) for turning on or off the source selection transistor SST to the source selection line SSL<1:2> in response to the transfer control signal VTR. In addition, the address decoder 307 may transmit a voltage (e.g., drain selection voltage VDSL or ground voltage VSS) for turning on or off the drain selection transistor DST to the drain selection line DSL<1:2> in response to the transfer control signal VTR.

[0077] The page buffer circuit 302 may include a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm may be connected to the memory cell array 201 through a plurality of bit lines BL1 to BLm, respectively. The plurality of page buffers PB1 to PBm may operate in response to the control of the control logic 304 .

[0078] The plurality of page buffers PB1 to PBm may communicate data DATA with the data input / output circuit 157. During a program operation, the plurality of page buffers PB1 to PBm may receive data DATA to be stored through the data input / output circuit 157 and the data lines DL.

[0079] After the program operation starts, the plurality of page buffers PB1 to PBm may store data DATA received from the outside through the data input / output circuit 305, and may transmit a program enable voltage or a program disable voltage to the bit lines BL1 to BLm in response to the stored data DATA. For example, the program enable voltage may be the ground voltage VSS, and the program disable voltage may be the power supply voltage VCORE.

[0080] After the read operation starts, the page buffers PB1 to PBm can sense data DATA based on the voltage or current of the bit lines BL1 to BLm, which is determined based on the threshold voltage of the memory cells of the selected page, and can transmit the sensed data DATA to the data input / output circuit 305 through the data line DL.

[0081] After the erase operation starts, the page buffers PB1 to PBm may float the bit lines BL1 to BLm or may apply a voltage of a ground voltage VSS to the bit lines BL1 to BLm.

[0082] The data input / output circuit 305 may include a plurality of input / output buffers (not shown) receiving data DATA input to the data input / output circuit 305. During a program operation, the data input / output circuit 305 may receive data DATA to be stored from the outside. The data input / output circuit 305 may output data DATA transmitted from the plurality of page buffers PB1 to PBm included in the page buffer circuit 302 to the outside during a read operation.

[0083] The checker 303 of the control circuit 309 may generate a reference current in response to a verification reference signal VRYBIT generated by the control logic 304 after a read operation or a verification operation starts, may compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current, and may output a pass signal PASS or a fail signal FAIL to the control logic 304. For example, when the level of the sensing voltage VPB is higher than or equal to the level of the reference voltage, the checker 303 may output a pass signal PASS to the control logic 304. When the level of the sensing voltage VPB is lower than the level of the reference voltage, the checker 303 may output a fail signal FAIL to the control logic 304.

[0084] FIG. 4A to FIG. 4C It is used to describe the embodiments according to the present disclosure. Figure 1 and Figure 2 Schematic diagram of a program loop included in a program operation of a memory device disclosed in FIG.

[0085] Reference Figure 1 , Figure 2 as well as FIG. 4A to FIG. 4C, each of the program loops PL1 to PL7 included in the program operation of the semiconductor memory device according to the embodiment of the present disclosure may include a voltage applying operation VIO, a word line holding operation HD, and a verification operation VER.

[0086] During the voltage application operation VIO, the controller 202 can apply the programming voltage PGM<1:7> to the selection word line SEL_WL, can apply the programming pass voltage VPGM to the unselected word lines UNSEL_WL1 and UNSEL_WL2, can apply the drain selection voltage VDSL to the drain selection line DSL connected to the gate of the drain selection transistor DST, and can apply the ground voltage VSS to the source selection line SSL connected to the gate of the source selection transistor SST.

[0087] Furthermore, in the voltage applying operation VIO, the controller 202 may apply one of the power supply voltage VCORE and the ground voltage VSS to each of the bit lines BL<1:m>. For example, the controller 202 may apply the ground voltage VSS to the bit lines connected to the memory cells whose threshold voltage levels have not reached their target levels among the bit lines BL<1:m>. As another example, the controller 202 may apply the power supply voltage VCORE to the bit lines connected to the memory cells whose threshold voltage levels have reached their target levels among the bit lines BL<1:m>.

[0088] In addition, during the word line hold operation HD, the controller 202 may apply a hold voltage HDV to the selected word line SEL_WL, and may apply a hold pass voltage HDVP to the unselected word lines UNSEL_WL1 and UNSEL_WL2. In addition, during the word line hold operation HD, the controller 202 may apply a ground voltage VSS to the source select line SSL and the drain select line DSL.

[0089] In this case, the controller 202 may set the level of the hold voltage HDV to a level equal to or higher than the level of the hold pass voltage HDVP.

[0090] Furthermore, during the verification operation VER, the controller 202 may apply a verification voltage VRY to the selection word line SEL_WL.

[0091] In addition, during the verification operation VER, the controller 202 may apply the verification pass voltage VRYP to K word lines ADJ_WL2 belonging to the first word line UNSEL_WL1 and the second word line UNSEL_WL2 among the unselected word lines UNSEL_WL1 and UNSEL_WL2. That is, the controller 202 may apply the hold pass voltage HDVP to the first word line UNSEL_WL1 and the K word lines ADJ_WL2 during the word line hold operation HD, and may apply the verification pass voltage VRYP having a level higher than that of the hold pass voltage HDVP to the first word line UNSEL_WL1 and the K word lines ADJ_WL2 in the verification operation VER after the word line hold operation HD.

[0092] In addition, during the verification operation VER, the controller 202 may apply the retention pass voltage HDVP to the remaining word lines REST_WL2 except for the K word lines ADJ_WL2 belonging to the second word line UNSEL_WL2 among the unselected word lines UNSEL_WL1 and UNSEL_WL2. That is, the controller 202 may apply the retention pass voltage HDVP to the remaining word lines REST_WL2 during the word line retention operation HD, and may apply the retention pass voltage HDVP to the remaining word lines REST_WL2 even in the verification operation VER after the word line retention operation HD.

[0093] As described above, the controller 202 may change the levels of some of the word lines UNSEL_WL1 and ADJ_WL2 among the unselected word lines UNSEL_WL1 and UNSEL_WL2, that is, may change the level of the hold pass voltage HDVP to the level of the verification pass voltage VRYP between the word line hold operation HD and the verification operation VER. Conversely, the controller 202 may hold the levels of the remaining word lines REST_WL2 except for the word lines UNSEL_WL1 and ADJ_WL2 among the unselected word lines UNSEL_WL1 and UNSEL_WL2, that is, may hold the level of the hold pass voltage HDVP between the word line hold operation HD and the verification operation VER.

[0094] In addition, during the verification operation VER, the controller 202 may apply a source selection voltage VSSL to the source selection line SSL, may apply a drain selection voltage VDSL to the drain selection line DSL, and may turn on the source selection transistor SST and the drain selection transistor DST. Therefore, the programming state of the selection cell connected to the selection word line SEL_WL may be determined by the page buffer circuit 302 (refer to Figure 3During the verification operation VER, the controller 202 may detect whether the threshold voltage level of each selection cell is higher than the level of the verification voltage VRY, and may determine whether programming for each selection cell has been completed based on the result of the detection.

[0095] K is an integer equal to or greater than 0. According to an embodiment, when K is 0, all word lines belonging to the second word line UNSEL_WL2 may be classified as the remaining word line REST_WL2. That is, Figure 4B As shown, all the 1st to i-1th word lines WL<1:i-1>, that is, the selection word line SEL_WL, belonging to the second word line UNSEL_WL2 and disposed below the i-th word line WLi can be classified as the rest word line REST_WL2. Figure 4B In the word line hold operation HD and the verification operation VER, the hold pass voltage HDVP may continue to be applied to all word lines belonging to the second word line UNSEL_WL2.

[0096] According to another embodiment, when K is 1, the second word line UNSEL_WL2 may be classified into the remaining word lines REST_WL2 except for one word line ADJ_WL2 physically adjacent to the selection word line SEL_WL. Figure 4C As shown, among the 1st to i-1th word lines WL<1:i-1>, i.e., the selection word line SEL_WL, which belong to the second word line UNSEL_WL2 and are disposed below the i-th word line WLi, only the i-1th word line WLi-1 may be classified as the K word lines ADJ_WL2 physically adjacent to the selection word line SEL_WL, and the 1st to i-2th word lines WL<1:i-2> may be classified as the remaining word lines REST_WL2. Therefore, in the word line hold operation HD and the verification operation VER, the hold pass voltage HDVP may continue to be applied to the 1st to i-2th word lines WL<1:i-2>, which belong to the second word line UNSEL_WL2 and are classified as the remaining word lines REST_WL2. In the word line hold operation HD, a hold pass voltage HDVP may be applied to the i-1th word line WLi-1 classified as the K word lines ADJ_WL2 , and in the verify operation VER, a verify pass voltage VRYP may be applied to the i-1th word line WLi-1 .

[0097] For reference, it can be seen Figure 4B and 4C Only shown Figure 1 The selected string CS11' and the selected string CS21' among the cell strings CS11' and CS21' shown in FIG. Figure 1 The first bit line BL1 among the bit lines BL<1:m> shown in FIG.

[0098] Figure 5It is used to describe the embodiments according to the present disclosure. Figure 1 and Figure 2 1 is a diagram of the order of programming operations of the memory device 150 disclosed in FIG.

[0099] Reference Figure 5 , a program command and an address may be input to the memory device 150 (in operation S10 ).

[0100] In operation S10, in response to input of a program command and an address, word lines may be classified into selected word lines and unselected word lines. In addition, unselected word lines may be classified into first word lines having a program state and second word lines having an erase state (in operation S20).

[0101] In operation S30 , a voltage applying operation VIO in a first program loop PL1 among program loops PL1 to PL7 included in the program operation may be performed.

[0102] In operation S40 , a word line holding operation HD included in the first program loop PL1 may be performed.

[0103] In operation S50 , a verification operation VER included in the first program loop PL1 may be performed.

[0104] Already referred to Figures 1 to 4A to Figure 4C A detailed operation of each of operations S20 to S50 is described and may not be further described.

[0105] In operation S60, it may be checked whether the programming operation is successful. When the programming operation is successful (i.e., in the case of "yes" in operation S60), the programming operation may be determined to be successful and may be terminated. When the programming operation is unsuccessful (i.e., in the case of "no" in operation S60), the current programming loop count may be increased (in operation S70). In this case, when the programming operation of the first programming loop PL1 is unsuccessful, in operation S70, the value of the current programming loop count may be increased from the first programming loop PL1 to the second programming loop PL2.

[0106] In operation S80, it may be checked whether the value of the current program loop count is a maximum program loop count value.

[0107] When the value of the current program loop count is the maximum program loop count value (ie, in case of “yes” in operation S80 ), it may be determined that the program operation has failed and may then be terminated.

[0108] When the value of the current program loop count is not the maximum program loop count value (ie, in case of 'NO' in operation S80), operations S30 to S80 may be sequentially performed again on the current program loop (eg, on the second program loop PL2).

[0109] It is obvious to those skilled in the art that the present disclosure is not limited to the above embodiments and the accompanying drawings, and the present disclosure may be replaced, modified and changed in various ways without departing from the technical spirit of the present disclosure. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A memory device, comprising: A memory cell array including a plurality of cell strings connected between a plurality of bit lines and a common source line and a plurality of word lines connected to the plurality of cell strings; as well as Controller: performing program loops until a program operation for a selected memory cell corresponding to a selected word line and a selected cell string succeeds, each of the program loops including a voltage application operation, a word line holding operation, and a verification operation; During the word line holding operation, applying a holding pass voltage having a level higher than a ground voltage to each of a first word line having a programmed state and a second word line having an erased state, the first word line and the second word line belonging to unselected word lines among the plurality of word lines; During the verification operation, applying a verification pass voltage having a level higher than the hold pass voltage to K word lines belonging to the first word line and the second word line, and applying the hold pass voltage to remaining word lines except the K word lines among the second word lines, Wherein K is an integer equal to or greater than 0.

2. The memory device of claim 1, wherein the controller: During the word line hold operation, applying a hold voltage having a level equal to or higher than a hold through voltage to the selection word line; and During the verification operation, a verification voltage is applied to the selection word line. 3 . The memory device of claim 1 , wherein the controller classifies the unselected word lines into the first word lines and the second word lines based on a set word line programming order. 4 . The memory device of claim 1 , wherein the controller classifies a set number of word lines that belong to the second word line and are physically adjacent to the selection word line as the K word lines.

5. The memory device of claim 2, wherein the controller comprises: a voltage generator that generates the hold pass voltage, the hold voltage, the verify voltage, and the verify pass voltage in response to a generate control signal; Address decoder: classifying the plurality of word lines into the selection word line and the first word line and the second word line, transmitting one of the hold voltage and the verification voltage to the selection word line in response to a transmission control signal, transmitting one of the hold pass voltage and the verify pass voltage to the first word line and the K word lines, and transmitting the hold pass voltage to the remaining word lines; as well as The control logic generates the generation control signal and the transfer control signal in response to an externally applied address and command.

6. The memory device according to claim 5, wherein: During the word line hold operation, the control logic sets the values ​​of the generation control signal and the transfer control signal so that the voltage generator generates the hold pass voltage and the hold voltage, and the address decoder transfers the hold voltage to the selection word line and transfers the hold pass voltage to each of the first word line and the second word line.

7. The memory device according to claim 5, wherein: During the verification operation, the control logic sets the values ​​of the generation control signal and the transfer control signal so that the voltage generator generates the hold pass voltage, the verification voltage, and the verification pass voltage, and the address decoder transfers the verification voltage to the selection word line, transfers the verification pass voltage to the first word line and the K word lines, and transfers the hold pass voltage to the remaining word lines.

8. A method for operating a memory device, the memory device comprising a plurality of cell strings connected between a plurality of bit lines and a common source line and a plurality of word lines connected to the plurality of cell strings, the method comprising: performing program loops until a program operation for a selected memory cell corresponding to a selected word line and a selected cell string succeeds, each of the program loops including a voltage application operation, a word line holding operation, and a verification operation; classifying the plurality of word lines into the selected word lines and unselected word lines, and classifying the unselected word lines into a first word line having a programmed state and a second word line having an erased state; during the word line hold operation, applying a hold pass voltage to each of the first word line and the second word line, and applying a hold voltage having a level higher than or equal to the hold pass voltage to the selection word line; as well as During the verification operation, a verification voltage is applied to the selection word line, a verification pass voltage having a level higher than the hold pass voltage is applied to K word lines belonging to the first word line and the second word line, and the hold pass voltage is applied to the remaining word lines among the second word lines except for the K word lines, Wherein K is an integer equal to or greater than 0.

9. The operating method according to claim 8, wherein: Classifying the unselected word lines includes classifying the unselected word lines into the first word lines and the second word lines based on a set word line programming order. 10 . The operating method according to claim 8 , further comprising classifying a set number of word lines that belong to the second word line and are physically adjacent to the selection word line into the K word lines.

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