Control circuit for speed regulation of SRAM (Static Random Access Memory)

Abstract

The invention provides a control circuit for speed regulation of an SRAM (Static Random Access Memory), which comprises a dual-port eight-transistor SRAM, and the dual-port eight-transistor SRAM comprises a six-transistor SRAM structure and a two-transistor reading port, the 6-transistor SRAM structure is controlled by signals A-WL, BL1 and BL2; the 6-transistor SRAM structure is connected with a storage unit working power supply Vdd; the back side bias voltage control module is used for controlling the back side voltage of the reading port of the transistor 2 and comprises a first potential offset module and a second potential offset module; a signal A control module, a signal B control module and a signal C control module; and the first control switch, the second control switch and the third control switch are respectively used for controlling the back side positive voltage, the back side negative voltage and the open state of 0V of the reading port of the transistor 2. When the B-WL is closed, the reading port is in a static mode, and the back side voltage is adjusted to be negative voltage, so that cut-off electric leakage is reduced to reduce power consumption; when the B-WL is started, the read port is in an operation mode, and the back side voltage is adjusted to be positive voltage, so that the conduction current rises to increase the operation speed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a control circuit for SRAM speed regulation. Background Art

[0002] In the past 20 to 30 years, with the rapid development of microelectronics technology, components have been miniaturized rapidly, chip density has increased, and computing performance has increased. Semiconductor memory is also developing in a significant direction. Among volatile memories, SRAM has the characteristics of low power consumption and high performance, and DRAM has the characteristics of low cost and large storage capacity.

[0003] Currently, various memories are embedded in SOC (system on a chip) to improve system performance, especially SRAM circuit (static random access memory circuit). Since this circuit is compatible with the current CMOS process and is usually used in the L1 / L2 cache (first / second level high-speed cache) in computing chips, it naturally becomes the first choice for embedded memory. Therefore, SRAM has a considerable proportion in the functions and applications of digital chips.

[0004] Mature process technology, planar transistors, use ion implantation to achieve the change of component threshold voltage Vt and on-state current Id.

[0005] Transistors with advanced technology use metal gate work functions to achieve changes in the threshold voltage Vt and on-state current Id of the device.

[0006] 8T2P SRAM (dual-port eight-transistor SRAM), the circuit diagram is as follows Figure 1 As shown, the function is Figure 2 As shown, a 2-port SRAM is composed of 8 transistors (Tr.).

[0007] Internal 6 transistors: The function is to write / read, the operation speed is normal, and the balance between reading and writing must be maintained. n1 and n2 are used to store signals. When AWL = 1, PG1 and PG2 are turned on, and BL1 and BL2 are used to write or read. BL1 and BL2 are 1 port.

[0008] External 2 transistors: for reading ports, the speed is relatively faster, so the corresponding leakage is slightly higher. When BWL = 1, RP PG is turned on, and RP BL is used for reading.

[0009] If the device Vt (threshold voltage) and Id (on-state current) are to be adjusted, changes must be made to the process flow. In mature process flow, planar transistors use ion implantation to achieve changes in the component's threshold voltage Vt and on-state current Id.

[0010] Transistors using advanced technology processes use metal gate work functions to achieve changes in the threshold voltage Vt and on-state current Id of the device.

[0011] Regardless of whether it is a planar transistor or a solid-state transistor, in digital circuits, the NFET bulk is connected to 0V and the PFET bulk is connected to Vdd.

[0012] After the chip goes through the manufacturing process, the performance of each component in the chip is fixed. Therefore, in SRAM operation, the speed of the static mode and the leakage of the operating mode are fixed. If the device Vt and Id need to be adjusted, changes must be made in the process flow.

[0013] In order to solve the above problems, it is necessary to propose a new control circuit for SRAM speed regulation. Summary of the invention

[0014] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a control circuit for SRAM speed regulation, which is used to solve the problem in the prior art that the speed of the static mode and the leakage of the operating mode are fixed in the SRAM operation. If the device Vt, Id is to be adjusted, the process flow must be changed.

[0015] To achieve the above-mentioned object and other related objects, the present invention provides a control circuit for SRAM speed regulation, comprising:

[0016] Dual-port, eight-transistor SRAM, including:

[0017] 6-transistor SRAM structure and 2-transistor read port;

[0018] The 6-transistor SRAM structure is controlled by signals A-WL, BL1, and BL2; the 6-transistor SRAM structure is connected to the storage unit working power supply Vdd;

[0019] The 2-transistor read port is controlled by signals RPBL and B-WL;

[0020] A backside bias voltage control module, which is used to control the backside voltage of the 2-transistor read port, includes:

[0021] First and second potential shift modules;

[0022] Signal A control module, signal B control module, signal C control module;

[0023] The first to third control switches are used to control the positive voltage, negative voltage and 0V of the back side voltage of the 2-transistor read port to be turned on respectively; wherein,

[0024] The first potential shift module is used to convert the enable signal EN of 1 or 0 into a signal M_EN of 1 or -1;

[0025] The second potential shift module is used to convert the word line signal B-WL of 1 or 0 into a signal M_WL of 1 or -1;

[0026] The signal A control module is used to control the opening state of the first switch according to the signal M_EN and the signal M_WL;

[0027] The signal B control module is used to control the opening state of the second switch according to the signal M_EN and the signal M_WL;

[0028] The signal C control module is used to control the opening state of the third switch according to the signal M_EN;

[0029] When the enable signal EN is 0, the backside voltage is adjusted to 0V;

[0030] When B-WL is turned off, the read port is in static mode, and the backside voltage is adjusted to a negative voltage, so that the cut-off leakage decreases to reduce power consumption;

[0031] When the B-WL is enabled, the read port is in operation mode and the backside voltage is adjusted to a positive voltage so that the on-current increases to increase the operation speed.

[0032] Preferably, the dual-port eight-transistor SRAM comprises:

[0033] Transistors PG1, PG2, PU1, PU2 and transistors PD1, PD2, RP PD, RP PG; wherein,

[0034] PD1, PD2, RP PD are pull-down tubes, PU1, PU2 are rise tubes, PG1 and PG2 are transmission tubes, RP PG are selection tubes; RP PD, RP PG are read ports;

[0035] The source electrodes of PU1 and PU2 are connected to the working power supply Vdd of the storage unit, and the drain electrodes of PU1 and PU2 are connected to the drain electrodes of PD1 and PD2 respectively;

[0036] The gate of PU1 is connected to the gate of PD1 to form a first storage node n2, and the gate of PU2 is connected to the gate of PD2 to form a second storage node n1;

[0037] The source of PD1 and PD2 is connected to the ground line;

[0038] The source of PG1 is connected to the signal BL1, the drain is connected to the first storage node n1, and the gate is connected to the signal A-WL;

[0039] The source of PG2 is connected to the signal BL2, the drain is connected to the second storage node n2, and the gate is connected to the signal A-WL;

[0040] The source of RP PD is connected to the ground line, the gate is connected to the first storage node n2, and the drain is connected to the source of RP PG;

[0041] The drain of RP PG is connected to the signal RP BL, and the gate is connected to the signal B-WL; wherein PG1, PG2, PU1, PU2, PD1, and PD2 form a 6-transistor SRAM structure, which is controlled by signals A-WL, BL1, and BL2.

[0042] Preferably, the transistors PG1 and PG2 are NMOS, and the transistors PU1 and PU2 and the transistors PD1, PD2, RPPD and RPPG are PMOS.

[0043] Preferably, the positive voltage is 0V to the working power supply of the storage unit.

[0044] Preferably, the negative voltage is 0V to a negative storage unit working power supply.

[0045] Preferably, the negative voltage is obtained by a working power supply Vdd through a charge pump.

[0046] Preferably, the storage unit has an operating power supply of 1V.

[0047] Preferably, the signal A control module is a NAND gate.

[0048] Preferably, the signal B control module is a NAND gate and an inverter, the signal M_EN is input to the input end of the NAND gate, and the signal M_WL is input to the input end of the NAND gate through the inverter.

[0049] Preferably, the signal C control module is an inverter.

[0050] As described above, the control circuit for SRAM speed regulation of the present invention has the following beneficial effects:

[0051] In the present invention, when the B-WL is turned off, the read port is in a static mode, and the back side voltage is adjusted to a negative voltage, so that the cut-off leakage decreases to reduce power consumption; when the B-WL is started, the read port is in an operating mode, and the back side voltage is adjusted to a positive voltage, so that the on-current increases to increase the operating speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 Shown is a schematic diagram of a dual-port eight-transistor SRAM structure of the prior art;

[0053] Figure 2 Shown is a schematic diagram of the port function of the prior art;

[0054] Figure 3 Schematic diagram showing the relationship between the back side voltage of the device of the present invention and the on-current and off-current

[0055] Figure 4 Shown is a schematic diagram of the control circuit of the present invention;

[0056] Figure 5 Shown is a schematic diagram of the effect of the backside voltage on the device performance of the present invention;

[0057] Figure 6 It is a schematic diagram showing the input signal conversion process of the backside bias voltage control module and the signal control module process of the present invention;

[0058] Figure 7 Shown is a timing diagram of the backside bias voltage control module of the present invention;

[0059] Figure 8 Shown is a truth representation of the backside bias voltage control module of the present invention;

[0060] Fig. 9 Shown is a schematic diagram of the charge pump circuit structure of the present invention;

[0061] Fig.10 Shown is a schematic diagram of the circuit structure of the potential shift module of the present invention;

[0062] Fig.11 Shown is a schematic diagram of the circuit structure of the signal C control module and the third switch of the present invention;

[0063] Fig.12 Shown is a circuit structure diagram of the signal A control module and the third switch of the present invention;

[0064] Fig.13 Shown is a schematic diagram of the circuit structure of the signal B control module and the third switch of the present invention;

[0065] Fig.14 Shown is a schematic diagram of the circuit structure of the backside bias voltage control module of the present invention. DETAILED DESCRIPTION

[0066] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0067] See also Figure 4 The present invention provides a control circuit for SRAM speed regulation, comprising:

[0068] Dual-port, eight-transistor SRAM, including:

[0069] 6-transistor SRAM structure and 2-transistor read port;

[0070] The 6-transistor SRAM structure is controlled by signals A-WL, BL1, and BL2; the 6-transistor SRAM structure is connected to the storage unit working power supply Vdd;

[0071] The 2-transistor read port is controlled by signals RP BL, B-WL; see Figure 3 The inventors found that due to the circuit characteristics of RP PG and RP PD of the dual-port eight-transistor SRAM, when the Vt (threshold voltage) and Id (on-current) of RP PG and RP PD are high or low, it will not affect the read / write balance (Read / Write Balance) during the internal 6T Bit cell signal operation. Therefore, adjusting the current of the read port, that is, adjusting the read port read speed, will not affect the state of the 6-transistor SRAM.

[0072] MOSFET body factor (bulk bias phenomenon), when the bulk voltage is different from the source terminal voltage, the resulting electrical behavior will change.

[0073] By adjusting the different backside voltages of the MOSFET, the dual-port eight-transistor SRAM can obtain different on-currents and off-leakages (device Ion & Ioff). The on-current increases or decreases linearly, while the off-leakage increases or decreases exponentially, as shown in the figure.

[0074] In some embodiments, a dual-port eight-transistor SRAM includes:

[0075] Transistors PG1, PG2, PU1, PU2 and transistors PD1, PD2, RP PD, RP PG; wherein,

[0076] PD1, PD2, RP PD are pull-down tubes, PU1, PU2 are rise tubes, PG1 and PG2 are transmission tubes, RP PG are selection tubes; RP PD, RP PG are read ports;

[0077] The source electrodes of PU1 and PU2 are connected to the working power supply Vdd of the storage unit, and the drain electrodes of PU1 and PU2 are connected to the drain electrodes of PD1 and PD2 respectively;

[0078] The gate of PU1 is connected to the gate of PD1 to form a first storage node n2, and the gate of PU2 is connected to the gate of PD2 to form a second storage node n1;

[0079] The source of PD1 and PD2 is connected to the ground line;

[0080] The source of PG1 is connected to the signal BL1, the drain is connected to the first storage node n1, and the gate is connected to the signal A-WL;

[0081] The source of PG2 is connected to the signal BL2, the drain is connected to the second storage node n2, and the gate is connected to the signal A-WL;

[0082] The source of RP PD is connected to the ground line, the gate is connected to the first storage node n2, and the drain is connected to the source of RP PG;

[0083] The drain of RP PG is connected to the signal RP BL, and the gate is connected to the signal B-WL; wherein PG1, PG2, PU1, PU2, PD1, and PD2 form a 6-transistor SRAM structure, which is controlled by signals A-WL, BL1, and BL2.

[0084] In some embodiments, transistors PG1 and PG2 are NMOS, and transistors PU1 and PU2 and transistors PD1 , PD2 , RPPD, and RP PG are PMOS.

[0085] See also Figure 6 , a backside bias voltage control module, which is used to control the backside voltage of the 2-transistor read port, including:

[0086] The first and second potential shift modules, the circuit of the potential shift module can be composed of Fig.10 As shown;

[0087] Signal A control module, signal B control module, signal C control module;

[0088] The first to third control switches are used to control the positive voltage, negative voltage and 0V of the back side voltage of the 2-transistor read port to be turned on respectively; wherein,

[0089] The first potential shift module is used to convert the enable signal EN of 1 or 0 into a signal M_EN of 1 or -1;

[0090] The second potential shift module is used to convert the word line signal B-WL of 1 or 0 into a signal M_WL of 1 or -1;

[0091] The signal A control module is used to control the opening state of the first switch according to the signal M_EN and the signal M_WL;

[0092] The signal B control module is used to control the opening state of the second switch according to the signal M_EN and the signal M_WL;

[0093] The signal C control module is used to control the opening state of the third switch according to the signal M_EN;

[0094] Figure 7 shows the timing diagram of the backside bias voltage control module, Figure 8 The truth table of the backside bias voltage control block is shown.

[0095] See also Figure 5 , when the enable signal EN is 0, the backside voltage is adjusted to 0V;

[0096] When B-WL is turned off, the read port is in static mode, and the backside voltage is adjusted to a negative voltage, so that the cut-off leakage decreases to reduce power consumption;

[0097] When the B-WL is enabled, the read port is in operation mode and the backside voltage is adjusted to a positive voltage so that the on-current increases to increase the operation speed.

[0098] In some embodiments, the positive voltage is 0V to the working power supply of the memory cell. For example, if the working power supply of the memory cell is 1V, the positive voltage is 0 to 1V.

[0099] In some embodiments, the negative voltage is 0V to -1V. For example, if the working power of the memory cell is 1V, the positive voltage is 0 to -1V.

[0100] In some embodiments, the negative voltage is obtained by the working power supply Vdd through the charge pump. The specific circuit structure of the charge pump can be Fig. 9 shown.

[0101] In some embodiments, the signal A control module is a NAND gate, and the circuit structure of the signal A control module and the first switch can be Fig.12 shown.

[0102] In some embodiments, the signal B control module is a NAND gate and an inverter, the signal M_EN is input to the input end of the NAND gate, the signal M_WL is input to the input end of the NAND gate through the inverter, and the circuit structure of the signal B control module and the second switch can be Fig.12 shown.

[0103] In some embodiments, the signal C control module is an inverter, and the circuit diagram of the signal C control module and the third switch can be represented by Fig.11 shown.

[0104] In some embodiments, the specific circuit diagram of the backside bias voltage control module can be obtained by Fig.14 shown.

[0105] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0106] In summary, when the B-WL is turned off, the read port is in a static mode, and the backside voltage is adjusted to a negative voltage, so that the cut-off leakage is reduced to reduce power consumption; when the B-WL is turned on, the read port is in an operating mode, and the backside voltage is adjusted to a positive voltage, so that the on-current is increased to increase the operating speed. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0107] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A control circuit for SRAM speed regulation, characterized in that: At least: Dual-port, eight-transistor SRAM, including: 6-transistor SRAM structure and 2-transistor read port; The 6-transistor SRAM structure is controlled by signals A-WL, BL1, and BL2; the 6-transistor SRAM structure is connected to the storage unit working power supply Vdd; The 2-transistor read port is controlled by signals RPBL and B-WL; A backside bias voltage control module, which is used to control the backside voltage of the 2-transistor read port, includes: First and second potential shift modules; Signal A control module, signal B control module, signal C control module; The first to third control switches are used to control the positive voltage, negative voltage and 0V of the back side voltage of the 2-transistor read port to be turned on respectively; wherein, The first potential shift module is used to convert the enable signal EN of 1 or 0 into a signal M_EN of 1 or -1; The second potential shift module is used to convert the word line signal B-WL of 1 or 0 into a signal M_WL of 1 or -1; The signal A control module is used to control the opening state of the first switch according to the signal M_EN and the signal M_WL; The signal B control module is used to control the opening state of the second switch according to the signal M_EN and the signal M_WL; The signal C control module is used to control the opening state of the third switch according to the signal M_EN; When the enable signal EN is 0, the backside voltage is adjusted to 0V; When B-WL is turned off, the read port is in static mode, and the backside voltage is adjusted to a negative voltage, so that the cut-off leakage decreases to reduce power consumption; When the B-WL is enabled, the read port is in operation mode and the backside voltage is adjusted to a positive voltage so that the on-current increases to increase the operation speed.

2. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The dual-port eight-transistor SRAM comprises: Transistors PG1, PG2, PU1, PU2 and transistors PD1, PD2, RP PD, RPPG; wherein, PD1, PD2, RP PD are pull-down tubes, PU1, PU2 are rise tubes, PG1 and PG2 are transmission tubes, RP PG are selection tubes; RPPD, RP PG are read ports; The source electrodes of PU1 and PU2 are connected to the working power supply Vdd of the storage unit, and the drain electrodes of PU1 and PU2 are connected to the drain electrodes of PD1 and PD2 respectively; The gate of PU1 is connected to the gate of PD1 to form a first storage node n2, and the gate of PU2 is connected to the gate of PD2 to form a second storage node n1; The source of PD1 and PD2 is connected to the ground line; The source of PG1 is connected to the signal BL1, the drain is connected to the first storage node n1, and the gate is connected to the signal A-WL; The source of PG2 is connected to the signal BL2, the drain is connected to the second storage node n2, and the gate is connected to the signal A-WL; The source of RPPD is connected to the ground line, the gate is connected to the first storage node n2, and the drain is connected to the source of RPPG; The drain of RPPG is connected to the signal RP BL, and the gate is connected to the signal B-WL; wherein PG1, PG2, PU1, PU2, PD1, and PD2 form a 6-transistor SRAM structure, which is controlled by signals A-WL, BL1, and BL2.

3. The control circuit for SRAM speed regulation according to claim 2, characterized in that: The transistors PG1 and PG2 are NMOS, and the transistors PU1 and PU2 and the transistors PD1, PD2, RPPD, and RPPG are PMOS.

4. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The positive voltage is 0V to the working power supply of the storage unit.

5. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The negative voltage is 0V to negative storage unit working power supply.

6. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The negative voltage is obtained by a working power supply Vdd through a charge pump.

7. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The storage unit has an operating power supply of 1V.

8. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The signal A control module is a NAND gate.

9. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The signal B control module is a NAND gate and an inverter. The signal M_EN is input to the input end of the NAND gate, and the signal M_WL is input to the input end of the NAND gate through the inverter.

10. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The signal C control module is an inverter.

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