Control circuit for speed regulation of SRAM (Static Random Access Memory)

Abstract

The invention provides a control circuit for speed regulation of an SRAM (Static Random Access Memory), which comprises a dual-port eight-transistor SRAM, and the dual-port eight-transistor SRAM comprises four transistors PG1, PG2, PU1 and PU2 and four transistors PD1, PD2, RP PD and RP PG; wherein the PD1, the PD2 and the RP PD are pull-down tubes, the PU1 and the PU2 are ascending tubes, the PG1 and the PG2 are transmission tubes, and the RP PG is a gate tube; the RP PD and the RP PG are used as reading ports; the back side bias voltage control module is used for controlling the back side voltage of the RP PD and the RP PG: when the B-WL is closed, the reading port is in a static mode, and the back side voltage is adjusted to be a first target value, so that cut-off electric leakage is reduced to reduce power consumption; when the B-WL is activated, the read port is in an operating mode, and the backside voltage is adjusted to a second target value such that the on-current rises to increase the operating speed. Under the condition that the technological process is not adjusted, the power consumption is reduced under the condition that cut-off leakage of the SRAM is adjusted, and the reading speed is increased by adjusting conduction current rise.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a control circuit for SRAM speed regulation. Background Art

[0002] In the past 20 to 30 years, with the rapid development of microelectronics technology, components have been miniaturized rapidly, chip density has increased, and computing performance has increased. Semiconductor memory is also developing in a significant direction. Among volatile memories, SRAM has the characteristics of low power consumption and high performance, and DRAM has the characteristics of low cost and large storage capacity.

[0003] Currently, various memories are embedded in SOC (system on a chip) to improve system performance, especially SRAM circuit (static random access memory circuit). Since this circuit is compatible with the current CMOS process and is usually used in the L1 / L2 cache (first / second level high-speed cache) in computing chips, it naturally becomes the first choice for embedded memory. Therefore, SRAM has a considerable proportion in the functions and applications of digital chips.

[0004] Mature process technology, planar transistors, use ion implantation to achieve the change of component threshold voltage Vt and on-state current Id.

[0005] Transistors with advanced technology use metal gate work functions to achieve changes in the threshold voltage Vt and on-state current Id of the device.

[0006] 8T2P SRAM (dual-port eight-transistor SRAM), the circuit diagram is as follows Figure 1 As shown, the function is Figure 2 As shown, a 2-port SRAM is composed of 8 transistors (Tr.).

[0007] Internal 6 transistors: The function is to write / read, the operation speed is normal, and the balance between reading and writing must be maintained. n1 and n2 are used to store signals. When AWL = 1, PG1 and PG2 are turned on, and BL1 and BL2 are used to write or read. BL1 and BL2 are 1 port.

[0008] External 2 transistors: for reading ports, the speed is relatively faster, so the corresponding leakage is slightly higher. When BWL = 1, RP PG is turned on, and RP BL is used for reading.

[0009] If the device Vt (threshold voltage) and Id (on-state current) are to be adjusted, changes must be made to the process flow. In mature process flow, planar transistors use ion implantation to achieve changes in the component's threshold voltage Vt and on-state current Id.

[0010] Transistors using advanced technology processes use metal gate work functions to achieve changes in the threshold voltage Vt and on-state current Id of the device.

[0011] Regardless of whether it is a planar transistor or a solid-state transistor, in digital circuits, the NFET bulk is connected to 0V and the PFET bulk is connected to Vdd.

[0012] After the chip goes through the manufacturing process, the performance of each component in the chip is fixed. Therefore, in SRAM operation, the speed of the static mode and the leakage of the operating mode are fixed. If the device Vt and Id need to be adjusted, changes must be made in the process flow.

[0013] In order to solve the above problems, it is necessary to propose a new control circuit for SRAM speed regulation. Summary of the invention

[0014] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a control circuit for SRAM speed regulation, which is used to solve the problem in the prior art that the speed of the static mode and the leakage of the operating mode are fixed in the SRAM operation. If the device Vt, Id is to be adjusted, the process flow must be changed.

[0015] To achieve the above-mentioned object and other related objects, the present invention provides a control circuit for SRAM speed regulation, comprising:

[0016] A dual-port eight-transistor SRAM comprising: a 6-transistor SRAM structure and a 2-transistor read port;

[0017] Backside bias voltage control module, which is used to control the backside voltage of the 2-transistor read port:

[0018] When the B-WL is turned off, the read port is in a static mode, and the backside voltage is adjusted to a first target value so that the cut-off leakage decreases to reduce power consumption;

[0019] When the B-WL is started, the read port is in operation mode, and the backside voltage is adjusted to a second target value so that the on-current increases to increase the operation speed.

[0020] Preferably, the dual-port eight-transistor SRAM comprises: 4 transistors PG1, PG2, PU1, PU2 and 4 transistors PD1, PD2, RP PD, RP PG; wherein PD1, PD2, RP PD are pull-down transistors, PU1 and PU2 are rise-up transistors, PG1 and PG2 are transmission transistors, and RP PG is a selection transistor; RP PD and RP PG serve as read ports; the source of PU1 and PU2 are connected to the storage unit working power supply Vdd, and the drains of PU1 and PU2 are connected to the drains of PD1 and PD2 respectively; the gate of PU1 is connected to the gate of PD1 to form a first storage node n2, and the gate of PU2 is connected to the gate of PD2 to form a second storage node n1; the sources of PD1 and PD2 are connected to the ground line; the source of PG1 is connected to the signal BL1, the drain is connected to the first storage node n1, and the gate is connected to the signal A-WL; the source of PG2 is connected to the signal BL2, the drain is connected to the second storage node n2, and the gate is connected to the signal A-WL; The source of PD is connected to the ground line, the gate is connected to the first storage node n2, and the drain is connected to the source of RP PG; the drain of RP PG is connected to the signal RP BL, and the gate is connected to the signal B-WL; among them, PG1, PG2, PU1, PU2, PD1, and PD2 form a 6-transistor SRAM structure, which is controlled by signals A-WL, BL1, and BL2.

[0021] Preferably, the transistors PG1 and PG2 are NMOS or PMOS; the transistors PU1 and PU2 are PMOS; and the transistors PD1, PD2, RP PD, and RP PG are NMOS.

[0022] Preferably, the first target value is 0V to -0.5Vdd.

[0023] Preferably, the first target value is 0V to -Vdd.

[0024] Preferably, the second target value is 0V to 0.5Vdd.

[0025] Preferably, the second target value is 0V to Vdd.

[0026] As described above, the control circuit for SRAM speed regulation of the present invention has the following beneficial effects:

[0027] The present invention can adjust the cut-off leakage of SRAM to reduce power consumption and adjust the on-current rise to increase the reading speed without adjusting the process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a schematic diagram of a dual-port eight-transistor SRAM structure of the prior art;

[0029] Figure 2Shown is a schematic diagram of the port function of the prior art;

[0030] Figure 3 It is a schematic diagram showing the relationship between the back side voltage of the device of the present invention and the on-current and off-current;

[0031] Figure 4 Shown is a schematic diagram of the effect of the backside voltage on the device performance of the present invention;

[0032] Figure 5 Shown is a schematic diagram of a control circuit for SRAM speed regulation of the present invention;

[0033] Figure 6 It is a schematic diagram showing the effect of the backside voltage on the read port performance of the present invention;

[0034] Figure 7 It is a timing diagram of the dual-port eight-transistor SRAM structure of the present invention. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] See also Figure 5 The present invention provides a control circuit for SRAM speed regulation, comprising:

[0037] A dual-port eight-transistor SRAM comprising: a 6-transistor SRAM structure and a 2-transistor read port;

[0038] In some embodiments, a dual-port eight-transistor SRAM includes: 4 transistors PG1, PG2, PU1, PU2 and 4 transistors PD1, PD2, RP PD, RP PG; wherein PD1, PD2, RP PD are pull-down transistors, PU1 and PU2 are rise-up transistors, PG1 and PG2 are transmission transistors, and RP PG is a selection transistor; RP PD and RP PG serve as read ports; the source of PU1 and PU2 are connected to the storage unit working power supply Vdd, and the drains of PU1 and PU2 are connected to the drains of PD1 and PD2 respectively; the gate of PU1 is connected to the gate of PD1 to form a first storage node n2, and the gate of PU2 is connected to the gate of PD2 to form a second storage node n1; the sources of PD1 and PD2 are connected to the ground line; the source of PG1 is connected to the signal BL1, the drain is connected to the first storage node n1, and the gate is connected to the signal A-WL; the source of PG2 is connected to the signal BL2, the drain is connected to the second storage node n2, and the gate is connected to the signal A-WL; The source of PD is connected to the ground line, the gate is connected to the first storage node n2, and the drain is connected to the source of RP PG; the drain of RP PG is connected to the signal RP BL, and the gate is connected to the signal B-WL; among them, PG1, PG2, PU1, PU2, PD1, and PD2 form a 6-transistor SRAM structure, which is controlled by signals A-WL, BL1, and BL2.

[0039] In some embodiments, the transistors PG1 and PG2 are NMOS or PMOS; the transistors PU1 and PU2 are PMOS; and the transistors PD1, PD2, RP PD, and RP PG are NMOS.

[0040] See also Figure 3 The inventors found that due to the circuit characteristics of RP PG and RP PD of the dual-port eight-transistor SRAM, when the Vt (threshold voltage) and Id (on-current) of RP PG and RP PD are high or low, it will not affect the read / write balance (Read / Write Balance) during the internal 6T Bit cell signal operation. Therefore, adjusting the current of the read port, that is, adjusting the read port read speed, will not affect the state of the 6-transistor SRAM.

[0041] MOSFET body factor (bulk bias phenomenon), when the bulk voltage is different from the source terminal voltage, the resulting electrical behavior will change.

[0042] By adjusting the different backside voltages of the MOSFET, the dual-port eight-transistor SRAM can obtain different on-current and off-leakage (device Ion & Ioff). The on-current increases and decreases linearly, and the off-leakage increases and decreases exponentially, as shown in the figure. Figure 3 Take N-type device as an example)

[0043] See also Figure 4 , taking N-type device as an example:

[0044] When the N-type device is in offstatus (quiescent mode), set Vb = 0 ~ -0.5Vdd (or –Vdd), then the off leakage can be reduced to reduce power consumption;

[0045] When the N-type device is in the on status (operation mode), Vb=0~+0.5Vdd (or +Vdd), then the conduction current can be increased to increase the speed.

[0046] Therefore, a backside bias voltage control module is added to the SRAM periphery (static random access memory peripheral circuit) to control the backside voltage of RP PD and RP PG. Figure 7 Timing diagram for an eight-transistor SRAM shown as a dual port:

[0047] See also Figure 6 , when the B-WL is turned off, the read port is in a static mode, and the backside voltage is adjusted to a first target value so that the cut-off leakage decreases to reduce power consumption;

[0048] See also Figure 6 , when B-WL is started, the read port is in operation mode, and the backside voltage is adjusted to a second target value so that the on-current increases to increase the operation speed.

[0049] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] In summary, the present invention can adjust the SRAM cut-off leakage to reduce power consumption and adjust the on-current to increase the reading speed without adjusting the process flow. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A control circuit for SRAM speed regulation, characterized in that: include: A dual-port eight-transistor SRAM comprising: a 6-transistor SRAM structure and a 2-transistor read port; Backside bias voltage control module, which is used to control the backside voltage of the 2-transistor read port: When the B-WL is turned off, the read port is in a static mode, and the backside voltage is adjusted to a first target value so that the cut-off leakage decreases to reduce power consumption; When the B-WL is started, the read port is in operation mode, and the backside voltage is adjusted to a second target value so that the on-current increases to increase the operation speed.

2. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The dual-port eight-transistor SRAM comprises: 4 transistors PG1, PG2, PU1, PU2 and 4 transistors PD1, PD2, RP PD, RP PG; wherein PD1, PD2, RP PD are pull-down transistors, PU1, PU2 are rise-up transistors, PG1 and PG2 are transmission transistors, and RP PG is a selection transistor; RPPD and RP PG are used as read ports; the sources of PU1 and PU2 are connected to the storage unit working power supply Vdd, and the drains of PU1 and PU2 are respectively connected to the drains of PD1 and PD2; the gate of PU1 is connected to the gate of PD1 to form a first storage node n2, and the gate of PU2 is connected to the gate of PD2 to form a second storage node n1; the sources of PD1 and PD2 are connected to the ground line; the source of PG1 is connected to the signal BL1, the drain is connected to the first storage node n1, and the gate is connected to the signal A-WL; the source of PG2 is connected to the signal BL2, the drain is connected to the second storage node n2, and the gate is connected to the signal A-WL; The source of PD is connected to the ground line, the gate is connected to the first storage node n2, and the drain is connected to the source of RP PG; the drain of RP PG is connected to the signal RP BL, and the gate is connected to the signal B-WL; among them, PG1, PG2, PU1, PU2, PD1, and PD2 form a 6-transistor SRAM structure, which is controlled by signals A-WL, BL1, and BL2.

3. The control circuit for SRAM speed regulation according to claim 2, characterized in that: The transistors PG1 and PG2 are NMOS or PMOS; the transistors PU1 and PU2 are PMOS; the transistors PD1, PD2, RP PD, and RP PG are NMOS.

4. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The first target value is 0V to -0.5Vdd.

5. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The first target value is 0V to -Vdd.

6. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The second target value is 0V to 0.5Vdd.

7. The control circuit for SRAM speed regulation according to claim 1, characterized in that: The second target value is 0V to Vdd.

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