Method for simulating electronically erasable rewritable read-only memory by flash memory and flash memory system

Abstract

The invention relates to a method for simulating an electronically erasable rewritable read-only memory by using a flash memory and a flash memory system using the same. The flash memory system comprises a control circuit and a flash memory. Each unit of the flash memory is divided into a data field and an address field, and a plurality of units are distributed in a first page. When the control circuit receives an instruction, a specific storage unit in the storage section is read, and starting from an initial unit of an initial webpage of the storage section, whether an address field of the unit is written or not is judged. And if the address field of the unit is judged to be in a written state, finding the next address according to the address of the address field of the unit until the address field of one unit is found to be not written. At this time, the control circuit reads the data field of the unit to which the address field is not written.

Description

Technical Field

[0001] The present disclosure relates to a flash memory technology, and in particular to a method for simulating an electronically erasable rewritable read-only memory using a flash memory and a flash memory system using the same. Background Art

[0002] Electrically-Erasable Programmable Read-Only Memory (EEPROM) was first introduced by Intel in 1978 to replace traditional ROM (Read-Only Memory). The unit of EEPROM is byte. In addition, the read and write operations of EEPROM are performed separately, and each byte needs to be read and written. Since the read and write operations of EEPROM need to be erased and written many times, the number of read and write operations can usually reach 100,000 to 1 million times.

[0003] Flash memory was introduced by the Japanese company Toshiba in 1988. It was developed mainly to solve the problem of long writing time of EEPROM. The writing speed of EEPROM is slower than that of flash memory, generally taking about 4ms. However, in some applications of microcontrollers (MCU), it is necessary to simulate the behavior of EEPROM. In addition to the characteristics of reading and writing in 1 byte or 2 bytes, EEPROM can also be written directly. For general flash memory, the entire page of data needs to be erased before writing. Therefore, flash memory does not have the random access characteristics of EEPROM. Summary of the invention

[0004] The present invention provides a method for simulating an EEPROM using a flash memory and a flash memory system using the method, which is used to implement a control method according to the address characteristics of both the flash memory and the EEPROM so that the flash memory can achieve a random access method similar to the EEPROM.

[0005] The embodiment of the present disclosure provides a method for simulating an electronically erasable rewritable read-only memory using a flash memory, which is used to simulate an electronically erasable rewritable read-only memory that can be read and written repeatedly in a flash memory. The method for simulating an electronically erasable rewritable read-only memory using a flash memory includes the following steps: dividing each unit of the flash memory into a data field and an address field; allocating multiple units into a page; allocating multiple pages into a storage segment; and when receiving an instruction, performing a data segment operation on a specific storage address in the storage segment. The method of using flash memory to simulate an electronically erasable rewritable read-only memory includes: starting from an initial unit of an initial web page of the storage segment (sector), determining whether the address field of the unit has been written; if the address field is in a written state, finding the next address according to the address field until a final unit is found, wherein the address field of the final unit is in an unwritten state; in addition, finding a writable unit, wherein both the data field and the address field of the writable unit are unwritten; and writing the data field of the above-mentioned writable unit, and writing the address field of the final unit into the address of the writable unit.

[0006] The embodiment of the present disclosure further provides a flash memory system, which includes a control circuit and a flash memory, wherein each unit of the flash memory is divided into a data field and an address field, and multiple units are allocated in a first page and in a storage segment. When the control circuit receives an instruction to read a specific storage address in the above storage segment, the control circuit starts from an initial unit of an initial web page of the above storage segment to determine whether the address field of the unit has been written. If the control circuit determines that the address field of the above unit is in a written state, the next address is found according to the address field until it is found that the address field of one of the units is not written. The control circuit reads the data field of the unit whose address field is not written.

[0007] According to the preferred embodiment of the present disclosure, a method for simulating an electronically erasable rewritable read-only memory using flash memory and a flash memory system using the same are described, wherein, when an instruction is received, a specific storage address in the above-mentioned storage segment (sector) is read. The method for simulating an electronically erasable rewritable read-only memory using flash memory includes: starting from an initial unit of an initial web page of the above-mentioned storage segment (sector), determining whether the address field of the unit has been written; if the address field is in a written state, finding the next address according to the address field until it is found that the address field of one of the units has not been written; and reading the data field of the above-mentioned unit.

[0008] According to the preferred embodiment of the present disclosure, the method of using flash memory to simulate an electronically erasable rewritable read-only memory and the flash memory system using the same further include the following steps: allocating at least one second page as a storage segment; wherein, when the instruction is received, writing the specific storage address in the storage segment. The method of using flash memory to simulate an electronically erasable rewritable read-only memory further includes: when the first page is full, searching for a unit of the second page, wherein the address field of the unit is not written; and writing the data field of the unit of the second page.

[0009] The disclosed embodiment further provides a method for simulating an electronically erasable rewritable read-only memory using a flash memory, which is used to simulate an electronically erasable rewritable read-only memory that can be read and written repeatedly in a flash memory. The method for simulating an electronically erasable rewritable read-only memory using a flash memory includes the following steps: dividing each unit of the flash memory into a data field and an address field; allocating multiple units into a first page and allocating them in a storage segment; when an instruction is received, reading a specific storage address in the storage segment. The method for simulating an electronically erasable rewritable read-only memory using a flash memory includes: starting from an initial unit of the first page of the storage segment, determining whether the address field of the unit has been written; if the address field is in a written state, finding the next address according to the address field until it is found that the address field of one of the units has not been written; and reading the data field of the above-mentioned unit.

[0010] In summary, the embodiments of the present disclosure adopt the partitioning method originally used for electronically erasable rewritable read-only memory in the flash memory and use it in the addressing method of the flash memory, and additionally configure a data field and an address pointer field in each writable unit. When the address pointer field is in a written state, it indicates that the data in the data field is not the latest written data. At this time, just continue to search for the address in the address pointer field until a unit is found. The address pointer field in this unit is in an unwritten state, indicating that the data in the data field in this unit is the latest data. In this way, the memory configuration of the electronically erasable rewritable read-only memory can be simulated, and the number of full-page erases of the flash memory can be reduced, thereby increasing the service life of the flash memory.

[0011] In order to further understand the technology, means and effects of the present disclosure, reference may be made to the following detailed description and drawings, so that the purpose, features and concepts of the present disclosure can be thoroughly and specifically understood. However, the following detailed description and drawings are only used for reference and explanation of the implementation of the present disclosure, and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are provided to enable those with ordinary knowledge in the technical field to which the present disclosure belongs to further understand the present disclosure, and are incorporated into and constitute a part of the specification of the present disclosure. The accompanying drawings show exemplary embodiments of the present disclosure, and are used together with the specification of the present disclosure to explain the principles of the present disclosure.

[0013] Figure 1 FIG. 4 is a system block diagram of a flash memory system according to an embodiment of the present disclosure.

[0014] Figure 2 FIG. 1 is a schematic diagram showing the configuration of storage blocks of a flash memory 101 according to an embodiment of the present disclosure.

[0015] Figure 3 FIG. 1 is a schematic diagram showing the configuration of a storage block of a flash memory unit according to an embodiment of the present disclosure.

[0016] Figure 4 FIG. 1 is a schematic diagram of using a flash memory to simulate data storage of an electrically erasable rewritable read-only memory according to an embodiment of the present disclosure.

[0017] Figure 5 FIG. 4 is a flow chart of a writing method of a method for simulating an electrically erasable rewritable read-only memory using a flash memory according to an embodiment of the present disclosure.

[0018] Figure 6 FIG. 1 is a flow chart of a reading method of a method for simulating an electrically erasable rewritable read-only memory using a flash memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to exemplary embodiments of the present disclosure, which are illustrated in the accompanying drawings. Where possible, the same component symbols are used in the drawings and the specification to refer to the same or similar components. In addition, the exemplary embodiments are only one of the implementation methods of the design concept of the present disclosure, and the following examples are not intended to limit the present disclosure.

[0020] Figure 1 FIG. 1 is a system block diagram of a flash memory system according to an embodiment of the present disclosure. Figure 1, this flash memory system is, for example, a single chip microcontroller 10. This flash memory system includes a control circuit 100 and a flash memory 101. In this embodiment, the flash memory 101 is used to simulate an electronically erasable rewritable read-only memory. Because flash memory has certain advantages in price and capacity compared to electronically erasable rewritable read-only memory. First, the price of flash memory is relatively low, which is mainly because the manufacturing process of flash memory is simpler than that of electronically erasable rewritable read-only memory, the production cost is lower, and the production scale is getting larger and larger, which also makes the price of flash memory further reduced. Secondly, the capacity of flash memory is also relatively large. The storage density of flash memory is higher than that of electronically erasable rewritable read-only memory, which means that under the same chip area, flash memory can store more data, thereby increasing storage capacity. In addition, since flash memory can have multiple sectors at the same time, the storage capacity is larger.

[0021] However, in some special applications, if flexible read and write operations are required and the capacity is small, the read and write of the electronically erasable rewritable read-only memory will still be used in the product. Therefore, in this embodiment, the characteristics of the flash memory 101 are used to avoid erasing the entire page for random access.

[0022] Figure 2 FIG. 1 is a schematic diagram showing the configuration of the storage blocks of the flash memory 101 according to an embodiment of the present disclosure. Figure 2 The flash memory 101 is, for example, a NAND flash memory. The flash memory 101 includes a plurality of storage sectors 200. Each storage sector 200 includes a plurality of pages 201. Each page 201 includes, for example, 16 units 202. Each unit 202 includes a data field 203 and an address field 204. In this embodiment, each unit has a total of 32 bits.

[0023] Figure 3 FIG. 1 is a schematic diagram showing the configuration of a storage block of a flash memory unit according to an embodiment of the present disclosure. Figure 3 In this embodiment, each unit includes a data field 203 for storing two bytes and an address field 204 for storing two bytes of a pointer.

[0024] Figure 4 FIG. 1 is a schematic diagram of a data storage method using a flash memory to simulate an electronically erasable rewritable read-only memory according to an embodiment of the present disclosure. Figure 4In this embodiment, the first 16 bytes of each page are set as the initial use address of the electronic erasable rewritable read-only memory. In which, four bytes are grouped together to simulate two bytes of data. Figure 4 In the figure, it can be seen that the left side represents the address of the flash memory, and the right side represents the address of the electronically erasable rewritable read-only memory. Initially, this simulated electronically erasable rewritable read-only memory is written with initial data, the data in the 0x00 unit is 1122h; the data in the 0x04 unit is 3344h; the data in the 0x08 unit is 5566h; the data in the 0x0c unit is 7788h. Among them, the flash memory addresses of the above 0x00, 0x04, 0x08, and 0x0c units correspond to the electronically erasable rewritable read-only memory addresses of the above 0x00, 0x02, 0x04, and 0x06 units, respectively. In addition, the address fields 204 of the above 0x00, 0x04, 0x08, and 0x0c units are all in an unwritten state, so the internal data of the address fields are all ffffh.

[0025] When the control circuit 100 receives an instruction to modify the data of the 0x00 unit of the EEPROM to 99aah, and the data of the 0x02 unit of the EEPROM to bbcch, as shown in reference numeral 401, the control circuit 100 writes 99aah to the 0x10 unit address of the flash memory, and writes bbcch to the 0x14 unit address of the flash memory. Afterwards, the control circuit 100 adds 0010h to the data field 203 of the 0x00 unit address of the flash memory to indicate that the updated data of the 0x00 of the EEPROM is stored at the 0x10 address of the flash memory, and adds 0014h to the data field 203 of the 0x04 unit address of the flash memory to indicate that the updated data of the 0x02 of the EEPROM is stored at the 0x14 address of the flash memory.

[0026] When the control circuit 100 receives an instruction again to modify the data of the 0x02 unit of the EEPROM to ddeeh, as shown in reference numeral 402, the control circuit 100 writes ddeeh to the address of the 0x18 unit of the flash memory. Afterwards, the control circuit 100 finds that the address field 204 of the 0x04 unit of the flash memory has been written, so according to the written 0014h, the address of the 0x14 unit is found, and then it is determined that the address field 204 of the 0x14 unit has not been written, indicating that this 0x14 unit is the last final data of the 0x02 unit of the EEPROM, so here, the control circuit 100 writes 0018h to the address field 204 of this 0x14 unit, indicating that the latest data of the 0x02 unit of the EEPROM is stored in the 0x18 unit.

[0027] According to the above embodiment, assuming that the control circuit 100 wants to read the data of the 0x02 unit of the electronically erasable rewritable read-only memory, the control circuit 100 will first find the address field of the 0x04 unit of the flash memory and determine whether it is written. If it is written, it means that the data in the data field of the 0x04 unit of the flash memory is not the latest data. At this time, the control circuit 100 will find the address field of the 0x14 unit of the flash memory according to the address field 0014h. At this time, the address field of the 0x14 unit of the flash memory has also been written, so the control circuit 100 will find the address field of the 0x18 unit of the flash memory according to the address field 0018h. At this time, the address field of the 0x18 unit of the flash memory is ffffh, which has not been written, indicating that the data in the data field of the 0x18 unit of the flash memory is the latest data, so the control circuit 100 reads out this data ddeeh as the data of the 0x02 unit of the electronically erasable rewritable read-only memory.

[0028] Next, assuming that the control circuit 100 receives an instruction again to modify the data of the 0x00 unit of the EEPROM to 1234h, as shown in label 404, the control circuit 100 will find that this page has been filled with data. At this time, the control circuit 100 will write 0x00 to 1234h in the new page of the same storage segment 200, and read the corresponding data of the EEPROM addresses of the 0x02, 0x04, and 0x06 units one by one using the above method, and write them into the data fields of the 0x04, 0x80, and 0x0c units in the new page accordingly. After that, the control circuit 100 will erase the page storing the old data.

[0029] Furthermore, since the capacity of a general EEPROM is extremely small, the capacity of the flash memory 101 is generally much larger than that of the EEPROM. Therefore, in the above embodiment, the flash memory 101 has a plurality of storage sectors 200, and the plurality of storage sectors 200 can respectively simulate a plurality of EEPROMs, and read or write is performed by using the address field as a memory address pointer.

[0030] Based on the above embodiments, the present disclosure can be summarized as a method for simulating an electronically erasable rewritable read-only memory using a flash memory. Figure 5 FIG. 1 is a flowchart of a method for simulating an electronically erasable rewritable read-only memory using flash memory according to an embodiment of the present disclosure. Figure 5 The writing method of the method of simulating the electronic erasable rewritable read-only memory using flash memory includes the following steps:

[0031] Step S501: Start.

[0032] Step S502: Divide each unit of the flash memory into a data field and an address field.

[0033] Step S503: Allocate a plurality of units into a first page and allocate them to a storage sector.

[0034] Step S504: Determine whether a write instruction is received. If a write instruction is received, proceed to step S505.

[0035] Step S505: Starting from the storage unit corresponding to the address of a page of the storage sector, determine whether the address field of the unit has been written. If it has been written, proceed to step S506. If not, proceed to step S507.

[0036] Step S506: Find the address of the next unit according to the address field, and return to step S505 until a final unit is found, wherein the address field of the final unit is not written.

[0037] Step S507: Find another writable unit, wherein the data field and the address field of the writable unit are not written in. If the page is full, the page can be changed and the writable unit can be found as in the above embodiment.

[0038] Step S508: Write the data field of the writable unit. If the page is full, the page can be changed and the writable unit can be found as in the above embodiment, and the data can be moved to the new page again.

[0039] Step S509: Write the address field of the final unit into the address of the above-mentioned writable unit.

[0040] Step S510: End.

[0041] Figure 6 FIG. 1 is a flowchart of a method for simulating an electronically erasable rewritable read-only memory using flash memory according to an embodiment of the present disclosure. Figure 6 The reading method of the method of simulating an electronically erasable rewritable read-only memory using a flash memory comprises the following steps:

[0042] Step S601: Start.

[0043] Step S602: Divide each unit of the flash memory into a data field and an address field.

[0044] Step S603: Allocate a plurality of units into a first page and allocate them in a storage sector.

[0045] Step S604: Determine whether a read instruction is received. If a read instruction is received, proceed to step S605.

[0046] Step S605: Starting from the storage unit corresponding to the address of a page of the storage sector, determine whether the address field of the unit has been written. If it has been written, proceed to step S606. If not, proceed to step S607.

[0047] Step S606: Find the address of the next unit according to the address field, and return to step S605 until a final unit is found, wherein the address field of the final unit is not written.

[0048] Step S607: Read the data field of the above unit.

[0049] Step S608: End.

[0050] In the above embodiment, if a plurality of electrically erasable and rewritable read-only memories are simulated, a plurality of sectors in the flash memory can be used as the electrically erasable and rewritable read-only memories to be simulated.

[0051] In summary, the embodiments of the present disclosure adopt the partitioning method originally used for electronically erasable rewritable read-only memory in the flash memory, and additionally configure a data field and an address pointer field in each writable unit. When the address pointer field is in a written state, it indicates that the data in the data field is not the latest written data. At this time, just continue to search for the address in the address pointer field until a unit is found. The address pointer field in this unit is in an unwritten state, indicating that the data in the data field in this unit is the latest data. In this way, the memory configuration of the electronically erasable rewritable read-only memory can be simulated, and the number of full-page erases of the flash memory can be reduced, thereby increasing the service life of the flash memory.

[0052] It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in view thereof will be suggested to those skilled in the art and are to be included within the spirit and scope of the present application and the scope of the appended claims.

Claims

1. A method for simulating an electronically erasable rewritable read-only memory using a flash memory, for simulating an electronically erasable rewritable read-only memory in a flash memory, the method for simulating an electronically erasable rewritable read-only memory using a flash memory comprising: Each unit of the flash memory is divided into a data field and an address field; Allocating a plurality of units into a first page and allocating the first page into a storage segment; When receiving an instruction, a first specific storage unit in the storage segment is written, and the method of using flash memory to simulate an electronically erasable rewritable read-only memory includes: Starting from the first specific memory cell of a first page of the memory segment, determining whether the address field of the cell has been written; If the address field is in a written state, then find the address of the next unit according to the address field until a final unit is found, wherein the address field of the final unit is not written; In addition, a writable unit is found, wherein both the data field and the address field of the writable unit are not written; and The data field of the above-mentioned writable unit is written, and the address field of the final unit is written into the address of the writable unit.

2. The method for simulating an electronically erasable rewritable read-only memory using a flash memory according to claim 1, wherein: When receiving an instruction to read a second specific storage unit in the storage segment, the method of using flash memory to simulate an electronically erasable rewritable read-only memory includes: Starting from a second specific storage unit in an initial page of the storage segment, determining whether an address field of the second specific storage unit has been written; If the address field is in a written state, find the address of the next unit according to the address field, and keep searching until it is found that the address field of one of the units has not been written; and Read the data field of the above cell.

3. The method of simulating an electronically erasable rewritable read-only memory using a flash memory according to claim 1, wherein: The flash memory is a non-AND type flash memory, and the non-AND type flash memory is built in a microprocessor.

4. The method of simulating an EEPROM using a flash memory according to claim 2, further comprising: Allocating at least one second page to the storage segment; When the instruction is received to perform a write operation on the second specific storage unit in the storage segment, the method of simulating an electronically erasable rewritable read-only memory using a flash memory further includes: When the first page is full, searching for a cell in the second page, wherein the address field of the cell is in an unwritten state; and The data field is written into the cell in the second page.

5. The method of simulating an electronically erasable rewritable read-only memory using a flash memory according to claim 1, wherein: The method is further used to write a plurality of simulated electronically erasable rewritable read-only memories, wherein the method of using flash memory to simulate electronically erasable rewritable read-only memories further includes: A plurality of storage sections are set corresponding to the addresses of the plurality of electronically erasable rewritable read-only memories.

6. A method for simulating an electronically erasable rewritable read-only memory using a flash memory, for simulating an electronically erasable rewritable read-only memory that can be read and written repeatedly in a flash memory, the method for simulating an electronically erasable rewritable read-only memory using a flash memory comprising: Each unit of the flash memory is divided into a data field and an address field; Allocating the plurality of units as a first page and allocating the first page in a storage segment; When receiving an instruction to read a first specific storage unit in the storage segment, the method of using flash memory to simulate an electronically erasable rewritable read-only memory includes: Starting from a first specific storage unit in a first page of the storage segment, determining whether an address field of the unit has been written; If the address field is in a written state, find the address of the next unit according to the address field, and keep searching until it is found that the address field of one of the units has not been written; and Read the data field of the above cell.

7. The method of simulating an electronically erasable rewritable read-only memory using a flash memory according to claim 6, wherein: When receiving an instruction to write into the second specific storage unit in the storage segment, the method of simulating an electronically erasable rewritable read-only memory using a flash memory includes: Starting from a first specific storage unit in a first page of the storage segment, determining whether an address field of the unit has been written; If the address field is in a written state, find the address of the next unit according to the address field, and keep searching until it is found that the address field of one of the units has not been written; and Write the data field of the above cell.

8. The method of simulating an EEPROM using a flash memory according to claim 7, further comprising: Allocating at least one second page to the storage segment; When the instruction is received to perform a write operation on the second specific storage unit in the storage segment, the method of simulating an electronically erasable rewritable read-only memory using a flash memory further includes: When the first page is full, searching for a cell in the second page, wherein the address field of the cell is in an unwritten state; and Write to the above unit.

9. A flash memory system, comprising: a control circuit; A flash memory, wherein each cell is divided into a data field and an address field, and a plurality of cells are allocated in a first page and simultaneously in a storage segment; When the control circuit receives an instruction to perform a write operation on a first specific storage unit in the storage segment, the control circuit starts from the first specific storage unit of the initial page of the storage segment and determines whether the address field of the unit has been written; If the control circuit determines that the address field of the above unit is in a written state, the address of the next unit is found according to the address field of the above unit, and the search continues until the address field of one of the final units is found to be unwritten; The control circuit also needs to find another writable unit, wherein both the data field and the address field of the writable unit have not been written; and The control circuit writes the data field into the above-mentioned writable unit, and writes the address field of the final unit into the address field of the writable unit.

10. A flash memory system, comprising: a control circuit; A flash memory, wherein each cell is divided into a data field and an address field, and a plurality of cells are allocated in a first page and simultaneously in a storage segment; When the control circuit receives an instruction to perform a read operation on a first specific storage unit in the storage segment, Wherein, the control circuit starts from the first specific storage unit of the initial page of the storage segment and determines whether the address field of the unit has been written; If the control circuit determines that the address field of the above unit is in a written state, the address of the next unit is found according to the address field of the above unit, and the search continues until it is found that the address field of one of the units has not been written; The control circuit reads the data field of the unit that has not been written into the address field.

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