Bit line voltage transmission circuit

Abstract

The application discloses a bit line voltage transmission circuit, and a gate voltage of a first NMOS transistor and a PMOS transistor of a transmission gate between an IO node and a bit line is connected with a first control signal and a second control signal respectively, and a lining electrode of the first PMOS transistor is connected with a third control signal. When the first control signal, the second control signal and the third control signal are a power voltage, a first negative voltage and a first positive voltage respectively, the transmission gate is turned on. The first positive voltage is greater than or equal to an IO voltage and less than the power voltage, and the first positive voltage is provided by a positive voltage signal generation circuit. The positive voltage signal generation circuit comprises a second NMOS transistor, a third NMOS transistor and a second PMOS transistor. The gate of the second NMOS transistor and the drain of the third NMOS transistor are connected to a first node. The source of the second NMOS transistor and the gate of the third NMOS transistor are connected to a second node, and the second node is used as an output end of the first positive voltage. The source of the third NMOS transistor is connected with the source of the second PMOS transistor, and the drain of the second PMOS transistor is grounded. A first pull-up circuit is formed between the first node and the power voltage. The first pull-up circuit and the second PMOS transistor are controlled by a first enable signal.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a bit line voltage transmission circuit. Background Technology

[0002] Embedded flash memory is an important component of MCUs, such as Figure 1 The diagram shown is a circuit diagram of a conventional selected-gate shared-gate (NORD) flash memory cell. Between the source and drain of the flash memory cell 101 are three gate structures arranged sequentially: a first gate structure 102a, a second gate structure, and a third gate structure 102b. Both the first gate structure 102a and the third gate structure 102b include a floating gate and a control gate. The floating gate is used to store information; therefore, the first gate structure 102a and the third gate structure 102b can each store one bit of data. Figure 1 In this configuration, the data stored in the first gate structure 102a is labeled as Bit1, and the data stored in the third gate structure 102b is labeled as Bit2. The second gate structure is located between the first gate structure 102a and the third gate structure 102b. The control gate of the first gate structure 102a is connected to the control gate CG1, the control gate of the third gate structure 102b is connected to the control gate CG2, and the polysilicon gate of the second gate structure is connected to the select gate SG.

[0003] When performing a read operation, such as reading Bit1, a high voltage needs to be applied to terminals CG1, CG2, and SG, with a potential of approximately 0.7V connected to the Drain terminal and the Source terminal grounded. The potential at the Drain terminal is typically generated by a sensitive amplifier. The IO voltage generated by the sensitive amplifier is transmitted to the corresponding BL via a multiplexer (YMUX).

[0004] A voltage drop is unavoidable when the I / O voltage is transferred to the BL. As the cell current increases, this voltage drop also increases, causing the BL voltage to be lower than the designed I / O voltage value. When the BL voltage decreases, the cell read current decreases, which affects the distinction between "0" cells and "1" cells, especially for cells with weak erase and weak program, resulting in read errors. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a bit line voltage transmission circuit that can provide a precise control voltage for the PMOS transistor of the transmission gate, i.e., the first PMOS transistor, and can keep the voltage drop across the transmission gate, i.e., the IO voltage and the bit line voltage, low when the cell current on the bit line is large, thereby increasing the accuracy of reading and improving the reliability of the flash memory system.

[0006] The bit line voltage transmission circuit provided by the present invention includes: a transmission gate.

[0007] The transmission gate is connected between the IO node and the selected positioning line.

[0008] The transmission gate includes a first NMOS transistor and a first PMOS transistor.

[0009] The drain of the first NMOS transistor and the source of the first PMOS transistor are connected to the IO node.

[0010] The source of the first NMOS transistor and the drain of the first PMOS transistor are connected to the selected positioning line.

[0011] The gate of the first NMOS transistor is connected to a first control signal, the gate of the first PMOS transistor is connected to a second control signal, and the pad electrode of the first PMOS transistor is connected to a third control signal.

[0012] When the first control signal is the power supply voltage, the second control signal is the first negative voltage, and the third control signal is the first positive voltage, the transmission gate is in the on state, and the IO voltage of the IO node is transmitted to the selected positioning line to form the bit line voltage.

[0013] The first positive voltage is greater than or equal to the IO voltage of the IO node and less than the power supply voltage, and the first positive voltage is provided by the positive voltage signal generation circuit.

[0014] The first negative voltage is less than or equal to the difference between the minimum value of the IO voltage and the absolute value of the first threshold voltage of the first PMOS transistor.

[0015] The positive voltage signal generation circuit includes: a second NMOS transistor, a third NMOS transistor, and a second PMOS transistor.

[0016] The gate of the second NMOS transistor and the drain of the third NMOS transistor are both connected to the first node.

[0017] The source of the second NMOS transistor and the gate of the third NMOS transistor are both connected to the second node, which serves as the output terminal of the first positive voltage.

[0018] The source of the third NMOS transistor is connected to the source of the second PMOS transistor, and the drain of the second PMOS transistor is grounded.

[0019] A first pull-up circuit is formed between the first node and the power supply voltage.

[0020] The first control terminal of the first pull-up circuit and the gate of the second PMOS transistor are both connected to the first enable signal.

[0021] The second NMOS transistor and the third NMOS transistor form a first negative feedback loop between the voltages of the first node and the second node and stabilize the first positive voltage.

[0022] When the first enable signal is low, both the first pull-up circuit and the second PMOS transistor are turned on. The series connection of the second PMOS transistor and the third NMOS transistor stabilizes the first positive voltage between the difference between the power supply voltage and the second threshold voltage and the sum of the absolute values ​​of the second threshold voltage and the third threshold voltage. The second threshold voltage is the threshold voltage of the second NMOS transistor, the third threshold voltage is the threshold voltage of the second PMOS transistor, and the threshold voltage of the third NMOS transistor is equal to the threshold voltage of the second NMOS transistor.

[0023] A further improvement is that the first negative pressure is provided by a negative pressure signal generating circuit, which includes a charge pump, a voltage divider circuit, and a comparator.

[0024] The charge pump outputs the first negative pressure.

[0025] The power supply terminal of the charge pump is connected to the power supply voltage, and the maximum negative voltage that the output terminal of the charge pump can generate is the negative value of the power supply voltage.

[0026] The voltage divider circuit is connected between the power supply voltage and the first negative voltage.

[0027] The voltage divider circuit provides the first voltage division.

[0028] The first voltage divider is connected to the first input terminal of the comparator, and the second input terminal of the comparator is grounded.

[0029] The comparator outputs a first feedback signal to the clock signal control terminal of the charge pump.

[0030] The clock input terminal of the charge pump is connected to a clock input signal, which is input to the charge pump under the control of the first feedback signal, thereby controlling the magnitude of the first negative pressure.

[0031] The first feedback signal controls the timing of the clock input signal being input to the charge pump based on the magnitude of the first voltage divider, thereby controlling the magnitude of the first negative voltage.

[0032] A further improvement is that the charge pump includes a symmetrical first sub-unit and a second sub-unit.

[0033] The first sub-unit and the second sub-unit have the same first circuit structure.

[0034] The first circuit structure includes: a pump capacitor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor.

[0035] The first terminal of the pump capacitor is connected to the first clock signal, and the second terminal of the pump capacitor is the first internal node.

[0036] The source of the fourth NMOS transistor, the drain of the fifth NMOS transistor, and the drain of the sixth NMOS transistor are all connected to the first internal node.

[0037] The drain of the fourth NMOS transistor, the gate of the fifth NMOS transistor, and the drain of the fourth PMOS transistor are all connected to the second internal node.

[0038] The source of the fifth NMOS transistor and the gate of the fourth PMOS transistor are both grounded.

[0039] The drain of the third PMOS transistor and the source of the fourth PMOS transistor are connected.

[0040] The source of the third PMOS transistor is connected to the power supply voltage.

[0041] The gates of the third PMOS transistor and the fourth NMOS transistor are both connected to the inverted signal of the first clock signal.

[0042] The gate of the sixth NMOS transistor is connected to the inverted signal of the first internal node.

[0043] The source of the sixth NMOS transistor outputs the first negative voltage.

[0044] In the charge pump, the connection relationship between the first subunit and the second subunit is as follows:

[0045] The first clock signal of the first sub-unit is an internal clock inverted signal, and the first clock signal of the second sub-unit is an internal clock signal. The internal clock signal and the internal clock inverted signal are inverses of each other and are both formed by the clock input signal.

[0046] The first internal node of the first sub-unit is connected to the gate of the sixth NMOS transistor of the second sub-unit; the first internal node of the second sub-unit is connected to the gate of the sixth NMOS transistor of the first sub-unit.

[0047] A further improvement is that the voltage divider circuit includes a first resistor and a second resistor.

[0048] The first terminal of the first resistor is connected to the power supply voltage.

[0049] The second end of the first resistor and the first end of the second resistor are connected together and serve as the output terminal of the first voltage divider.

[0050] The second end of the second resistor is connected to the output end of the charge pump.

[0051] The absolute value of the ratio of the first negative voltage to the power supply voltage is the ratio of the second resistor to the first resistor. The first negative voltage is adjusted by adjusting the ratio of the second resistor to the first resistor.

[0052] A further improvement is that a fifth PMOS transistor is connected between the first resistor, the first terminal, and the power supply voltage. The source of the fifth PMOS transistor is connected to the power supply voltage, and the drain of the fifth PMOS transistor is connected to the first terminal of the first resistor.

[0053] The gate of the fifth PMOS transistor is connected to the first enable signal.

[0054] A further improvement is that a decoupling capacitor is connected between the output terminal of the charge pump and ground.

[0055] A further improvement is that the negative pressure signal generating circuit also includes a first inverter.

[0056] The input terminal of the first inverter is connected to the first feedback signal, and the output terminal of the first inverter outputs a second feedback signal, which is then output to the clock signal control terminal of the charge pump.

[0057] A further improvement is that the first pull-up circuit includes a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor.

[0058] The source of the sixth PMOS transistor is connected to the power supply voltage.

[0059] The drain of the sixth PMOS transistor, the source of the seventh PMOS transistor, and the source of the eighth PMOS transistor are connected together.

[0060] The gate of the seventh PMOS transistor is connected to the first enable signal.

[0061] The drain of the seventh PMOS transistor, the gate of the eighth PMOS transistor, and the drain of the eighth PMOS transistor are connected to the first node.

[0062] A further improvement is that the positive pressure signal generation circuit also includes:

[0063] The ninth PMOS transistor has its source connected to the power supply voltage, its drain connected to the drain of the second NMOS transistor, and its gate grounded.

[0064] A further improvement is that the positive pressure signal generation circuit also includes:

[0065] The tenth PMOS transistor has its source connected to the power supply voltage. The drain of the ninth PMOS transistor is connected to the second node. The gate of the ninth PMOS transistor is connected to a first enable inverted signal, which is the inverted signal of the first enable signal.

[0066] A further improvement is that the positive voltage signal generation circuit also includes an eleventh PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor.

[0067] The source of the eleventh PMOS transistor and the drain of the seventh NMOS transistor are both connected to the second node.

[0068] The drain of the eleventh PMOS transistor and the source of the seventh NMOS transistor are both connected to the drain of the eighth NMOS transistor.

[0069] The source of the eighth NMOS transistor is grounded.

[0070] The gate of the eleventh PMOS transistor is connected to the first enable signal, and the gate of the seventh NMOS transistor is connected to the first enable inverted signal, wherein the first enable inverted signal is the inverted signal of the first enable signal.

[0071] The gate connection current control signal of the eighth NMOS transistor.

[0072] A further improvement is that the selected bit line is the bit line selected from a plurality of bit lines of the memory array by means of a column address signal.

[0073] The storage array is composed of multiple storage cells arranged together.

[0074] A further improvement is that the storage unit includes a selected-gate shared-gate flash memory unit.

[0075] A further improvement is that the IO node is a node connected to the sensitive amplifier and the bit line, and the IO voltage is generated by the sensitive amplifier.

[0076] A further improvement is that the second NMOS transistor is an intrinsic NMOS transistor, and the third NMOS transistor is an intrinsic NMOS transistor.

[0077] This invention specifically sets the voltages of the substrate electrode and gate of the first PMOS transistor when the transmission gate of the bit-line voltage transmission circuit is turned on. The voltage of the substrate electrode of the first PMOS transistor is a first positive voltage, and the gate voltage is a first negative voltage. The first positive voltage is provided by a positive voltage signal generation circuit. The second and third NMOS transistors in the positive voltage signal generation circuit are connected to form a first negative feedback loop structure. The second NMOS transistor enables the voltage of the second node to change in phase with the voltage of the first node and makes the voltage of the second node smaller than the voltage of the first node by the threshold voltage of the second NMOS transistor, i.e., the second threshold voltage. The third NMOS transistor enables the voltage of the first node to change in opposite phase with the voltage of the second node, and finally enables the potentials of the first and second nodes to stabilize. By setting the second PMOS transistor and the third NMOS transistor in a series structure with their sources connected, the voltage of the second node can be made greater than the second PMOS transistor's threshold voltage. The gate voltage of the MOS transistor, plus the absolute value of the threshold voltage of the second PMOS transistor (i.e., the third threshold voltage) and the second threshold voltage, ultimately stabilizes the first positive voltage between the difference between the power supply voltage and the second threshold voltage, and the sum of the absolute values ​​of the second and third threshold voltages. Therefore, the first positive voltage of this invention ensures that the substrate electrode voltage of the first PMOS transistor during conduction remains small while meeting the condition of being greater than or equal to the IO voltage. Simultaneously, combined with the setting of the first negative voltage, it enables the first PMOS transistor to maintain optimal conduction conditions, keeping the voltage drop across the transmission gate (i.e., the IO voltage and the voltage drop across the bit line voltage) low even when the cell current on the bit line is large. Therefore, this invention provides a precise control voltage for the PMOS transistor of the transmission gate, keeping the voltage drop across the transmission gate (i.e., the IO voltage and the voltage drop across the bit line voltage) low even when the cell current on the bit line is large, thereby increasing read accuracy and improving the reliability of the flash memory system.

[0078] This invention is particularly suitable for reading memory cells when the power supply voltage is continuously decreasing and the current required to read the cell is large. When the power supply voltage is low, this invention can maintain a large bit line voltage by precisely controlling the voltage drop on both sides of the transmission gate, thereby preventing the current of the cell to be read from decreasing. This is beneficial for distinguishing memory cells with stored information of 0 and 1, and in particular, it can enhance the distinction between memory cells with weak erase and weak programming, preventing read errors. Attached Figure Description

[0079] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0080] Figure 1 This is a circuit diagram of an existing NORD flash memory cell;

[0081] Figure 2 This is a circuit diagram of the transmission gate of the bit line voltage transmission circuit according to an embodiment of the present invention;

[0082] Figure 3 This is a circuit diagram of the positive voltage signal generation circuit of the bit line voltage transmission circuit in an embodiment of the present invention;

[0083] Figure 4 This is a circuit diagram of the negative voltage signal generation circuit of the bit line voltage transmission circuit in an embodiment of the present invention;

[0084] Figure 5 This is a circuit diagram of the charge pump in the negative voltage signal generation circuit of the bit line voltage transmission circuit according to an embodiment of the present invention;

[0085] Figure 6 yes Figure 5 Timing diagrams of each node in the process;

[0086] Figure 7 This is a simulation diagram of the first positive voltage and the first negative voltage of the bit line voltage transmission circuit according to an embodiment of the present invention. Detailed Implementation

[0087] like Figure 2 The diagram shown is a circuit diagram of the transmission gate 201 of the bit line voltage transmission circuit according to an embodiment of the present invention; the bit line voltage transmission circuit according to an embodiment of the present invention includes: transmission gate 201.

[0088] The transmission gate 201 is connected between the IO node and the selection line BL. Figure 2 In this context, the IO nodes are directly represented using IO.

[0089] The transmission gate 201 includes a first NMOS transistor NM1 and a first PMOS transistor PM1.

[0090] The drain of the first NMOS transistor NM1 and the source of the first PMOS transistor PM1 are connected to the IO node.

[0091] The source of the first NMOS transistor NM1 and the drain of the first PMOS transistor PM1 are connected to the selected positioning line BL.

[0092] The gate of the first NMOS transistor NM1 is connected to a first control signal, the gate of the first PMOS transistor PM1 is connected to a second control signal, and the pad electrode of the first PMOS transistor PM1 is connected to a third control signal.

[0093] When the first control signal is the power supply voltage VDD, the second control signal is the first negative voltage VNEG, and the third control signal is the first positive voltage VDDA, the transmission gate 201 is in the on state, and the IO voltage of the IO node is transmitted to the selected bit line BL to form the bit line BL voltage. Figure 2The image shows the specific signals of the three control signals of the transmission gate 201 in the on state, and directly uses VDD to represent the first control signal, VNEG to represent the second control signal, and VDDA to represent the third control signal.

[0094] The first positive voltage VDDA is greater than or equal to the IO voltage of the IO node and less than the power supply voltage VDD. The first positive voltage VDDA is provided by the positive voltage signal generation circuit.

[0095] The first negative voltage VNEG is less than or equal to the difference between the minimum value of the IO voltage and the absolute value of the first threshold voltage of the first PMOS transistor PM1.

[0096] like Figure 3 The diagram shown is a circuit diagram of the positive voltage signal generation circuit of the bit line voltage transmission circuit according to an embodiment of the present invention; the positive voltage signal generation circuit includes: a second NMOS transistor NM2, a third NMOS transistor NM3, and a second PMOS transistor PM2.

[0097] The gate of the second NMOS transistor NM2 and the drain of the third NMOS transistor NM3 are both connected to the first node C.

[0098] The source of the second NMOS transistor NM2 and the gate of the third NMOS transistor NM3 are both connected to the second node, which serves as the output terminal of the first positive voltage VDDA.

[0099] The source of the third NMOS transistor NM3 is connected to the source of the second PMOS transistor PM2, and the drain of the second PMOS transistor PM2 is grounded to GND.

[0100] A first pull-up circuit is formed between the first node C and the power supply voltage VDD.

[0101] The first control terminal of the first pull-up circuit and the gate of the second PMOS transistor PM2 are both connected to the first enable signal EN.

[0102] The second NMOS transistor NM2 and the third NMOS transistor NM3 form a first negative feedback loop between the voltages of the first node C and the second node, and stabilize the first positive voltage VDDA.

[0103] When the first enable signal EN is low, both the first pull-up circuit and the second PMOS transistor PM2 are turned on. The series connection of the second PMOS transistor PM2 and the third NMOS transistor NM3 stabilizes the first positive voltage VDDA between the difference between the power supply voltage VDD and the second threshold voltage, and the sum of the absolute values ​​of the second threshold voltage and the third threshold voltage. The second threshold voltage is the threshold voltage of the second NMOS transistor NM2, the third threshold voltage is the threshold voltage of the second PMOS transistor PM2, and the threshold voltage of the third NMOS transistor NM3 is equal to the threshold voltage of the second NMOS transistor NM2.

[0104] In this embodiment of the invention, the second NMOS transistor NM2 is an intrinsic NMOS transistor, and the third NMOS transistor NM3 is an intrinsic NMOS transistor. The threshold voltage of the intrinsic NMOS transistor is relatively small, for example, below 150mV.

[0105] In this embodiment of the invention, the first pull-up circuit includes: a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, and an eighth PMOS transistor PM8.

[0106] The source of the sixth PMOS transistor PM6 is connected to the power supply voltage VDD.

[0107] The drain of the sixth PMOS transistor PM6, the source of the seventh PMOS transistor PM7, and the source of the eighth PMOS transistor PM8 are connected together.

[0108] The gate of the seventh PMOS transistor PM7 is connected to the first enable signal EN.

[0109] The drain of the seventh PMOS transistor PM7, the gate of the eighth PMOS transistor PM8, and the drain of the eighth PMOS transistor PM8 are connected to the first node C.

[0110] The positive pressure signal generation circuit also includes:

[0111] The ninth PMOS transistor PM9 has its source connected to the power supply voltage VDD, its drain connected to the drain of the second NMOS transistor NM2, and its gate grounded to GND.

[0112] The tenth PMOS transistor PM10 has its source connected to the power supply voltage VDD. The drain of the ninth PMOS transistor PM9 is connected to the second node. The gate of the ninth PMOS transistor PM9 is connected to the first enable inverted signal ENb, which is the inverted signal of the first enable signal EN. The first enable signal EN is input to the input terminal of an inverter, and the first enable inverted signal ENb can be obtained at the output terminal of the inverter.

[0113] The positive voltage signal generation circuit also includes: the eleventh PMOS transistor PM11, the seventh NMOS transistor NM7, and the eighth NMOS transistor NM8.

[0114] The source of the eleventh PMOS transistor PM11 and the drain of the seventh NMOS transistor NM7 are both connected to the second node.

[0115] The drain of the eleventh PMOS transistor PM11 and the source of the seventh NMOS transistor NM7 are both connected to the drain of the eighth NMOS transistor NM8.

[0116] The source of the eighth NMOS transistor NM8 is grounded to GND.

[0117] The gate of the eleventh PMOS transistor PM11 is connected to the first enable signal EN, and the gate of the seventh NMOS transistor NM7 is connected to the first enable inverted signal ENb, wherein the first enable inverted signal ENb is the inverted signal of the first enable signal EN.

[0118] The gate connection current control signal Ic of the eighth NMOS transistor NM8.

[0119] In this embodiment of the invention, the first negative pressure VNEG is provided by a negative pressure signal generation circuit. For example... Figure 4 The diagram shown is a circuit diagram of the negative voltage signal generation circuit of the bit line voltage transmission circuit according to an embodiment of the present invention; the negative voltage signal generation circuit includes: a charge pump 202, a voltage divider circuit 203 and a comparator 204.

[0120] The first negative pressure VNEG is output from the output terminal of the charge pump 202.

[0121] The power supply terminal of the charge pump 202 is connected to the power supply voltage VDD, and the maximum negative voltage that the output terminal of the charge pump 202 can generate is the negative value of the power supply voltage VDD, i.e., -VDD.

[0122] The voltage divider circuit 203 is connected between the power supply voltage VDD and the first negative voltage VNEG.

[0123] The voltage divider circuit 203 provides the first voltage division. Figure 4In this process, the first voltage divider is output by node Z.

[0124] The first voltage divider is connected to the first input terminal of the comparator 204, and the second input terminal of the comparator 204 is grounded to GND. Figure 4 In this circuit, the first input terminal of the comparator 204 is the + input terminal, and the second input terminal of the comparator 204 is the - input terminal.

[0125] The output of the comparator 204 outputs a first feedback signal to the clock signal control terminal of the charge pump 202.

[0126] The clock input terminal of the charge pump 202 is connected to the clock input signal CLK. The clock input signal CLK is input to the charge pump 202 under the control of the first feedback signal, thereby controlling the magnitude of the first negative pressure VNEG.

[0127] The first feedback signal controls the timing of the clock input signal CLK being input into the charge pump 202 based on the magnitude of the first voltage divider, thereby controlling the magnitude of the first negative voltage VNEG.

[0128] The voltage divider circuit 203 includes a first resistor R1 and a second resistor R2.

[0129] The first terminal of the first resistor R1 is connected to the power supply voltage VDD.

[0130] The second end of the first resistor R1 and the first end of the second resistor R2 are connected together and serve as the output terminal of the first voltage divider, i.e., node Z.

[0131] The second end of the second resistor R2 is connected to the output end of the charge pump 202.

[0132] The absolute value of the ratio of the first negative voltage VNEG to the power supply voltage VDD is the ratio of the second resistor R2 to the first resistor R1. The first negative voltage VNEG is adjusted by adjusting the ratio of the second resistor R2 to the first resistor R1.

[0133] A fifth PMOS transistor PM5 is also connected between the first terminal of the first resistor R1 and the power supply voltage VDD. The source of the fifth PMOS transistor PM5 is connected to the power supply voltage VDD, and the drain of the fifth PMOS transistor PM5 is connected to the first terminal of the first resistor R1.

[0134] The gate of the fifth PMOS transistor PM5 is connected to the first enable signal EN.

[0135] A decoupling capacitor C101 is also connected between the output terminal of the charge pump 202 and ground.

[0136] The negative pressure signal generation circuit also includes a first inverter 205.

[0137] The input terminal of the first inverter 205 is connected to the first feedback signal, and the output terminal of the first inverter 205, i.e. node FB, outputs the second feedback signal. The second feedback signal is output to the clock signal control terminal of the charge pump 202.

[0138] Figure 4 In this context, the charge pump 202 is also represented as pump_N0P4.

[0139] like Figure 5 The diagram shown is a circuit diagram of the charge pump 202 of the negative voltage signal generation circuit of the bit line voltage transmission circuit in an embodiment of the present invention. In this embodiment of the present invention, the charge pump 202 includes a symmetrical first subunit 202a and a second subunit 202b.

[0140] The first subunit 202a and the second subunit 202b have the same first circuit structure, the difference between them is that the signals they are connected to are different.

[0141] The following is based on Figure 5 The structure of the first sub-unit 202a shown illustrates the first circuit structure, which includes: pump capacitor C1, fourth NMOS transistor NM4, fifth NMOS transistor NM5, sixth NMOS transistor NM6, third PMOS transistor PM3, and fourth PMOS transistor PM4.

[0142] The first terminal of the pump capacitor C1 is connected to the first clock signal, and the second terminal of the pump capacitor C1 is the first internal node B1.

[0143] The source of the fourth NMOS transistor NM4, the drain of the fifth NMOS transistor NM5, and the drain of the sixth NMOS transistor NM6 are all connected to the first internal node B1.

[0144] The drain of the fourth NMOS transistor NM4, the gate of the fifth NMOS transistor NM5, and the drain of the fourth PMOS transistor PM4 are all connected to the second internal node A1.

[0145] The source of the fifth NMOS transistor NM5 and the gate of the fourth PMOS transistor PM4 are both grounded to GND.

[0146] The drain of the third PMOS transistor PM3 and the source of the fourth PMOS transistor PM4 are connected.

[0147] The source of the third PMOS transistor PM3 is connected to the power supply voltage VDD.

[0148] The gates of the third PMOS transistor PM3 and the fourth NMOS transistor NM4 are both connected to the inverted signal of the first clock signal.

[0149] The gate of the sixth NMOS transistor NM6 is connected to the inverted signal of the first internal node B1.

[0150] The source of the sixth NMOS transistor NM6 outputs the first negative voltage VNEG.

[0151] Figure 5 In the second sub-unit 202b, the fourth NMOS transistor is individually labeled NM4a, the fifth NMOS transistor is individually labeled NM5a, the sixth NMOS transistor is individually labeled NM6a, the third PMOS transistor is individually labeled PM3a, and the fourth PMOS transistor is individually labeled PM4a.

[0152] The first internal node in the second subunit 202b is labeled B2, and the second internal node is labeled A1. Based on the above labeling, the connection relationship between the first subunit 202a and the second subunit 202b is further explained as follows:

[0153] In the charge pump 202, the connection relationship between the first subunit 202a and the second subunit 202b is as follows:

[0154] The first clock signal of the first subunit 202a adopts the internal clock inverted signal CKb, and the first clock signal of the second subunit 202b adopts the internal clock signal CK. The internal clock signal CK and the internal clock inverted signal CKb are inverted and are both formed by the clock input signal CLK.

[0155] The first internal node B1 of the first sub-unit 202a is connected to the gate of the sixth NMOS transistor NM6 of the second sub-unit 202b; the first internal node B1 of the second sub-unit 202b is connected to the gate of the sixth NMOS transistor NM6 of the first sub-unit 202a.

[0156] In this embodiment of the invention, the selected bit line BL is the bit line BL selected from a plurality of bit lines BL of the memory array by means of a column address signal.

[0157] The storage array is composed of multiple storage cells arranged together.

[0158] The storage unit includes a selected-gate shared-gate flash memory unit. Please refer to [reference needed] for the structure of the selected-gate shared-gate flash memory unit. Figure 1 As shown. Further details will not be provided here.

[0159] The IO node is a node connected to the sensitive amplifier and the bit line BL, and the IO voltage is generated by the sensitive amplifier.

[0160] In this embodiment of the invention, the voltages of the substrate electrode and gate of the first PMOS transistor PM1 are specially configured when the transmission gate 201 of the bit line voltage transmission circuit is turned on. The voltage of the substrate electrode of the first PMOS transistor PM1 is a first positive voltage VDDA, and the gate voltage is a first negative voltage VNEG. The first positive voltage VDDA is provided by a positive voltage signal generation circuit. The second NMOS transistor NM2 and the third NMOS transistor NM3 in the positive voltage signal generation circuit are connected to form a first negative feedback loop structure. The second NMOS transistor NM2 enables the voltage of the second node to change in phase with the voltage of the first node C and makes the voltage of the second node smaller than the voltage of the first node C by the threshold voltage of the second NMOS transistor NM2, i.e., the second threshold voltage. The third NMOS transistor NM3 enables the voltage of the first node C to change in opposite phase with the voltage of the second node, and finally enables the potentials of the first node C and the second node to reach stability. By setting the second PMOS transistor PM2 and the third NMOS transistor NM3 in a series structure with their sources connected, the voltage of the second node can be made greater than that of the first NMOS transistor NM2. The gate voltage of the second PMOS transistor PM2, plus the absolute value of the threshold voltage of the second PMOS transistor (i.e., the third threshold voltage) and the second threshold voltage, ultimately stabilizes the first positive voltage VDDA between the difference between the power supply voltage VDD and the second threshold voltage, and the sum of the absolute values ​​of the second and third threshold voltages. Therefore, in this embodiment of the invention, the first positive voltage VDDA ensures that the substrate electrode voltage of the first PMOS transistor PM1 remains small when it is turned on, provided that it is greater than or equal to the IO voltage. Simultaneously, combined with the setting of the first negative voltage VNEG, the first PMOS transistor PM1 maintains optimal conduction conditions. This allows the voltage drop across the transmission gate 201 (i.e., the IO voltage to the voltage drop across the bit line BL) to remain low even when the cell current on the bit line BL is large. Therefore, this invention provides a precise control voltage for the PMOS transistor of the transmission gate 201, and maintains a low voltage drop across the transmission gate 201 (i.e., the IO voltage to the voltage drop across the bit line BL) even when the cell current on the bit line BL is large, thereby increasing read accuracy and improving the reliability of the flash memory system.

[0161] This invention is particularly suitable for reading memory cells when the power supply voltage VDD is continuously decreasing and the current required to read the cell is large. This invention can maintain a large value of the bit line BL voltage by precisely controlling the voltage drop across the transmission gate 201 when the power supply voltage VDD is low, thereby preventing the current of the cell to be read from decreasing. This is beneficial for distinguishing memory cells with stored information of 0 and 1, and can especially enhance the distinction between memory cells with weak erase and weak program, preventing read errors.

[0162] The bit line voltage transmission circuit of this invention is based on a positive and negative voltage transmission structure, including positive and negative voltage generation circuits for bit line transmission. This bit line voltage transmission circuit can be used as a YMUX, ensuring that the positive and negative voltage YMUX maintains a small voltage drop even under large cell currents, further improving the accuracy of embedded flash memory reads and enhancing the reliability of the flash memory system. The working principle of each component of the bit line voltage transmission circuit of this invention is further explained below:

[0163] The working principle of the positive pressure signal generation circuit is as follows:

[0164] Combination Figure 3 As shown, NM2 and NM3 are intrinsic MOSFETs with relatively low threshold voltages, typically around 150mV. When the EN signal is 0, the circuit starts working, and point C is quickly pulled up to VDD. At this time, VDDA = VDD - V_THNZ, where V_THNZ is the threshold voltage of NM2. NM3 is then turned on. Due to the strong driving capability of NM3 and PM2, point C is pulled down, causing VDDA to decrease along with point C. NM2, NM3, and PM2 form a negative feedback structure, ultimately stabilizing VDDA at a potential of approximately 0.8V. The above directly uses... Figure 3 The corresponding markers in the diagram represent the corresponding transistors and nodes.

[0165] The working principle of the negative pressure signal generation circuit is as follows:

[0166] Figure 4 In this circuit, the negative voltage signal generation circuit mainly consists of PUMP_N0P4 and a feedback control circuit. PUMP_N0P4 can generate a minimum voltage of -VDD. When the node Z potential is below 0V, the output signal of comparator 204, i.e., the signal of node FB, causes PUMP_N0P4 to stop working; when the node Z potential is above 0V, PUMP_N0P4 starts working. VNEG = -R2 / R1*VDD. Since the node G corresponding to the first negative voltage VNEG is connected to a large external capacitor C101, VNEG can be stabilized at the set value. For example, when VDD = 1.1V, R2 / R1 = 0.36, and a VNEG signal of approximately -0.4V can be obtained. Above, PUMP_N0P4 is directly used to represent the charge pump 202, and each signal or node is also directly represented by its corresponding mark.

[0167] The working principle of the VNEG signal generation circuit, i.e., the charge pump, is as follows:

[0168] like Figure 6 As shown, is Figure 5 Timing diagrams of each node; taking the first subunit 202a as an example for explanation and in conjunction with... Figure 5 and Figure 6As shown, CK and CKb are the clock signals with amplitudes VDD and GND, respectively. When CK is GND, PM3 is on, PM4 is normally on, A1 is pulled up to VDD, NM5 is on, and B1 is pulled down to GND. When CK is VDD, PM3 is off, the path from A1 to VDD is cut off, NM4 is on, and the potentials of A1 and B1 are consistent. At this time, CKb jumps from VDD to GND. Based on the law of conservation of capacitance charge, B1 jumps to -VDD, and A1 follows B1 to -VDD. NM5 is off, the path from B1 to GND is cut off, and at the same time, B2 is pulled down to GND. Therefore, NM4 conducts. Due to the very large decoupling capacitor connected to VNEG, plus the influence of the external modulation circuit, the potentials of A1, B1, and VNEG are finally consistent, close to the design value of -0.4V. The corresponding transistors or nodes are directly represented by corresponding labels above. Figure 6 In the diagram, the nodes corresponding to each curve are marked on the left side of the curve.

[0169] like Figure 7 The diagram shown is a simulation of the first positive voltage and the first negative voltage of the bit line voltage transmission circuit according to an embodiment of the present invention. Figure 7 In the simulation, the nodes corresponding to each curve are marked on the left side of the curve. It can be seen that when the EN signal is low, VDDA will stabilize at about 0.83V after feedback, and VNEG will reach the design value of about -0.4V after multiple pumps, as shown by the values ​​of VDDA and VNEG at line AA.

[0170] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A bit line voltage transfer circuit, characterized by, The application relates to a transmission gate, which comprises: a transmission gate; the transmission gate is connected between an IO node and a selected bit line; the transmission gate comprises a first NMOS transistor and a first PMOS transistor; the drain of the first NMOS transistor and the source of the first PMOS transistor are connected to the IO node; the source of the first NMOS transistor and the drain of the first PMOS transistor are connected to the selected bit line; the gate of the first NMOS transistor is connected to a first control signal, the gate of the first PMOS transistor is connected to a second control signal, and the back electrode of the first PMOS transistor is connected to a third control signal; when the first control signal is a power voltage, the second control signal is a first negative voltage, and the third control signal is a first positive voltage, the transmission gate is in a conducting state, and an IO voltage of the IO node is transmitted to the selected bit line to form a bit line voltage; the first positive voltage is greater than or equal to the IO voltage of the IO node and smaller than the power voltage, and the first positive voltage is provided by a positive voltage signal generation circuit; the first negative voltage is smaller than the difference between the minimum value of the IO voltage and the absolute value of a first threshold voltage of the first PMOS transistor; the positive voltage signal generation circuit comprises a second NMOS transistor, a third NMOS transistor and a second PMOS transistor; the gate of the second NMOS transistor and the drain of the third NMOS transistor are both connected to a first node; the source of the second NMOS transistor and the gate of the third NMOS transistor are both connected to a second node, and the second node serves as an output end of the first positive voltage; the source of the third NMOS transistor is connected to the source of the second PMOS transistor, and the drain of the second PMOS transistor is grounded; a first pull-up circuit is formed between the first node and the power voltage; the first control end of the first pull-up circuit and the gate of the second PMOS transistor are both connected to a first enable signal; the second NMOS transistor and the third NMOS transistor form a first negative feedback loop between the voltages of the first node and the second node and stabilize the first positive voltage; when the first enable signal is at a low level, the first pull-up circuit and the second PMOS transistor are both turned on; the series structure of the second PMOS transistor and the third NMOS transistor stabilizes the first positive voltage between the difference between the power voltage and a second threshold voltage and the sum of the absolute value of the second threshold voltage and a third threshold voltage, the second threshold voltage is the threshold voltage of the second NMOS transistor, the third threshold voltage is the threshold voltage of the second PMOS transistor, and the threshold voltage of the third NMOS transistor is equal to the threshold voltage of the second NMOS transistor.

2. The bit line voltage transfer circuit of claim 1, wherein: the first negative voltage is provided by a negative voltage signal generation circuit, and the negative voltage signal generation circuit comprises a charge pump, a voltage dividing circuit and a comparator; the output end of the charge pump outputs the first negative voltage; the power end of the charge pump is connected to the power voltage, and the maximum negative voltage that can be generated by the output end of the charge pump is the negative value of the power voltage; the voltage dividing circuit is connected between the power voltage and the first negative voltage; the voltage dividing circuit provides a first voltage division; The first voltage divider is connected to a first input of the comparator, and a second input of the comparator is grounded; An output of the comparator outputs a first feedback signal to a clock signal control end of the charge pump; A clock input end of the charge pump is connected to a clock input signal, which is input to the charge pump under control of the first feedback signal and thereby controls the size of the first negative voltage; The first feedback signal controls the time of the clock input signal input to the charge pump and thereby controls the size of the first negative voltage according to the size of the first voltage divider.

3. The bit line voltage transfer circuit of claim 2, wherein: The charge pump comprises a symmetric first subunit and a second subunit; The first subunit and the second subunit have the same first circuit structure; The first circuit structure comprises a pump capacitor, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a third PMOS tube and a fourth PMOS tube; A first end of the pump capacitor is connected to a first clock signal, and a second end of the pump capacitor is a first internal node; The source of the fourth NMOS tube, the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are all connected to the first internal node; The drain of the fourth NMOS tube, the gate of the fifth NMOS tube and the drain of the fourth PMOS tube are all connected to a second internal node; The source of the fifth NMOS tube and the gate of the fourth PMOS tube are grounded; The drain of the third PMOS tube and the source of the fourth PMOS tube are connected; The source of the third PMOS tube is connected to the power supply voltage; The gate of the third PMOS tube and the gate of the fourth NMOS tube are both connected to an inverted signal of the first clock signal; The gate of the sixth NMOS tube is connected to an inverted signal of the first internal node; The source of the sixth NMOS tube outputs the first negative voltage; In the charge pump, the connection relationship of the first subunit and the second subunit is: The first clock signal of the first subunit adopts an internal clock inverted signal, and the first clock signal of the second subunit adopts an internal clock signal, the internal clock signal and the internal clock inverted signal are mutually inverted and are both formed by the clock input signal; The first internal node of the first subunit is connected to the gate of the sixth NMOS tube of the second subunit, and the first internal node of the second subunit is connected to the gate of the sixth NMOS tube of the first subunit.

4. The bit line voltage transfer circuit of claim 3, wherein: The voltage divider circuit comprises a first resistor and a second resistor; A first end of the first resistor is connected to the power supply voltage; A second end of the first resistor and a first end of the second resistor are connected together and serve as an output end of the first voltage divider; A second end of the second resistor is connected to an output end of the charge pump; The absolute value of the ratio of the first negative voltage to the power supply voltage is the ratio of the second resistor to the first resistor, and the first negative voltage is adjusted by adjusting the ratio of the second resistor to the first resistor.

5. The bit line voltage transfer circuit of claim 4, wherein: A fifth PMOS transistor is further connected between the first end of the first resistor and the power voltage, with the source of the fifth PMOS transistor connected to the power voltage and the drain of the fifth PMOS transistor connected to the first end of the first resistor. The gate of the fifth PMOS transistor is connected to the first enable signal.

6. The bit line voltage transfer circuit of claim 4, wherein: A decoupling capacitor is further connected between the output of the charge pump and the ground.

7. The bit line voltage transfer circuit of claim 2, wherein: The negative voltage signal generation circuit further comprises a first inverter. The input of the first inverter is connected to the first feedback signal, and the output of the first inverter outputs a second feedback signal, which is output to the clock signal control end of the charge pump.

8. The bit line voltage transfer circuit of claim 1, wherein: The first pull-up circuit comprises a sixth PMOS transistor, a seventh PMOS transistor and an eighth PMOS transistor. The source of the sixth PMOS transistor is connected to the power voltage. The drain of the sixth PMOS transistor, the source of the seventh PMOS transistor and the source of the eighth PMOS transistor are connected together. The gate of the seventh PMOS transistor is connected to the first enable signal. The drain of the seventh PMOS transistor, the gate of the eighth PMOS transistor and the drain of the eighth PMOS transistor are connected to the first node.

9. The bit line voltage transfer circuit of claim 8, wherein: The positive voltage signal generation circuit further comprises: A ninth PMOS transistor, with the source of the ninth PMOS transistor connected to the power voltage, the drain of the ninth PMOS transistor connected to the drain of the second NMOS transistor, and the gate of the ninth PMOS transistor grounded.

10. The bit line voltage transfer circuit of claim 8, wherein: The positive voltage signal generation circuit further comprises: A tenth PMOS transistor, with the source of the tenth PMOS transistor connected to the power voltage, the drain of the tenth PMOS transistor connected to the second node, and the gate of the tenth PMOS transistor connected to a first enable inverse signal, which is the inverse signal of the first enable signal.

11. The bit line voltage transfer circuit of claim 8, wherein: The positive voltage signal generation circuit further comprises an eleventh PMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor. The source of the eleventh PMOS transistor and the drain of the seventh NMOS transistor are both connected to the second node. The drain of the eleventh PMOS transistor and the source of the seventh NMOS transistor are both connected to the drain of the eighth NMOS transistor. The source of the eighth NMOS transistor is grounded. The gate of the eleventh PMOS transistor is connected to the first enable signal, and the gate of the seventh NMOS transistor is connected to a first enable inverse signal, which is the inverse signal of the first enable signal. The gate of the eighth NMOS transistor is connected to a current control signal.

12. The bit line voltage transfer circuit of claim 1, wherein: The selected bit line is the bit line selected from a plurality of bit lines of a memory array by a column address signal. The memory array is arranged by a plurality of memory cells.

13. The bit line voltage transfer circuit of claim 12, wherein: The memory cell comprises a select gate shared split-gate flash memory cell.

14. The bit line voltage transfer circuit of claim 13, wherein: The IO node is a node connected by a sense amplifier and the bit line, and the IO voltage is generated by the sense amplifier.

15. The bit line voltage transfer circuit of claim 13, wherein: The second NMOS transistor is an intrinsic NMOS transistor, and the third NMOS transistor is an intrinsic NMOS transistor.

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