Semiconductor device and manufacturing method thereof
By using nitrogen oxide material as a blocking layer during the semiconductor device manufacturing process, it is covered on the oxidation layer of the polysilicon structure and the side wall structure, which solves the problem of being susceptible to wetting and erosion of the side wall structure, and realized the effective protection of the side wall structure The effect of the device has improved the performance of the high temperature working life of the device.
Patent Information
- Application Number
- CN202310913065.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-24
- Publication Date
- 2025-01-28
AI Technical Summary
During the manufacturing process of semiconductor devices, the sidewall structure of the polycrystalline silicon structure is susceptible to wet cleaning due to the exposed oxide layer, resulting in bird beak defects, affecting the high-temperature working life test performance of the device.
The nitrogen oxide material is used as the blocking layer, covering the oxidation layer of the polysilicon structure and the side wall structure, and forming a window through the drying and wetting method to ensure that the blocking layer is fully covered with the side wall structure to prevent the wet etching from etching. erosion.
Effectively protect the corrosion of the side wall structure from the erosion of the wet etching, avoid the defect of the beak, and improve the high -temperature work life test performance of semiconductor devices.
Smart Images
Figure CN119381244A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] With the continuous development of integrated circuit process technology, in order to improve the integration of integrated circuits, while increasing the operating speed of devices and reducing their power consumption, the characteristic size of semiconductor processes continues to shrink, and the size of the gate, source and drain active areas of transistors will also shrink accordingly, and their equivalent series resistance will increase accordingly, thus affecting the speed of the circuit. In order to improve the equivalent series resistance of the source and drain active areas of transistors and the contact resistance of contact holes, metal silicide (Salicide) process technology has been developed. The metal silicide process technology not only forms metal silicide on the polysilicon gate, but also forms metal silicide in the source and drain active areas. It also improves the equivalent series resistance of the gate, source and drain active areas of the transistor and the contact resistance of the contact holes. Due to the change in the height of the two sides of the polysilicon, when the height of the sidewall structure on both sides of the polysilicon is too large, the oxide layer on the sidewall structure will be partially exposed and eroded by the wet cleaning containing hydrofluoric acid (HF), resulting in bird's beak defects in the sidewall structure, such as Figure 1 A bird's beak defect occurs at the position indicated by the middle circle, which affects the high temperature operating life test (HTOL) performance of the semiconductor device. Summary of the invention
[0003] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which adopts SION material as a barrier layer. Since the barrier layer of SION material can adhere to the sidewall structure well, it can effectively protect the surface of the sidewall structure, so that the sidewall structure is protected from being etched by the wet etching process, thereby avoiding bird beak defects.
[0004] In a first aspect, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, on which a polycrystalline silicon structure and sidewall structures located on both sides of the polycrystalline silicon structure are formed, and an oxide layer is formed on the sidewall structure; forming a barrier layer on the semiconductor substrate, the barrier layer covering the polycrystalline silicon structure and the oxide layer on the sidewall structure, the material of the barrier layer being silicon oxynitride; removing the barrier layer on the top of the polycrystalline silicon structure by sequentially performing dry etching and wet etching to form a window exposing the top of the polycrystalline silicon structure, the opening width of the window being less than or equal to the width of the polycrystalline silicon structure; forming a self-aligned silicide on the window, the self-aligned silicide covering the exposed polycrystalline silicon structure.
[0005] The method provided by the present invention has the following beneficial effects: on the one hand, a barrier layer of SION material is used to protect the sidewall structure. Since the barrier layer of SION material can be well adhered to the sidewall structure, the oxide layer inside the sidewall structure can be effectively protected, so that the sidewall structure is protected from being etched by the wet etching process. At the same time, due to good adhesion, the barrier layer is also tightly bonded to the sidewall structure during the formation of metal silicide, reducing the probability of being opened and avoiding the formation of a bird's beak structure. On the other hand, by limiting the opening width of the window to be less than or equal to the width of the polysilicon structure, it is ensured that the barrier layer can still completely cover the sidewall structure, and the erosion of the oxide layer and the silicon oxynitride layer on the top of the sidewall structure by wet etching is reduced.
[0006] In a possible embodiment, the barrier layer on the top of the polysilicon structure is removed by sequentially performing dry etching and wet etching to form a window exposing the top of the polysilicon structure, including the following process steps: forming a photoresist layer covering the barrier layer on the semiconductor substrate; etching the photoresist layer to form a desired pattern through exposure and development processes; using the patterned photoresist layer as a mask, removing most of the thickness of the barrier layer located on the top of the polysilicon structure through dry etching to form a pre-window; removing the remaining barrier layer on the top of the polysilicon structure through wet etching to form a window that completely exposes the top of the polysilicon structure, and the remaining barrier layer still completely covers the sidewall structure; removing the remaining photoresist. This embodiment can achieve the purpose of accurately etching the window by first removing most of the barrier layer by dry etching and then removing the remaining barrier layer by wet etching.
[0007] In another possible embodiment, self-aligned silicide is formed on the window, including the following process steps: depositing a metal material on the semiconductor substrate to form a metal layer; using an annealing process and an etching process to make the metal material react with the silicon in the semiconductor substrate and the polysilicon structure respectively to form a self-aligned silicide on the window.
[0008] In another possible embodiment, after the pre-window is obtained by dry etching, the thickness of the barrier layer remaining on the top of the polysilicon structure is H, and the vertical shortest distance from the vertical single-side edge of the opening of the pre-window to the sidewall structure on that side is D, wherein H is less than or equal to D. This embodiment is used to ensure that after etching on both sides, the vertical side edge of the window can always cover the top of the sidewall structure on both sides of the polysilicon, play a role in protecting the sidewall structure, and do not form a bird's beak in the top area of the sidewall structure.
[0009] In another possible embodiment, the opening width of the window is W, wherein D is 1% to 10% of W. The purpose of this requirement is that when the remaining thickness H of the barrier layer on the top of the polysilicon structure is completely etched away, D' is consumed outward in D on the side of the pre-window to ensure the relationship between D and W, so that after D' is consumed, the size of the window will not be too small, that is, the window can expose the top of the polysilicon structure as much as possible while achieving the covering effect. Because after the second etching (wet etching), if the opening W of the window formed is too small, the area of the metal silicide formed on the top of the polysilicon structure will be reduced, which will further lead to a large contact resistance of the device, affecting the device performance, so it is necessary to ensure that W is as large as possible after two etchings.
[0010] In another possible embodiment, after the pre-window is obtained by dry etching, the vertical shortest distance from the vertical single-side edge of the opening of the pre-window to the sidewall structure on the side is D, and the opening width of the window is W, wherein D is 1% to 10% of W. In this embodiment, when the remaining thickness of the barrier layer on the top of the polysilicon is completely etched away, the side edge of the pre-window is partially consumed outward, and the entire width D of the window is presented, ensuring that the relationship between D and W is 1% to 10%, so that the window is not too small, that is, D cannot be too large relative to W, that is, the window can expose as much polysilicon as possible while achieving the covering effect, so as to form more metal silicide and reduce the contact resistance of the device.
[0011] In another possible embodiment, the self-aligned silicide is nickel silicide or cobalt silicide.
[0012] In other possible embodiments, the metal layer includes nickel, platinum, titanium, nickel or cobalt, or a combination of several metals.
[0013] In another possible embodiment, the sidewall structure includes a combination of at least one oxide layer and one silicon nitride layer alternately arranged from inside to outside, wherein the inner side of the sidewall structure is a side adjacent to the polysilicon structure, and the innermost side of the sidewall structure 400 is the oxide layer.
[0014] In the second aspect, the present invention provides a semiconductor device, comprising: a semiconductor substrate; a polysilicon structure located on the surface of the semiconductor substrate, a self-aligned silicide located on the surface of the polysilicon structure; a sidewall structure located on both sides of the stacked structure formed by the self-aligned silicide and the gate layer, the sidewall structure is completely covered with a barrier layer, and the material of the barrier layer is silicon oxynitride; a gate channel layer located in the semiconductor substrate; a source electrode located in the semiconductor substrate and located on one side of the gate channel layer; a drain electrode located in the semiconductor substrate and located on the side of the gate channel layer away from the source electrode; the gate channel layer, the source electrode and the drain electrode have the same ion doping type, and the self-aligned silicide is located at the source electrode, the drain electrode and the gate electrode. The specific beneficial effects can be referred to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A schematic diagram of a side wall structure with a bird beak defect provided in the prior art;
[0016] Figure 2 A schematic cross-sectional structure diagram of a semiconductor device provided by the present invention;
[0017] Figure 3 A flowchart of a method for manufacturing a semiconductor device provided by the present invention;
[0018] 4A to 4D It is a schematic diagram of the intermediate structure cross-section of each process preparation stage provided by the present invention.
[0019] Description of figure markings:
[0020] Semiconductor substrate 100; polysilicon structure 200; salicide 300; sidewall structure 400;
[0021] Blocking layer 500 ; insulating layer 201 ; gate layer 202 . DETAILED DESCRIPTION
[0022] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.
[0023] Figure 2 The cross-sectional structure diagram of a semiconductor device provided by the present invention is shown, comprising: a semiconductor substrate 100, a polysilicon structure 200 located on the surface of the semiconductor substrate, a self-aligned silicide 300 located on the surface of the polysilicon structure 200; a sidewall structure 400 located on opposite sides of the stacked structure composed of the self-aligned silicide and the polysilicon structure 200, and a barrier layer 500 covering the surface of the sidewall structure 400. The polysilicon structure 200 may include an insulating layer 201 located on the surface of the semiconductor substrate and a gate layer 202 covering the insulating layer 201, and the sidewall structure 200 includes a combination of at least one oxide layer and one silicon nitride layer alternately arranged from the inside to the outside, in some embodiments, there may be two oxide layers with a silicon nitride layer in between, or four layers, namely a silicon nitride layer, an oxide layer, a silicon nitride layer, and an oxide layer; or more layers alternately arranged in this way, wherein the inner side of the sidewall structure 400 is a side adjacent to the polysilicon structure 200, and the innermost side of the sidewall structure 400 is an oxide layer.
[0024] Among them, the gate channel layer is located in the semiconductor substrate; the source is located in the semiconductor substrate and on one side of the gate channel layer; the drain is located in the semiconductor substrate and on the side of the gate channel layer away from the source; the gate channel layer, the source and the drain have the same ion doping type, and the self-aligned silicide is located at the source, the drain and the gate.
[0025] The formation process of the semiconductor device is described below in conjunction with the manufacturing process of the semiconductor device. Figure 3 A schematic diagram of a method for manufacturing a semiconductor device is shown. 4A to 4D Schematic diagrams of the intermediate structure cross-sections of each process preparation stage in this example are shown respectively.
[0026] See also Figure 3 The method for manufacturing a semiconductor device provided by an embodiment of the present invention comprises the following steps:
[0027] S301 , providing a semiconductor substrate 100 , on which a polysilicon structure 200 and sidewall structures 400 located on both sides of the polysilicon structure are formed.
[0028] For example, Figure 4AAs shown, the semiconductor substrate 100 may be an N-type or P-type silicon substrate. The material of the semiconductor substrate 100 includes one or more combinations of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The semiconductor substrate 100 may also be a silicon semiconductor substrate on an insulator or a germanium semiconductor substrate on an insulator. The polysilicon structure 200 located on the surface of the semiconductor substrate, and the sidewall structure 400 located on opposite sides of the stacked structure composed of the salicide and the polysilicon structure 200.
[0029] S302 , forming a barrier layer 500 on the polysilicon structure and the sidewall structure, wherein the barrier layer 500 covers the polysilicon structure 200 and the sidewall structure 400 , and the material of the barrier layer 500 is silicon oxynitride.
[0030] For example, Figure 4B As shown, a barrier layer 500 is deposited on the surface of the semiconductor substrate 100. The barrier layer 500 may be silicon oxynitride (SiON) with good adhesion and adhered to the upper surface of the sidewall structure, so it can effectively protect the surface of the sidewall structure, and can be used as a barrier layer for the self-aligned silicide barrier layer (SAB) process, and can also prevent the formation of a bird's beak on the top of the sidewall structure.
[0031] S303, removing the barrier layer 500 on the top of the polysilicon structure by sequentially performing dry etching and wet etching to form a window exposing the top of the polysilicon structure 200, wherein the opening width of the window is less than or equal to the width of the polysilicon structure.
[0032] like Figure 4CAs shown, the barrier layer 500 is subjected to photolithography and etching processes to form a window. Specifically, the process steps include: forming a photoresist layer covering the barrier layer 500 on the semiconductor substrate 100; etching the photoresist layer to form a desired pattern through exposure and development processes; using the patterned photoresist layer as a mask, removing most of the thickness of the barrier layer 500 located at the top of the polysilicon structure 200 through dry etching to form a pre-window; removing the remaining thickness of the barrier layer 500 at the top of the polysilicon structure 200 through wet etching. In this embodiment, the thickness of the barrier layer remaining at the top of the polysilicon structure is H, and the vertical shortest distance from the vertical single-side side edge of the opening of the pre-window to the sidewall structure on that side is D, wherein H is less than or equal to D, so as to ensure that after etching on both sides, the vertical side edge of the window can always cover the top of the sidewall structure on both sides of the polysilicon, play a role in protecting the sidewall structure, and not form a bird's beak in the top area of the sidewall structure. Finally, a window W is formed to expose the top of the polysilicon structure, wherein D is 1% to 10% of W, and then the remaining photoresist is removed. The purpose of this requirement is that when the remaining thickness H of the barrier layer on the top of the polysilicon structure is completely etched away, D' is consumed outward in the D on the side of the pre-window, ensuring the relationship between D and W, so that after D' is consumed, the size of the window W will not be too small, that is, the window can expose the top of the polysilicon structure as much as possible while achieving the covering effect. Because after the second etching (wet etching), if the opening W of the window formed is too small, the area of the metal silicide formed on the top of the polysilicon structure will be reduced, which will further lead to a large contact resistance of the device, affecting the device performance, so it is necessary to ensure that W is as large as possible after two etchings.
[0033] In a possible embodiment, after the pre-window is obtained by dry etching, the vertical shortest distance from the vertical single-side edge of the opening of the pre-window to the sidewall structure on that side is D, and the opening width of the window is W, wherein D is 1% to 10% of W. The effect of this is that when the remaining thickness of the barrier layer on the top of the polysilicon is completely etched away, the side edge of the pre-window is partially consumed outward, and the entire width D of the window is presented, ensuring that the relationship between D and W is 1% to 10%, so that the window is not too small, that is, D cannot be too large relative to W, that is, the window can expose as much polysilicon as possible while achieving the covering effect, so as to form more metal silicide and reduce the contact resistance of the device. It can be seen that using SION as a barrier layer to adhere to the surface of the sidewall structure can avoid being etched by dry and wet methods. Moreover, by limiting the size of the window, it can be avoided that the window is too large to cause the oxide layer on the inside of the sidewall structure to be wet etched, and finally the oxide layer next to the polysilicon structure is not corroded to improve the bird's beak defect.
[0034] S304 , forming a salicide 300 on the window, wherein the salicide 300 covers the exposed polysilicon structure 200 .
[0035] This embodiment includes the following process steps: depositing a metal material on the semiconductor substrate to form a metal layer; using an annealing process and an etching process to make the metal material react with the semiconductor substrate and silicon in the polysilicon structure respectively to form a self-aligned silicide on the window, such as Figure 4D As shown. The self-aligned silicide may be a metal silicide such as nickel silicide (NiSi) or cobalt silicide (CoSi), and the metal silicide may also include NiSi2, TiSi2, CoSi2 and NiPtSi. The metal layer may include nickel, platinum, titanium, nickel or cobalt, or a combination of several metals.
[0036] In this embodiment, the Silicide process technology is based on the standard complementary metal oxide semiconductor (CMOS) process technology and adds the relevant process steps of metal silicide. The Silicide process steps are performed after the source and drain ion implantation is completed. The Ni Silicide process is widely used in the chip preparation process of 65nm to 28nm. In addition to the above steps, the basic process steps for forming Ni Silicide can also include pre-treatment of the semiconductor substrate surface (Pre-Silicideclean), the main purpose of which is to remove the native oxide layer (Native Oxide Layer) formed on the polysilicon gate and active area on the surface of the silicon substrate during the process transmission. In addition, it can be specifically deposited on the polysilicon gate, source and drain active areas by physical vapor deposition (PVD) through a process machine for depositing metal. The deposited metal materials include NiPt, Ti and Co, etc. In addition, a process machine for removing unreactive metals can be used to perform selective wet etching to remove unreacted metals. It should be noted here that the deposited metal NiPt can be directly regarded as metal Ni. Because metal Ni is easy to diffuse, in the Ni Silicide process, adding a certain amount of platinum (Pt) can prevent nickel (Ni) from diffusing onto the silicon substrate before the thermal annealing process.
[0037] In this embodiment, a barrier layer of SION material is used to protect the oxide layer on the sidewall structure, so that the sidewall structure is protected from being etched by the wet etching process. At the same time, due to good adhesion, the barrier layer is also tightly bonded to the sidewall structure during the formation of metal silicide, reducing the probability of being opened and avoiding bird beak defects. On the other hand, by limiting the opening width of the window to be less than or equal to the width of the polysilicon structure, it is ensured that the barrier layer can still completely cover the sidewall structure, and the erosion of the oxide layer and silicon oxynitride layer on the top of the sidewall structure by wet etching is reduced.
[0038] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor substrate; A polysilicon structure and sidewall structures located on both sides of the polysilicon structure are formed on the semiconductor substrate; forming a barrier layer on the polysilicon structure and the sidewall structure, wherein the barrier layer covers the polysilicon structure and the sidewall structure, and the material of the barrier layer is silicon oxynitride; Performing dry etching and wet etching in sequence to remove the barrier layer on the top of the polysilicon structure to form a window exposing the top of the polysilicon structure; the opening width of the window is less than or equal to the width of the polysilicon structure; A salicide is formed on the window, wherein the salicide covers the exposed polysilicon structure.
2. The method according to claim 1, characterized in that The barrier layer on the top of the polysilicon structure is removed by sequentially performing dry etching and wet etching to form a window exposing the top of the polysilicon structure, including the following process steps: forming a photoresist layer covering the barrier layer on the semiconductor substrate; Etching a desired pattern on the photoresist layer through exposure and development processes; Using the patterned photoresist layer as a mask, removing most of the thickness of the barrier layer located on the top of the polysilicon structure by dry etching to form a pre-window; Removing the remaining barrier layer on the top of the polysilicon structure by wet etching to form a window that completely exposes the top of the polysilicon structure, and the remaining barrier layer still completely covers the sidewall structure; Remove the remaining photoresist.
3. The method according to claim 1 or 2, characterized in that: Forming a self-aligned silicide on the window includes the following process steps: Depositing a metal material on the semiconductor substrate to form a metal layer; The metal material is made to react with the semiconductor substrate and the silicon in the polysilicon structure respectively by using an annealing process and an etching process, so as to form a self-aligned silicide on the window.
4. The method according to claim 2, characterized in that: After the pre-window is obtained by dry etching, the thickness of the barrier layer remaining on the top of the polysilicon structure is H, and the vertical shortest distance from the vertical single-side edge of the opening of the pre-window to the sidewall structure on that side is D, where H is less than or equal to D.
5. The method according to claim 4, characterized in that The opening width of the window is W, wherein D is 1% to 10% of W.
6. The method according to claim 2, characterized in that After the pre-window is obtained by dry etching, the vertical shortest distance from the vertical single side edge of the opening of the pre-window to the sidewall structure on this side is D, and the opening width of the window is W, wherein D is 1% to 10% of W.
7. The method according to claim 3, characterized in that The self-aligned silicide is nickel silicide or cobalt silicide.
8. The method according to claim 3, characterized in that The metal layer includes nickel, platinum, titanium, nickel or cobalt, or a combination of several metals.
9. The method according to claim 1, characterized in that: The sidewall structure includes a combination of at least one oxide layer and one silicon nitride layer alternately arranged from inside to outside, wherein the inner side of the sidewall structure is a side adjacent to the polysilicon structure, and the innermost side of the sidewall structure is the oxide layer.
10. A semiconductor device, characterized in that: include: Semiconductor substrate; A polysilicon structure located on the surface of the semiconductor substrate, and a self-aligned silicide located on the surface of the polysilicon structure; Sidewall structures located on opposite sides of the stacked structure composed of the salicide and the polysilicon structure, the sidewall structures are completely covered with a barrier layer, the barrier layer is made of silicon oxynitride; a gate channel layer is located in the semiconductor substrate; The source is located in the semiconductor substrate and on one side of the gate channel layer; the drain is located in the semiconductor substrate and on a side of the gate channel layer away from the source; the gate channel layer, the source and the drain have the same ion doping type, and self-aligned silicide is located at the source, the drain and the gate.