Formation method of semiconductor structure

Abstract

The embodiment of the invention provides a method for forming a semiconductor structure. The method comprises the following steps: providing a substrate; forming a first mask layer and a second mask layer with a first preset pattern on the surface of the substrate; wherein the hardness of the second mask layer is greater than that of the spin-coating hard mask; patterning the first mask layer and the substrate based on the second mask layer to form an etching groove in the substrate; and forming a word line in the etching groove.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a method for forming a semiconductor structure. Background Art

[0002] In order to improve the integration of dynamic random access memory (DRAM) to speed up the operation speed of components and meet consumers' demand for miniaturized electronic devices, buried word line (BWL) dynamic random access memory has been developed in recent years to meet the above-mentioned various needs.

[0003] In the semiconductor process, the conventional process of forming a buried word line structure is: a word line trench is opened on a semiconductor substrate through multiple etching steps, and a metal material is filled in the word line trench to form a buried word line structure. However, the buried word line structure prepared in the related art has a high profile roughness and poor symmetry. Summary of the invention

[0004] In view of this, an embodiment of the present disclosure provides a method for forming a semiconductor structure.

[0005] The present disclosure provides a method for forming a semiconductor structure, the method comprising:

[0006] providing a substrate;

[0007] Forming a first mask layer and a second mask layer having a first preset pattern on the surface of the substrate; wherein the hardness of the second mask layer is greater than the hardness of the spin-coated hard mask;

[0008] Based on the second mask layer, patterning the first mask layer and the substrate to form an etched groove in the substrate;

[0009] Word lines are formed in the etched trenches.

[0010] In some embodiments, the Young's modulus of the second mask layer is less than the Young's modulus of the spin-on hard mask.

[0011] In some embodiments, the material of the second mask layer includes polysilicon.

[0012] In some embodiments, the thickness of the second mask layer is less than 70 nanometers.

[0013] In some embodiments, the first mask layer includes a first hard mask layer and a first anti-reflective layer located on a surface of the first hard mask layer;

[0014] Based on the second mask layer, patterning the first mask layer and the substrate to form an etching groove in the substrate includes:

[0015] Based on the second mask layer, etching the first anti-reflection layer to form the first anti-reflection layer having a first preset pattern;

[0016] removing the second mask layer;

[0017] Based on the first anti-reflection layer having the first preset pattern, the first hard mask layer and the substrate are etched to form the etched grooves.

[0018] In some embodiments, forming a first mask layer and a second mask layer having a first preset pattern on the surface of the substrate includes:

[0019] forming the first hard mask layer, the first anti-reflection layer and a third mask layer having a second preset pattern in sequence on the surface of the substrate;

[0020] Based on the third mask layer, a sidewall layer having a third preset pattern is formed; wherein the density of the third preset pattern is twice the density of the second preset pattern;

[0021] A second mask layer having the first preset pattern is formed in the gap between the spacer layers.

[0022] In some embodiments, forming a sidewall spacer layer having a second preset pattern based on the third mask layer includes:

[0023] forming an initial sidewall layer covering the third mask layer;

[0024] The initial spacer layer on the top surface of the third mask layer and a portion of the surface of the first mask layer is removed until the third mask layer and the first mask layer are exposed; the remaining initial spacer layer located on the sidewall of the third mask layer constitutes the spacer layer, and the third mask layer is removed.

[0025] In some embodiments, the substrate includes an array region and a peripheral region; a pattern density of the first preset pattern in the array region is greater than a pattern density of the first preset pattern in the peripheral region;

[0026] Forming a second mask layer having the first preset pattern in the gap between the spacer layers, comprising:

[0027] A covering layer is formed in the gap between the spacer layers, on the surface of the spacer layer and on the surface of the peripheral region; wherein a step is provided between the covering layer on the surface of the peripheral region and the covering layer on the surface of the array region;

[0028] The cover layer is etched back until the top of the sidewall layer and the peripheral area are exposed; the remaining cover layer constitutes the second mask layer.

[0029] In some embodiments, a height of the second mask layer is smaller than a height of the third mask layer.

[0030] In some embodiments, after forming the second mask layer and before forming the first anti-reflection layer having the second preset pattern, the method further includes:

[0031] The sidewall layer is removed, and a second photoresist layer is formed on the surface of the peripheral area.

[0032] In some embodiments, the second photoresist layer is removed simultaneously with the removal of the second mask layer.

[0033] In some embodiments, the third mask layer having the second preset pattern is formed by the following steps:

[0034] forming a third hard mask layer, a third anti-reflection layer and a first photoresist layer having the second preset pattern in sequence on the surface of the first anti-reflection layer;

[0035] patterning the third anti-reflective layer and the third hard mask layer based on the first photoresist layer;

[0036] The patterned third anti-reflection layer is removed, and the patterned third hard mask layer constitutes the third mask layer.

[0037] In some embodiments, the substrate includes a plurality of active regions arranged at intervals, and a shallow trench isolation structure between the active regions;

[0038] The etched trench passes through the active area and the shallow trench isolation structure at the same time.

[0039] In some embodiments, forming a word line in the etched trench includes:

[0040] A conductive material is deposited at the bottom of the etched groove to form the word line.

[0041] In some embodiments, the method further comprises:

[0042] An insulating layer is formed on the surface of the word line, and the insulating layer fills the etched groove.

[0043] The method for forming a semiconductor structure provided in an embodiment of the present disclosure includes: providing a substrate; forming a first mask layer and a second mask layer having a first preset pattern on the surface of the substrate; wherein the hardness of the second mask layer is greater than the hardness of the spin-coated hard mask; based on the second mask layer, patterning the first mask layer and the substrate to form an etching groove located in the substrate; and forming a word line in the etching groove. Since the second mask layer having a hardness greater than that of the spin-coated hard mask is used as an etching mask when forming the word line in the embodiment of the present disclosure, the height of the second mask layer is lower than that of the spin-coated hard mask, and only the second mask layer is used as the etching mask, and the symmetry of the mask pattern is high, so that the contour line of the word line finally formed is smooth and highly symmetrical, which is beneficial to improving the performance and manufacturing yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0045] Figures 1 to 6 Schematic diagram of various structures in a process of preparing a buried word line structure;

[0046] Figure 7 A schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0047] Figures 8 to 18 A schematic diagram of a structure during the formation of a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0049] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0050] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0051] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0052] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] Figures 1 to 6 Schematic diagram of various structures of a buried word line structure preparation process, the preparation method of the buried word line structure includes the following steps 1 to 9:

[0054] Step 1: Provide Figure 1 The substrate 10 shown;

[0055] Step 2: A bottom mask layer 20, a top mask layer 30 and a photoresist layer 40 having a first pattern are sequentially formed on the surface of the substrate 10; wherein the bottom mask layer 20 includes a bottom hard mask layer 201 and a bottom anti-reflection layer 202 located on the surface of the bottom hard mask layer 201, and the top mask layer 30 includes a top hard mask layer 301 and a top anti-reflection layer 302 located on the surface of the top hard mask layer 301. The bottom hard mask layer 201 may be, for example, an amorphous carbon layer (ACL), the top hard mask layer 301 may be, for example, a spin-on hard mask layer (SOH), and the bottom anti-reflection layer 202 and the top anti-reflection layer 302 may be, for example, silicon nitride layers.

[0056] Step 3: Etching the top mask layer 30 through the photoresist layer 40 to transfer the first pattern into the top mask layer 30 to form Figure 2 The top anti-reflective layer 302 after etching and the top hard mask layer 301 after etching are shown;

[0057] Step 4: forming a film covering the top anti-reflection layer 302, the top hard mask layer 301 and the bottom mask layer 20. Figure 3 The oxide layer 41 is shown, and a spin-on hard mask layer 42 (such as Figure 3 shown);

[0058] Step 5: Please refer to Figure 4 , planarizing the spin-on hard mask layer 42 and the oxide layer 41 until the top anti-reflection layer 302 is exposed, and retaining the oxide layer 41 and the spin-on hard mask layer 42 located on the sidewalls of the top anti-reflection layer 302 and the top hard mask layer 301;

[0059] Step 6: Figure 4 An oxide layer 41 is formed again on the top surface of the structure shown in the figure, and a portion of the oxide layer 41 is etched to form an etched groove (not shown), and a etched groove and a surface of the oxide layer 41 are formed as shown in the figure. Figure 5 The anti-reflection layer 43 is shown;

[0060] Step 7: Etching the anti-reflection layer 43 and the oxide layer 41 until the spin-coated hard mask layer 42 is exposed, then stopping the etching, and removing the oxide layer 41 between the spin-coated hard mask layers 42, and the remaining spin-coated hard mask layer 42 and the oxide layer 41 at the bottom of the spin-coated hard mask layer 42 constitute an etching mask;

[0061] Step 8: Etch the bottom anti-reflection layer through the etching mask to transfer the pattern in the etching mask to the bottom anti-reflection layer 202 to form Figure 6 The structure shown;

[0062] Step nine: using the etched bottom anti-reflection layer 202 as a mask, etching the top mask layer 201 and the substrate 10 to form a groove in the substrate, and forming a buried word line structure in the groove.

[0063] In this embodiment, the oxide layer 41 and the spin-on hard mask layer 42 constitute an etching mask for finally forming a word line structure, and the height h of the spin-on hard mask layer 42 (eg Figure 5 As shown in the figure, the height h is relatively large, for example, the height h is 70 nanometers, resulting in a high Young's modulus, which in turn leads to a large roughness of the contour line of the formed buried word line structure; on the other hand, the etching mask composed of the oxide layer 41 and the spin-coated hard mask layer 42 has an asymmetric pattern of adjacent patterns, which also leads to an imbalance (i.e., poor symmetry) of the finally formed buried word line structure.

[0064] Based on this, the embodiment of the present disclosure provides a method for forming a semiconductor structure, the method comprising: providing a substrate; forming a first mask layer and a second mask layer having a first preset pattern on the surface of the substrate; wherein the hardness of the second mask layer is greater than the hardness of the spin-coated hard mask; based on the second mask layer, patterning the first mask layer and the substrate to form an etching groove located in the substrate; and forming a word line in the etching groove. Since the second mask layer having a hardness greater than that of the spin-coated hard mask is used as an etching mask when forming the word line in the embodiment of the present disclosure, the height of the second mask layer is lower than that of the spin-coated hard mask, and only the second mask layer is used as the etching mask, and the symmetry of the mask pattern is high, so that the contour line of the word line finally formed is smooth and highly symmetrical, which is conducive to improving the performance and manufacturing yield of the semiconductor structure.

[0065] Figure 7 A schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure, Figures 8 to 18 The schematic diagram of the structure of the semiconductor structure formed in the embodiment of the present disclosure is shown below. Figures 7 to 18 The formation process of the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0066] like Figure 7 As shown, the method for forming a semiconductor structure includes the following steps S701 to S704:

[0067] First, refer to Figure 7 and Figure 8 , execute step S701 to provide a substrate 70.

[0068] In the disclosed embodiment, the base 70 may be a semiconductor substrate; the semiconductor substrate may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof. In other embodiments, the semiconductor substrate may also be a substrate after ion doping, such as a P-type doped substrate or an N-type doped substrate.

[0069] Please note that, see Figure 8 In the embodiment of the present disclosure, the substrate 70 includes a plurality of active areas 701 arranged at intervals, and a shallow trench isolation structure 702 located between the active areas 701; the shallow trench isolation structure 702 is used to isolate two adjacent active areas 701, and it can also be understood that the active area 701 is defined by the shallow trench isolation structure 702.

[0070] It is worth noting that please continue to see Figure 8 , the shallow trench isolation structure 702 in the embodiment of the present disclosure is also located on the surface of the active area 701 .

[0071] It should also be noted that the substrate 70 includes an array area (AA) and a peripheral area (PA). The array area AA is used to form a memory cell of a semiconductor structure, such as a DRAM cell, a static random access memory (SRAM) cell, a phase-change memory (PCM) cell, a NAND Flash memory cell, or a Nor Flash memory cell. The peripheral area PA can be used to decode, detect the memory cell array, and read data. More specifically, the peripheral area PA can be formed with at least one of a sense amplifier, a row decoder, a column decoder, a control circuit, an input / output buffer, and the like.

[0072] Next, continue to refer to Figures 7 to 15 , executing step S702, forming a first mask layer 80 and a second mask layer 94 having a first preset pattern F on the surface of the substrate 70; wherein the hardness of the second mask layer 94 is greater than the hardness of the spin-coated hard mask;

[0073] It should be noted that since the word lines of the subsequently formed semiconductor structure are located in the array area AA, the initial mask pattern for forming the word lines (i.e., the first preset pattern F) is located in the array area AA, that is, the pattern density of the first preset pattern F in the array area AA is greater than the pattern density of the first preset pattern F in the peripheral area PA.

[0074] In some embodiments, the first mask layer 80 includes a first hard mask layer 801 and a first anti-reflection layer 802 located on the surface of the first hard mask layer 801; wherein the first hard mask layer 801 can be an advanced patterning film (APF), and the thickness of the first hard mask layer 801 can be, for example, 165 nanometers (nm); the first anti-reflection layer 802 can be, for example, a silicon-rich silicon oxynitride layer (Si-rich SION), and the thickness of the first anti-reflection layer 802 can be, for example, 25nm.

[0075] In the embodiment of the present disclosure, the Young's modulus of the second mask layer 94 is smaller than the Young's modulus of the spin-on hard mask SOH.

[0076] In some embodiments, the Young's modulus, thickness and roughness of the mask satisfy the following formula (1):

[0077]

[0078] Among them, γ represents roughness, σ represents stress, E represents Young's modulus, h represents depth or thickness, and w represents width. It can be seen that the roughness γ is proportional to the thickness of the mask, and the roughness γ is inversely proportional to the Young's modulus of the mask. Therefore, in the embodiment of the present disclosure, the second mask layer 94 with a smaller Young's modulus and higher hardness than the spin-on hard mask SOH is used as an etching mask for forming a word line, which can reduce the roughness of the word line finally formed, so that the contour of the word line finally formed is smooth.

[0079] In some embodiments, the material of second mask layer 94 includes polysilicon.

[0080] In some embodiments, the thickness of second mask layer 94 is less than 70 nanometers.

[0081] It should be noted that when the spin-on hard mask SOH is used as an etching mask to form the buried word line, the thickness of the spin-on hard mask SOH is 70 nm.

[0082] In some embodiments, step S702 may include the following steps 1 to 3:

[0083] Step 1: forming a first hard mask layer 801, a first anti-reflection layer 802 and a third mask layer 903 having a second preset pattern on the surface of the substrate 70 in sequence;

[0084] In some embodiments, a third mask layer 903 having a second preset pattern can be formed by the following steps: sequentially forming a third hard mask layer 901, a third anti-reflection layer 902 and a first photoresist layer 91 having a second preset pattern H on the surface of the first anti-reflection layer 801 in the first mask layer 80; patterning the third anti-reflection layer 902 and the third hard mask layer 901 based on the first photoresist layer 91; removing the patterned third anti-reflection layer 903, and the patterned third hard mask layer 901 constitutes the third mask layer 903.

[0085] During implementation, first, a first hard mask material, a first anti-reflection material, a third hard mask material, and a third anti-reflection material are sequentially deposited on the surface of the substrate 70 to form a Figure 8 The first hard mask layer 801, the first anti-reflection layer 802, the third hard mask layer 901 and the third anti-reflection layer 902 are shown, and a first photoresist layer 91 having a second preset pattern H is formed on the surface of the third anti-reflection layer 902 (eg, Figure 8 ); secondly, the third anti-reflection layer 902 and the third hard mask layer 901 are etched through the first photoresist layer 91 to transfer the second preset pattern H to the third anti-reflection layer 902 and the third hard mask layer 901 to form a patterned third anti-reflection layer 902 and a patterned third hard mask layer 901; finally, for example, the patterned third anti-reflection layer 902 can be removed by dry etching technology, and the remaining patterned third hard mask layer 901 is as shown. Fig. 9 A third mask layer 903 is shown.

[0086] In some embodiments, the third hard mask layer 901 may be an advanced patterning layer APF, and the thickness of the third hard mask layer 901 may be, for example, 65 nm; the third anti-reflective layer 902 may be, for example, an oxygen-rich silicon oxynitride layer (O-rich SION), and the thickness of the third anti-reflective layer 902 may be, for example, 18 nm.

[0087] In the embodiment of the present disclosure, the first hard mask layer 801, the first anti-reflective layer 802, the third hard mask layer 901 and the third anti-reflective layer 902 can be formed by any suitable deposition process, for example, it can be a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, a physical vapor deposition (Physical Vapor Deposition, PVD) process, an atomic layer deposition (Atomic Layer Deposition, ALD) process, a spin coating process or a coating process.

[0088] Step 2: Based on the third mask layer 903, a sidewall layer 92 having a third preset pattern is formed; wherein the density of the third preset pattern E is twice the density of the second preset pattern H;

[0089] In some embodiments, based on the third mask layer 903, forming a sidewall layer 92 having a third preset pattern E may include the following steps: forming an initial sidewall layer 92a covering the third mask layer 903; removing the initial sidewall layer 92a on the top surface of the third mask layer 903 and a portion of the surface of the first mask layer 80 until the top surface of the third mask layer 903 and a portion of the first mask layer 80 are exposed; the remaining initial sidewall layer 92a located on the side wall of the third mask layer 903 constitutes the sidewall layer 92, and the third mask layer 903 is removed.

[0090] It should be noted that, in the embodiment of the present disclosure, the self-aligned double patterning technology (SADP) can be used to double the pattern density of the second preset pattern H to form the sidewall layer of the specific third preset pattern E.

[0091] During implementation, first, a sidewall material is deposited on the surface of the third mask layer 903 and the first anti-reflection layer 802 to form a Fig.10 The initial sidewall layer 92a is shown; secondly, the initial sidewall layer 92a is dry-etched (for example, plasma-etched) to remove the initial sidewall layer 92a on the top surface of the third mask layer 903, and to remove a portion of the initial sidewall layer 92a on the surface of the first anti-reflection layer 802, exposing the third mask layer 903 and a portion of the top surface of the third mask layer 903. Finally, the third mask layer 903 is removed, and the remaining initial sidewall layer 92a located on the sidewall of the third mask layer 903 is formed as shown in FIG. Fig.11 The spacer layer 92 shown has a third preset pattern E.

[0092] Step 3: forming a second mask layer 94 having a first preset pattern F in the gaps between the spacer layers 92 .

[0093] In some embodiments, forming a second mask layer 94 having a first preset pattern F in the gap between the side wall layers 92 may include the following steps: forming a covering layer 93 in the gap between the side wall layers 92, on the surface of the side wall layer 92, and on the surface of the peripheral area PA; wherein there is a step between the covering layer 93 on the surface of the peripheral area PA and the covering layer 93 on the surface of the array area AA; etching back the covering layer 93 until the top of the side wall layer 92 and the peripheral area PA are exposed; and the remaining covering layer 93 constitutes the second mask layer 94.

[0094] During implementation, a mask material is deposited in the gaps between the spacer layers 92, on the surface of the spacer layers 92, and on the surface of the peripheral area PA to form a Fig.12Here, the mask material may be polysilicon, for example; Next, the cover layer 93 is etched back by dry etching technology until the cover layer 93 on the top surface of the peripheral area PA is completely removed, and the remaining cover layer 93 in the array area AA is formed as shown in FIG. Fig.13 A second mask layer 94 is shown.

[0095] In the embodiment of the present disclosure, the cover layer 93 may be formed by chemical vapor deposition, for example.

[0096] It should be noted that, since the pattern density of the first preset pattern F in the array area AA is greater than that in the peripheral area PA, the cover layer 93 has a step between the array area AA and the peripheral area PA, and when the cover layer 93 is etched back, when the cover layer 93 on the surface of the peripheral area PA is completely removed, the thickness of the removed cover layer 93 in the array area AA is greater, so that the following is formed: Fig.13 The structure shown.

[0097] It should be noted that, in the embodiment of the present disclosure, the initial spacer layer 92a on the top surface of the third mask layer 903 and part of the surface of the first mask layer 80 is first removed to form the spacer layer 92, and then the second mask layer 94 is formed in the gap between the spacer layers 92, and the spacer layer 92 is removed. In this way, it can be ensured that there is no initial spacer layer material (i.e., no initial spacer layer 92a or spacer layer 92) in the formed second mask layer 94, so that a uniform second mask layer 94 can be formed, and the uniform second mask layer 94 is conducive to forming a pattern with high symmetry.

[0098] In some embodiments, the height of the second mask layer 94 is less than the height of the third mask layer 903 .

[0099] Please refer to Fig.13 The height of the second mask layer 94 is less than that of the sidewall layer 92 , and the height of the sidewall layer 92 is equal to that of the third mask layer 903 , for example, the height of the sidewall layer 92 is 65 nm. Therefore, the height of the second mask layer 94 is less than 65 nm.

[0100] In the embodiment of the present disclosure, the height (65nm) of the second mask layer 94 etched to form the word line is smaller than the height (70nm) of the spin-coated hard mask SOH in the related art, and according to the above analysis, the mask height is proportional to the roughness of the word line, that is, the higher the mask height, the rougher the profile of the word line formed. Therefore, the use of a second hard mask with a smaller height in the embodiment of the present disclosure can improve the profile of the word line finally formed and reduce the roughness of the word line.

[0101] In addition, in the embodiment of the present disclosure, only the second mask layer 94 is used as an etching mask for forming word lines, and the second mask layer 94 includes a plurality of adjacent sub-masks, and the constituent materials and heights of the adjacent sub-masks are the same, that is, the second mask layer 94 has high symmetry as an etching mask. In this way, the symmetry of the word line structure finally formed can be improved, which is beneficial to improving the performance and manufacturing yield of the semiconductor structure.

[0102] In some embodiments, after forming the second mask layer 94, the method for forming the semiconductor structure further includes: removing the spacer layer 92 (eg, Fig.14 As shown), and a surface of the peripheral area PA is formed as shown Fig.15 The second photoresist layer 95 is shown.

[0103] It should be noted that in the embodiment of the present disclosure, dry etching technology or wet etching technology can be used to remove the sidewall layer 92. The second photoresist layer 95 formed on the surface of the peripheral area PA can be used to shield the peripheral area PA to avoid damage to the peripheral area PA during subsequent etching.

[0104] Next, refer to Figure 7 , Fig.16 and Fig.17 , executing step S703 , patterning the first mask layer 80 and the substrate 70 based on the second mask layer 94 to form an etched groove 96 located in the substrate 70 .

[0105] In some embodiments, step S703 may include the following steps:

[0106] Based on the second mask layer 94 , the first anti-reflection layer 801 is etched to form a first anti-reflection layer 802 having a first preset pattern F; the second mask layer is removed; based on the first anti-reflection layer 802 having the first preset pattern F, the first hard mask layer 801 and the substrate 70 are etched to form an etched groove 76 .

[0107] In the embodiment of the present disclosure, the first anti-reflection layer 801 is etched by dry etching technology through the second mask layer 94 having the first preset pattern F, so as to transfer the first preset pattern F to the first anti-reflection layer 802, forming Fig.16 Next, the first anti-reflection layer 802 having the first preset pattern F is used as an etching mask to further etch the first hard mask layer 801 and the substrate 70 to transfer the first preset pattern F to the first hard mask layer 801 and the substrate 70, thereby forming a first anti-reflection layer 802 having the first preset pattern F in the substrate 70. Fig.17 Etched trenches 96 are shown.

[0108] It should be noted that the etched trench 76 passes through the active area 701 and the shallow trench isolation structure 702 at the same time, that is, the word line finally formed is a continuous line, and the word line passes through the active area 701 and the shallow trench isolation structure 702 .

[0109] It is also necessary to explain that please continue to refer to Fig.16 , the second photoresist layer 95 is removed while the second mask layer 94 is removed.

[0110] In the embodiment of the present disclosure, for example, the second mask layer 94 and the second photoresist layer 95 may be removed simultaneously by using a dry etching technique or a wet etching technique.

[0111] In some embodiments, after forming the etched trench 96, the method for forming the semiconductor structure further includes:

[0112] The first hard mask layer 801 having the first predetermined pattern F is removed.

[0113] In the embodiment of the present disclosure, for example, the first hard mask layer 801 may be removed by using a dry etching technique or a wet etching technique.

[0114] Finally, reference Figure 7 and Fig.18 , execute step S704 to form word line 98 in the etched groove 96.

[0115] In some embodiments, step S704 may include the following steps: depositing a conductive material at the bottom of the etched groove 96 to form a Fig.18 Word line 98 is shown.

[0116] It should be noted that the word line 98 in the embodiment of the present disclosure is composed of a gate conductive layer in a gate structure in a semiconductor structure. Therefore, before forming the word line 98 , a gate dielectric layer 97 is first formed on the inner wall of the etched trench 96 .

[0117] Specifically, first, a gate dielectric material is deposited on the inner wall of the etched trench 96 to form an initial gate dielectric layer (not shown); secondly, a gate conductive material is filled in the etched trench 96 having the initial gate dielectric layer to form an initial gate conductive layer (not shown); next, the initial gate conductive layer and the initial gate dielectric layer are etched back to expose a portion of the inner wall of the etched trench 96 to form a gate conductive layer as shown in FIG. Fig.18 The gate dielectric layer 97 and the gate conductive layer (ie, word line 98) are shown.

[0118] In the embodiment of the present disclosure, the gate dielectric material may be silicon oxide or other suitable materials; the gate conductive material may be any material with good conductive properties, such as titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), copper (Cu) or any one or a combination thereof.

[0119] In some embodiments, after forming the word line 98 , the method further includes: forming an insulating layer 99 on a surface of the word line 98 , wherein the insulating layer 99 fills the etched groove 96 .

[0120] During implementation, an insulating material may be deposited on the surface of the gate dielectric layer 97 and the word line 98 to form a Fig.18 The insulating layer 99 shown in FIG. The insulating layer 99 fills the etched groove 96 and is flush with the top surface of the substrate 70 , and is used to isolate the word line 98 from other functional structures (such as the word line structure) on the surface of the substrate 70 .

[0121] It should be noted that the semiconductor structure in the embodiment of the present disclosure may be a DRAM structure, and the method for forming the semiconductor structure further includes: forming a bit line structure and a capacitor structure on the surface of the substrate 70 .

[0122] Since the second mask layer with a hardness greater than that of the spin-coated hard mask is used as an etching mask when forming the word line in the embodiment of the present disclosure, the height of the second mask layer is lower than the height of the spin-coated hard mask, and only the second mask layer is used as the etching mask, the mask pattern has high symmetry. In this way, the contour line of the word line finally formed is smooth and highly symmetrical, which is beneficial to improving the performance and manufacturing yield of the semiconductor structure.

[0123] The disclosed embodiments can eliminate the problems of buried word line asymmetry and line defects, improve the profile of the buried word line (BWL), and thus improve the performance of a semiconductor structure (e.g., DRAM). On the other hand, it also solves the problem of buried word line load leading to wafer scrapping and waste of production costs and time.

[0124] In the disclosed embodiment, if the buried word line contour is symmetrical and the roughness is greatly improved, the performance of the semiconductor structure is improved and the cost of money and time is saved.

[0125] In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0126] The features disclosed in several method or structural embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0127] The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Forming a first mask layer and a second mask layer having a first preset pattern on the surface of the substrate; wherein the hardness of the second mask layer is greater than the hardness of the spin-coated hard mask; Based on the second mask layer, patterning the first mask layer and the substrate to form an etched groove in the substrate; Word lines are formed in the etched trenches.

2. The method according to claim 1, characterized in that The Young's modulus of the second mask layer is smaller than the Young's modulus of the spin-on hard mask.

3. The method according to claim 1, characterized in that The material of the second mask layer includes polysilicon.

4. The method according to claim 1, characterized in that: The thickness of the second mask layer is less than 70 nanometers.

5. The method according to any one of claims 1 to 4, characterized in that: The first mask layer includes a first hard mask layer and a first anti-reflection layer located on a surface of the first hard mask layer; Based on the second mask layer, patterning the first mask layer and the substrate to form an etching groove in the substrate includes: Based on the second mask layer, etching the first anti-reflection layer to form the first anti-reflection layer having a first preset pattern; removing the second mask layer; Based on the first anti-reflection layer having the first preset pattern, the first hard mask layer and the substrate are etched to form the etched grooves.

6. The method according to claim 5, characterized in that A first mask layer and a second mask layer having a first preset pattern are formed on the surface of the substrate, comprising: forming the first hard mask layer, the first anti-reflection layer and a third mask layer having a second preset pattern in sequence on the surface of the substrate; Based on the third mask layer, a sidewall layer having a third preset pattern is formed; wherein the density of the third preset pattern is twice the density of the second preset pattern; A second mask layer having the first preset pattern is formed in the gap between the spacer layers.

7. The method according to claim 6, characterized in that Based on the third mask layer, a sidewall layer having a second preset pattern is formed, comprising: forming an initial sidewall layer covering the third mask layer; The initial spacer layer on the top surface of the third mask layer and a portion of the surface of the first mask layer is removed until the third mask layer and the first mask layer are exposed; the remaining initial spacer layer located on the sidewall of the third mask layer constitutes the spacer layer, and the third mask layer is removed.

8. The method according to claim 6, characterized in that The substrate comprises an array region and a peripheral region; a pattern density of the first preset pattern in the array region is greater than a pattern density of the first preset pattern in the peripheral region; Forming a second mask layer having the first preset pattern in the gap between the spacer layers, comprising: A covering layer is formed in the gap between the spacer layers, on the surface of the spacer layer and on the surface of the peripheral region; wherein a step is provided between the covering layer on the surface of the peripheral region and the covering layer on the surface of the array region; The cover layer is etched back until the top of the sidewall layer and the peripheral area are exposed; the remaining cover layer constitutes the second mask layer.

9. The method according to claim 8, characterized in that The height of the second mask layer is smaller than the height of the third mask layer.

10. The method according to claim 8, characterized in that After forming the second mask layer and before forming the first anti-reflection layer having a second preset pattern, the method further includes: The sidewall layer is removed, and a second photoresist layer is formed on the surface of the peripheral area.

11. The method according to claim 10, characterized in that The second photoresist layer is removed while the second mask layer is removed.

12. The method according to claim 6, characterized in that The third mask layer having the second preset pattern is formed by the following steps: forming a third hard mask layer, a third anti-reflection layer and a first photoresist layer having the second preset pattern in sequence on the surface of the first anti-reflection layer; patterning the third anti-reflective layer and the third hard mask layer based on the first photoresist layer; The patterned third anti-reflection layer is removed, and the patterned third hard mask layer constitutes the third mask layer.

13. The method according to claim 1, characterized in that The substrate includes a plurality of active areas arranged at intervals, and a shallow trench isolation structure located between the active areas; The etched trench passes through the active area and the shallow trench isolation structure at the same time.

14. The method according to claim 13, characterized in that Forming a word line in the etched trench, comprising: A conductive material is deposited at the bottom of the etched groove to form the word line.

15. The method according to claim 14, characterized in that The method further comprises: An insulating layer is formed on the surface of the word line, and the insulating layer fills the etched groove.

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