Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and relates to the technical field of semiconductors. The forming method comprises the following steps: forming a stacking structure on a substrate, wherein the stacking structure comprises a first material layer and a second material layer; etching the stack structure by using a first etching gas to form a first opening penetrating through the second material layer, the first etching gas including fluorine ions; first protective gas and first auxiliary gas are introduced into the first opening at the same time for reaction, so that a protective layer is formed on the side wall of the first opening, the first protective gas comprises silicon ions, and the first auxiliary gas comprises oxygen ions; continuously etching the stacked structure by using a first etching gas to form a second opening penetrating through the first material layer; and introducing a first protective gas and a first auxiliary gas into the second opening at the same time and carrying out a reaction so as to form a protective layer on the side wall of the second opening. According to the forming method, the protection layer is formed on the side wall of the opening, so that the collimation and integrity of the side wall of the opening can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] As the process technology evolves, the integration level of semiconductor devices increases, the characteristic size of the devices decreases, and the arrangement density increases. Due to the size limitation, the arrangement density of components in planar semiconductor devices has reached the limit. Therefore, in order to increase the density of the device, the semiconductor device can adopt a structure including multiple components stacked vertically to obtain a higher device arrangement density.

[0003] At present, since the multi-layer component stacking structure needs to be processed in the film layer stacking direction, especially when deep holes need to be formed through the stacking structure, defects will occur in the deep hole etching profile, such as misaligned etching profile, which limits the structural layout and performance improvement of semiconductor devices in the stacking direction.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In view of this, a semiconductor structure and a method for forming the same are provided. The semiconductor structure formed by the method can avoid damage to the sidewalls of the formed opening, improve the straightness of the sidewalls of the opening, and thus enhance device performance.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0008] forming a stacked structure on a substrate, the stacked structure comprising at least one first material layer and at least one second material layer stacked in a direction perpendicular to the substrate, the first material layer and the second material layer being made of different materials;

[0009] Etching the stacked structure using a first etching gas to form a first opening penetrating the second material layer, wherein the first etching gas includes fluorine ions;

[0010] A first protective gas and a first auxiliary gas are introduced into the first opening at the same time and reacted to form a protective layer on the sidewall of the first opening, wherein the first protective gas includes silicon ions and the first auxiliary gas includes oxygen ions;

[0011] Continue etching the stacked structure using the first etching gas to form a second opening penetrating the first material layer, wherein the second opening at least partially overlaps with an orthographic projection of the first opening on the substrate;

[0012] The first protective gas and the first auxiliary gas are introduced into the second opening simultaneously and react with each other to form the protective layer on the side wall of the second opening.

[0013] In an exemplary embodiment of the present disclosure, the stacked structure further includes a third material layer, the third material layer is located between at least one pair of the first material layer and the second material layer, and the first material layer, the second material layer and the third material layer are made of different materials, and the method further includes:

[0014] Etching the third material layer using a second etching gas to form a third opening penetrating the third material layer, wherein the first opening, the second opening, and the third opening have orthographic projections on the substrate at least partially overlap, wherein the second etching gas includes chloride ions;

[0015] The first auxiliary gas and the first protective gas are introduced into the third opening and react with each other to form the protective layer on the side wall of the third opening.

[0016] In an exemplary embodiment of the present disclosure, the method includes:

[0017] After forming the first opening, simultaneously introducing the first protective gas and the first auxiliary gas into the first opening;

[0018] Alternatively, during the process of forming the first opening, the first protective gas and the first auxiliary gas are continuously introduced into the formed first opening simultaneously.

[0019] In an exemplary embodiment of the present disclosure, the method includes:

[0020] After forming the second opening, simultaneously introducing the first protective gas and the first auxiliary gas into the second opening;

[0021] Or, during the process of forming the second opening, the first protective gas and the first auxiliary gas are continuously introduced into the formed second opening simultaneously.

[0022] In an exemplary embodiment of the present disclosure, the method includes:

[0023] After forming the third opening, simultaneously introducing the first protective gas and the first auxiliary gas into the third opening;

[0024] Alternatively, during the process of forming the third opening, the first protective gas and the first auxiliary gas are continuously introduced into the formed third opening simultaneously.

[0025] In an exemplary embodiment of the present disclosure, the method further includes:

[0026] The protection layer is removed, and an opening having aligned sidewalls and penetrating the stack structure is formed in the stack structure to form a target semiconductor structure.

[0027] In an exemplary embodiment of the present disclosure, after forming the stacked structure on the substrate, the method further includes:

[0028] forming a mask structure on a side of the stacked structure away from the substrate, the mask structure comprising a first mask layer and a second mask layer, the first mask layer and the second mask layer being made of different materials;

[0029] The stacked structure is etched using the mask structure, the first etching gas, and the second etching gas.

[0030] In an exemplary embodiment of the present disclosure, the method includes:

[0031] forming a photoresist layer on a side of the second mask layer away from the substrate;

[0032] patterning the photoresist layer;

[0033] The second mask layer is etched using the patterned photoresist layer to form a patterned second mask layer.

[0034] In an exemplary embodiment of the present disclosure, before forming the stacked structure, the method further includes:

[0035] forming an etching stop layer on the substrate, wherein the stacked structure is formed on a side of the etching stop layer away from the substrate;

[0036] After forming an opening penetrating the stack structure, the opening extends into the etch stop layer or the opening penetrates the etch stop layer.

[0037] In an exemplary embodiment of the present disclosure, the gas flow rate of the first protective gas is 10 sccm to 100 sccm, and the gas flow rate of the first auxiliary gas is 100 sccm to 500 sccm.

[0038] In an exemplary embodiment of the present disclosure, the method includes:

[0039] Under the condition of a pressure of 5 mT to 30 mT, the first auxiliary gas reacts with the first protective gas.

[0040] In an exemplary embodiment of the present disclosure, the method includes:

[0041] Under the condition that the bias voltage is 1000W-1500W, the first auxiliary gas reacts with the first protective gas.

[0042] In an exemplary embodiment of the present disclosure, the first protective gas includes at least one of silicon tetrachloride, monosilane, silylene, disilane or silicate.

[0043] In an exemplary embodiment of the present disclosure, the first auxiliary gas includes at least one of oxygen, methanol or ethanol.

[0044] In an exemplary embodiment of the present disclosure, the first etching gas includes C X F Y , S X F Y 、N X F Y , wherein X is a positive integer greater than or equal to 1, and Y is a positive integer greater than or equal to 1.

[0045] In an exemplary embodiment of the present disclosure, the second etching gas includes chlorine gas.

[0046] The present invention provides a method for forming a semiconductor structure. By introducing a first protective gas and a first auxiliary gas while etching an opening in a stacked structure, the first protective gas and the first auxiliary gas can form a protective layer on the side wall of the opening to protect the structure of the etched partial opening from being damaged by the etching gas in subsequent etching, thereby making the side wall of the opening formed in the stacked structure aligned with the substrate, breaking the limitation on the number of stacked layers of the film layer in the stacked structure, increasing the density of the device, and optimizing the structural layout of the device, thereby improving the performance of the device.

[0047] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0049] Figure 1 The present invention discloses a flow chart of a method for forming a semiconductor structure in an exemplary embodiment.

[0050] Figure 2 It is a schematic structural diagram of a conventional semiconductor structure in an exemplary embodiment of the present disclosure.

[0051] Figure 3 It is a schematic structural diagram of a semiconductor structure forming a stacked structure in an exemplary embodiment of the present disclosure.

[0052] Figure 4 It is a schematic structural diagram of a semiconductor structure for forming a mask structure in an exemplary embodiment of the present disclosure.

[0053] Figure 5 It is a schematic structural diagram of a semiconductor structure for forming a patterned mask structure in an exemplary embodiment of the present disclosure.

[0054] Figure 6 It is a schematic structural diagram of a semiconductor structure in which a first opening is formed in an exemplary embodiment of the present disclosure.

[0055] Figure 7 It is a schematic structural diagram of a semiconductor structure having a first opening with a protection layer formed in an exemplary embodiment of the present disclosure.

[0056] Figure 8 It is a schematic structural diagram of a semiconductor structure having a second opening with a protection layer formed in an exemplary embodiment of the present disclosure.

[0057] Fig. 9 It is a schematic structural diagram of a semiconductor structure having an opening with a protective layer in an exemplary embodiment of the present disclosure.

[0058] Fig.10 It is a schematic structural diagram of a target semiconductor structure in an exemplary embodiment of the present disclosure.

[0059] Fig.11 It is a schematic diagram of the final structure of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0060] Fig.12 It is a schematic structural diagram of a semiconductor structure forming a stacked structure in another exemplary embodiment of the present disclosure.

[0061] Fig.13 It is a structural schematic diagram of a semiconductor structure for forming a mask structure in another exemplary embodiment of the present disclosure.

[0062] Fig.14 It is a schematic structural diagram of a semiconductor structure for forming a patterned mask structure in another exemplary embodiment of the present disclosure.

[0063] Fig.15 It is a schematic structural diagram of a semiconductor structure in which a first opening is formed in another exemplary embodiment of the present disclosure.

[0064] Fig.16 It is a schematic structural diagram of a semiconductor structure having a first opening with a protective layer in another exemplary embodiment of the present disclosure.

[0065] Fig.17 It is a schematic structural diagram of a semiconductor structure having a second opening with a protective layer in another exemplary embodiment of the present disclosure.

[0066] Fig.18 It is a schematic structural diagram of a semiconductor structure having a third opening with a protection layer in another exemplary embodiment of the present disclosure.

[0067] Fig.19 It is a schematic structural diagram of a semiconductor structure having an opening with a protective layer in another exemplary embodiment of the present disclosure.

[0068] Fig. 20 FIG. 4 is a schematic structural diagram of a target semiconductor structure in another exemplary embodiment of the present disclosure.

[0069] Fig.21 It is a schematic diagram of the final structure of a semiconductor structure in another exemplary embodiment of the present disclosure.

[0070] The reference numerals are described as follows:

[0071] 100, substrate; 200, stacked structure; 201, first material layer; 202, second material layer; 203, third material layer; 210, first opening; 220, second opening; 230, third opening; 300, mask structure; 301, first mask layer; 302, second mask layer; 303, photoresist layer; 400, protective layer; 500, etch stop layer; 600, dielectric layer; 700, conductive material layer; 1000, notch; 2000, opening. DETAILED DESCRIPTION

[0072] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0073] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0074] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0075] In the related art, in order to improve the storage density and performance of the memory and to obtain a smaller size, the design of the memory can utilize vertically stacked memory cells to increase the effective storage capacity of the memory, thereby providing more storage space in the same physical space, providing new possibilities for high performance, high density and low power consumption of electronic devices.

[0076] As an indispensable device in memory, capacitors can also be designed in a stacked manner to achieve higher capacitance density, better performance and smaller size. The design of capacitors can utilize the spatial distribution of electrodes and dielectric layers to increase the effective surface area of ​​capacitors, thereby providing higher capacitance values ​​in the same physical space. For example, stacked capacitors are realized by stacking multiple electrodes and dielectric layers in the vertical direction, thereby increasing their capacitance values.

[0077] However, as the number of stacked layers increases, defects often form when deep hole etching is performed, such as when etching film layers of different materials. Figure 2 As shown, due to different etching characteristics, a notch 1000 may exist on the side wall of the deep hole after etching, which may affect the overall performance of subsequent devices and the structural layout of the devices.

[0078] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, combined Figures 3 to 21 The forming method includes: step S10 to step S50.

[0079] Wherein, step S10: forming a stacked structure 200 on a substrate 100, the stacked structure 200 comprising at least one first material layer 201 and at least one second material layer 202 stacked in a direction perpendicular to the substrate 100, the first material layer 201 and the second material layer 202 being made of different materials;

[0080] Step S20: etching the stacked structure 200 using a first etching gas to form a first opening 210 penetrating the second material layer 202, wherein the first etching gas includes fluorine ions;

[0081] Step S30: introducing a first protective gas and a first auxiliary gas into the first opening 210 at the same time and reacting with each other to form a protective layer 400 on the sidewall of the first opening 210, wherein the first protective gas includes silicon ions and the first auxiliary gas includes oxygen ions;

[0082] Step S40: continue to etch the stacked structure 200 using the first etching gas to form a second opening 220 penetrating the first material layer 201 , wherein the second opening 220 at least partially overlaps with the orthographic projection of the first opening 210 on the substrate 100 ;

[0083] Step S50 : introducing the first protective gas and the first auxiliary gas into the second opening 220 at the same time and reacting with each other to form a protective layer 400 on the sidewall of the second opening 220 .

[0084] The method for forming a semiconductor structure provided by the present invention, by introducing a first protective gas and a first auxiliary gas while etching an opening 2000 in a stacked structure 200, the first protective gas and the first auxiliary gas can form a protective layer 400 on the side wall of the opening 2000 to protect the structure of the etched portion of the opening 2000 from being damaged by the etching gas in subsequent etching, thereby making the side wall of the opening 2000 formed in the stacked structure 200 aligned with the substrate 100, breaking the limitation on the number of stacked layers of the film layer in the stacked structure 200, increasing the density of the device, and optimizing the structural layout of the device, thereby improving the performance of the device.

[0085] The following will describe in detail the steps of the method for forming a semiconductor structure provided by the embodiment of the present disclosure in conjunction with the accompanying drawings:

[0086] In the embodiment provided by the present disclosure, in step S10, as Figure 3 As shown, a stacked structure 200 is formed on a substrate 100 , and the stacked structure 200 includes at least one first material layer 201 and at least one second material layer 202 stacked in a direction perpendicular to the substrate 100 , and the first material layer 201 and the second material layer 202 are made of different materials.

[0087] Wherein, the substrate 100 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs). The embodiments provided in the present disclosure are described by taking the substrate 100 as a substrate including silicon (Si) ions as an example. Of course, for other types of substrates, corresponding deformations or improvements can be made to the embodiments of the present disclosure, all of which are within the protection scope of the present disclosure.

[0088] A stacking structure 200 is formed on a substrate 100, and the stacking structure 200 includes at least one first material layer 201 and at least one second material layer 202, wherein the number of the first material layer 201 and the second material layer 202 in the stacking structure 200 can be selected according to the actual design requirements of the device structure, for example, the number of the first material layer 201 and the second material layer 202 can be one, two, four, six, eight or even more, respectively, and the more the number of material layers of the stacking structure 200 is, the greater the arrangement density of the formed device structure is. The first material layer 201 and the second material layer 202 are made of different materials.

[0089] In the present disclosure, the first material layer 201 may be a conductive layer, a dielectric layer 600 or a semiconductor layer, and its material may be a metal, such as tungsten (W), copper (Cu), etc.; or a semiconductor layer, such as polysilicon (poly), etc.; or a dielectric layer 600, such as silicon nitride (SiN x ) etc. The second material layer 202 may be an isolation layer or an insulating layer, such as silicon oxide (SiO x In the following embodiments, the first material layer 201 is made of metal tungsten and the second material layer 202 is made of silicon oxide. When the first material layer 201 and the second material layer 202 are made of other materials, the following embodiments can be adaptively modified and all are within the protection scope of the present disclosure.

[0090] The first material layer 201 can be formed by chemical vapor deposition (CVD), such as atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD); or physical vapor deposition (PVD), such as sputtering, electron beam evaporation (E-beam Evaporation); or atomic layer epitaxy (ALE); or chemical vapor infiltration (CVI). The second material layer 202 can be formed by one or more of the above methods, which will not be repeated here.

[0091] In the embodiments provided in the present disclosure, Figure 3 As shown, before step S10, the formation method further includes: forming an etch stop layer 500 on the substrate 100, and the stacked structure 200 is formed on a side of the etch stop layer 500 away from the substrate 100. The etch stop layer 500 covers the surface of the substrate 100, and when the stacked structure 200 is etched, since the etch stop layer 500 has a smaller etching selectivity relative to the substrate 100 and the film layer in the stacked structure 200, the etch stop layer 500 can protect the film layer thereunder from being damaged, thereby ensuring the integrity of the structure and the accuracy of the process.

[0092] The etching stop layer 500 can be made of aluminum oxide (AlO x ), titanium nitride (TiN) and other materials, and its thickness can be 20nm (nanometer) to 100nm (nanometer), such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc. Its thickness can be adaptively selected according to the thickness of the film layer located thereon and the etching method to ensure the protection of the film layer thereunder by the etching stop layer 500.

[0093] After the opening 2000 penetrating the stacked structure 200 is subsequently formed, in order to ensure the vertical size of the opening 2000, the opening 2000 may extend to the inside of the etching stop layer 500 or penetrate the etching stop layer 500. Of course, the bottom of the opening 2000 may also be flush with the surface of the etching stop layer 500, and the opening 2000 only needs to expose the surface of the etching stop layer 500.

[0094] The substrate 100 below the etching stop layer 500 may further include a circuit layer (not shown in the figure), and the circuit layer may include a driving circuit or a wire wiring structure. The opening 2000 may penetrate the etching stop layer 500, so that the opening 2000 is connected to the circuit layer, and the device located on the etching stop layer 500 may be electrically connected to the circuit layer through the opening 2000. Of course, it is also possible to form an electrical connection with the circuit layer by forming other structures on the semiconductor structure, such as through structures such as conductive leads, and the opening 2000 does not need to penetrate the etching stop layer 500, which is not described in detail here.

[0095] In the embodiment provided by the present disclosure, after step S10, the forming method further includes: Figure 4 As shown, a mask structure 300 is formed on a side of the stack structure 200 away from the substrate 100 , and the mask structure 300 includes a first mask layer 301 and a second mask layer 302 , and the first mask layer 301 and the second mask layer 302 are made of different materials.

[0096] Among them, the first mask layer 301 is formed on the side of the stacked structure 200 away from the substrate 100. The first mask layer 301 can be a bottom anti-reflective coating (BARC), a photoresist anti-reflective coating (APF), a top anti-reflective coating (TARC), an organic anti-reflective coating (OARC), an inorganic anti-reflective coating (IARC) or a self-anti-reflective photoresist, etc., which is used to reduce or eliminate the reflection problem in the photolithography process, thereby improving the accuracy and resolution of the pattern transfer. The first mask layer 301 can be positive or negative, and can be selected according to the type of subsequent photoresist and the photolithography process requirements.

[0097] The second mask layer 302 may be made of materials such as aluminum oxide (AlOx) or titanium nitride (TiN). Figure 5As shown, the formation method further includes: forming a photoresist layer 303 on a side of the second mask layer 302 away from the substrate 100; patterning the photoresist layer 303; etching the second mask layer 302 using the patterned photoresist layer 303 to form a patterned second mask layer 302. The patterned second mask layer 302 can select a corresponding etchant according to its material. In some embodiments, when the second mask layer 302 can be aluminum oxide, dry etching can be selected, and the etchant can be chlorine and boron trichloride; in some embodiments, the second mask layer 302 can also be wet etched for patterning.

[0098] In the present disclosure, after the mask structure 300 is formed, when the stack structure 200 is subsequently etched, the patterned mask structure 300 can be used as a mask to perform etching in a preset direction within the stack structure 200 .

[0099] In the embodiments provided in the present disclosure, Figure 6 As shown, in step S20 , the stack structure 200 is etched using a first etching gas to form a first opening 210 penetrating the second material layer 202 , wherein the first etching gas includes fluorine ions.

[0100] The first etching gas may be C X F Y , S X F Y 、N X F Y , wherein X is a positive integer greater than or equal to 1, and Y is a positive integer greater than or equal to 1. Specifically, the first etching gas may be one or more of etching gases containing fluoride ions such as CF4, C4F6, C4F8, SF6 or NF3.

[0101] The first etching gas is C X F Y For example, the second material layer 202 on the top of the stacked structure 200 is etched using the patterned mask structure 300 and the first etching gas, wherein the first etching gas is decomposed into carbon ions and fluorine ions through the reaction chamber, and the second material layer 202 is bombarded by the fluorine ions to etch the second material layer 202, wherein SiO2+F - →SiF4↑+O2↑, SiF4 and O2 can be extracted in the form of gas, thereby etching the silicon dioxide film layer to form a first opening 210 in the second material layer 202. In some embodiments, the oxygen in the mixed gas of SiF4 and O2 can be purified and reused to form a recycling of resources, which is beneficial to environmental protection.

[0102] In the embodiments provided in the present disclosure, Figure 7As shown, in step S30 , a first protective gas and a first auxiliary gas are simultaneously introduced into the first opening 210 and reacted to form a protective layer 400 on the sidewall of the first opening 210 , wherein the first protective gas includes silicon ions and the first auxiliary gas includes oxygen ions.

[0103] The first protective gas may be at least one of silicon tetrachloride (SiCl4), monosilane (SiH4), silylene (SiH2), disilane (Si2H6) or silicate, wherein silicate is a salt containing silicon ions, and its composition can be determined according to actual use requirements. The first auxiliary gas may be at least one of oxygen (O2), methanol (CH3OH) or ethanol (C2H5OH).

[0104] Taking the case where the first protective gas is silicon tetrachloride (SiCl4) and the first auxiliary gas is oxygen (O2) as an example, the first protective gas and the first auxiliary gas react to form a protective layer 400, and the protective layer 400 is attached to the side wall of the first opening 210, wherein the reaction process is SiCl4+O2→SiO2+Cl2↑, wherein silicon dioxide forms the protective layer 400, and the chlorine is drawn away, and in the subsequent etching process, the protective layer 400 can ensure that the side wall shape of the first opening 210 is not destroyed, thereby ensuring the integrity of the first opening 210. Of course, the chlorine can also be separated and recycled.

[0105] Similarly, if the first protective gas and the first auxiliary gas are other gases, the reaction process includes Si + +O - →SiO 2 chemical reaction, and the generated byproducts can be pumped away or vaporized, so that silicon dioxide is deposited on the sidewalls of the first opening 210 to form a protection layer 400 .

[0106] It should be noted that when the protective layer 400 is formed on the sidewall of the first opening 210, due to process limitations, the protective layer 400 is also formed on the bottom of the first opening 210 (the surface of the first material layer 201). Figures 7 to 9 as well as Figures 16 to 19 As shown, when the first material layer 201 is subsequently etched, the protective layer 400 at the bottom of the first opening 210 is removed at the same time. In addition, a protective layer 400 is also formed on the sidewall and top surface of the mask structure 300 (not shown in the drawings), but it does not affect the protective effect of the protective layer 400 on the sidewall of the opening 2000. In the subsequent process step of removing the protective layer 400, the protective layer 400 formed on the surface and sidewall of the mask structure 300 can be removed at the same time.

[0107] In some embodiments, there may be two entry nodes for the first auxiliary gas and the first protective gas in the first opening 210, wherein the first entry node may be, after the first opening 210 is formed, a mixed gas of the above two gases is introduced into the first opening 210, so that the two gases react to form a protective layer 400 to cover the side wall of the first opening 210, and this method may simplify the process; the second method may be, in the process of forming the first opening 210, passing the mixed gas of the two gases through the formed part of the first opening 210, that is, passing the first auxiliary gas and the first mixed gas through the process of etching the second material layer 202, so as to form a protective layer 400 during the etching process, and this method may improve the alignment of the side wall of the opening. Of course, for different second material layers 202, the same entry node may be used, or different entry nodes may be used, which may be selected as needed according to the actual process.

[0108] In the embodiment provided in the present disclosure, the reaction conditions of the first auxiliary gas and the first protective gas are as follows:

[0109] The gas flow rate of the first shielding gas is 10 sccm (cubic centimeters per minute) to 100 sccm, for example, it can be 10 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, etc. The gas flow rate of the first auxiliary gas is 100 sccm to 500 sccm, for example, it can be 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, etc. The flow rates of the first shielding gas and the first auxiliary gas can be adaptively adjusted within the above range according to actual process requirements.

[0110] The reaction pressure is 5 mT (milliton force per square meter) to 30 mT, for example, 5 mT, 10 mT, 15 mT, 20 mT, 25 mT, 30 mT, etc. The reaction pressure can be selected and adjusted according to actual process requirements.

[0111] The reaction bias voltage is 1000W (watt) to 1500W, for example, it can be 1000W, 1100W, 1200W, 1300W, 1400W, 1500W, etc. The reaction bias voltage can be adaptively selected and adjusted according to actual process requirements.

[0112] In the embodiments provided in the present disclosure, Figure 8 As shown, in step S40 , the stacked structure 200 is further etched using the first etching gas to form a second opening 220 penetrating the first material layer 201 , and the second opening 220 at least partially overlaps with the orthographic projection of the first opening 210 on the substrate 100 .

[0113] The first material layer 201 is further etched by the first etching gas, wherein the first etching gas is decomposed into carbon ions and fluorine ions by the reaction chamber, and the first material layer 201 is bombarded by the fluorine ions to etch the first material layer 201, wherein W+F - →WF6↑, WF6 is pumped away in the form of gas, thereby etching tungsten to form a second opening 220 in the first material layer 201.

[0114] Since the materials of the first material layer 201 and the second material layer 202 are different, their etching selectivity ratios are different under the same etching gas and etching conditions, resulting in that the formation of the first opening 210 and the second opening 220 cannot be completely consistent or similar, especially since the second material layer 202 tends to be anisotropic in its etching characteristics, and the sidewalls of the formed first opening 210 are relatively straight, while the first material layer 201 tends to be isotropic in its etching characteristics, and the sidewall profile of the formed second opening 220 is curved, that is, the orthographic projections of the first opening 210 and the second opening 220 on the substrate 100 have overlapping parts.

[0115] In order to improve the overall structure and shape of the opening 2000, a protective layer 400 can be formed on the side walls of the second opening 220 when etching the first material layer 201, so as to prevent the first etching gas from continuing to etch the side walls of the second opening 220 when etching the first material layer 201, thereby preventing the side walls of the second opening 220 from bending.

[0116] In the embodiments provided in the present disclosure, Figure 8 As shown, in step S50 , the first protective gas and the first auxiliary gas are introduced into the second opening 220 and reacted to form a protective layer 400 on the sidewall of the second opening 220 .

[0117] After the second opening 220 is formed in the first material layer 201, the first protective gas and the first auxiliary gas are introduced into the second opening 220, and the first protective gas and the first auxiliary gas are allowed to react, wherein the reaction process is SiCl4+O2→SiO2+Cl2↑, wherein silicon dioxide forms a protective layer 400, and the chlorine gas is extracted, and in the subsequent etching process, the protective layer 400 can ensure that the side wall shape of the second opening 220 is not destroyed, thereby ensuring the integrity of the second opening 220.

[0118] In addition, the first protective gas and the first auxiliary gas used here are the same as or similar to the first protective gas and the first auxiliary gas introduced into the first opening 210 , and their specific types and reaction conditions are not described in detail.

[0119] In some embodiments, there may be two entry nodes for the first auxiliary gas and the first protective gas in the second opening 220, wherein the first entry node may be, after forming the second opening 220, to introduce a mixed gas of the above two gases into the second opening 220, so that the two gases react to form a protective layer 400 to cover the side wall of the second opening 220, and this method may simplify the process; the second entry node may be, in the process of forming the second opening 220, to pass the mixed gas of the two gases through the formed part of the second opening 220, that is, in the process of etching the first material layer 201, to pass the first auxiliary gas and the first mixed gas to form a protective layer 400 during the etching process, and this method may ensure that the collimation of the formed opening side wall is higher. Of course, for different first material layers 201, the same entry node may be used, or different entry nodes may be used, which may be selected as needed according to the actual process.

[0120] And so on, such as Fig. 9 As shown, the protective layer 400 formation process provided by the above embodiment can be alternately implemented in multiple film layer pairs, and each time a film layer is etched, a protective layer 400 will be formed in the film layer where the opening 2000 has been formed, so as to protect the sidewall shape of the opening 2000 from being damaged by the subsequent etching process, thereby ensuring the integrity of the opening 2000. In particular, when a high-aspect ratio contact (HARC) is formed in a semiconductor structure, the formation method provided by the present disclosure can ensure the structural integrity and alignment of the HARC, and provide a good structural foundation for the formation of subsequent devices.

[0121] The aspect ratio of the HARC structure described above can be understood to be greater than or equal to 5:1, which can meet the aspect ratio requirement of the HARC structure. Of course, different aspect ratios can be selected according to the actual design requirements of the device.

[0122] Further, such as Figures 12 to 21 As shown, in order to increase the adhesion between the first material layer 201 and the second material layer 202, a third material layer 203 may be formed between the first material layer 201 and the second material layer 202, wherein the materials of the first material layer 201, the second material layer 202 and the third material layer 203 are different.

[0123] The third material layer 203 can be made of materials such as titanium nitride (TiN), which can be formed by chemical vapor deposition (CVD), such as plasma-enhanced chemical vapor deposition (PECVD); or physical vapor deposition (PVD), such as sputtering, electron beam evaporation (E-beam Evaporation), ion plating (Ion Plating); or atomic layer deposition (ALD); or electrochemical deposition; or laser cladding and other methods.

[0124] It should be noted that the third material layer 203 is formed between at least one pair of first material layers 201 and second material layers 202. For example, the third material layer can be formed between each pair of adjacent film layers in the stacked structure 200, or can be located between some adjacent film layers. The formation position of the third material layer 203 can be adaptively arranged according to the actual structure.

[0125] like Figures 15 to 18 As shown, when the stacked structure 200 includes the third material layer 203, the method further includes:

[0126] The third material layer 203 is etched using a second etching gas to form a third opening 230 that penetrates the third material layer 203, and the orthographic projections of the first opening 210, the second opening 220 and the third opening 230 on the substrate 100 at least partially overlap, wherein the second etching gas includes chloride ions; the first auxiliary gas and the first protective gas are introduced into the third opening 230 and reacted to form a protective layer 400 on the side wall of the third opening 230.

[0127] The second etching gas may be chlorine. When forming the third opening 230, the third material layer 203 may be etched by chlorine. The reaction process may include W+Cl － →WCl4↑, tungsten tetrachloride is extracted to form a third opening 230 penetrating the third material layer 203 .

[0128] After the third opening 230 is formed, the first protective gas and the first auxiliary gas are introduced into the third opening 230, and the first protective gas and the first auxiliary gas are allowed to react, wherein the reaction process is SiCl4+O2→SiO2+Cl2↑, wherein silicon dioxide forms a protective layer 400, and the chlorine gas can be reused. In the subsequent etching process, the protective layer 400 can ensure that the side wall shape of the third opening 230 is not destroyed, thereby ensuring the integrity of the third opening 230.

[0129] In some embodiments, there may be two entry nodes for the first auxiliary gas and the first protective gas in the third opening 230, wherein the first entry node may be, after the third opening 230 is formed, a mixed gas of the above two gases is introduced into the third opening 230, so that the two gases react to form a protective layer 400 to cover the side wall of the third opening 230, and this method may simplify the process engineering; the second method may be, in the process of forming the third opening 230, passing the mixed gas of the two gases through the formed part of the third opening 230, that is, passing the first auxiliary gas and the first mixed gas in the process of etching the third material layer 203, so as to form a protective layer 400 in the etching process, and this method may ensure that the collimation of the formed opening side wall is higher. Of course, for different third material layers 203, the same entry node may be used, or different entry nodes may be used, which may be selected as needed according to the actual process.

[0130] In the embodiments provided in the present disclosure, Fig.10 and Fig. 20 As shown, after the opening 2000 penetrating the stacked structure 200 is formed, the forming method further includes: removing the protection layer 400 , forming an opening 2000 with aligned sidewalls and penetrating the stacked structure 200 in the stacked structure 200 , so as to form a target semiconductor structure.

[0131] It should be noted that, in the present disclosure, the sidewall alignment of the opening 2000 may refer to the sidewall of the opening 2000 being perpendicular to the surface of the substrate 100. The vertical mentioned here may refer to vertical in a strict sense, that is, the sidewall of the opening 2000 is strictly 90 degrees to the substrate 100; it may also refer to approximately vertical. Due to process limitations, the sidewall of the opening 2000 may be approximately perpendicular to the substrate 100, such as the angle between the two may be between 85 degrees and 105 degrees, and the sidewall of the opening 2000 may be considered to be aligned.

[0132] The protective layer 400 may be removed by wet chemical etching, dry chemical etching or the like. For example, when wet chemical etching is used, hydrofluoric acid (HF) or a mixed solution thereof (such as buffered hydrofluoric acid, BHF) may be used to etch silicon dioxide.

[0133] In the embodiments provided in the present disclosure, Fig.10 and Fig. 20As shown, the formation method further includes: removing the mask structure 300 to expose the surface of the stacked structure 200. Removing the mask structure 300 includes removing the first mask layer 301 and the second mask layer 302. For example, chemical mechanical polishing (CMP), wet chemical etching, dry chemical etching and other methods can be used, and the corresponding removal method can be used according to the specific material selected for the mask structure 300.

[0134] In the embodiments provided in the present disclosure, Fig.11 and Fig.21 As shown, the forming method may further include: conformally forming a dielectric layer 600 in the opening 2000 of the target semiconductor structure; and forming a conductive material layer 700 in the opening 2000 so that a surface of the conductive material layer 700 is flush with a surface of the stacked structure 200 .

[0135] The dielectric layer 600 may be a high dielectric constant film layer such as hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium aluminate (HfAlO), zirconium hafnium oxide (ZrHfO), strontium titanate (SrTiO3), strontium niobate (SrNbO3), strontium tantalate (SrTaO3) or barium strontium titanate (BaTiO3). The conductive material layer 700 may be aluminum (Al), copper (Cu), gold (Au), tungsten (W) or titanium (Ti).

[0136] The present invention provides a method for forming a semiconductor structure. By introducing a first protective gas and a first auxiliary gas while etching an opening 2000 in a stacked structure 200, the first protective gas and the first auxiliary gas can form a protective layer 400 on the side wall of the opening 2000 to protect the structure of the etched portion of the opening 2000 from being damaged by the etching gas in subsequent etching, thereby making the side wall of the opening 2000 formed in the stacked structure 200 aligned with the substrate 100, breaking the limitation on the number of stacked layers of the film layer in the stacked structure 200, increasing the density of the device, and optimizing the structural layout of the device, thereby improving the performance of the device.

[0137] It should be noted that, although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0138] The present disclosure also provides a semiconductor structure, such as Fig.10 As shown, the semiconductor structure includes: a substrate 100 , a stacked structure 200 and an opening 2000 .

[0139] Among them, the stacking structure 200 is formed on the substrate 100, and the stacking structure 200 includes at least one first material layer 201 and at least one second material layer 202 stacked in a direction perpendicular to the substrate 100, and the materials of the first material layer 201 and the second material layer 202 are different; the opening 2000 runs through the stacking structure 200, and the opening 2000 includes a first opening 210 and a second opening 220, the first opening 210 runs through the second material layer 202, and the second opening 220 runs through the first material layer 201; the first opening 210 coincides with the orthographic projection of the second opening 220 having the protective layer 400 on the substrate 100, and the side wall of the opening 2000 is aligned with the surface of the substrate 100.

[0140] The semiconductor structure provided by the present disclosure has an opening 2000 penetrating the stacked structure 200 with straight sidewalls, and has good device structure integrity and good functionality.

[0141] In the embodiments provided in the present disclosure, Fig.21 As shown, the stacked structure 200 also includes a third material layer 203, which is formed between the first material layer 201 and the second material layer 202. The opening 2000 also includes a third opening 230, which passes through the third material layer 203. The sidewalls of the third opening 230 include a protective layer 400. The first opening 210 with the protective layer 400 and the third opening 230 with the protective layer 400 have their orthographic projections on the substrate 100 coincide with each other, so as to ensure the integrity and alignment of the opening 2000 formed in the stacked structure 200.

[0142] The semiconductor structure provided in the present disclosure can be formed by the above-mentioned method for forming a semiconductor structure, and the specific structure of the semiconductor structure can refer to the embodiment content provided in the formation method part.

[0143] The semiconductor structure provided by the present disclosure can be applied to memories such as dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory. Of course, it can also be applied to other storage devices not listed here, which will not be listed one by one.

[0144] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming a stacked structure on a substrate, the stacked structure comprising at least one first material layer and at least one second material layer stacked in a direction perpendicular to the substrate, the first material layer and the second material layer being made of different materials; Etching the stacked structure using a first etching gas to form a first opening penetrating the second material layer, wherein the first etching gas includes fluorine ions; A first protective gas and a first auxiliary gas are introduced into the first opening at the same time and reacted to form a protective layer on the sidewall of the first opening, wherein the first protective gas includes silicon ions and the first auxiliary gas includes oxygen ions; Continue etching the stacked structure using the first etching gas to form a second opening penetrating the first material layer, wherein the second opening at least partially overlaps with an orthographic projection of the first opening on the substrate; The first protective gas and the first auxiliary gas are introduced into the second opening simultaneously and react with each other to form the protective layer on the side wall of the second opening.

2. The method for forming a semiconductor structure according to claim 1, wherein: The stacked structure further includes a third material layer, the third material layer is located between at least one pair of the first material layer and the second material layer, the first material layer, the second material layer and the third material layer are made of different materials, and the method further includes: Etching the third material layer using a second etching gas to form a third opening penetrating the third material layer, wherein the first opening, the second opening, and the third opening have orthographic projections on the substrate at least partially overlap, wherein the second etching gas includes chloride ions; The first auxiliary gas and the first protective gas are introduced into the third opening and react with each other to form the protective layer on the side wall of the third opening.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method comprises: After forming the first opening, simultaneously introducing the first protective gas and the first auxiliary gas into the first opening; Alternatively, during the process of forming the first opening, the first protective gas and the first auxiliary gas are continuously introduced into the formed first opening simultaneously.

4. The method for forming a semiconductor structure according to claim 2, wherein: The method comprises: After forming the second opening, simultaneously introducing the first protective gas and the first auxiliary gas into the second opening; Or, during the process of forming the second opening, the first protective gas and the first auxiliary gas are continuously introduced into the formed second opening simultaneously.

5. The method for forming a semiconductor structure according to claim 2, wherein: The method comprises: After forming the third opening, simultaneously introducing the first protective gas and the first auxiliary gas into the third opening; Alternatively, during the process of forming the third opening, the first protective gas and the first auxiliary gas are continuously introduced into the formed third opening simultaneously.

6. The method for forming a semiconductor structure according to claim 2, wherein: The method further comprises: The protection layer is removed, and an opening having aligned sidewalls and penetrating the stack structure is formed in the stack structure to form a target semiconductor structure.

7. The method for forming a semiconductor structure according to claim 2, wherein: After forming the stacked structure on the substrate, the method further includes: forming a mask structure on a side of the stacked structure away from the substrate, the mask structure comprising a first mask layer and a second mask layer, the first mask layer and the second mask layer being made of different materials; The stacked structure is etched using the mask structure, the first etching gas, and the second etching gas.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: The method comprises: forming a photoresist layer on a side of the second mask layer away from the substrate; patterning the photoresist layer; The second mask layer is etched using the patterned photoresist layer to form a patterned second mask layer.

9. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the stacked structure, the method further includes: forming an etching stop layer on the substrate, wherein the stacked structure is formed on a side of the etching stop layer away from the substrate; After forming an opening penetrating the stack structure, the opening extends into the etch stop layer or the opening penetrates the etch stop layer.

10. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that: The gas flow rate of the first protective gas is 10 sccm to 100 sccm, and the gas flow rate of the first auxiliary gas is 100 sccm to 500 sccm.

11. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that: The method comprises: Under the condition of a pressure of 5 mT to 30 mT, the first auxiliary gas reacts with the first protective gas.

12. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that: The method comprises: Under the condition that the bias voltage is 1000W-1500W, the first auxiliary gas reacts with the first protective gas.

13. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that: The first protective gas includes at least one of silicon tetrachloride, monosilane, silylene, disilane or silicate.

14. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that: The first auxiliary gas includes at least one of oxygen, methanol or ethanol.

15. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that: The first etching gas includes C X F Y , S X F Y 、N X F Y , wherein X is a positive integer greater than or equal to 1, and Y is a positive integer greater than or equal to 1.

16. The method for forming a semiconductor structure according to any one of claims 2 to 8, characterized in that: The second etching gas includes chlorine gas.

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