Preparation method of semiconductor structure

Abstract

A preparation method of a semiconductor structure comprises the steps that a substrate is provided, an interconnection conducting layer is embedded in the substrate, the surface of the interconnection conducting layer is exposed out of the substrate, a stacking layer covering the substrate is formed on the substrate, and a through hole penetrating through the stacking layer and exposed out of the surface of the interconnection conducting layer is formed in the stacking layer; forming a side wall material layer at least covering the side wall and the bottom of the through hole, wherein the material of the side wall material layer is silicon oxide; forming a protective material layer covering the side wall material layer, wherein the protective material layer is made of amorphous silicon; performing heat treatment on the protective material layer to enable the protective material layer to realize a material phase change process; etching to remove the material above the interconnection conducting layer at the bottom of the through hole so as to expose the surface of the interconnection conducting layer, taking the side wall material layer covering the side wall of the through hole as a side wall layer, and taking the residual protection material layer covering the side wall layer as a protection layer; and removing the protective layer. The working performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] Pillar electrical connection structure plays an important role in electronic devices, especially in situations where high density, high reliability and stable electrical connection are required. It is widely used in integrated circuits, semiconductor devices, packaging technology and other fields, providing strong support for the performance improvement and reliability guarantee of electronic products.

[0003] With the rapid development of electronic technology, columnar electrical connection structures have also undergone continuous technological innovation and optimization. From the initial simple columnar structure to the current complex three-dimensional structure, its performance and reliability have been significantly improved. At the same time, with the continuous progress of material science, nanotechnology and precision manufacturing technology, the design and manufacture of columnar electrical connection structures have become more sophisticated and efficient. Summary of the invention

[0004] An embodiment of the present invention provides a method for preparing a semiconductor structure, so as to at least partially solve the technical problems existing in the existing method for preparing a columnar electrical connection structure and improve the working performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for preparing a semiconductor structure, comprising: providing a substrate, in which an interconnection conductive layer is embedded, the substrate exposes the surface of the interconnection conductive layer, a stacking layer covering the substrate is formed on the substrate, and a through hole penetrating the stacking layer and exposing the surface of the interconnection conductive layer is formed in the stacking layer; forming a sidewall material layer covering at least the sidewall and bottom of the through hole, the sidewall material layer is made of silicon oxide; forming a protective material layer covering the sidewall material layer, the protective material layer is made of amorphous silicon; heat-treating the protective material layer to enable the protective material layer to achieve a material phase change process; etching and removing the material at the bottom of the through hole above the interconnection conductive layer to expose the surface of the interconnection conductive layer, while the sidewall material layer covering the sidewall of the through hole serves as the sidewall layer, and the remaining protective material layer covering the sidewall layer serves as the protective layer; and removing the protective layer.

[0006] Optionally, in the step of heat treating the protective material layer, the material of the protective material layer is converted from amorphous silicon to polycrystalline silicon.

[0007] Optionally, in the step of heat-treating the protective material layer, the heat treatment includes rapid thermal treatment.

[0008] Optionally, after the protective material layer is heated and before the material at the bottom of the through hole above the interconnect conductive layer is etched away, the preparation method also includes: oxidizing the protective material layer to completely oxidize the protective material layer at the bottom of the through hole and partially oxidize the protective material layer on the side wall of the through hole to form a sacrificial layer, and the sacrificial layer at least covers the remaining protective material layer on the side wall of the through hole.

[0009] Optionally, the step of etching away the material at the bottom of the through hole above the interconnect conductive layer includes: etching away the sacrificial layer and the sidewall material layer at the bottom of the through hole.

[0010] Optionally, in the step of oxidizing the protective material layer, the material of the sacrificial layer is the same as that of the sidewall material layer; and the sacrificial layer and the sidewall material layer at the bottom of the through hole are etched away in the same process.

[0011] Optionally, the step of oxidizing the protective material layer includes: oxidizing the protective material layer using an in-situ steam oxidation process or a furnace tube oxidation process.

[0012] Optionally, a wet etching process is used to remove the sacrificial layer and the sidewall material layer at the bottom of the through hole.

[0013] Optionally, before the protective material layer is oxidized, the method further includes: forming a buffer layer covering the protective material layer; and the step of etching away the sacrificial layer and the sidewall material layer at the bottom of the through hole further includes: removing the buffer layer.

[0014] Optionally, in the step of forming a buffer layer covering the protective material layer, the material of the buffer layer includes any one of silicon oxide, silicon nitride and silicon oxynitride.

[0015] Optionally, the step of oxidizing the protective material layer includes: forming a buffer layer covering the protective material layer, the material of the buffer layer is an oxide material, and while forming the buffer layer, the buffer layer is diffused and oxidized into the protective material layer to completely oxidize the protective material layer at the bottom of the through hole and partially oxidize the protective material layer on the side wall of the through hole to form a sacrificial layer; the step of etching to remove the sacrificial layer and the side wall material layer at the bottom of the through hole also includes: removing the buffer layer.

[0016] Optionally, an atomic layer deposition process is used to form a buffer layer covering the protective material layer.

[0017] Optionally, in the step of forming a buffer layer covering the protective material layer, the material of the buffer layer is the same as that of the sacrificial layer; and the sacrificial layer and the buffer layer are removed in the same process.

[0018] Optionally, an atomic layer deposition process is used to form a sidewall material layer that at least covers the sidewall and bottom of the through hole.

[0019] Optionally, a chemical vapor deposition process is used to form a protective material layer covering the sidewall material layer.

[0020] Optionally, a wet etching process is used to remove the protective layer.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0022] In the preparation method provided by the embodiment of the present invention, a protective material layer covering the sidewall material layer is formed, the material of the protective material layer is amorphous silicon, the protective material layer is heat-treated to enable the protective material layer to realize a material phase change process, and the material located above the interconnection conductive layer at the bottom of the through hole is etched away to expose the surface of the interconnection conductive layer; in the embodiment of the present invention, before etching away the material located above the interconnection conductive layer at the bottom of the through hole, the protective material layer is heat-treated to enable the protective material layer to realize a material phase change process, which is beneficial to eliminate pinhole defects in the protective material layer through lattice reorganization during the transformation process from amorphous silicon to polycrystalline silicon, and improve the film forming effect of the protective material layer. In the step of etching away the material located above the interconnection conductive layer at the bottom of the through hole to expose the surface of the interconnection conductive layer, the protective effect of the protective material layer on the sidewall of the through hole on the sidewall material layer is improved, and the damage to the sidewall material layer on both sides of the bottom of the through hole due to the pinhole defects when removing the protective material layer and the sidewall material layer at the bottom of the through hole is avoided or improved, thereby facilitating improving the film quality of the sidewall layer, reducing or avoiding leakage, and further facilitating improving the working performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in the method for preparing a semiconductor structure in the prior art;

[0024] Figures 6 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for preparing a semiconductor structure of the present invention;

[0025] Figures 13 to 15 is a schematic structural diagram corresponding to each step in another embodiment of a method for preparing a semiconductor structure of the present invention;

[0026] Fig.16 It is a schematic structural diagram corresponding to each step in another embodiment of the method for preparing a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, it is currently difficult to improve the working performance of semiconductor structures. Now, in combination with a method for preparing a semiconductor structure, the reasons why the working performance of the semiconductor structure still needs to be improved are analyzed.

[0028] Figures 1 to 5 The present invention is a schematic diagram of structures corresponding to each step in a method for preparing a semiconductor structure.

[0029] refer to Figure 1 A substrate 10 is provided, in which an interconnection conductive layer 11 is embedded, the surface of the interconnection conductive layer 11 is exposed on the substrate 10, a stacking layer 20 covering the substrate 10 is formed on the substrate 10, and a through hole 21 is formed in the stacking layer 20 that penetrates the stacking layer 20 and exposes the surface of the interconnection conductive layer 11.

[0030] refer to Figure 2 , forming a spacer material layer 30 that at least covers the sidewall and bottom of the through hole 21, and the material of the spacer material layer 30 is silicon oxide.

[0031] refer to Figure 3 , forming a protection material layer 40 covering the spacer material layer 30 , wherein the material of the protection material layer 40 is amorphous silicon.

[0032] refer to Figure 4 , the material at the bottom of the through hole 21 located above the interconnect conductive layer 11 is etched away to expose the surface of the interconnect conductive layer 11, and at the same time, the sidewall material layer 30 covering the sidewall of the through hole 21 serves as the sidewall layer 31, and the protective material layer 40 covering the sidewall layer 31 serves as the protective layer 41.

[0033] Since the material of the protective material layer 40 is amorphous silicon, and since the depth-to-width ratio and size (CD) of the through hole 21 are relatively large, the thickness of the amorphous silicon protective material layer 40 is usually relatively thin, and there will be film discontinuity, that is, pinhole defects will exist on the film layer. During the process of dry etching to remove the material located above the interconnect conductive layer 11 at the bottom of the through hole 21, the protective effect of the protective material layer 40 on the side wall material layer 30 is relatively weak, and the side wall material layer 30 can be damaged by dry etching through the pinholes.

[0034] Moreover, dry etching is required to remove the material located above the interconnection conductive layer 11 at the bottom of the through hole 21, and etching residues caused by dry etching are likely to remain at the bottom of the through hole 21. Therefore, cleaning treatment is required before the subsequent removal of the protective layer 41. The film layer of the protective layer 41 has pinhole defects. During the cleaning treatment, the cleaning liquid is likely to penetrate the protective layer 41 and damage the sidewall layer 31. When the protective layer 41 is subsequently removed by wet etching, the etching liquid is also likely to penetrate the protective layer 41 and damage the sidewall layer 31. In addition, dry etching is used to remove the material located above the interconnection conductive layer 11 at the bottom of the through hole 21. The size of the interconnection conductive layer 11 exposed by opening the bottom of the through hole 21 varies greatly in different regions, which affects the process size accuracy of the material located above the interconnection conductive layer 11 except for the bottom of the through hole 21, resulting in poor uniformity of the size of the interconnection conductive layer 11 exposed at the bottom of the through hole 21 in different regions, which results in poor consistency of contact resistance when the subsequent interconnection conductive layer 11 is electrically connected through the bottom of the through hole 21, affecting the working performance of the semiconductor structure.

[0035] refer to Figure 5 , remove the protective layer 41.

[0036] After removing the protective layer 41, the interconnected conductive layer 11 is electrically connected through the bottom of the through hole 21. Damage to the sidewall layer 31 can easily lead to poor protection of the interconnected conductive layer 11 being electrically connected through the bottom of the through hole 21, thereby affecting the working performance of the semiconductor structure.

[0037] In order to solve the technical problem, an embodiment of the present invention provides a method for preparing a semiconductor structure, including: providing a substrate, in which an interconnection conductive layer is embedded, the substrate exposes the surface of the interconnection conductive layer, a stacking layer covering the substrate is formed on the substrate, and a through hole penetrating the stacking layer and exposing the surface of the interconnection conductive layer is formed in the stacking layer; forming a sidewall material layer covering at least the sidewall and bottom of the through hole, the material of the sidewall material layer is silicon oxide; forming a protective material layer covering the sidewall material layer, the material of the protective material layer is amorphous silicon; heat treating the protective material layer to enable the protective material layer to realize a material phase change process; etching and removing the material at the bottom of the through hole above the interconnection conductive layer to expose the surface of the interconnection conductive layer, while the sidewall material layer covering the sidewall of the through hole serves as the sidewall layer, and the remaining protective material layer covering the sidewall layer serves as the protective layer; removing the protective layer.

[0038] In an embodiment of the present invention, before etching away the material located above the interconnection conductive layer at the bottom of the through hole, the protective material layer is heat treated to cause the protective material layer to realize a material phase change process, which is beneficial to eliminating pinhole defects in the protective material layer through lattice reorganization during the transformation from amorphous silicon to polycrystalline silicon, and improving the film-forming effect of the protective material layer. Then, in the step of etching away the material located above the interconnection conductive layer at the bottom of the through hole to expose the surface of the interconnection conductive layer, the protective effect of the protective material layer on the side wall of the through hole on the side wall material layer is improved, and damage to the side wall material layers on both sides of the bottom of the through hole due to pinhole defects when removing the protective material layer and the side wall material layer at the bottom of the through hole is avoided or improved, thereby facilitating improving the film quality of the side wall layer, and further facilitating improving the protective effect of the side wall layer on the electrical connection of the interconnection conductive layer through the bottom of the through hole, reducing or avoiding leakage, and further facilitating improving the working performance of the semiconductor structure.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figures 6 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for preparing a semiconductor structure of the present invention.

[0041] refer to Figure 6A substrate 100 is provided, in which an interconnection conductive layer 110 is embedded, the surface of the interconnection conductive layer 110 is exposed on the substrate 100, a stacking layer 200 covering the substrate 100 is formed on the substrate 100, and a through hole 210 is formed in the stacking layer 200, which penetrates the stacking layer 200 and exposes the surface of the interconnection conductive layer 110.

[0042] The substrate 100 is used to provide a process operation basis for the preparation process of the semiconductor structure.

[0043] In this embodiment, an interconnection conductive layer 110 is embedded in the substrate 100 , and the surface of the interconnection conductive layer 110 is exposed on the substrate 100 .

[0044] The interconnection conductive layer 110 is used for external electrical connection to realize a basic circuit. The substrate 100 exposes the surface of the interconnection conductive layer 110 so that the interconnection conductive layer 110 realizes electrical connection with the outside through the exposed surface of the substrate 100 .

[0045] In this embodiment, the interconnection conductive layer 110 is made of metal material.

[0046] As an example, in this embodiment, the interconnection conductive layer 110 is a bottom metal layer.

[0047] The stacked layer 200 is used to provide a process operation basis for forming the through hole 210 .

[0048] Specifically, in this embodiment, the stacked layer 200 includes an etch stop layer (not shown) located at the bottom.

[0049] The etch stop layer is used as an etch stop position when forming the through hole 210, so that the formation of the through hole 210 is simpler and more accurate, and is conducive to improving the height consistency of the through holes 210 in different areas.

[0050] The through hole 210 is used to provide a spatial location for the subsequent formation of a spacer layer and an interconnect structure for realizing electrical connection between the interconnect conductive layer 110 and the outside.

[0051] In this embodiment, the through hole 210 penetrates the stacked layer 200 and exposes the surface of the interconnection conductive layer 110 , so that the interconnection structure subsequently formed in the through hole 210 is in contact with the interconnection conductive layer 110 and is electrically connected.

[0052] refer to Figure 7 , forming a spacer material layer 300 that at least covers the sidewall and bottom of the through hole 210, and the material of the spacer material layer 300 is silicon oxide.

[0053] The spacer material layer 300 is used to form a spacer layer later.

[0054] In the present embodiment, the material of the side wall material layer 300 is silicon oxide, so that the isolation performance and protection ability of the side wall layer formed subsequently are better. Moreover, a sacrificial layer covering the side wall material layer 300 will be formed subsequently, and the material of the sacrificial layer is silicon oxide. The material of the sacrificial layer is also silicon oxide, which is conducive to making the side wall material layer 300 at the bottom of the through hole 210 connected with the sacrificial layer as an integrated structure, so that it is easy to remove the sacrificial layer and the side wall material layer 300 at the bottom of the through hole 210 in the same process.

[0055] Specifically, in the present embodiment, in the step of forming the spacer material layer 300 that at least covers the sidewall and the bottom of the through hole 210 , the spacer material layer 300 also covers the top of the stacked layer 20 .

[0056] In this embodiment, an atomic layer deposition (ALD) process is used to form the spacer material layer 300 that at least covers the sidewall and the bottom of the through hole 210 .

[0057] The spacer material layer 300 formed by the atomic layer deposition process has good thickness uniformity and good step coverage, so that the spacer material layer 300 can conformally cover the bottom and sidewall of the through hole 210 and the top of the stacked layer 200. It is also beneficial to make the thickness uniformity of the spacer layer formed subsequently better.

[0058] refer to Figure 8 , forming a protection material layer 400 covering the spacer material layer 300 , wherein the material of the protection material layer 400 is amorphous silicon.

[0059] The protection material layer 400 is used to protect the sidewall material layer 300 in subsequent processes.

[0060] In this embodiment, the material of the protective material layer 400 is amorphous silicon (A-Si), which is conducive to forming a protective material layer 400 with good continuity and uniformity. Moreover, the amorphous silicon material can be subsequently transformed into polycrystalline silicon through lattice reorganization through heat treatment to eliminate pinhole defects as much as possible.

[0061] Specifically, in the present embodiment, in the step of forming the protective material layer 400 covering the spacer material layer 300 , the protective material layer 400 covers the spacer material layer 300 located on the sidewall and bottom of the through hole 210 , and the spacer material layer 300 located on the top of the stacked layer 200 .

[0062] In this embodiment, a chemical vapor deposition (CVD) process is used to form the protection material layer 400 covering the spacer material layer 300 .

[0063] The chemical vapor deposition process has a faster deposition rate and a better deposition effect, which is conducive to more efficiently forming the protective material layer 400 with better film continuity.

[0064] refer to Fig. 9 , the protective material layer 400 is heat-treated to enable the protective material layer 400 to achieve a material phase change process.

[0065] The protective material layer 400 is heat-treated to achieve a material phase change process in the protective material layer 400, i.e., the amorphous silicon undergoes lattice reorganization and is transformed into polycrystalline silicon, so as to eliminate pinhole defects in the protective material layer 400 as much as possible, thereby improving the protective effect of the protective material layer 400 on the sidewall material layer 300.

[0066] In this embodiment, in the step of heat treating the protective material layer 400 , the material of the protective material layer 400 is converted from amorphous silicon to polycrystalline silicon.

[0067] Specifically, amorphous silicon undergoes thermal treatment to undergo lattice reorganization and is converted into polycrystalline silicon, and the resulting polycrystalline silicon has fewer pinhole defects.

[0068] In this embodiment, in the step of performing heat treatment on the protective material layer 300 , the heat treatment includes rapid thermal processing (RTP).

[0069] The rapid thermal processing has the characteristics of high efficiency, flexibility, low pollution and low energy consumption, and can perform efficient and rapid heating processing on the protective material layer 300 .

[0070] refer to Fig.10 After the protective material layer 400 is heated, before the material at the bottom of the through hole 210 located above the interconnect conductive layer 110 is etched away, the preparation method further includes: oxidizing the protective material layer 400 to completely oxidize the protective material layer 400 at the bottom of the through hole 210 and partially oxidize the protective material layer 400 on the side wall of the through hole 210 to form a sacrificial layer 500, and the sacrificial layer 500 at least covers the remaining protective material layer 400 on the side wall of the through hole 210.

[0071] The protective material layer 400 is oxidized to completely oxidize the protective material layer 400 at the bottom of the through hole 210 and partially oxidize the protective material layer 400 at the side wall of the through hole 210 to form a sacrificial layer 500. The sacrificial layer 500 can be removed by a wet etching process. When the sacrificial layer 500 is removed, the sacrificial layer 500 can have a large etching selectivity with the remaining protective material layer 400, so that the sacrificial layer 500 can be easily removed and the remaining protective material layer 400 can be retained. Moreover, the protective material layer 400 at the bottom of the through hole 210 is completely oxidized, and the protective material layer 400 at the side wall of the through hole 210 is partially oxidized. By partially oxidizing the protective material layer 400 on the side wall of the through hole 210, when the sacrificial layer 500 is subsequently removed, the protective material layer 300 at the bottom of the through hole 210 can be completely removed to expose the side wall material layer 300 at the bottom of the through hole 210, so that the side wall material layer 300 at the bottom of the through hole 210 can be removed again, and the protective material layer 300 with a partial thickness on the side wall of the through hole 210 can be removed to retain the remaining protective material layer 300 to protect the side wall material layer 300 on the side wall of the through hole 210, so that the side wall material layer 300 on the side wall of the through hole 210 can be protected during the etching process.

[0072] Specifically, in this embodiment, the sacrificial layer 500 also covers the remaining protective material layer 400 on the top of the stacked layer 200 .

[0073] It should be noted that, in the present embodiment, in the step of forming the protective material layer 400 covering the spacer material layer 300, based on the limitation of silicon deposition step coverage, the spacer material layer 300 at other positions will be thicker than the spacer material layer 300 at the bottom position, and as the aspect ratio of the through hole 210 increases, the thickness difference will become more obvious. Therefore, in the step of oxidizing the protective material layer 400, the protective material layer 400 at the bottom of the through hole 210 can be completely oxidized while the protective material layer 400 on the side wall of the through hole 210 can be partially oxidized.

[0074] Moreover, in the step of forming the protective material layer 400 covering the sidewall material layer 300, the thickness of the protective material layer 400 at the bottom of the through hole 210 can be obtained, and then the thickness of the sacrificial layer 500 of silicon oxide at the bottom of the through hole 210 obtained after oxidation can be calculated using the formula for the polysilicon consumed by oxidizing polysilicon to form silicon oxide. Then, according to the calculated thickness of the sacrificial layer 500 of silicon oxide at the bottom of the through hole 210, the process parameters for oxidizing the protective material layer 400 are selected, thereby achieving more precise control of the oxidation thickness, so as to completely oxidize the protective material layer 400 at the bottom of the through hole 210 and partially oxidize the protective material layer 400 on the side wall of the through hole 210.

[0075] In this embodiment, the protective material layer 400 is oxidized to completely oxidize the protective material layer 400 at the bottom of the through hole 210 and partially oxidize the protective material layer 400 at the sidewall of the through hole 210 to form the sacrificial layer 500. The material of the sacrificial layer 500 is silicon oxide.

[0076] Correspondingly, in the present embodiment, in the step of performing oxidation treatment on the protection material layer 400 , the material of the sacrificial layer 500 is the same as the material of the spacer material layer 300 .

[0077] The material of the sacrificial layer 500 is the same as that of the sidewall material layer 300 . Then, at the bottom of the through hole 210 , the sacrificial layer 500 can be connected to the sidewall material layer 300 as an integrated structure, so that in the subsequent step of removing the sacrificial layer 500 , the sidewall material layer 300 at the bottom of the through hole 210 can be removed together.

[0078] In this embodiment, the step of performing oxidation treatment on the protective material layer 400 includes: performing oxidation treatment on the protective material layer 400 by using an in situ steam generation (ISSG) process or a furnace tube oxidation process.

[0079] The in-situ water vapor oxidation process is easy to form a film quickly, has good process flexibility, and is less polluting.

[0080] The furnace tube oxidation process has good process stability, is easy to operate, and has low cost.

[0081] refer to Fig.11 , the material at the bottom of the through hole 210 located above the interconnect conductive layer 110 is etched away to expose the surface of the interconnect conductive layer 110, and at the same time, the sidewall material layer 300 covering the sidewall of the through hole 210 serves as the sidewall layer 310, and the remaining protective material layer 400 covering the sidewall layer 310 serves as the protective layer 410.

[0082] The material at the bottom of the through hole 210 above the interconnection conductive layer 110 is removed by etching to expose the surface of the interconnection conductive layer 110 to prepare for the subsequent electrical connection between the interconnection conductive layer 110 and the outside. At the same time, the sidewall material layer 300 covering the sidewall of the through hole 210 serves as a sidewall layer 310 for protecting the interconnection structure subsequently formed in the through hole 210. The remaining protection material layer 400 covering the sidewall layer 310 serves as a protection layer 410 for protecting the sidewall layer 310 during the etching process.

[0083] In this embodiment, before etching and removing the material located above the interconnection conductive layer 110 at the bottom of the through hole 210, the protective material layer 400 is heat-treated to make the protective material layer 400 realize a material phase change process, which is conducive to eliminating the pinhole defects in the protective material layer 400 through the lattice reorganization in the process of transformation from amorphous silicon to polycrystalline silicon, and improving the film-forming effect of the protective material layer 400. Then, in the step of etching and removing the material located above the interconnection conductive layer 110 at the bottom of the through hole 210 to expose the surface of the interconnection conductive layer 110, the protective effect of the protective material layer 400 on the sidewall of the through hole 210 on the sidewall material layer 300 is improved, and the sidewall material layer 300 on both sides of the bottom of the through hole 210 due to the pinhole defects when removing the protective material layer 400 and the sidewall material layer 300 at the bottom of the through hole 210 is avoided or improved. 00 is damaged, thereby helping to improve the film quality of the sidewall layer 310, and further helping to improve the protective effect of the sidewall layer 310 on the interconnection conductive layer 110 being electrically connected through the bottom of the through hole 210; and the polysilicon protective material layer at the bottom of the through hole 210 is completely oxidized, and the material located above the interconnection conductive layer 110 at the bottom of the through hole 210, namely silicon oxide, can be removed in one step by wet etching, which is helpful to improve the process dimensional accuracy of removing the protective material layer 400 and the sidewall material layer 300 at the bottom of the through hole 210, thereby helping to improve the dimensional uniformity of the interconnection conductive layer 110 exposed at the bottom of the through hole 210 in different regions, and helping to improve the contact resistance consistency when the interconnection conductive layer 110 is electrically connected through the bottom of the through hole 210, and further helping to improve the working performance of the semiconductor structure.

[0084] Accordingly, in this embodiment, the step of etching away the material at the bottom of the through hole 210 above the interconnect conductive layer 110 includes: etching away the sacrificial layer 500 and the spacer material layer 300 at the bottom of the through hole 210 .

[0085] The sacrificial layer 500 and the sidewall material layer 300 at the bottom of the through hole 210 are etched away to expose the top surface of the interconnected conductive layer 110. The sacrificial layer 500 has an etching selectivity with the remaining protective material layer 400, and the sidewall material layer 300 also has an etching selectivity with the remaining protective material layer 400. Thus, in the process of etching away the sacrificial layer 500 and the sidewall material layer 300 at the bottom of the through hole 210, the top surface of the interconnected conductive layer 110 can be exposed, while the remaining protective material layer 400 can better protect the sidewall material layer 300 on the side wall of the through hole 210.

[0086] In this embodiment, the sacrificial layer 500 and the spacer material layer 500 are made of the same material, so that the sacrificial layer 500 and the spacer material layer 300 at the bottom of the through hole 210 are etched away in the same process, which is beneficial to improving process efficiency and saving process cost.

[0087] In this embodiment, a wet etching process is used to remove the sacrificial layer 500 and the spacer material layer 300 at the bottom of the through hole 210 .

[0088] The wet etching process has relatively low cost and simple operation steps, and can also achieve a larger etching selectivity ratio, which is beneficial for reducing damage to the remaining protective material layer 400 during the process of removing the sacrificial layer 500 and the sidewall material layer 300 at the bottom of the through hole 210.

[0089] Moreover, the sacrificial layer 500 and the spacer material layer 300 at the bottom of the through hole 210 can be easily removed by using a wet etching process, and almost no etching residue is left at the bottom of the through hole 210 .

[0090] In other embodiments, a dry etching process can also be used to remove the sacrificial layer and the side wall material layer at the bottom of the through hole. After etching, the etching residue is cleaned. Since the pinhole defects of the protective layer have been basically eliminated at this time, the cleaning liquid of the cleaning process will hardly penetrate the protective layer and damage the side wall layer, thereby ensuring the film quality of the side wall layer.

[0091] It should be noted that in some other embodiments, after the protective material layer is heat-treated, the step of oxidizing the protective material layer is not performed, and the protective material layer and the side wall material layer at the bottom of the through hole are directly etched away, and a dry etching process is used for etching. After etching, the etching residue is cleaned. Since the pinhole defects of the protective layer have been basically eliminated at this time, the cleaning liquid of the cleaning treatment will hardly penetrate the protective layer and damage the side wall layer, thereby ensuring the film quality of the side wall layer.

[0092] refer to Fig.12 , remove the protective layer 410.

[0093] The protective layer 410 is removed to prepare for the subsequent formation of an interconnection structure electrically connected to the interconnection conductive layer 110 in the through hole 210 .

[0094] In this embodiment, a wet etching process is used to remove the protection layer 410 .

[0095] The cost of the wet etching process is relatively low, and the operation steps are simple. It can also achieve a larger etching selectivity ratio, which is beneficial to reduce the damage to the remaining sidewall layer 310 and the interconnect conductive layer 110 during the removal of the protective layer 410.

[0096] Figures 13 to 15 It is a schematic structural diagram corresponding to each step in another embodiment of the method for preparing a semiconductor structure of the present invention.

[0097] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that before the protective material layer is oxidized, a buffer layer covering the protective material layer is formed.

[0098] refer to Fig.13 Before the protective material layer 401 is oxidized, the method further includes: forming a buffer layer 601 covering the protective material layer 401 .

[0099] A buffer layer 601 is formed to cover the protective material layer 401 , so as to slow down the oxidation rate in the subsequent oxidation process of the protective material layer 401 .

[0100] Accordingly, in this embodiment, in the step of forming the buffer layer 601 covering the protective material layer 401 , the buffer layer 601 covers the protective material layer 401 on the sidewall and bottom of the through hole 211 and the protective material layer 401 on the top of the stacked layer 201 .

[0101] In this embodiment, in the step of forming the buffer layer 601 covering the protective material layer 401 , the material of the buffer layer 601 includes any one of silicon oxide, silicon nitride and silicon oxynitride.

[0102] The buffer layer 601 formed of any one of silicon oxide, silicon nitride and silicon oxynitride can achieve a good oxidation buffer effect.

[0103] In this embodiment, in the step of forming the buffer layer 601 covering the protection material layer 401 , the material of the buffer layer 601 is the same as that of the sacrificial layer.

[0104] The material of the buffer layer 601 is the same as that of the sacrificial layer to be formed subsequently, so the buffer layer 601 can be removed together with the sacrificial layer.

[0105] As an example, in the present embodiment, in the step of forming a buffer layer 601 covering the protective material layer 401, the material of the buffer layer 601 is silicon oxide. After the protective material layer 401 is subsequently oxidized, the material of the formed sacrificial layer is also silicon oxide. The buffer layer 601 and the sacrificial layer are made of the same material and can be connected into an integrated structure, so that the buffer layer 601 can be removed together with the sacrificial layer subsequently.

[0106] In this embodiment, the buffer layer 601 covering the protective material layer 401 is formed by an atomic layer deposition process.

[0107] The buffer layer 601 formed by the atomic layer deposition process has good thickness uniformity and good step coverage capability, so that the buffer layer 601 can conformally cover the protective material layer 401 on the side wall and bottom of the through hole 211 and the protective material layer 401 on the top of the stacked layer 201.

[0108] refer to Fig.14 After forming a buffer layer 601 covering the protective material layer 401 , the protective material layer 401 is oxidized to completely oxidize the protective material layer 401 at the bottom of the through hole 211 and partially oxidize the protective material layer 401 at the side wall of the through hole 211 to form a sacrificial layer 501 .

[0109] During the oxidation process of the protective material layer 401, the oxidation diffusion rate is slowed down due to the barrier buffering of the buffer layer 601, which is conducive to more precise control of the oxidation process parameters, and thus more precise control of the oxidation thickness, so as to completely oxidize the protective material layer 401 at the bottom of the through hole 211 and partially oxidize the protective material layer 401 on the side wall of the through hole 211.

[0110] refer to Fig.15 The step of etching and removing the sacrificial layer 501 and the sidewall material layer 311 at the bottom of the through hole 211 also includes: removing the buffer layer 601.

[0111] The buffer layer 601 is removed to expose the top surface of the interconnection conductive layer 111 in the substrate 101 .

[0112] In this embodiment, the material of the buffer layer 601 is the same as that of the sacrificial layer 501 . Accordingly, removing the sacrificial layer 501 and the buffer layer 601 in the same process is beneficial to improving process efficiency and saving process cost.

[0113] Fig.16 It is a schematic structural diagram corresponding to each step in another embodiment of the method for preparing a semiconductor structure of the present invention.

[0114] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that a buffer layer covering the protective material layer is formed to form a sacrificial layer.

[0115] refer to Fig.16 The step of oxidizing the protective material layer 402 includes: forming a buffer layer 602 covering the protective material layer 402, the material of the buffer layer 602 is an oxide material, and while forming the buffer layer 602, the buffer layer 602 is diffused and oxidized into the protective material layer 402 to completely oxidize the protective material layer 402 at the bottom of the through hole 212 and partially oxidize the protective material layer 402 on the side wall of the through hole 212 to form a sacrificial layer 502.

[0116] The material of the buffer layer 602 is an oxide material. In the process of forming the buffer layer 602 covering the protective material layer 402, the amount of oxygen introduced is appropriately increased so that while the buffer layer 602 is being formed, the oxygen can diffuse into the protective material layer 402 and oxidize the entire protective material layer 402 at the bottom of the through hole 212 and part of the protective material layer 402 on the side wall of the through hole 212 into a sacrificial layer 502.

[0117] In this embodiment, the buffer layer 602 covering the protective material layer 402 is formed while the sacrificial layer 502 is formed, which is beneficial to simplify the process flow, improve the process efficiency, and save the process cost.

[0118] As an example, in this embodiment, a buffer layer 602 is formed to cover the protective material layer 402 , and the material of the buffer layer 602 is silicon oxide.

[0119] It should be noted that, in the present embodiment, after forming the buffer layer 602 covering the protective material layer 402, the step of oxidizing the protective material layer 402 by using the in-situ steam oxidation process or the furnace tube oxidation process may not be performed, or the step of oxidizing the protective material layer 402 by using the in-situ steam oxidation process or the furnace tube oxidation process may still be performed.

[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein an interconnection conductive layer is embedded in the substrate, the surface of the interconnection conductive layer is exposed on the substrate, a stacking layer covering the substrate is formed on the substrate, and a through hole penetrating the stacking layer and exposing the surface of the interconnection conductive layer is formed in the stacking layer; Forming a sidewall material layer that at least covers the sidewall and bottom of the through hole, wherein the sidewall material layer is made of silicon oxide; forming a protective material layer covering the sidewall material layer, wherein the material of the protective material layer is amorphous silicon; Performing heat treatment on the protective material layer to make the protective material layer realize a material phase change process; Etching and removing the material at the bottom of the through hole above the interconnect conductive layer to expose the surface of the interconnect conductive layer, while the sidewall material layer covering the sidewall of the through hole serves as a sidewall layer, and the remaining protective material layer covering the sidewall layer serves as a protective layer; The protective layer is removed.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: In the step of heat treating the protective material layer, the material of the protective material layer is converted from amorphous silicon to polycrystalline silicon.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: In the step of heat-treating the protective material layer, the heat-treating includes rapid thermal processing.

4. The method for preparing a semiconductor structure according to claim 1, wherein: After the protective material layer is heated, before the material at the bottom of the through hole above the interconnect conductive layer is etched away, the preparation method further includes: oxidizing the protective material layer to completely oxidize the protective material layer at the bottom of the through hole and partially oxidize the protective material layer on the side wall of the through hole to form a sacrificial layer, and the sacrificial layer at least covers the remaining protective material layer on the side wall of the through hole.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The step of etching away the material at the bottom of the through hole above the interconnect conductive layer includes: etching away the sacrificial layer and the sidewall material layer at the bottom of the through hole.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: In the step of performing oxidation treatment on the protective material layer, the material of the sacrificial layer is the same as the material of the sidewall material layer; The sacrificial layer and the sidewall material layer at the bottom of the through hole are removed by etching in the same process.

7. The method for preparing a semiconductor structure according to claim 4, characterized in that: The step of oxidizing the protective material layer includes: oxidizing the protective material layer using an in-situ steam oxidation process or a furnace tube oxidation process.

8. The method for preparing a semiconductor structure according to claim 4, characterized in that: The sacrificial layer and the sidewall material layer at the bottom of the through hole are removed by a wet etching process.

9. The method for preparing a semiconductor structure according to claim 5, characterized in that: Before the protective material layer is oxidized, the method further includes: forming a buffer layer covering the protective material layer; The step of etching and removing the sacrificial layer and the sidewall material layer at the bottom of the through hole also includes: removing the buffer layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: In the step of forming a buffer layer covering the protective material layer, the material of the buffer layer includes any one of silicon oxide, silicon nitride and silicon oxynitride.

11. The method for preparing a semiconductor structure according to claim 4, characterized in that: The step of oxidizing the protective material layer comprises: forming a buffer layer covering the protective material layer, wherein the material of the buffer layer is an oxide material, and while forming the buffer layer, the buffer layer is diffused and oxidized into the protective material layer to completely oxidize the protective material layer at the bottom of the through hole and partially oxidize the protective material layer at the side wall of the through hole to form the sacrificial layer; The step of etching and removing the sacrificial layer and the sidewall material layer at the bottom of the through hole also includes: removing the buffer layer.

12. The method for preparing a semiconductor structure according to claim 9 or 11, characterized in that: An atomic layer deposition process is used to form a buffer layer covering the protective material layer.

13. The method for preparing a semiconductor structure according to claim 9 or 11, characterized in that: In the step of forming a buffer layer covering the protective material layer, the material of the buffer layer is the same as that of the sacrificial layer; The sacrificial layer and the buffer layer are removed in the same process.

14. The method for preparing a semiconductor structure according to claim 1, wherein: An atomic layer deposition process is used to form a sidewall material layer that at least covers the sidewall and bottom of the through hole.

15. The method for preparing a semiconductor structure according to claim 1, wherein: A protective material layer covering the sidewall material layer is formed by a chemical vapor deposition process.

16. The method for preparing a semiconductor structure according to claim 1, wherein: The protective layer is removed by a wet etching process.

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