Semiconductor structure and semiconductor chip

Abstract

The invention provides a semiconductor structure and a semiconductor chip. The semiconductor structure includes a semiconductor substrate, an electronic circuit, a first seal ring, a buffer region, and a conductive wiring. The semiconductor substrate has a circuit region and a seal ring region surrounding the circuit region. The electronic circuit is disposed in a circuit region on the semiconductor substrate. The first seal ring is disposed on a seal ring region on the semiconductor substrate and surrounds the circuit region. The buffer region is located in the seal ring region and between the circuit region and the first seal ring. The first seal ring is separated from the circuit region by the buffer region. The conductive wiring is disposed in a buffer region on the semiconductor substrate. The conductive wiring is electrically connected with the electronic circuit.

Description

Technical Field

[0001] The invention relates to a semiconductor structure and a semiconductor chip, in particular to a sealing ring structure of the semiconductor structure and a sealing ring structure of the semiconductor chip. Background Art

[0002] In each semiconductor chip of a wafer, a seal ring is usually formed between the scribe line and the peripheral area of ​​the integrated circuit. The seal ring is formed by stacking dielectric layers and metal layers. These metal layers are connected by vias that pass through the dielectric layers. When the wafer cutting process is performed along the scribe line, the seal ring can prevent unwanted cracks in the scribe line. These cracks may be generated in the integrated circuit by the stress of the wafer cutting process. In addition, the seal ring can block moisture, prevent damage from acid or alkaline chemicals, and prevent the diffusion of contaminant species. In current semiconductor technology, a double seal ring structure has been developed to solve more serious crack problems. However, the area occupied by the seal ring may limit the wiring area of ​​the semiconductor chip. In high-speed and multi-function applications, semiconductor chips with limited wiring areas may encounter electrical problems such as crosstalk, signal propagation delay, and electromagnetic interference with radio frequency circuits.

[0003] Therefore, a new semiconductor chip having a seal ring and having improved electrical performance is desirable. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, an electronic circuit, a first sealing ring, a buffer zone, and a conductive wiring. The semiconductor substrate has a circuit area and a sealing ring area surrounding the circuit area. The electronic circuit is arranged in the circuit area on the semiconductor substrate. The first sealing ring is arranged in the sealing ring area on the semiconductor substrate and surrounds the circuit area. The buffer zone is located in the sealing ring area and is placed between the circuit area and the first sealing ring. The first sealing ring is separated from the circuit area by the buffer zone. The conductive wiring is arranged in the buffer zone on the semiconductor substrate. The conductive wiring is electrically connected to the electronic circuit.

[0005] Another embodiment of the present invention provides a semiconductor chip. The semiconductor chip includes a circuit area, a sealing ring area, an electronic circuit, a sealing ring structure, and a signal wiring. The sealing ring area surrounds the circuit area. The sealing ring area includes a buffer zone surrounding the boundary of the circuit area. The electronic circuit is arranged in the circuit area. The sealing ring structure is arranged in the sealing ring area and surrounds the circuit area. The sealing ring structure is separated from the boundary of the circuit area by the buffer zone. The signal wiring is arranged in the buffer zone and extends to the circuit area. The signal wiring is electrically connected to the electronic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention may be more fully understood by reading the following detailed description and referring to the examples in the accompanying drawings, in which:

[0007] Figure 1 is a top view of a semiconductor device according to some embodiments of the present invention;

[0008] Figure 2 According to some embodiments of the present invention, Figure 1 A cross-sectional view of the semiconductor device shown along line AA' in FIG.

[0009] Figure 3A , Figure 3B and Figure 3C According to some embodiments of the present invention, Figure 2 FIG. 1 is a magnified view of a semiconductor device in FIG. 1 showing the arrangement of conductive wiring within a buffer zone in the seal ring area. DETAILED DESCRIPTION

[0010] The following description of the invention is intended to illustrate the general principles of the disclosure and is not to be construed in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0011] The inventive concept is fully described by reference to the accompanying drawings and by showing exemplary embodiments. The advantages and features of the inventive concept and the methods for achieving them will become apparent through the exemplary embodiments to be described in more detail below. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments and can be implemented in various forms. Therefore, the exemplary embodiments are only used to disclose the inventive concept and to let those skilled in the art understand the categories of the inventive concept. In addition, the drawings shown are only schematic and non-restrictive. In the drawings, for illustrative purposes, the size of some elements may be exaggerated and not drawn to scale. The dimensions and relative dimensions do not correspond to the actual dimensions in the practice of the present invention.

[0012] Figure 1 is a top view of a semiconductor device 500 according to some embodiments of the present invention. Figure 2 According to some embodiments of the present invention Figure 1 FIG. 5 is a cross-sectional view of the semiconductor device 500 shown along line AA′ in FIG. Figure 1 and Figure 2 As shown, a semiconductor device 500, such as a semiconductor chip 500, includes a semiconductor substrate 200, one or more electronic circuits 210, a seal ring structure 504R (including seal rings 504-1 and 504-2), a buffer zone 504B and a conductive wiring structure 320. Figure 1 and Figure 2In the subsequent figures, directions 100 and 110 are directions substantially parallel to the top surface 200T of the semiconductor substrate 200, and can also be referred to as lateral directions. Direction 120 is a direction substantially perpendicular to the top surface 200T, and can also be referred to as a longitudinal (vertical) direction (or can be referred to as a channel length direction). In order to clearly show the arrangement of the conductive wiring structures 320 in the buffer region 504B, Figure 1 Conductive pad 250, passivation layer 252, passivation layer 254, passivation layer 256, and dielectric layer 230G are not shown. In addition, direction 100 is perpendicular to direction 110 and direction 120, direction 110 is perpendicular to direction 100 and direction 120, and direction 120 is perpendicular to direction 100 and direction 110.

[0013] like Figure 1 and Figure 2 As shown, the semiconductor substrate 200 has a circuit region 502, a seal ring region 504 surrounding the circuit region 502, and a scribe line region 506 surrounding the seal ring region 504. The scribe line region 506 is close to the edge 500E of the semiconductor device 500. In some embodiments, the semiconductor substrate 200 may include silicon. In alternative embodiments, SiGe, bulk semiconductors, strained semiconductors, compound semiconductors, semiconductors on insulators (SOI), and other commonly used semiconductor substrates may be used as the semiconductor substrate 200. The semiconductor substrate 200 may have a desired conductivity type by implanting p-type or n-type impurities. In some embodiments, the isolation feature 202 includes a buried oxide layer and a shallow trench isolation (STI) feature (not shown) formed on the top of the semiconductor substrate 200. The isolation feature 202 may surround and provide physical and electrical isolation for an active region 205 on the semiconductor substrate 200. The active region 205 may be doped with a p-type dopant and / or an n-type dopant.

[0014] Semiconductor device 500 further includes interconnect structure 260 disposed on semiconductor substrate 200. In some embodiments, interconnect structure 260 includes dielectric layers 230 and 230G, conductive layer patterns (eg, metal layer patterns) 300M and 300MT, contact plugs 220, and conductive vias 240V.

[0015] The dielectric layer 230 and the dielectric layer 230G are disposed on the circuit region 502, the seal ring region 504, and the scribe line region 506 of the semiconductor substrate 200. The dielectric layer 230 is stacked vertically (in the direction 120) on the semiconductor substrate 200. The dielectric layer 230G is disposed on the dielectric layer 230. The dielectric layer 230 may serve as an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer 230, and the dielectric layer 230G may serve as the topmost intermetallic dielectric (IMD) layer 230G. In some embodiments, the dielectric layer 230G disposed on the dielectric layer 230 has a first dielectric constant (k), and the dielectric layer 230 disposed between the dielectric layer 230G and the semiconductor substrate 200 has a second dielectric constant (k), and the second dielectric constant (k) is lower than the first dielectric constant (k). The dielectric layer 230 may be made of a low-k dielectric material (e.g., a dielectric constant less than that of silicon dioxide) having a dielectric constant (k) between about 2.9 and 3.8, an ultra-low-k dielectric material having a dielectric constant (k) between about 2.5 and 3.9, and / or an extremely low-k (ELK) dielectric material having a dielectric constant (k) less than about 2.5. For example, the dielectric layer 230 may include a carbon-doped oxide, a porous carbon-doped silicon dioxide, a polymer such as a polyimide or a silicon-oxygen-carbon polymer (SiOC), or a combination thereof. In addition, the dielectric layer 230G may be made of a non-low-k dielectric material having a dielectric constant (k) greater than about 3.8. For example, the dielectric layer 230G may include silicon dioxide, silicon oxynitride, undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or a combination thereof. In some embodiments, dielectric layer 230G is formed by plasma enhanced chemical vapor deposition (PECVD). It should be noted that the number of (low-k) dielectric layers 230 and the number of (non-low-k) dielectric layers 230G are defined by customer design and the scope of the present invention is not limited.

[0016] In some embodiments, interconnect structure 260 may have multiple conductive layers embedded in dielectric layer 230 and dielectric layer 230G. Figure 2 As shown, the interconnect structure 260 may have 15 conductive layers, which are represented as a first conductive layer M0, a second conductive layer M1, a third conductive layer M2, a fourth conductive layer M3, a fifth conductive layer M4, a sixth conductive layer M5, a seventh conductive layer M6, an eighth conductive layer M7, a ninth conductive layer M8, a tenth conductive layer M9, an eleventh conductive layer M10, a twelfth conductive layer M11, a thirteenth conductive layer M12, a fourteenth conductive layer M13 and a fifteenth conductive layer M14, from bottom to top.

[0017] In addition, the interconnect structure 260 may have multiple layers of conductive vias alternately arranged and electrically connected to the conductive layers. Figure 2As shown, the interconnect structure 260 may have 14 layers of conductive vias, represented as a first via V0, a ​​second via V1, a third via V2, a fourth via V3, a fifth via V4, a sixth via V5, a seventh via V6, an eighth via V7, a ninth via V8, a tenth via V9, an eleventh via V10, a twelfth via V11, a thirteenth via V12 and a fourteenth via V13, from bottom to top.

[0018] One or more electronic circuits 210 are disposed in a circuit region 502 on the semiconductor substrate 200. In some embodiments, the electronic circuit 210 may be located near a boundary 502E of the circuit region 502. The electronic circuit 210 may be covered by and embedded in a dielectric layer 230. In some embodiments, the electronic circuit 210 may include an analog circuit and / or a radio frequency circuit connected to the active and / or passive components by active components (such as transistors), passive components (such as resistors, inductors, and capacitors), and electrical connections (including conductive layer patterns (not shown) belonging to the first conductive layer M0 to the fifteenth conductive layer M14 and conductive vias belonging to the first through hole V0 to the fourteenth through hole V13). In these embodiments, the electronic circuit 210 may include an analog circuit.

[0019] like Figure 1 and Figure 2 As shown, a seal ring structure 504R is disposed on the semiconductor substrate 200 and is located in the seal ring region 504. The seal ring structure 504R includes a seal ring 504-1 and a seal ring 504-2 separated from each other. The seal ring 504-1 surrounds the circuit region 502, and the seal ring 504-2 surrounds the seal ring 504-1. In addition, the seal ring 504-2 is surrounded by a scribe line region 506. The seal ring 504-1 and the seal ring 504-2 may be electrically connected to a doped region 205P (such as a P-type doped region) in the active region 205 on the semiconductor substrate 200, respectively. The seal ring 504-1 and the seal ring 504-2 are both formed in the interconnect structure 260. The seal ring 504-1 and the seal ring 504-2 both include a contact plug 220, a conductive via 240V, a conductive layer pattern (e.g., a metal layer pattern) 300M and a conductive layer pattern 300MT. The conductive layer patterns 300M and the conductive layer patterns 300MT are alternately arranged and electrically connected to the contact plugs 220 and the conductive vias 240V.

[0020] In the sealing ring 504-1 and the sealing ring 504-2, the contact plug 220 through the dielectric layer 230 is connected between the active area 205 and the conductive layer pattern 300M belonging to the first conductive layer M0. The conductive via 240V through the corresponding dielectric layer 230 and the dielectric layer 230G is connected to the corresponding conductive layer pattern 300M embedded in the corresponding dielectric layer 230 and the conductive layer pattern 300MT embedded in the dielectric layer 230G. The conductive via 240V may belong to the first via V0 to the fourteenth via V13. The conductive via 240V may connect the conductive layer patterns 300M of two adjacent levels. In addition, the conductive layer pattern 300M and the conductive layer pattern 300MT are located in the conductive layer of the interconnect structure 260 from the bottom layer (the first conductive layer M0) to the top layer (the fifteenth conductive layer M14). More specifically, the conductive layer pattern 300M may belong to the first conductive layer M0 to the fourteenth conductive layer M13. The conductive layer pattern 300MT may belong to the fifteenth conductive layer M14. In this embodiment, the conductive layer pattern 300MT may also be referred to as the top metal layer pattern 300MT. The conductive layer pattern 300M belonging to the fourteenth conductive layer M13 may also be referred to as the sub-top metal layer pattern 300M, and so on. The conductive layer pattern 300M belonging to the first conductive layer M0 to the thirteenth conductive layer M12 may also be used as the lower metal layer pattern 300M. It is worth noting that the number of the contact plug 220, the conductive via 240V, the conductive layer pattern 300M, and the conductive layer pattern 300MT is defined by the customer design, and the scope of the present invention is not limited thereto.

[0021] In some embodiments, the interconnect structure 260 further includes a conductive pad 250, a passivation layer 252, a passivation layer 254, and a passivation layer 256. The conductive pad 250 covers the seal ring 504-1 and the seal ring 504-2 of the seal ring structure 504R. The conductive pad 250 is formed on and electrically connected to the conductive layer pattern 300MT of the seal rings 504-1 and 504-2. In some embodiments, the conductive pad 250 is made of aluminum (other metals are also suitable and can be used).

[0022] Passivation layer 252 and passivation layer 254 are then deposited on semiconductor substrate 200 and cover seal ring 504-1 and seal ring 504-2. Passivation layer 252 may have openings (not shown) to expose conductive pad 250 located on seal ring 504-1 and seal ring 504-2. Passivation layer 254 may cover conductive pad 250. In one embodiment, passivation layer 252 and passivation layer 254 are formed of the same material, such as silicon dioxide or silicon nitride. In another embodiment, passivation layer 252 and passivation layer 254 are formed of different materials. For example, passivation layer 252 is formed of an inorganic material (e.g., silicon dioxide or silicon nitride), while passivation layer 254 is formed of an organic material (e.g., a solder mask). Passivation layer 256 may be selectively deposited on semiconductor substrate 200 and cover passivation layer 254. Passivation layer 256 may be formed of polyimide.

[0023] like Figure 1 and Figure 2 As shown, the semiconductor structure 500 may further include a buffer zone (also referred to as a seal ring enhancement zone (SREZ)) 504B located in the seal ring region 504. The buffer zone 504B completely surrounds the boundary 502E of the circuit region 502. In addition, the buffer zone 504B is placed between the circuit region 502 and the seal ring 504-1. The seal ring 504-1 (or the seal ring 504-2) is separated from the circuit region 502 by the buffer zone 504B. The buffer zone 504B may have an appropriate lateral size. During the formation of the seal ring structure 504R, the buffer zone 504B may prevent the electronic circuit 210 in the circuit region 502 from being damaged.

[0024] In some embodiments, the semiconductor structure 500 may further include a dummy pattern 310 on the semiconductor substrate 200 in the buffer region 504B. The dummy pattern 310 will enhance the mechanical strength of the seal ring structure 504R after the wafer sawing process along the scribe line region 506. In some embodiments, the dummy pattern 310 includes a dummy active region 205D surrounded by an isolation feature 202 in the semiconductor substrate, a dummy polycrystalline pattern 212D, a dummy conductive pattern 300D, or a combination thereof. The conductive pattern 300D may belong to the first conductive layer M0 to the fifteenth conductive layer M14 of the conductive layer of the interconnect structure 260. In some embodiments, the dummy pattern 310 is electrically suspended.

[0025] In some embodiments, buffer 504B may provide additional routing space for electronic circuits 210 in circuit area 502. Figure 1 and Figure 2 As shown, the semiconductor structure 500 may further include one or more conductive wiring structures 320 (included in Figure 3A , Figure 3B and Figure 3CThe conductive wiring structure 320A, the conductive wiring structure 320B, and the conductive wiring structure 320C shown in FIG. 3 are disposed on the semiconductor substrate 200 in the buffer zone 504B. The conductive wiring structure 320 is disposed in the interconnect structure 260. The conductive wiring structure 320 is surrounded by the seal ring structure 504R and is Figure 1 In the top view shown, the conductive wiring structure 320C is electrically connected to the electronic circuit 210. It is worth noting that the conductive wiring structure 320C is only used as the conductive wiring structure 320 in the Figure 2 An example of a cross-sectional view is shown in FIG. Various embodiments of the conductive wiring structure 320 can be Figure 3A , Figure 3B and Figure 3C In addition, the location and number of the conductive wiring structure 320 are not limited to the disclosed embodiments. For example, the conductive wiring structure 320 can be implemented to include one or more conductive layers and / or one or more conductive vias, corresponding to any level of conductive layers and conductive vias of the interconnect structure 260, such as M0 to M14 and V0 to V13.

[0026] like Figure 1 and Figure 2 As shown, the conductive wiring structure 320 may extend approximately along the buffer region 504B. In addition, the conductive wiring structure 320 may extend approximately along and separately from the boundary 502E of the circuit region 502. In some embodiments, the conductive wiring structure 320 includes one or more connecting portions 320E extending from the buffer region 504B to the corresponding electronic circuit 210. The connecting portion 320E is electrically connected to the corresponding electronic circuit 210. In some embodiments, the conductive wiring structure 320 is a signal wiring structure. For example, the conductive wiring structure 320 is used to transmit an analog signal (e.g., a clock signal), and the electronic circuit 210 is an analog circuit. The conductive wiring structure 320 is separated from the sealing ring 504-1 and the sealing ring 504-2. In addition, in some embodiments, the conductive wiring structure 320 is separated from the dummy pattern 310.

[0027] Figure 3A , Figure 3B and Figure 3C According to certain embodiments of the disclosure, Figure 2 FIG. 5 is an enlarged view of a region 270 of a semiconductor device 500 in FIG. 504B, showing the arrangement of a conductive wiring structure 320A, a conductive wiring structure 320B, and a conductive wiring structure 320C disposed in a buffer region 504B.

[0028] In such Figure 3AIn some embodiments shown, the conductive wiring structure 320A may include a conductive wiring 320MA. The conductive wiring 320MA may be embedded in the dielectric layer 230 of the interconnect structure 260. Alternatively, the conductive wiring 320MA may be embedded in the dielectric layer 230G of the interconnect structure 260. In some embodiments, the conductive wiring 320MA is a signal wiring. The conductive wiring 320MA is electrically isolated from the sealing ring 504-1 and the sealing ring 504-2. In some embodiments, the conductive wiring 320MA may belong to any level of the conductive layer of the interconnect structure 260, not limited to the disclosed embodiments. For example, the conductive wiring 320MA may belong to the first conductive layer M0, the second conductive layer M1, the third conductive layer M2, the fourth conductive layer M3, the fifth conductive layer M4, the sixth conductive layer M5, the seventh conductive layer M6, the eighth conductive layer M7, the ninth conductive layer M8, the tenth conductive layer M9, the eleventh conductive layer M10, the twelfth conductive layer M11, the thirteenth conductive layer M12, the fourteenth conductive layer M13 and the fifteenth conductive layer M14.

[0029] In certain embodiments, such as Figure 3B As shown, the conductive wiring structure 320B may include a conductive wiring 320MA and a shielding structure 320MS1. The shielding structure 320MS1 may be disposed within the interconnect structure 260 in the buffer 504B. The shielding structure 320MS1 may be embedded in the dielectric layer 230 and the dielectric layer 230G of the interconnect structure 260. The shielding structure 320MS1 surrounds and is separated from the conductive wiring 320MA in an extension direction (e.g., direction 110). The shielding structure 320MS1 can help reduce the impact of electrical noise on signals transmitted along the conductive wiring 320MA. In some embodiments, the shielding structure 320MS1 is grounded.

[0030] In some embodiments, the shielding structure 320MS1 includes a conductive layer pattern 320MT, a conductive layer pattern 320MB, a conductive layer pattern 320MA-1, and a conductive layer pattern 320MA-2. In the vertical direction 120, the conductive layer pattern 320MT is located above the top surface 320MA-T of the conductive wiring 320MA. The conductive layer pattern 320MB is located below the bottom surface 320MA-B of the conductive wiring 320MA. In other words, the conductive layer pattern 320MT and the conductive layer pattern 320MB are located on opposite surfaces of the conductive wiring 320MA (i.e., the top surface 320MA-T and the bottom surface 320MA-B). Figure 3BIn the cross-sectional view shown, the conductive layer pattern 320MA-1 and the conductive layer pattern 320MA-2 are disposed beside the opposite side surfaces 320MA-S1 and 320MA-S2 of the conductive wiring 320MA, in a direction (e.g., direction 100) that is substantially perpendicular to the extending direction (e.g., direction 110) of the conductive wiring 320MA. The conductive layer pattern 320MT and the conductive layer pattern 320MB may overlap each other in the vertical direction 120. The conductive wiring 320MA and the conductive layer pattern 320MA-1 and the conductive layer pattern 320MA-2 are interposed between the conductive layer pattern 320MT and the conductive layer pattern 320MB in the vertical direction 120. The conductive layer pattern 320MT and the conductive layer pattern 320MB may overlap the conductive wiring 320MA and the conductive layer pattern 320MA-1 and the conductive layer pattern 320MA-2 in the vertical direction 120. Furthermore, conductive layer pattern 320MT and conductive layer pattern 320MB may completely cover top surface 320MA-T and bottom surface 320MA-B of conductive routing 320MA. In some embodiments, conductive layer pattern 320MT, conductive layer pattern 320MB, conductive layer pattern 320MA-1, and conductive layer pattern 320MA-2 are grounded.

[0031] In some embodiments, the conductive layer pattern 320MT, the conductive layer pattern 320MB, and the conductive wiring 320MA belong to different conductive layer levels of the interconnect structure 260. For example, the conductive layer pattern 320MT is located at a higher level than the conductive wiring 320MA in the vertical direction 120. The conductive layer pattern 320MB is located at a lower level than the conductive wiring 320MA in the vertical direction 120. For example, in this embodiment, the conductive wiring 320MA may belong to X th Conductive layer M X, , where X is a positive integer between 2 and 14, and the conductive layer pattern 320MT may belong to Y th Conductive layer M Y, , where Y is a positive integer between 3 and 15, and the conductive layer pattern 320MB may belong to Z th Conductive layer M Z, , where Z is a positive integer between 1 and 13.

[0032] In some embodiments, the conductive layer pattern 320MT and the conductive wiring 320MA may belong to adjacent conductive layer levels of the interconnect structure 260. Similarly, the conductive layer pattern 320MB and the conductive wiring 320MA may belong to adjacent conductive layer levels of the interconnect structure 260. For example, in this embodiment, the conductive wiring 320MA may belong to X th Conductive layer M X, , the conductive layer pattern 320MT may belong to (X+1) th Conductive layer M (X+1),, the conductive layer pattern 320MB may belong to (X-1) th Conductive layer M (X-1) , where X is a positive integer between 2 and 14.

[0033] In some embodiments, the conductive layer pattern 320MT and the conductive wiring 320MA may be separated by at least two conductive layer levels of the interconnect structure 260. Similarly, the conductive layer pattern 320MB and the conductive wiring 320MA may be separated by at least two conductive layer levels of the interconnect structure 260. In some embodiments, the conductive layer pattern 320MT and the conductive layer pattern 320MB may be separated by the conductive wiring 320MA at the same or different distances in the direction 120. For example, in this embodiment, the conductive wiring 320MA may belong to X th Conductive layer M X, , the conductive layer pattern 320MT may belong to (X+N) th Conductive layer M (X+1) ,, the conductive layer pattern 320MB may belong to (XM) th Conductive layer M (X-1) , where X, N and M are positive integers, 2≤X≤14, N≥2 and 3≤(X+N)≤15, M≥2 and 1≤(XM)≤13.

[0034] In certain embodiments, such as Figure 3B As shown, the conductive layer pattern 320MA-1, the conductive layer pattern 320MA-2, and the conductive wiring 320MA belong to the same conductive layer level of the interconnect structure 260. In some embodiments, the conductive layer pattern 320MA-1, the conductive layer pattern 320MA-2, and the conductive wiring 320MA belong to different conductive layer levels of the interconnect structure 260 and are located between the conductive layer pattern 320MT and the conductive layer pattern 320MB in the vertical direction 120.

[0035] like Figure 3B As shown (in the cross-sectional view, the direction (e.g., direction 100) is substantially perpendicular to the extension direction (e.g., direction 110) of the conductive wiring 320MA), the conductive wiring 320MA may have a width W1, the conductive layer pattern 320MT may have a width W2, the conductive layer pattern 320MB may have a width W3, the conductive layer pattern 320MA-1 may have a width W4, and the conductive layer pattern 320MA-2 may have a width W5. In some embodiments, the width W1 is smaller than the width W2 and the width W3. In some embodiments, the width W2 and the width W3 may have the same or different values. In some embodiments, the width W4 and the width W5 are both smaller than the width W2 and the width W3. In some embodiments, the width W4 and the width W5 may have the same or different values. In some embodiments, the width W1, the width W4, and the width W5 may have the same or different values.

[0036] In some embodiments, Figure 3C As shown, the conductive wiring structure 320C may include a conductive wiring 320MA and a shielding structure 320MS2. At least one difference between the shielding structure 320MS1 and the shielding structure 320MS2 is that the shielding structure 320MS2 further includes a conductive via 340V. The conductive via 340V is located near the opposite side surfaces 320MA-S1, 320MA-S2 of the conductive wiring 320MA. The conductive via 340V is connected between the conductive layer pattern 320MT and the conductive layer pattern 320MB. In the direction 120, the conductive via 340V is connected between the conductive layer pattern 320MT and the conductive layer pattern 320MA-1 (or the conductive layer pattern 320MA-2), and between the conductive layer pattern 320MA-1 (or the conductive layer pattern 320MA-2) and the conductive layer pattern 320MB. In addition, the conductive layer pattern 320MA-1 (or the conductive layer pattern 320MA-2) is connected between the conductive vias 340V. Therefore, the conductive layer pattern 320MT is electrically connected to the conductive layer pattern 320MB through the conductive via 340V and the conductive layer pattern 320MA-1 and the conductive layer pattern 320MA-2. In some embodiments, the number of the conductive vias 340V between the conductive layer pattern 320MT and the conductive layer pattern 320MA-1 (or the conductive layer pattern 320MA-2), and between the conductive layer pattern 320MA-1 (or the conductive layer pattern 320MA-2) and the conductive layer pattern 320MB may be equal to or greater than 1. In some embodiments, the shielding structure 320MS2 is grounded.

[0037] Since the buffer 504B is used as an additional wiring space for the electronic circuit 210 in the circuit area 502, the electronic circuits 210 having the same or similar functions can be arranged near the boundary 502E and electrically connected through the conductive wiring structure 320 located in the buffer 504B. The wiring area in the circuit area 502 can be further reduced. When the electronic circuit 210 includes an analog circuit and the conductive wiring structure 320 includes a clock signal wiring, interference with other electronic circuits (e.g., an RF circuit) in the circuit area 502 can be reduced. When some conductive wiring is moved outside the circuit area 502, the wiring area in the circuit area 502 can be released to improve wiring flexibility. The size of the semiconductor structure 500 (such as a semiconductor chip) can be further reduced.

[0038] An embodiment provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, an electronic circuit, a first sealing ring, a buffer zone, and a conductive wiring. The semiconductor substrate has a circuit area and a sealing ring area surrounding the circuit area. The electronic circuit is arranged in the circuit area on the semiconductor substrate. The first sealing ring is arranged in the sealing ring area on the semiconductor substrate and surrounds the circuit area. The buffer zone is located in the sealing ring area and is placed between the circuit area and the first sealing ring. The first sealing ring is separated from the circuit area by the buffer zone. The conductive wiring is arranged in the buffer zone on the semiconductor substrate. The conductive wiring is electrically connected to the electronic circuit.

[0039] In some embodiments, the conductive trace includes a connection portion extending from the buffer region to the circuit region.

[0040] In some embodiments, the conductive routing is separated from the first sealing ring.

[0041] In some embodiments, the semiconductor structure further includes an interconnect structure and a shielding structure. The interconnect structure is disposed on the semiconductor substrate. The shielding structure and the conductive wiring are embedded in the dielectric layer of the interconnect structure of the buffer zone. The shielding structure surrounds and is separated from the conductive wiring. The shielding structure includes a first conductive layer pattern, a second conductive layer pattern, and a third conductive layer pattern. The first conductive layer pattern is located above the top surface of the conductive wiring. The second conductive layer pattern is located below the bottom surface of the conductive wiring. The first conductive layer pattern and the second conductive layer pattern overlap each other. The third conductive layer pattern is disposed beside the opposite side surface of the conductive wiring.

[0042] In some embodiments, the conductive trace is a signal trace and the shielding structure is grounded.

[0043] In some embodiments, the first conductive layer pattern, the second conductive layer pattern, and the conductive wiring belong to different conductive layer levels of the interconnect structure.

[0044] In some embodiments, the first conductive layer pattern and the conductive wiring belong to adjacent conductive layer levels of the interconnect structure.

[0045] In some embodiments, the second conductive layer pattern and the conductive wiring belong to adjacent conductive layer levels of the interconnect structure.

[0046] In some embodiments, the third conductive layer pattern and the conductive wiring belong to the same conductive layer level of the interconnect structure.

[0047] In some embodiments, the shielding structure further includes conductive vias adjacent to opposite side surfaces of the conductive wiring. The first conductive layer pattern is electrically connected to the second conductive layer pattern through the conductive vias and the third conductive layer pattern.

[0048] In some embodiments, the semiconductor structure further includes a dummy pattern disposed on the semiconductor substrate in the buffer region.

[0049] In some embodiments, the dummy pattern is electrically suspended.

[0050] In some embodiments, the dummy pattern includes a dummy active area surrounded by isolation features in the semiconductor substrate, a dummy poly pattern, a dummy conductive pattern, or a combination thereof.

[0051] In some embodiments, the semiconductor structure further includes a second sealing ring disposed on the semiconductor substrate. The second sealing ring is located in the sealing ring area. The second sealing ring surrounds the first sealing ring. The second sealing ring is surrounded by the scribe line area of ​​the semiconductor substrate. The conductive wiring is separated from the second sealing ring.

[0052] In some embodiments, the semiconductor structure further includes an interconnect structure disposed on the semiconductor substrate. The interconnect structure includes a dielectric layer, a conductive layer pattern, and a conductive via. The dielectric layer is stacked on the semiconductor substrate. The conductive layer pattern is embedded in the dielectric layer. The conductive via is alternately arranged and electrically connected to the conductive layer pattern. The first sealing ring and the second sealing ring include conductive layer patterns alternately arranged and electrically connected to the conductive via in the sealing ring region. The conductive layer patterns of the first sealing ring and the second sealing ring are from the bottom layer to the top layer of the interconnect structure.

[0053] An embodiment provides a semiconductor chip. The semiconductor chip includes a circuit area, a sealing ring area, an electronic circuit, a sealing ring structure, and a signal wiring. The sealing ring area surrounds the circuit area. The sealing ring area includes a buffer zone surrounding the boundary of the circuit area. The electronic circuit is arranged in the circuit area. The sealing ring structure is arranged in the sealing ring area and surrounds the circuit area. The sealing ring structure is separated from the boundary of the circuit area by the buffer zone. The signal wiring is arranged in the buffer zone and extends to the circuit area. The signal wiring is electrically connected to the electronic circuit.

[0054] In some embodiments, the semiconductor chip further includes a semiconductor substrate, an interconnection structure and a shielding structure. The sealing ring structure and the signal wiring are arranged on the semiconductor substrate. The interconnection structure is arranged on the semiconductor substrate. The shielding structure is arranged in the interconnection structure of the buffer zone. The shielding structure surrounds and is separated from the signal wiring. The shielding structure includes a first conductive layer pattern, a second conductive layer pattern and a third conductive layer pattern. The first conductive layer pattern and the second conductive layer pattern are located on opposite surfaces of the signal wiring. The third conductive layer pattern is located next to the signal wiring and between the first conductive layer pattern and the second conductive layer pattern.

[0055] In some embodiments, the shielding structure further includes a conductive via adjacent to the opposite side surface of the signal wiring. The first conductive layer pattern is electrically connected to the second conductive layer pattern through the conductive via and the third conductive layer pattern.

[0056] In some embodiments, the first conductive layer pattern, the second conductive layer pattern and the signal wiring belong to different conductive layer levels of the interconnect structure. The shielding structure is grounded.

[0057] In some embodiments, the semiconductor chip further includes a dummy pattern disposed on the semiconductor substrate of the buffer region, wherein the dummy pattern is electrically suspended.

[0058] The semiconductor structure (such as a semiconductor chip) utilizes a buffer zone located inside the sealing ring area to accommodate conductive wiring connected to the electronic circuit in the circuit area. Therefore, electronic circuits with the same or similar functions can be arranged near the boundary of the circuit area and electrically connected to each other through the conductive wiring structure in the buffer zone. The wiring area in the circuit area can be further reduced. When the electronic circuit includes an analog circuit and the conductive wiring includes clock signal wiring, interference with other electronic circuits (for example, radio frequency circuits) in the circuit area can be reduced. When some conductive wiring is moved outside the circuit area, the wiring area in the circuit area can be released to increase wiring flexibility. The size of the semiconductor structure (such as a semiconductor chip) can be further reduced.

[0059] Although the present invention has been described by way of examples and preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (which will be obvious to those skilled in the art). Therefore, the attached claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor structure, characterized in that: include: A semiconductor substrate having a circuit area and a seal ring area surrounding the circuit area; an electronic circuit disposed on the semiconductor substrate, located in the circuit region; A first sealing ring disposed on the semiconductor substrate, located in the sealing ring area and surrounding the circuit area; a buffer zone located in the sealing ring region and disposed between the circuit region and the first sealing ring, wherein the first sealing ring is separated from the circuit region by the buffer zone; and A conductive wiring is arranged on the semiconductor substrate and is located in the buffer zone, wherein the conductive wiring is electrically connected to the electronic circuit.

2. The semiconductor structure according to claim 1, wherein: The conductive wiring includes a connection portion extending from the buffer region to the circuit region.

3. The semiconductor structure according to claim 1, wherein: The conductive wiring is separated from the first sealing ring.

4. The semiconductor structure according to claim 1, wherein: Further including: an interconnect structure disposed on the semiconductor substrate; as well as A shielding structure, wherein the shielding structure and the conductive wiring are embedded in the dielectric layer of the interconnect structure, located in the buffer zone, wherein the shielding structure surrounds and is separated from the conductive wiring, and the shielding structure comprises: a first conductive layer pattern located above the top surface of the conductive wiring; a second conductive layer pattern located below a bottom surface of the conductive wiring, wherein the first conductive layer pattern and the second conductive layer pattern overlap each other; and A third conductive layer pattern is located beside the opposite side surface of the conductive wiring.

5. The semiconductor structure according to claim 4, characterized in that The conductive wiring is a signal wiring, and the shielding structure is grounded.

6. The semiconductor structure according to claim 4, wherein: The first conductive layer pattern, the second conductive layer pattern and the conductive wiring belong to different conductive layer levels of the interconnect structure.

7. The semiconductor structure according to claim 4, wherein: The first conductive layer pattern and the conductive wiring belong to adjacent conductive layer levels of the interconnect structure.

8. The semiconductor structure according to claim 4, wherein: The second conductive layer pattern and the conductive wiring belong to adjacent conductive layer levels of the interconnect structure.

9. The semiconductor structure according to claim 4, characterized in that The third conductive layer pattern and the conductive wiring belong to the same conductive layer level of the interconnect structure.

10. The semiconductor structure according to claim 4, wherein: The shielding structure further comprises: A conductive via is disposed near the opposite side surface of the conductive wiring, wherein the first conductive layer pattern is electrically connected to the second conductive layer pattern through the conductive via and the third conductive layer pattern.

11. The semiconductor structure according to claim 1, wherein: Further including: A dummy pattern is located on the semiconductor substrate and is located in the buffer zone.

12. The semiconductor structure according to claim 11, wherein: The dummy pattern is electrically suspended.

13. The semiconductor structure according to claim 11, wherein: The dummy pattern includes a dummy active area surrounded by isolation features in the semiconductor substrate, a dummy poly pattern, a dummy conductive pattern, or a combination thereof.

14. The semiconductor structure according to claim 1, wherein: Further including: A second sealing ring is arranged on the semiconductor substrate and is located in the sealing ring area, wherein the second sealing ring surrounds the first sealing ring and is surrounded by the scribe line area of ​​the semiconductor substrate, wherein the conductive wiring is separated from the second sealing ring.

15. The semiconductor structure according to claim 14, wherein: Further including: An interconnect structure disposed on the semiconductor substrate, wherein the interconnect structure comprises: A dielectric layer stacked on the semiconductor substrate; a conductive layer pattern embedded in the dielectric layer; and Conductive vias alternately arranged with and electrically connected to the conductive layer pattern, Each of the first sealing ring and the second sealing ring includes a conductive layer pattern alternately arranged and electrically connected with the conductive through holes in the sealing ring area, and the conductive layer patterns of the first sealing ring and the second sealing ring are from the bottom layer to the top layer of the interconnect structure.

16. A semiconductor chip, characterized in that: include: a circuit area; a seal ring region surrounding the circuit region, wherein the seal ring region includes a buffer zone surrounding a boundary of the circuit region; an electronic circuit disposed in the circuit area; a seal ring structure disposed in the seal ring area, surrounding the circuit area, wherein the seal ring structure is separated from a boundary of the circuit area by the buffer zone; and A signal wiring is arranged in the buffer area and extends to the circuit area, wherein the signal wiring is electrically connected to the electronic circuit.

17. The semiconductor chip according to claim 16, wherein: Further including: a semiconductor substrate, wherein the seal ring structure and the signal wiring are disposed on the semiconductor substrate; An interconnect structure is disposed on a semiconductor substrate; as well as A shielding structure is disposed in a buffer zone in the interconnect structure, wherein the shielding structure surrounds and is separated from the signal wiring, wherein the shielding structure comprises: a first conductive layer pattern and a second conductive layer pattern located on a surface opposite to the signal wiring; as well as The third conductive layer pattern is located beside the signal wiring and between the first conductive layer pattern and the second conductive layer pattern.

18. The semiconductor chip according to claim 17, wherein: The shielding structure further comprises: A conductive via is provided near the opposite side surface of the signal wiring, wherein the first conductive layer pattern is electrically connected to the second conductive layer pattern through the conductive via and the third conductive layer pattern.

19. The semiconductor chip according to claim 17, wherein: The first conductive layer pattern, the second conductive layer pattern, and the signal wiring belong to different conductive layer levels of the interconnect structure, and wherein the shielding structure is grounded.

20. The semiconductor chip according to claim 17, wherein: Further including: A dummy pattern is disposed in a buffer region on a semiconductor substrate, wherein the dummy pattern is electrically suspended.

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