Reinforcement member with one or more passages

Abstract

The present disclosure relates to a reinforcement member having one or more passages. Novel tools and techniques are provided for implementing a semiconductor package or chip package, and more particularly, methods, systems, and apparatus are provided for implementing a semiconductor package or chip package including a reinforcement member with vias. In various embodiments, an apparatus includes a substrate and a connector electrically coupled to the substrate. A reinforcement member is disposed between the substrate and the connector and is configured to confine at least one of the substrate or the connector. A via extends through the body of the reinforcement member and electrically couples the connector to the substrate.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure relates generally to methods, systems, and apparatus for implementing semiconductor packages or chip packages, and more particularly, to methods, systems, and apparatus for implementing semiconductor packages or chip packages that include a stiffener having one or more vias. Background Art

[0004] Conventional stiffener rings are purely mechanical and do not contain any electrical features. As more connectors and connections are added to the chip package, mechanical stiffener rings compete for space with the connectors and connections in the chip package. Once connectors and connections are added to the chip package, there is little room left for mechanical stiffener rings. However, without stiffener rings, chip package warpage may be high due to thermal expansion coefficient mismatch between the substrate and the circuit board.

[0005] Therefore, there is a need for more robust and scalable solutions for implementing semiconductor packages and chip packages.Accordingly, methods, systems and apparatus for implementing semiconductor packages or chip packages including a stiffening member having one or more vias are provided. Summary of the invention

[0006] In one aspect, the present disclosure provides an apparatus comprising: a substrate; a connector coupled to the substrate; and a component disposed between the substrate and the connector and configured to restrict at least one of the substrate or the connector, the component comprising a via coupled to the connector and the substrate.

[0007] On the other hand, the present disclosure provides a semiconductor device, comprising: a substrate including an interconnect; a connector configured to couple to the interconnect of the substrate; and a component between the substrate and the connector and configured to limit at least one of the substrate or the connector, the component comprising a passage coupling the interconnect of the substrate to the connector.

[0008] On the other hand, the present disclosure provides a method, comprising: providing a substrate; providing a connector; and coupling a component to the substrate and the connector, the component being configured to restrict at least one of the substrate or the connector, wherein the component is between the substrate and the connector and includes a passage, the passage being coupled to the connector and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of this specification and the accompanying drawings, wherein like reference numerals are used to refer to like components. In some instances, a sub-label is associated with a reference numeral to identify one of multiple similar components. When a reference numeral is cited without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0010] Figure 1A , 1C and 1E to 1J are schematic cross-sectional views of semiconductor devices having components including one or more vias according to various embodiments;

[0011] Figure 1B and 1D is a top perspective view of a component including one or more passageways according to various embodiments;

[0012] Figures 2A to 2F is a schematic cross-sectional view of a semiconductor device having a component including one or more vias according to various embodiments;

[0013] Figure 3 is a schematic cross-sectional view of a semiconductor device having a component including one or more vias according to various embodiments; and

[0014] Figure 4 is a flow chart of a method of fabricating a semiconductor device having a component including one or more vias according to various embodiments. DETAILED DESCRIPTION

[0015] Various embodiments provide tools and techniques for implementing a semiconductor package or chip package including a stiffener having one or more vias.

[0016] In a first aspect, a device is provided that includes a substrate. A connector is coupled to the substrate. A member is disposed between the substrate and the connector. The member constrains at least one of the substrate or the connector. In addition, a passage extends through a body of the member. The passage is coupled to the connector and the substrate.

[0017] In some embodiments, the area of ​​the first surface of the member adjacent to the first surface of the substrate is characterized by being approximately the same in area size as the area of ​​the first surface of the substrate. The member is configured to uniformly constrain the substrate across the area of ​​the first surface of the substrate. In other cases, the area of ​​the first surface of the member adjacent to the first surface of the substrate is smaller than the area of ​​the second surface of the member adjacent to the first surface of the connector.

[0018] In various cases, the connector includes a printed circuit board. An area of ​​a second surface of the member adjacent to a first surface of the printed circuit board is characterized as being substantially the same in size as an area of ​​the first surface of the printed circuit board.

[0019] In some embodiments, the connector comprises at least one of an optical connector, a high-speed data connector, a high-power connector, or a backplane connector, or the like. An area of ​​a second surface of the member adjacent to a first surface of at least one of the optical connector, the high-speed data connector, the high-power connector, or the backplane connector is characterized by being substantially the same or greater in size than an area of ​​the first surface of at least one of the optical connector, the high-speed data connector, the high-power connector, or the backplane connector.

[0020] In various cases, the member has a coefficient of thermal expansion that is substantially the same as the substrate. The member includes at least one of copper, aluminum, ceramic, steel, stainless steel, Teflon, silicon, or a polymer, and the via includes at least one of copper, aluminum, gold, silver, tin, nickel, or lead. The member includes at least two adjacent vias. The ratio between the distance between the at least two adjacent vias and the width of each of the at least two adjacent vias is at least 2:1. The ratio between the length of the member and the thickness of the member is equal to or greater than 10:1.

[0021] In another aspect, a semiconductor device includes: a substrate including an interconnect; a connector configured to couple to the interconnect of the substrate; and a member between the substrate and the connector. The member is configured to constrain at least one of the substrate or the connector. A via extends through the member and couples the interconnect of the substrate to the connector.

[0022] In some examples, the first surface of the member adjacent to the first surface of the substrate uniformly constrains the substrate across the first surface of the substrate. In some examples, the area of ​​the first surface of the member adjacent to the first surface of the substrate is greater than the area of ​​the first surface of the substrate.

[0023] In various embodiments, the connector comprises a printed circuit board. A second surface of the member adjacent to a first surface of the printed circuit board uniformly constrains the printed circuit board across the first surface of the printed circuit board. In other cases, the connector comprises at least one of an optical connector, a high-speed data connector, a high-power connector, or a backplane connector, or the like.

[0024] In some cases, the via is located in a first layer of the component, and the component further includes a second redistribution layer electrically coupled to the via.

[0025] In another aspect, a method of manufacturing a semiconductor having a component is provided. The method includes providing a substrate and a connector. The method continues by coupling the component to the substrate and the connector. The component is between the substrate and the connector. The via extends through the component and electrically couples the substrate to the connector.

[0026] In the following description, for the purpose of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be combined with other embodiments. However, for the same reason, a single feature or several features of any described embodiment should not be considered essential to each embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0027] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0028] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, between, below, near, or in some other relative manner), it is understood that the element may be directly disposed relative to the other element (e.g., disposed directly above the other element) or that there may be intervening elements between the elements. Conversely, when an element is referred to as being "directly disposed" relative to another element, it is understood that in the "direct" instance there are no intervening elements. However, the presence of a direct disposition does not exclude other instances in which there may be intervening elements.

[0029] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include multiple different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include multiple dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intervening elements that exist between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which intervening elements may exist.

[0030] In addition, the terms left, right, front, back, top, bottom, front, back, clockwise and counterclockwise are used only for explanation purposes and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0031] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context dictates otherwise, intervening processes may occur before and / or after any portion of the described processes and further various processes may be reordered, added, and / or omitted according to various embodiments.

[0032] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, etc. should be understood as being modified in all instances by the term "substantially." As used herein, the term "substantially" or "approximately" refers to a variation of ±10% or less (e.g., ±10%, ±5%, etc.) relative to a reference value or ratio, including the endpoints of the range.

[0033] In this application, the use of the singular includes the plural unless specifically stated otherwise, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "including" and "having" as well as other forms such as "includes," "included," "has," "have," and "had" should be considered non-exclusive. Also, terms such as "element" or "component" encompass both elements and components constituting one unit and elements and components constituting more than one unit, unless specifically stated otherwise.

[0034] As used herein, the phrase "at least one of ..." preceding a series of items (where the terms "and" or "or" are used to separate any of the items) modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one of ..." does not require selection of at least one of each listed item; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of the items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where selection of "at least one of each of A, B, and C" or, alternatively, "at least one of A, at least one of B, and at least one of C" is desired, it is explicitly described as such.

[0035] In conventional semiconductor or chip packages, the stiffener ring is purely mechanical and has no electrical features. However, as chip packages become more complex, stiffener rings compete for space with connectors within the chip package.

[0036] The proposed embodiments may be a semiconductor or chip module (e.g., an integrated circuit (IC), chip, or other semiconductor device) that provides a reinforcement member having one or more passages. By implementing a reinforcement member having one or more passages, the reinforcement member may be configured to provide one or more electrical connections between one or more connectors and a substrate of the semiconductor or chip module. Thus, such an improved reinforcement member provides an electrical connection between the substrate and the one or more connectors while still controlling warpage between the substrate and the one or more connectors.

[0037] Figure 1A , 1C 1E to 1E are schematic cross-sectional views of different embodiments of a semiconductor device 100 according to various embodiments. Figure 1B and 1D 1 to 3 are top perspective views of component 130 according to various embodiments. It should be noted that various components of semiconductor device 100 are schematically illustrated in FIGS. 1 to 3 , and modifications to various components, orientations, and other arrangements of semiconductor device 100 are possible according to various embodiments. In addition, although FIGS. 1 to 3 are described as separate embodiments for ease of description, a person of ordinary skill will understand that various modifications to each embodiment may be applicable to other embodiments.

[0038] In various embodiments, the semiconductor device 100 includes a substrate 105. The substrate 105 is a supporting material (e.g., silicon, silicon dioxide, aluminum oxide, gallium, germanium, ceramics, organic structures, laminated organic structures, and / or any other material or combination of materials) on or within which elements or components of the semiconductor device 100 (e.g., connector 110, component 130, interconnect 125, or the like) are fabricated or attached.

[0039] In some examples, semiconductor device 100 includes one or more connectors 110. One or more connectors 110 are capable of connecting (e.g., electrically coupling, attaching, or the like) to one or more elements, components, accessories, mechanisms, devices, or the like of substrate 105. In some cases, one or more connectors 110 include a circuit board 115 (e.g., a printed circuit board (PCB)). Additionally or alternatively, one or more connectors 110 (e.g., one or more connectors 120) include at least one of an optical connector, a high-speed data connector, a high-power connector, a backplane connector, or the like.

[0040] In various cases, the substrate 105 includes one or more layers. The layers may include one or more power layers, ground layers, other conductive interconnect layers, non-conductive layers, redistribution layers, conductive structures, and other layers and structures. The layers may further include one or more layers configured to provide component interconnection. For example, a wiring layer is a layer of the substrate 105 through which interconnections can be established between components of the semiconductor device 100. In a non-limiting example, the interconnection can be configured to connect (e.g., electrically connect) one or more connectors 120 to the circuit board 115. For example, a connector can be routed through the substrate 105 via one or more interconnects 125. The interconnect 125 is one or more structures that couple (e.g., electrically couple or the like) two or more elements of a semiconductor device (e.g., substrate 105, connector 110, component 130, or the like together) together. Interconnect 125 may include one or more copper or metal pads, copper or metal traces, copper or metal through-hole vias, copper or metal microbumps, copper or metal solder balls, copper or metal pillars or pillars, and / or other suitable interconnects.

[0041] In some cases, interconnect 125 extends through substrate 105 or is coupled to a surface of substrate 105. In a non-limiting example, Figure 1A and Figure 2B As shown in , trace 125a extends through substrate 105 and is electrically coupled to solder ball 125b, which is coupled to a surface of substrate 105.

[0042] In various embodiments, the semiconductor device 100 further includes a member (eg, a stiffener member, a stiffening member, a stiffener ring, a stiffening ring, or the like) 130. The stiffener member 130 is disposed between the substrate 105 and the connector 110. Figures 1A to 1I In the case of , the member 130 is disposed between the substrate 105 and the printed circuit board 115. Alternatively, as Figures 2A to 2F, the member 130 is disposed between the substrate 105 and the connector(s) 120. Alternatively, as shown in Figure 3 As shown in , the first member 130a is disposed between the substrate 105 and the connector(s) 120 and the second member 130b is disposed between the substrate 105 and the printed circuit board 115.

[0043] The member 130 is configured to constrain at least one of the substrate 105 or the connector 110. For example, to constrain at least one of the substrate 105 or the connector 110, the member 130 controls or prevents in-plane thermal expansion or contraction along the length of the substrate 105 or the connector 110. In other words, the member 130 controls or prevents the substrate 105 or the connector 110 from expanding or contracting along the length L5 or the width W3 of the substrate 105 or the connector 110. Additionally, to constrain at least one of the substrate 105 or the connector 110, the member 130 controls or prevents out-of-plane (relative to a plane extending along the length of the substrate) rotation of the substrate 105 or the connector 110. In other words, the stiffening member 130 controls or prevents the substrate 105 or the connector 110 from bending or curling out of plane relative to a plane extending along the length of the substrate. In some cases, the member 130 provides control of out-of-plane warpage to the extent that the out-of-plane warpage of an equivalent stiffener-free semiconductor device is halved. Such control is critical for practical uses where a high degree of flatness is required for components such as semiconductor device 100, substrate 105, or connector 110, or the like. For example, situations such as component electrical testing and component assembly require a high degree of flatness.

[0044] The member 130 may be in direct or indirect contact with the substrate 105 or the connector 110 to constrain at least one of the substrate 105 or the connector 110. By constraining at least one of the substrate 105 or the connector 110, the member 130 is configured to control or prevent warping or deformation of at least one of the substrate 105 or the connector 110. Warping or deformation of at least one of the substrate 105 or the connector 110 may occur due to different construction materials used for the substrate 105 and the connector 110, due to mismatch in thermal expansion coefficients between the substrate 105 and the connector 110, or the like. A semiconductor device that is warped or deformed by more than a predetermined amount may become useless because one or more interconnects 125 of the substrate 105 cannot be connected to the one or more connectors 110. The member 130 is used to constrain, prevent, or control warping of at least one of the substrate or the connector by more than a predetermined amount and ensure that the one or more interconnects 125 of the substrate 105 are connected to the one or more connectors 110.

[0045] In some embodiments, component 130 includes one or more of metal, ceramic, polymer, or any combination thereof. Even more specifically, component 130 may include any combination of copper, aluminum, ceramic, steel, stainless steel, Teflon, silicon, or a polymer filled with silicon dioxide or aluminum oxide, or the like.

[0046] The member 130 is configured to have a coefficient of thermal expansion that is substantially the same or similar to that of the substrate 105. The coefficient of thermal expansion measures the fractional change in the size of an object per degree of temperature change at a constant pressure (e.g., atmospheric pressure at sea level or other constant pressure). By forming the member 130 from a material having a coefficient of thermal expansion that is substantially the same or similar to that of the substrate 105, the member 130 may have similar coefficient of thermal expansion properties as the substrate (e.g., having similar expansion / contraction properties based on temperature). Having similar coefficient of thermal expansion properties between the substrate and the reinforcement member helps couple the member 130 to the substrate and further constrain the substrate 105 to reduce warping of the substrate 105 by helping to control out-of-plane curling or bending of the substrate.

[0047] The member 130 may also constrain the substrate 105 based on the stiffness or Young's modulus of the member 130. A higher stiffness or modulus will further constrain the substrate 105 or connector 110 to reduce warping of the substrate 105. The effectiveness of the member 130 in constraining the substrate 105 or connector 110 is due to 1) its stiffness, which is a function of the Young's modulus, and 2) its geometry (described below with respect to Figures 1A to 3 Each of these properties together serves to constrain the substrate 105 or connector 110.

[0048] The component 130 further includes one or more vias 135. The one or more vias 135 may extend completely through the body 134 of the component 130 (e.g., a "through" via), may extend from an outer surface through a portion of the component 130 (e.g., a "blind" via), or may extend through a portion of the body 134 of the component 130 and be completely hidden from external view (e.g., a "buried" via), and / or the like. The one or more vias 135 may be filled, plated, or coated with a conductive material. The conductive material may include a metal, such as copper, aluminum, gold, silver, tin, nickel, lead, or a combination of metals / alloys, or may be formed by other conductive materials or combinations of conductive materials. The one or more vias 135 are configured to form an electrical connection for allowing an electrical signal to travel from the one or more connectors 110 to the substrate 105 or from the substrate 105 to the one or more connectors 110. In other words, the one or more vias 135 electrically couple the substrate 105 to the one or more connectors 110.

[0049] In some cases, such as Figure 1A, component 130 includes at least two adjacent passages (e.g., passages 135a and 135b). The ratio between the distance D1 between the inner edges (or centers) of the at least two adjacent passages 135a and 135b and the width W1 of each of the at least two adjacent passages 135a and 135b is at least 2:1. By making the ratio between the distance between the at least two adjacent passages and the width of each of the at least two adjacent passages at least 2:1, crosstalk between adjacent passages is minimized while space usage within component 130 is maximized. In some cases, such as Figure 1C As shown in FIG. 1 , the ratio between the length L1 of the member 130 and the thickness T1 of the member 130 is equal to or greater than 10: 1. By making the member 130 as thin as possible, crosstalk between adjacent vias is minimized while space usage within the member 130 is maximized.

[0050] The one or more vias 135 may be electrically connected to the substrate 105, the one or more connectors 110, and / or the one or more interconnects 125 of the substrate 105 via one or more interconnects 140. The one or more interconnects 140 include, but are not limited to, one or more copper or metal pads, one or more copper or metal traces, one or more through-hole vias, micro-bumps, one or more solder balls or bumps, one or more copper or metal pillars or posts, other suitable interconnects, combinations of interconnects, or the like.

[0051] Various embodiments of the member 130 will now be described with respect to Figures 1 to 3. Although for ease of description, Figures 1A to 1F , 2A to 2E and 3 are described as separate embodiments, but a person of ordinary skill will understand that various modifications to the component 130 in each embodiment may be applicable to other embodiments of the component 130.

[0052] Steering Figure 1A and 1B , the member 130 is a ring (e.g., rectangular, circular, triangular, etc.) having an opening 150. One or more interconnects 125c may be disposed in the opening 150 to electrically couple the circuit board 115 to the substrate 105. The member 130 is located between the substrate 105 and the circuit board 115. The member 130 extends along the length and width or perimeter of the substrate 105 or the circuit board 115, such as Figure 1A and 1B When the member 130 is a ring, the member 130 imposes a limit on the perimeter of the substrate 105 to prevent or control warping of the substrate 105. Figure 1A In this case, the first surface 155 of the member 130 pushes against the first surface 160 of the substrate 105 to prevent the substrate 105 from deforming or warping.

[0053] exist Figures 1C to 1FIn the embodiment, the component 130 is a continuous layer without openings except for one or more vias 135. The component 130 has an area size that is approximately or substantially the same as the area of ​​the first surface 160 of the substrate 105 ( Figure 1C shown in) or larger ( Figure 1E ) or smaller than the area of ​​the first surface 160 of the substrate 105 ( Figure 1F 160 ). When the first surface 155 of the component 130 is approximately the same size or larger in area than the first surface 160 of the substrate 105, the first surface 155 uniformly applies the restriction across substantially the entire area of ​​the first surface 160 of the substrate 105. As used herein, uniformly applying the restriction means that the component 130 substantially uniformly controls (1) in-plane thermal expansion of the substrate 105 or connector 110 and (2) out-of-plane rotation of the substrate 105 or connector 110 about substantially the entire area of ​​the first surface 160 of the substrate. By uniformly applying the restriction across the area of ​​the first surface 160 of the substrate 105, warping or deformation of the substrate 105 can be prevented across the entire substrate 105, not just at the periphery of the substrate 105. Figure 1C and 1E In this case, the first surface 155 of the member 130 pushes against the first surface 160 of the substrate 105 to prevent the substrate 105 from deforming or warping.

[0054] In some cases, such as Figure 1E , component 130 has an area of ​​second surface 165 that is approximately or substantially the same in size as an area of ​​first surface 170 of circuit board 115. When second surface 165 of component 130 is approximately the same in size or larger in size than the area of ​​first surface 170 of circuit board 115, second surface 165 of component 130 applies restraint uniformly across substantially the entire area of ​​first surface 170 of circuit board 115. As used herein, applying restraint uniformly means that component 130 substantially uniformly controls (1) in-plane thermal expansion of substrate 105 or connector 110 and (2) out-of-plane rotation of substrate 105 or connector 110 about substantially the entire area of ​​first surface 170 of circuit board 115. By applying restraint uniformly across the area of ​​first surface 170 of circuit board 115, warping or deformation of circuit board 115 may be prevented across the entire circuit board 115, not just at the perimeter of circuit board 115. Figure 1C and 1E In this case, the second surface 165 of the component 130 is pulled against the first surface 170 of the circuit board 115 to prevent the circuit board 115 from deforming or warping.

[0055] In some cases, such as Figure 1F, the component 130 may have an area of ​​the first surface 155 that is less than the area of ​​the first surface 160 of the substrate 105. One or more interconnects 125 may be disposed on an outer edge 157 of the component 130 between the circuit board 115 and the substrate 105.

[0056] In some embodiments, the length of the component 130 varies from the first surface 155 of the component 130 to the second surface 165 of the component 130. The length of the component 130 can vary based on the length L2 of the substrate and the length L3 of the circuit board 115. In a non-limiting example, Figure 1G , if substrate 105 is smaller than circuit board 115, length L2 of first surface 155 of member 130 may be substantially the same length as length L2 of first surface 160 of substrate 105, while length L3 of second surface 165 of member 130 may be substantially the same length as length L3 of first surface 170 of circuit board 115. Alternatively, if substrate 105 is smaller than circuit board 115, length of first surface 155 of member 130 may be substantially the same length as length of first surface 160 of substrate 105, while length of second surface 165 of member 130 may be substantially the same length as length of first surface 170 of circuit board 115. In some cases, to change the length of member 130, member 130 may include one or more inclined sidewalls 175. By varying the length of component 130 based on the lengths of substrate 105 and circuit board 115 , first surface 155 of component 130 applies restriction uniformly across substantially the entire area of ​​first surface 160 of substrate 105 , and second surface 165 of component 130 applies restriction uniformly across substantially the entire area of ​​first surface 170 of circuit board 115 .

[0057] like Figure 1H , one or more members 130 may be selectively placed at different locations between the substrate 105 and the circuit board 115. In a non-limiting example, the member 130 may be a ring 130c and have a portion 130d positioned toward the middle of the substrate 105, the circuit board 115, the member 130b, or the like. One or more openings 180 between different portions of the member 130 may be used to add one or more additional connectors 110, interconnects 140, or other components.

[0058] In some cases, component 130 is formed from one or more layers (eg, layers 131, 132, and 133), such as Fig. 1I and 1J130 to different locations on the component 130. Redistribution layers 132 are required when electrical connectors within the substrate 105, component 130, and / or circuit board 115 are not aligned. In a non-limiting example, a redistribution layer 132 having one or more interconnects 185 within the component 130 can be used to connect one or more vias 135 at different locations of the component 130, such as Fig. 1I Alternatively, a redistribution layer 132 having one or more interconnects 185 within component 130 may be used to connect one or more vias 135 to one or more interconnects 125 of substrate 105 or circuit board 115, such as Figure 1J As shown in .

[0059] Steering Figure 2A , member 130 is located between connector 120 and substrate 105. In this case, member 130 is a continuous layer with no openings except for one or more vias 135. However, member 130 may be Figure 1A and 1B The member 130 may have an area size that is approximately or substantially the same as the area of ​​the second surface 187 of the substrate 105 ( Figure 2A When the first surface 155b of the member 130 is approximately the same size or larger in area as the second surface 187 of the substrate 105, the first surface 155 uniformly applies the restriction across substantially the entire area of ​​the second surface 187 of the substrate 105. By uniformly applying the restriction across the area of ​​the second surface 187 of the substrate 105, warping or deformation of the substrate 105 can be prevented across the entire substrate 105, not just at the periphery of the substrate 105. Figure 2A In this case, the member 130 pulls the second surface 187 of the substrate 105 to prevent the substrate 105 from deforming or warping.

[0060] Steering Figure 2B , member 130 is located between connector 120 and substrate 105. In this case, member 130 is a continuous layer without openings other than one or more vias 135. Member 130 may have an area size that is approximately or substantially the same as the area of ​​first surface 195 of connector 120 ( Figure 2AWhen the second surface 190 of the member 130 is approximately the same size or larger in area as the first surface 195 of the connector 120, the second surface 190 uniformly applies the restriction across substantially the entire area of ​​the first surface 195 of the connector 120. By uniformly applying the restriction across the area of ​​the first surface 195 of the connector 120, warping or deformation of the connector 120 can be prevented across the entire substrate 105, not just at the perimeter of the connector 120. In some cases, Figure 1F Similarly, the length of the member may vary based on the length of the substrate 105 and the connector 120 .

[0061] In some cases, such as Figure 2C As shown in , there are two or more connectors 120 (eg, connectors 120a and 120b) and the member 130 is disposed between the two or more connectors 120a and 120b and the substrate 105. Figure 2C In the case of, member 130 is a ring. Widths W2a and W2b of member 130 may vary based on a first surface (e.g., first surfaces 195a and 195b) of connector 120 (e.g., connectors 120a and 120b). In a non-limiting example, width W2a of a first side of member 130 is substantially the same width as first surface 195a of connector 120a, while width W2b of a second side opposite to the first side of member 130 is substantially the same width as first surface 195b of connector 120b. Width W2a and width W2a may be the same width or different widths depending on the widths of first surfaces 195a and 195b of connector 120.

[0062] exist Figure 2D 1 , the member 130 is a continuous layer without openings except for one or more passages 135. The member 130 is disposed between two or more connectors 120 (e.g., connectors 120a and 120b). The one or more passages 135 are selectively disposed in a position where one or more connectors 120 are present, and are not disposed in a position where no connector 120 is present.

[0063] like Figure 2E , the member 130 can have one or more openings selectively disposed on the member 130. One or more openings between different portions of the member 130 can be configured to surround one or more additional connectors 197, interconnects, or other components.

[0064] In various embodiments, such as Figure 2F, the thickness of the member 130 can vary across the length L4 of the member 130. In a non-limiting example, the member 130 can be thicker or thinner in the middle portion 198 of the member 130. In some cases, the thickness of the middle portion 198 of the member 130 can be configured to be substantially flush or consistent with the second surface 199 of at least one of the one or more connectors 120.

[0065] Steering Figure 3 , two components 130a and 130b may be provided. The first component 130a is located between the substrate and the one or more connectors 120, and the second component 130b is located between the substrate and the circuit board 115.

[0066] It should be noted that although for ease of description, Figure 1J , 2A 2F and 3 are described as separate embodiments, but a person of ordinary skill will understand that various modifications to the component 130 in each embodiment may be applicable to other embodiments of the component 130. In a non-limiting example, the component 130 between the substrate 105 and the connector 120 may also have a Fig. 1I and 1J In addition, although member 130 is depicted as including a substantially rectangular or square cross-section, it should be appreciated that any shape or combination of shapes may be used for member 130. In some non-limiting examples, member 130 may include a tubular shape (e.g., a circular or elliptical cross-section), a polygonal cross-section, a triangular cross-section, or the like.

[0067] Figure 4 4 is a flow chart of a method 400 of manufacturing a semiconductor device 100 according to various embodiments. The method 400 may begin at block 405 by providing or forming a substrate. As known to those skilled in the art, forming the substrate may include, but is not limited to, various additive and / or subtractive manufacturing processes. In further examples, the substrate may be formed using manufacturing technologies that are being developed and / or yet to be developed. Therefore, it should be understood that the method 400 is not limited to any particular method of manufacturing a particular substrate.

[0068] The method 400 continues by providing or forming a connector at block 410. The connector may include at least one of a circuit board, an optical connector, a high-speed data connector, a high-power connector, or a backplane connector, or the like.

[0069] The method 400 continues at block 415 by coupling a reinforcement member to the substrate and the connector. The member is between the substrate and the connector. The member includes one or more vias. The one or more vias extend through the member and electrically couple the substrate to the connector.

[0070] The semiconductor device 100 of FIGS. 1-3 and / or components thereof may be fabricated using the techniques and processes described above with respect to the various embodiments, as described herein.

[0071] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. In addition, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented in any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context dictates otherwise, this functionality may be distributed among various other system components according to several embodiments.

[0072] In addition, although the processes of the methods and processes described herein are described in a particular order for ease of description, various processes may be reordered, added, and / or omitted according to various embodiments unless the context dictates otherwise. In addition, processes described with respect to one method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized in an alternative structural architecture and / or incorporated into other described systems. Therefore, although various embodiments are described with or without certain features for ease of description and explanation of aspects of those embodiments, various components and / or features described herein with respect to a particular embodiment may be replaced, added, and / or deleted from other described embodiments unless the context dictates otherwise. Therefore, although several embodiments are described above, it will be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A device comprising: substrate; a connector coupled to the substrate; and A member disposed between the substrate and the connector and configured to constrain at least one of the substrate or the connector includes a via coupled to the connector and the substrate.

2. The apparatus of claim 1, wherein an area of ​​a first surface of the member adjacent to the first surface of the substrate is characterized by being approximately the same in size as an area of ​​the first surface of the substrate.

3. The apparatus of claim 2, wherein the means is configured to uniformly confine the substrate across the area of ​​the first surface of the substrate. 4 . The apparatus of claim 1 , wherein a first surface of the member adjacent to the first surface of the substrate has a smaller area than a second surface of the member adjacent to the first surface of the connector.

5. The apparatus of claim 1, wherein the connector comprises a printed circuit board.

6. The apparatus of claim 5, wherein an area of ​​a second surface of the member adjacent to the first surface of the printed circuit board is characterized as being approximately the same size in area as an area of ​​the first surface of the printed circuit board.

7. The apparatus of claim 1, wherein the connector comprises at least one of an optical connector, a high-speed data connector, a high-power connector, or a backplane connector.

8. The apparatus of claim 7, wherein an area of ​​a second surface of the member adjacent to the first surface of the connector is characterized as being approximately the same or greater in size than an area of ​​the first surface of the connector.

9. The apparatus of claim 1, wherein the member has substantially the same coefficient of thermal expansion as the substrate.

10. The apparatus of claim 1, wherein the member comprises at least two adjacent passages, and wherein a ratio between a distance between the at least two adjacent passages and a width of each of the at least two adjacent passages is at least 2:

1.

11. The apparatus of claim 1, wherein a ratio between a length of the member and a thickness of the member is equal to or greater than 10:

1.

12. The apparatus of claim 1, wherein the member comprises at least one of copper, aluminum, ceramic, steel, stainless steel, Teflon, silicon, or a polymer, and wherein the via comprises at least one of copper, aluminum, gold, silver, tin, nickel, or lead.

13. A semiconductor device comprising: a substrate including an interconnect; a connector configured to couple to the interconnect of the substrate; and A member between the substrate and the connector and configured to constrain at least one of the substrate or the connector includes a via coupling the interconnect of the substrate to the connector. 14 . The semiconductor device of claim 13 , wherein a first surface of the member adjacent to the first surface of the substrate uniformly constrains the substrate across the first surface of the substrate. 15 . The semiconductor device according to claim 13 , wherein an area of ​​a first surface of the member adjacent to the first surface of the substrate is larger than an area of ​​the first surface of the substrate.

16. The semiconductor device according to claim 13, wherein the connector comprises a printed circuit board. 17 . The semiconductor device of claim 16 , wherein a second surface of the member adjacent to the first surface of the printed circuit board uniformly constrains the printed circuit board across the first surface of the printed circuit board.

18. The semiconductor device of claim 13, wherein the connector comprises at least one of an optical connector, a high-speed data connector, a high-power connector, or a backplane connector.

19. The semiconductor device according to claim 13, wherein the via is located in the first layer of the member, and The component further includes a second redistribution layer electrically coupled to the via.

20. A method comprising: providing a substrate; Provide connectors; and A member is coupled to the substrate and the connector, the member being configured to constrain at least one of the substrate or the connector, wherein the member is between the substrate and the connector and includes a via coupled to the connector and the substrate.

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