Semiconductor structure and forming method thereof
By forming a multi -layer metal connection structure on the surface of the chip, the problem of copper column and welding cushion misalignment during the FCBGA packaging process is solved, and the effect of reducing the stress of the low -agency constant material and improving the reliability of the chip.
Patent Information
- Application Number
- CN202310935395.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-27
- Publication Date
- 2025-01-28
AI Technical Summary
During the FCBGA packaging process, due to the inconsistent thermal expansion coefficients of the substrate and chip, the central position of the copper column and substrate pads are offset after reflow soldering, which increases the risk of chip rupture and reliability problems.
By forming a multi -layer metal connection structure on the surface of the chip, including the first metal connection structure, the second metal connection structure, and the third metal connection structure, the secondary metal connection structure connect the first metal connection structure and the third metal connection structure to ensure the ensuring The third metal connection structure can flexibly adjust the position to avoid misplace during the packaging process.
Effectively avoid misalignment of copper columns and welded cushions, reduce the stress of the low -dielectric constant material layer, and improve the reliability of the chip.
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Figure CN119381369A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] As the size of FCBGA (Flip Chip Ball Grid Array Package) flip chips and packages become larger and larger, the thermal expansion coefficients of the substrate and chip are inconsistent, resulting in the center position of the copper pillar (bump) at the chip end and the substrate pad being offset after reflow. The larger the size, the greater the offset of the edge, especially the four corners of the chip. In addition, the chip and substrate designs of each product vary greatly, resulting in the inability to predict and judge this shrinkage size in advance. The industry currently uses a 0.1% shrinkage of the substrate. However, actual products still have misalignment between the center of the copper pillar and the substrate pad, and the warping of the substrate causes excessive stress, so the risk of cracking the low-dielectric constant material layer in the chip is huge.
[0003] At present, in the initial design of FCBGA (Flip Chip Ball Grid Array Package) products, the center of the copper pillar is vertically aligned with the center of the substrate pad, allowing the substrate manufacturer to shrink the substrate end. However, when the copper pillar and the substrate pad are misaligned, the substrate design drawings are often determined, and redesigning the shrinkage value is labor-intensive, time-consuming, and expensive, and cannot be achieved.
[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to avoid the misalignment of copper pillars and pads and reduce chip reliability. Summary of the invention
[0005] The present application provides a semiconductor structure and a method for forming the same, which can avoid misalignment of copper pillars and solder pads during chip packaging and reduce chip reliability.
[0006] One aspect of the present application provides a method for forming a semiconductor structure, including: providing a chip, wherein a first metal connection structure, a first dielectric layer and a first passivation layer are sequentially formed on the surface of the chip, wherein a portion of the first metal connection structure penetrates the first dielectric layer and extends into the first passivation layer and is exposed by the first passivation layer; forming a second metal connection structure on the surface of the first metal connection structure exposed by the first passivation layer, wherein the top surface area of the second metal connection structure is greater than the top surface area of the first metal connection structure and the top surface of the second metal connection structure completely covers the top surface of the first metal connection structure; and forming a third metal connection structure on the top surface of the second metal connection structure, wherein the third metal connection structure is completely located on the top surface of the second metal connection structure.
[0007] In some embodiments of the present application, the method for forming a second metal connection structure on the surface of the first metal connection structure exposed by the first passivation layer includes: forming a first barrier layer and a first seed layer in sequence on the surface of the first metal connection structure exposed by the first passivation layer and on the surface of the first passivation layer; forming a first photoresist layer on the surface of the first seed layer, the first photoresist layer including a first opening exposing a portion of the second seed layer, the first opening defining the second metal connection structure; electroplating and growing a first electroplating layer in the first opening with the exposed first seed layer as a matrix, the first electroplating layer, the first seed layer and the first barrier layer constituting the second metal connection structure; removing the first photoresist layer and the first seed layer and the first barrier layer outside the area covered by the first electroplating layer to expose a portion of the first passivation layer.
[0008] In some embodiments of the present application, the method for forming the semiconductor structure further includes: forming a second passivation layer on the exposed surface of the first passivation layer, the sidewall and surface of the second metal connection structure, wherein the second passivation layer exposes a portion of the first electroplating layer.
[0009] In some embodiments of the present application, a method for forming a third metal connection structure on the top surface of the second metal connection structure includes: forming a second barrier layer and a second seed layer in sequence on the surface of the first electroplating layer exposed by the second passivation layer and the surface of the second passivation layer; forming a second photoresist layer on the surface of the second seed layer, the second photoresist layer including a second opening exposing a portion of the second seed layer, the second opening defining the third metal connection structure; electroplating and growing a second electroplating layer in the second opening with the exposed second seed layer as a matrix, the second electroplating layer, the second seed layer and the second barrier layer constituting the third metal connection structure; forming a welding layer on the surface of the second electroplating layer; and removing the second seed layer and the second barrier layer outside the second photoresist layer and the area covered by the second electroplating layer.
[0010] In some embodiments of the present application, the first metal connection structure includes a first part located on the surface of the chip, a second part penetrating the first dielectric layer and electrically connected to the first part, and a third part located in the first passivation layer and electrically connected to the second part, the third part is exposed by the first passivation layer, the area of the third part is larger than the area of the second part and completely covers the second part.
[0011] In some embodiments of the present application, the top surface patterns of the second metal connection structure are all oriented toward the central axis of the chip.
[0012] In some embodiments of the present application, the top surface of the first metal connection structure is circular, the top surface of the third metal connection structure is circular, the top surface diameter of the third metal connection structure is smaller than the top surface diameter of the first metal connection structure, the length of the second metal connection structure is greater than the sum of the top surface diameters of the first metal connection structure and the third metal connection structure, and the width of the second metal connection structure is greater than the top surface diameter of the first metal connection structure.
[0013] Another aspect of the present application also provides a semiconductor structure, including: a chip, a first metal connection structure, a first dielectric layer and a first passivation layer are sequentially formed on the surface of the chip, a portion of the first metal connection structure penetrates the first dielectric layer and extends into the first passivation layer and is exposed by the first passivation layer; a second metal connection structure is located on the surface of the first metal connection structure exposed by the first passivation layer, the top surface area of the second metal connection structure is larger than the top surface area of the first metal connection structure and the top surface of the second metal connection structure completely covers the top surface of the first metal connection structure; a third metal connection structure is located on the top surface of the second metal connection structure, and the third metal connection structure is completely located on the top surface of the second metal connection structure.
[0014] In some embodiments of the present application, the second metal connection structure includes a first barrier layer, a first seed layer, and a first electroplating layer, which are sequentially located on the surface of the first metal connection structure exposed by the first passivation layer.
[0015] In some embodiments of the present application, the semiconductor structure further includes: a second passivation layer located on the exposed surface of the first passivation layer, the sidewall and the surface of the second metal connection structure, and the second passivation layer exposes a portion of the first electroplating layer.
[0016] In some embodiments of the present application, the third metal connection structure includes a second barrier layer, a second seed layer, a second electroplating layer and a welding layer which are sequentially located on the surface of the first electroplating layer exposed by the second passivation layer.
[0017] In some embodiments of the present application, the first metal connection structure includes a first part located on the surface of the chip, a second part penetrating the first dielectric layer and electrically connected to the first part, and a third part located in the first passivation layer and electrically connected to the second part, the third part is exposed by the first passivation layer, the area of the third part is larger than the area of the second part and completely covers the second part.
[0018] In some embodiments of the present application, the top surface patterns of the second metal connection structure are all oriented toward the central axis of the chip.
[0019] In some embodiments of the present application, the top surface of the first metal connection structure is circular, the top surface of the third metal connection structure is circular, the top surface diameter of the third metal connection structure is smaller than the top surface diameter of the first metal connection structure, the length of the second metal connection structure is greater than the sum of the top surface diameters of the first metal connection structure and the third metal connection structure, and the width of the second metal connection structure is greater than the top surface diameter of the first metal connection structure.
[0020] The present application provides a semiconductor structure and a method for forming the same, which utilizes a second metal connection structure to connect a first metal connection structure and a third metal connection structure, thereby preventing the copper pillar and the solder pad from being misaligned during chip packaging, causing the low dielectric constant material layer to break and reduce chip reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.
[0022] in:
[0023] Figures 1 to 11 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application;
[0024] Fig.12 A schematic diagram of the positional relationship between the top surface patterns of the first metal connection structure, the second metal connection structure, and the third metal connection structure in the semiconductor structure according to an embodiment of the present application;
[0025] Fig.13 Schematic diagram of the distribution of the second metal connection structure on the chip in the semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION
[0026] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.
[0027] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.
[0028] Figures 1 to 11 The following is a schematic diagram of the structure of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail in conjunction with the accompanying drawings.
[0029] refer to Figure 1 As shown, a chip 100 is provided, and a first metal connection structure 110, a first dielectric layer 120 and a first passivation layer 130 are sequentially formed on the surface of the chip 100, and a portion of the first metal connection structure 110 penetrates the first dielectric layer 120 and extends into the first passivation layer 130 and is exposed by the first passivation layer 130.
[0030] In some embodiments of the present application, the chip 100 is located on a wafer, and the wafer may include several chips 100. The chip 100 includes active devices and the like.
[0031] In some embodiments of the present application, the material of the first metal connection structure 110 is aluminum. The top surface of the first metal connection structure 110 is circular.
[0032] In some embodiments of the present application, the material of the first dielectric layer 120 includes a low dielectric constant material such as silicon oxide or silicon nitride.
[0033] In some embodiments of the present application, the material of the first passivation layer 130 includes silicon oxide or silicon nitride.
[0034] In some embodiments of the present application, the first metal connection structure 110 includes a first portion 111 located on the surface of the chip 100, a second portion 112 penetrating the first dielectric layer 120 and electrically connected to the first portion 111, and a third portion 113 located in the first passivation layer 130 and electrically connected to the second portion 112, wherein the third portion 113 is exposed by the first passivation layer 130, and an area of the third portion 113 is greater than an area of the second portion 112 and completely covers the second portion 112.
[0035] refer to Figures 2 to 5 As shown, a second metal connection structure 140 is formed on the surface of the first metal connection structure 110 exposed by the first passivation layer 130, the top surface area of the second metal connection structure 140 is larger than the top surface area of the first metal connection structure 110, and the top surface of the second metal connection structure 110 completely covers the top surface of the first metal connection structure 110. The top surface of the second metal connection structure 110 completely covers the top surface of the first metal connection structure 110, which means that the projection of the top surface of the second metal connection structure 110 in the vertical direction completely covers the projection of the top surface of the first metal connection structure 110 in the vertical direction.
[0036] refer to Figure 2 As shown, a first barrier layer 141 and a first seed layer 142 are sequentially formed on the surface of the first metal connection structure 110 exposed by the first passivation layer 130 and the surface of the first passivation layer 130 .
[0037] In some embodiments of the present application, the material of the first barrier layer 141 includes titanium. The method of forming the first barrier layer 141 includes a chemical vapor deposition process or a physical vapor deposition process.
[0038] In some embodiments of the present application, the material of the first seed layer 142 includes copper. The method of forming the first seed layer 142 includes a chemical vapor deposition process or a physical vapor deposition process.
[0039] refer to Figure 3 As shown, a first photoresist layer 150 is formed on the surface of the first seed layer 142 . The first photoresist layer 150 includes a first opening 151 exposing a portion of the second seed layer 142 . The first opening 151 defines the second metal connection structure 140 .
[0040] refer to Figure 4 As shown, the first electroplating layer 143 is electroplated and grown in the first opening 151 with the exposed first seed layer 142 as a matrix, and the first electroplating layer 143 , the first seed layer 142 and the first barrier layer 141 constitute the second metal connection structure 140 .
[0041] In some embodiments of the present application, the material of the first electroplating layer 143 is copper.
[0042] refer to Figure 5 As shown, the first seed layer 142 and the first barrier layer 141 outside the area covered by the first photoresist layer 150 and the first electroplating layer 143 are removed to expose a portion of the first passivation layer 130 .
[0043] In some embodiments of the present application, the total thickness of the second metal connection structure 140 is 5-20 um.
[0044] refer to Figure 6 As shown, in some embodiments of the present application, the method for forming the semiconductor structure also includes: forming a second passivation layer 160 on the exposed surface of the first passivation layer 130 and the sidewall and surface of the second metal connection structure 140, wherein the second passivation layer 160 exposes a portion of the first electroplating layer 143.
[0045] In some embodiments of the present application, the material of the second passivation layer 160 includes Polymide. The method of forming the second passivation layer 160 includes a chemical vapor deposition process or a physical vapor deposition process.
[0046] refer to Figures 7 to 11 As shown, a third metal connection structure 170 is formed on the top surface of the second metal connection structure 140 , and the third metal connection structure 170 is completely located on the top surface of the second metal connection structure 140 .
[0047] refer to Figure 7 As shown, a second barrier layer 171 and a second seed layer 172 are sequentially formed on the surface of the first electroplating layer 143 exposed by the second passivation layer 160 and on the surface of the second passivation layer 160 .
[0048] In some embodiments of the present application, the material of the second barrier layer 171 includes titanium. The method of forming the second barrier layer 171 includes a chemical vapor deposition process or a physical vapor deposition process.
[0049] In some embodiments of the present application, the material of the second seed layer 172 includes copper. The method of forming the second seed layer 172 includes a chemical vapor deposition process or a physical vapor deposition process.
[0050] refer to Figure 8 As shown, a second photoresist layer 180 is formed on the surface of the second seed layer 172 . The second photoresist layer 180 includes a second opening 181 exposing a portion of the second seed layer 172 . The second opening 181 defines the third metal connection structure 170 .
[0051] refer to Fig. 9 As shown, the second electroplating layer 173 is electroplated and grown in the second opening 181 with the exposed second seed layer 172 as a matrix, and the second electroplating layer 173 , the second seed layer 172 and the second barrier layer 171 constitute the third metal connection structure 170 .
[0052] In some embodiments of the present application, the material of the second electroplating layer 173 is copper.
[0053] refer to Fig.10 As shown, a solder layer 190 (solder) is formed on the surface of the second electroplating layer 173 .
[0054] In some embodiments of the present application, the material of the welding layer 190 is tin.
[0055] refer to Fig.11As shown, the second seed layer 172 and the second barrier layer 171 outside the area covered by the second photoresist layer 180 and the second electroplating layer 173 are removed.
[0056] Fig.12 Schematic diagram of the positional relationship among the top surface patterns of the first metal connection structure, the second metal connection structure and the third metal connection structure in the semiconductor structure described in an embodiment of the present application.
[0057] refer to Fig.12 As shown, in some embodiments of the present application, the top surface of the first metal connection structure 110 is circular, the top surface of the third metal connection structure 170 is circular, the top surface diameter of the third metal connection structure 170 is smaller than the top surface diameter of the first metal connection structure 110, the length of the second metal connection structure 140 is greater than the sum of the top surface diameters of the first metal connection structure 110 and the third metal connection structure 170, and the width of the second metal connection structure 140 is greater than the top surface diameter of the first metal connection structure 110. The length of the second metal connection structure 140 refers to the dimension of the second metal connection structure 140 in a longer direction, and the width of the second metal connection structure 140 refers to the dimension of the second metal connection structure 140 in a shorter direction. Fig.12 It is shown in Fig.11 Schematic diagram of the positional relationship between the top surface graphics of the first metal connection structure, the second metal connection structure and the third metal connection structure in the top view direction. That is, the positional relationship between the projections of the top surface graphics of the first metal connection structure, the second metal connection structure and the third metal connection structure in the vertical direction.
[0058] In some embodiments of the present application, the top surface shape of the second metal connection structure 140 includes a rectangle or an ellipse. Fig.12 It is shown that in some embodiments, the top surface pattern of the second metal connection structure 140 is a pattern consisting of a rectangle and two semicircles.
[0059] In some embodiments of the present application, the vertical projection of the first metal connection structure 110 may also be located at the center of the vertical projection of the second metal connection structure 140. The vertical projection of the first metal connection structure 110 partially overlaps with the vertical projection of the third metal connection structure 170.
[0060] In some embodiments of the present application, the length of the second metal connection structure 140 is equal to the sum of the top surface diameters of the first metal connection structure 110 and the third metal connection structure 170 plus 10 microns, and the width of the second metal connection structure 140 is equal to the top surface diameter of the first metal connection structure 110 plus 10 microns. Such a size setting can ensure that the third metal connection structure 170 can be arbitrarily replaced on the second metal connection structure 140 without affecting the electrical connection between the first metal connection structure 110, the second metal connection structure 140 and the third metal connection structure 170.
[0061] For example, the diameter of the first metal connection structure 110 is 120 micrometers, the diameter of the third metal connection structure 170 is 80 micrometers, the length of the second metal connection structure 140 is 210 micrometers, and the width of the second metal connection structure 140 is 130 micrometers.
[0062] Fig.13 Schematic diagram of the distribution of the second metal connection structure on the chip in the semiconductor structure described in an embodiment of the present application.
[0063] refer to Fig.13 As shown, in some embodiments of the present application, there are multiple second metal connection structures 140 on each chip 100 , and the top surface patterns of the second metal connection structures 140 are all oriented toward the central axis of the chip 100 .
[0064] Subsequently, the third metal connection structure 170 is generally aligned with the substrate pad on the substrate, and then the chip is packaged on the substrate. However, since the third metal connection structure 170 and the first metal connection structure 110 are completely aligned in the conventional process, the third metal connection structure 170 cannot be changed in position. If the third metal connection structure 170 is misaligned with the substrate pad on the substrate, there is no remedial measure, which will cause the low dielectric constant material layer in the chip to rupture and reduce the chip reliability. In the technical solution of the present application, since the second metal connection structure 140 is added, when the third metal connection structure 170 is misaligned with the substrate pad on the substrate, the position of the third metal connection structure 170 on the second metal connection structure 140 can be changed so that the third metal connection structure 170 is aligned with the substrate pad on the substrate.
[0065] In the technical solution of the present application, the added second metal connection structure can increase the thickness of the total metal connection structure and reduce the impact on the low dielectric constant material layer. The center of the chip aluminum pad (first metal connection structure) and the copper column (third metal connection structure) can be misaligned (due to the large area of the second metal connection structure, the first metal connection structure and the third metal connection structure can be misaligned), and part of the shear force of the copper column is borne by the second passivation layer, and the stress on the low dielectric constant material layer is greatly reduced.
[0066] The technical solution of the present application adds an elliptical second metal connection structure (copper pad) to the first metal connection structure (aluminum pad), and extends the elliptical copper pad along the center of the chip, with the long side larger than the aluminum pad and the short side close to the aluminum pad. Then the bumping factory can arbitrarily make the third connection structure (copper column, bump) longer than the elliptical copper pad. Therefore, when the copper column and the substrate are misaligned after the package is sliced, the position of the copper column on the elliptical copper pad can be changed to quickly meet the purpose of aligning the center of the copper column and the center of the substrate pad. Then the design increases the total thickness of the metal connection structure, and the copper column can be misaligned with the chip aluminum pad. These three advantages effectively avoid the rupture of the low dielectric constant material layer on the chip and improve the chip reliability.
[0067] The present application provides a method for forming a semiconductor structure, which utilizes a second metal connection structure to connect a first metal connection structure and a third metal connection structure, thereby avoiding misalignment of copper pillars and solder pads during chip packaging and reducing chip reliability.
[0068] The embodiment of the present application also provides a semiconductor structure, referring to Fig.11 As shown, it includes: a chip 100, on the surface of which a first metal connection structure 110, a first dielectric layer 120 and a first passivation layer 130 are sequentially formed, a portion of the first metal connection structure 110 penetrates the first dielectric layer 120 and extends into the first passivation layer 130 and is exposed by the first passivation layer 130; a second metal connection structure 140, located on the surface of the first metal connection 110 structure exposed by the first passivation layer 130, the top surface area of the second metal connection structure 140 is larger than the top surface area of the first metal connection structure 110 and the top surface of the second metal connection structure 140 completely covers the top surface of the first metal connection structure 110; a third metal connection structure 170, located on the top surface of the second metal connection structure 140, and the third metal connection structure 170 is completely located on the top surface of the second metal connection structure 140.
[0069] In some embodiments of the present application, the chip 100 is located on a wafer, and the wafer may include several chips 100. The chip 100 includes active devices and the like.
[0070] In some embodiments of the present application, the material of the first metal connection structure 110 is aluminum. The top surface of the first metal connection structure 110 is circular.
[0071] In some embodiments of the present application, the material of the first dielectric layer 120 includes a low dielectric constant material such as silicon oxide or silicon nitride.
[0072] In some embodiments of the present application, the material of the first passivation layer 130 includes silicon oxide or silicon nitride.
[0073] In some embodiments of the present application, the first metal connection structure 110 includes a first portion 111 located on the surface of the chip 100, a second portion 112 penetrating the first dielectric layer 120 and electrically connected to the first portion 111, and a third portion 113 located in the first passivation layer 130 and electrically connected to the second portion 112, wherein the third portion 113 is exposed by the first passivation layer 130, and an area of the third portion 113 is greater than an area of the second portion 112 and completely covers the second portion 112.
[0074] In some embodiments of the present application, the second metal connection structure 140 includes a first barrier layer 141 , a first seed layer 142 , and a first electroplating layer 143 which are sequentially located on the surface of the first metal connection structure 110 exposed by the first passivation layer 130 .
[0075] In some embodiments of the present application, the material of the first barrier layer 141 includes titanium.
[0076] In some embodiments of the present application, the material of the first seed layer 142 includes copper.
[0077] In some embodiments of the present application, the material of the first electroplating layer 143 is copper.
[0078] Continue to refer Fig.11 As shown, in some embodiments of the present application, the semiconductor structure also includes: a second passivation layer 160 located on the exposed surface of the first passivation layer 130, the sidewall and surface of the second metal connection structure 140, and the second passivation layer 160 exposes a portion of the first electroplating layer 143.
[0079] In some embodiments of the present application, the material of the second passivation layer 160 includes polyimide.
[0080] In some embodiments of the present application, the third metal connection structure 170 includes a second barrier layer 171 , a second seed layer 172 , a second electroplating layer 173 and a welding layer 174 which are sequentially located on the surface of the first electroplating layer 143 exposed by the second passivation layer 160 .
[0081] In some embodiments of the present application, the material of the second barrier layer 171 includes titanium.
[0082] In some embodiments of the present application, the material of the second seed layer 172 includes copper.
[0083] In some embodiments of the present application, the material of the second electroplating layer 173 is copper.
[0084] In some embodiments of the present application, the material of the welding layer 190 is tin.
[0085] refer to Fig.12 As shown, in some embodiments of the present application, the top surface of the first metal connection structure 110 is circular, the top surface of the third metal connection structure 170 is circular, the top surface diameter of the third metal connection structure 170 is smaller than the top surface diameter of the first metal connection structure 110, the length of the second metal connection structure 140 is greater than the sum of the top surface diameters of the first metal connection structure 110 and the third metal connection structure 170, and the width of the second metal connection structure 140 is greater than the top surface diameter of the first metal connection structure 110. The length of the second metal connection structure 140 refers to the dimension of the second metal connection structure 140 in a longer direction, and the width of the second metal connection structure 140 refers to the dimension of the second metal connection structure 140 in a shorter direction. Fig.12 It is shown in Fig.11 Schematic diagram of the positional relationship between the top surface graphics of the first metal connection structure, the second metal connection structure and the third metal connection structure in the top view direction. That is, the positional relationship between the projections of the top surface graphics of the first metal connection structure, the second metal connection structure and the third metal connection structure in the vertical direction.
[0086] In some embodiments of the present application, the top surface shape of the second metal connection structure 140 includes a rectangle or an ellipse. Fig.12 It is shown that in some embodiments, the top surface pattern of the second metal connection structure 140 is a pattern consisting of a rectangle and two semicircles.
[0087] In some embodiments of the present application, the vertical projection of the first metal connection structure 110 may also be located at the center of the vertical projection of the second metal connection structure 140. The vertical projection of the first metal connection structure 110 partially overlaps with the vertical projection of the third metal connection structure 170.
[0088] In some embodiments of the present application, the length of the second metal connection structure 140 is equal to the sum of the top surface diameters of the first metal connection structure 110 and the third metal connection structure 170 plus 10 microns, and the width of the second metal connection structure 140 is equal to the top surface diameter of the first metal connection structure 110 plus 10 microns. Such a size setting can ensure that the third metal connection structure 170 can be arbitrarily replaced on the second metal connection structure 140 without affecting the electrical connection between the first metal connection structure 110, the second metal connection structure 140 and the third metal connection structure 170.
[0089] For example, the diameter of the first metal connection structure 110 is 120 micrometers, the diameter of the third metal connection structure 170 is 80 micrometers, the length of the second metal connection structure 140 is 210 micrometers, and the width of the second metal connection structure 140 is 130 micrometers.
[0090] Fig.13 Schematic diagram of the distribution of the second metal connection structure on the chip in the semiconductor structure described in an embodiment of the present application.
[0091] refer to Fig.13 As shown, in some embodiments of the present application, there are multiple second metal connection structures 140 on each chip 100 , and the top surface patterns of the second metal connection structures 140 are all oriented toward the central axis of the chip 100 .
[0092] Subsequently, the third metal connection structure 170 is generally aligned with the substrate pad on the substrate, and then the chip is packaged on the substrate. However, since the third metal connection structure 170 and the first metal connection structure 110 are completely aligned in the conventional process, the third metal connection structure 170 cannot be changed in position. If the third metal connection structure 170 is misaligned with the substrate pad on the substrate, there is no remedial measure, which will cause the low dielectric constant material layer in the chip to rupture and reduce the chip reliability. In the technical solution of the present application, since the second metal connection structure 140 is added, when the third metal connection structure 170 is misaligned with the substrate pad on the substrate, the position of the third metal connection structure 170 on the second metal connection structure 140 can be changed so that the third metal connection structure 170 is aligned with the substrate pad on the substrate.
[0093] In the technical solution of the present application, the added second metal connection structure can increase the thickness of the total metal connection structure and reduce the impact on the low dielectric constant material layer. The center of the chip aluminum pad (first metal connection structure) and the copper column (third metal connection structure) can be misaligned (due to the large area of the second metal connection structure, the first metal connection structure and the third metal connection structure can be misaligned), and part of the shear force of the copper column is borne by the second passivation layer, and the stress on the low dielectric constant material layer is greatly reduced.
[0094] The technical solution of the present application adds an elliptical second metal connection structure (copper pad) to the first metal connection structure (aluminum pad), and extends the elliptical copper pad along the center of the chip, with the long side larger than the aluminum pad and the short side close to the aluminum pad. Then the bumping factory can arbitrarily make the third connection structure (copper column, bump) longer than the elliptical copper pad. Therefore, when the copper column and the substrate are misaligned after the package is sliced, the position of the copper column on the elliptical copper pad can be changed to quickly meet the purpose of aligning the center of the copper column and the center of the substrate pad. Then the design increases the total thickness of the metal connection structure, and the copper column can be misaligned with the chip aluminum pad. These three advantages effectively avoid the rupture of the low dielectric constant material layer on the chip and improve the chip reliability.
[0095] The present application provides a semiconductor structure and a method for forming the same, which utilizes a second metal connection structure to connect a first metal connection structure and a third metal connection structure, thereby preventing the copper pillar and the solder pad from being misaligned during chip packaging and reducing chip reliability.
[0096] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.
[0097] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can also be intermediate elements.
[0098] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.
[0099] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.
[0100] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a chip, wherein a first metal connection structure, a first dielectric layer and a first passivation layer are sequentially formed on the surface of the chip, and a portion of the first metal connection structure penetrates the first dielectric layer and extends into the first passivation layer and is exposed by the first passivation layer; forming a second metal connection structure on the surface of the first metal connection structure exposed by the first passivation layer, wherein the top surface area of the second metal connection structure is greater than the top surface area of the first metal connection structure and the top surface of the second metal connection structure completely covers the top surface of the first metal connection structure; A third metal connection structure is formed on the top surface of the second metal connection structure, and the third metal connection structure is completely located on the top surface of the second metal connection structure.
2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming a second metal connection structure on the surface of the first metal connection structure exposed by the first passivation layer comprises: Sequentially forming a first barrier layer and a first seed layer on the surface of the first metal connection structure exposed by the first passivation layer and the surface of the first passivation layer; Forming a first photoresist layer on the surface of the first seed layer, wherein the first photoresist layer includes a first opening exposing a portion of the second seed layer, and the first opening defines the second metal connection structure; Using the exposed first seed layer as a matrix, electroplating and growing a first electroplating layer in the first opening, wherein the first electroplating layer, the first seed layer and the first barrier layer constitute the second metal connection structure; The first seed layer and the first barrier layer outside the area covered by the first photoresist layer and the first electroplating layer are removed to expose a portion of the first passivation layer.
3. The method for forming a semiconductor structure according to claim 2, wherein: Also includes: A second passivation layer is formed on the exposed surface of the first passivation layer, the sidewall and the surface of the second metal connection structure, and the second passivation layer exposes a portion of the first electroplating layer.
4. The method for forming a semiconductor structure according to claim 3, wherein: The method of forming a third metal connection structure on the top surface of the second metal connection structure comprises: Sequentially forming a second barrier layer and a second seed layer on the surface of the first electroplating layer exposed by the second passivation layer and the surface of the second passivation layer; forming a second photoresist layer on the surface of the second seed layer, wherein the second photoresist layer includes a second opening exposing a portion of the second seed layer, and the second opening defines the third metal connection structure; Using the exposed second seed layer as a matrix, electroplating and growing a second electroplating layer in the second opening, wherein the second electroplating layer, the second seed layer and the second barrier layer constitute the third metal connection structure; forming a welding layer on the surface of the second electroplating layer; The second seed layer and the second barrier layer outside the area covered by the second photoresist layer and the second electroplating layer are removed.
5. The method for forming a semiconductor structure according to claim 1, wherein: The first metal connection structure includes a first part located on the surface of the chip, a second part penetrating the first dielectric layer and electrically connected to the first part, and a third part located in the first passivation layer and electrically connected to the second part, the third part is exposed by the first passivation layer, the area of the third part is larger than the area of the second part and completely covers the second part.
6. The method for forming a semiconductor structure according to claim 1, wherein: The top surface patterns of the second metal connection structures are all oriented toward the central axis of the chip.
7. The method for forming a semiconductor structure according to claim 1, wherein: The top surface of the first metal connection structure is circular, the top surface of the third metal connection structure is circular, the top surface diameter of the third metal connection structure is smaller than the top surface diameter of the first metal connection structure, the length of the second metal connection structure is greater than the sum of the top surface diameters of the first metal connection structure and the third metal connection structure, and the width of the second metal connection structure is greater than the top surface diameter of the first metal connection structure.
8. A semiconductor structure, characterized in that: include: A chip, wherein a first metal connection structure, a first dielectric layer and a first passivation layer are sequentially formed on the surface of the chip, and a portion of the first metal connection structure penetrates the first dielectric layer and extends into the first passivation layer and is exposed by the first passivation layer; A second metal connection structure is located on the surface of the first metal connection structure exposed by the first passivation layer, the top surface area of the second metal connection structure is larger than the top surface area of the first metal connection structure and the top surface of the second metal connection structure completely covers the top surface of the first metal connection structure; The third metal connection structure is located on the top surface of the second metal connection structure, and the third metal connection structure is completely located on the top surface of the second metal connection structure.
9. The semiconductor structure according to claim 8, characterized in that The second metal connection structure includes a first barrier layer, a first seed layer and a first electroplating layer which are sequentially located on the surface of the first metal connection structure exposed by the first passivation layer.
10. The semiconductor structure according to claim 9, wherein: Also includes: A second passivation layer is located on the exposed surface of the first passivation layer, the sidewall and the surface of the second metal connection structure, and the second passivation layer exposes a portion of the first electroplating layer.
11. The semiconductor structure according to claim 10, characterized in that The third metal connection structure includes a second barrier layer, a second seed layer, a second electroplating layer and a welding layer which are sequentially located on the surface of the first electroplating layer exposed by the second passivation layer.
12. The semiconductor structure according to claim 8, wherein: The first metal connection structure includes a first part located on the surface of the chip, a second part penetrating the first dielectric layer and electrically connected to the first part, and a third part located in the first passivation layer and electrically connected to the second part, the third part is exposed by the first passivation layer, the area of the third part is larger than the area of the second part and completely covers the second part.
13. The semiconductor structure according to claim 8, wherein: The top surface patterns of the second metal connection structures are all oriented toward the central axis of the chip.
14. The semiconductor structure according to claim 8, wherein: The top surface of the first metal connection structure is circular, the top surface of the third metal connection structure is circular, the top surface diameter of the third metal connection structure is smaller than the top surface diameter of the first metal connection structure, the length of the second metal connection structure is greater than the sum of the top surface diameters of the first metal connection structure and the third metal connection structure, and the width of the second metal connection structure is greater than the top surface diameter of the first metal connection structure.