Semiconductor structure and manufacturing method of semiconductor structure

Abstract

The invention provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a lead frame, a first chip, a second chip, a conductive connecting part and a plastic packaging layer. The lead frame comprises a first base island and a second base island which are arranged in parallel. The first chip is mounted on the first base island. The first chip comprises a first surface and a second surface opposite to the first surface, the first surface is provided with a first electrode, the second surface is provided with a second electrode, and the first electrode is electrically connected with the first base island. The second chip is mounted on the second base island. The second chip comprises a third surface and a fourth surface opposite to the third surface, the third surface is provided with a third electrode, the fourth surface is provided with a fourth electrode, and the third electrode is electrically connected with the second base island. The conductive connecting parts are located on the second surface and the fourth surface and electrically connected with the second electrode and the fourth electrode respectively. The plastic package layer encapsulates the lead frame, the first chip, the second chip and the conductive connection part, and the surface, away from the lead frame, of the conductive connection part is exposed out of the plastic package layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] The power device TVS (Transient Voltage Suppressor) includes two transient voltage suppressor diodes, which are connected in series or in parallel to protect the circuit from overvoltage.

[0003] However, in the existing power device TVS, two transient suppression diodes are stacked and electrically connected through a copper sheet, and each transient suppression diode is connected to a pin of a lead frame through the copper sheet, resulting in a large thickness of the power device TVS and poor heat dissipation effect. Summary of the invention

[0004] Embodiments of the present application provide a semiconductor structure and a method for manufacturing the semiconductor structure.

[0005] A first aspect of an embodiment of the present application provides a semiconductor structure. The semiconductor structure comprises:

[0006] A lead frame, comprising a first base island and a second base island arranged in parallel;

[0007] A first chip is mounted on the first base island; the first chip comprises a first surface facing the first base island and a second surface opposite to the first surface, the first surface is provided with a first electrode, the second surface is provided with a second electrode, and the first electrode is electrically connected to the first base island;

[0008] a second chip mounted on the second base island; the second chip comprises a third surface facing the second base island and a fourth surface opposite to the third surface, the third surface is provided with a third electrode, the fourth surface is provided with a fourth electrode, and the third electrode is electrically connected to the second base island;

[0009] A conductive connection portion, located on the second surface and the fourth surface, and electrically connected to the second electrode and the fourth electrode respectively; the conductive connection portion is an integral structure;

[0010] The plastic encapsulation layer encapsulates the lead frame, the first chip, the second chip and the conductive connection portion, and the conductive connection portion is away from the surface of the lead frame to expose the plastic encapsulation layer.

[0011] In one embodiment, the first electrode and the fourth electrode are positive electrodes, and the second electrode and the third electrode are negative electrodes; or, the first electrode and the fourth electrode are negative electrodes, and the second electrode and the third electrode are positive electrodes.

[0012] In one embodiment, the lead frame also includes a pin located on the side of the first base island, and the conductive connection portion is connected to the pin; the first electrode and the third electrode are positive electrodes, and the second electrode and the fourth electrode are negative electrodes; or, the first electrode and the third electrode are negative electrodes, and the second electrode and the fourth electrode are positive electrodes.

[0013] In one embodiment, a surface of the pin facing away from the conductive connection portion, a surface of the first base island facing away from the conductive connection portion, and a surface of the second base island facing away from the conductive connection portion are in the same plane.

[0014] In one embodiment, a surface of the first base island facing away from the conductive connection portion and a surface of the second base island facing away from the conductive connection portion expose the plastic encapsulation layer.

[0015] In one embodiment, a surface of the conductive connection portion facing the lead frame is provided with a groove; a portion of an orthographic projection of at least one of the grooves on the plane where the second surface is located falls within the second surface, and a gap exists between the surface of the groove facing the lead frame and the second surface; a portion of an orthographic projection of at least one of the grooves on the plane where the fourth surface is located falls within the fourth surface, and a gap exists between the surface of the groove facing the lead frame and the fourth surface.

[0016] A second aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method for manufacturing a semiconductor structure comprising:

[0017] Providing a lead frame, the lead frame comprising a first base island and a second base island arranged in parallel;

[0018] Mounting a first chip on the first base island, and mounting a second chip on the second base island; the first chip comprises a first surface facing the first base island and a second surface opposite to the first surface, the first surface is provided with a first electrode, the second surface is provided with a second electrode, and the first electrode is electrically connected to the first base island; the second chip comprises a third surface facing the second base island and a fourth surface opposite to the third surface, the third surface is provided with a third electrode, the fourth surface is provided with a fourth electrode, and the third electrode is electrically connected to the second base island;

[0019] Disposing a conductive connection portion on the second surface and the fourth surface, wherein the conductive connection portion is electrically connected to the second electrode and the fourth electrode respectively;

[0020] A plastic encapsulation layer is formed, wherein the plastic encapsulation layer encapsulates the lead frame, the first chip, the second chip and the conductive connection portion, and the conductive connection portion is away from a surface of the lead frame to expose the plastic encapsulation layer.

[0021] In one embodiment, the first electrode and the fourth electrode are positive electrodes, and the second electrode and the third electrode are negative electrodes; or, the first electrode and the fourth electrode are negative electrodes, and the second electrode and the third electrode are positive electrodes.

[0022] In one embodiment, the lead frame also includes a pin located on the side of the first base island, and the conductive connection portion is connected to the pin; the first electrode and the third electrode are positive electrodes, and the second electrode and the fourth electrode are negative electrodes; or, the first electrode and the third electrode are negative electrodes, and the second electrode and the fourth electrode are positive electrodes.

[0023] In one embodiment, before mounting the first chip on the first base island and mounting the second chip on the second base island, the method for manufacturing the semiconductor structure further comprises: coating a conductive adhesive material on surfaces of the first base island and the second base island;

[0024] After mounting the first chip on the first base island and mounting the second chip on the second base island, the method for manufacturing the semiconductor structure further includes: coating a conductive adhesive material on the second surface and the fourth surface;

[0025] After providing the conductive connection parts on the second surface and the fourth surface, the method for manufacturing the semiconductor structure further includes: curing the conductive adhesive material.

[0026] The main technical effects achieved by the embodiments of the present application are:

[0027] The semiconductor structure and the manufacturing method of the semiconductor structure provided by the embodiments of the present application are as follows: since the lead frame includes a first base island and a second base island arranged in parallel, the first chip mounted on the first base island and the second chip mounted on the second base island are arranged in parallel, which can reduce the thickness of the semiconductor structure compared to the solution in which the first chip and the second chip are stacked, and the size of the semiconductor structure in the horizontal direction is larger, which is conducive to the heat dissipation of the semiconductor structure; the conductive connection portion is located on the side of the first chip and the second chip away from the lead frame, and the surface of the conductive connection portion away from the lead frame exposes the plastic sealing layer, and the surface of the conductive connection portion away from the lead frame can effectively improve the heat dissipation effect of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a top view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0029] Figure 2 yes Figure 1 A cross-sectional view of the semiconductor structure shown;

[0030] Figure 3 is a top view of a semiconductor structure provided by another exemplary embodiment of the present application;

[0031] Figure 4 yes Figure 3 A cross-sectional view of the semiconductor structure shown;

[0032] Figure 5 is a flow chart of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application. Specific embodiments

[0033] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0034] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0035] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0036] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0037] The present application embodiment provides a semiconductor structure. Figures 1 to 4 As shown, the semiconductor structure includes a lead frame 10 , a first chip 20 , a second chip 30 , a conductive connection portion 40 and a plastic packaging layer 50 .

[0038] The lead frame 10 includes a first base island 11 and a second base island 12 arranged in parallel. The first chip 20 is mounted on the first base island 11. The first chip 20 includes a first surface 21 facing the first base island 11 and a second surface 22 opposite to the first surface 21, the first surface 21 is provided with a first electrode, the second surface 22 is provided with a second electrode, and the first electrode is electrically connected to the first base island 11. The second chip 30 is mounted on the second base island 12. The second chip 30 includes a third surface 31 facing the second base island 12 and a fourth surface 32 opposite to the third surface 31, the third surface 31 is provided with a third electrode, the fourth surface 32 is provided with a fourth electrode, and the third electrode is electrically connected to the second base island 12. The conductive connecting portion 40 is located on the second surface 22 and the fourth surface 32, and is electrically connected to the second electrode and the fourth electrode respectively. The conductive connecting portion 40 is an integral structure. The plastic encapsulation layer 50 encapsulates the lead frame 10 , the first chip 20 , the second chip 30 , and the conductive connection portion 40 , and the surface of the conductive connection portion 40 facing away from the lead frame 10 exposes the plastic encapsulation layer 50 .

[0039] In the semiconductor structure provided by the embodiment of the present application, since the lead frame includes a first base island and a second base island arranged in parallel, the first chip mounted on the first base island and the second chip mounted on the second base island are arranged in parallel, which can reduce the thickness of the semiconductor structure compared to the solution in which the first chip and the second chip are stacked, and the size of the semiconductor structure in the horizontal direction is larger, which is conducive to the heat dissipation of the semiconductor structure; the conductive connection part is located on the side of the first chip and the second chip away from the lead frame, and the surface of the conductive connection part away from the lead frame exposes the plastic sealing layer, and the surface of the conductive connection part away from the lead frame can effectively improve the heat dissipation effect of the semiconductor structure; the conductive connection part is an integrated structure, so the conductive connection part can electrically connect the first chip and the second chip, and there is no need to set up other structures to connect the first chip and the second chip, which helps to simplify the structural complexity of the semiconductor structure.

[0040] In the embodiments of the present application, Figures 1 to 4 As shown, the first base island 11 and the second base island 12 are spaced apart from each other, that is, the first base island 11 and the second base island 12 are not connected.

[0041] In one embodiment, Figure 2 and Figure 4As shown, the surface of the first base island 11 away from the conductive connection part 40 and the surface of the second base island 12 away from the conductive connection part 40 expose the plastic sealing layer 50. The surface of the first base island 11 away from the conductive connection part 40 and the surface of the second base island 12 away from the conductive connection part 40 can be used to electrically connect with an external structure, for example, can be electrically connected to a circuit board. Compared with the solution of electrically connecting with an external structure through the pins of the lead frame, the number of pins in the lead frame can be reduced or the lead frame can be provided with no pins, thereby improving the utilization rate of the lead frame and reducing the cost of the semiconductor structure. In addition, the surface of the lead frame away from the conductive connection part 40 exposes the plastic sealing layer 50, and the side of the semiconductor structure away from the conductive connection part 40 can be dissipated through the surface of the lead frame 10 exposing the plastic sealing layer 50, which can further improve the heat dissipation performance of the semiconductor structure.

[0042] In one embodiment, Figure 2 and Figure 4 As shown, the semiconductor structure further includes a conductive adhesive material 60 located between the first base island 11 and the first surface 21 of the first chip 20, and a conductive adhesive material 60 located between the second base island 12 and the third surface 31 of the second chip 30. The conductive adhesive material 60 located between the first base island 11 and the first surface 21 of the first chip 20 can make the first chip 20 mounted on the first base island 11 more firmly, and at the same time, the first electrode set on the first surface 21 of the first chip 20 can be electrically connected to the first base island 11 through the conductive adhesive material 60; the conductive adhesive material 60 located between the second base island 12 and the third surface 31 of the second chip 30 can make the second chip 30 mounted on the second base island 12 more firmly, and at the same time, the third electrode set on the third surface 31 of the second chip 30 can be electrically connected to the second base island 12 through the conductive adhesive material 60.

[0043] In one embodiment, the conductive adhesive material 60 can be obtained by coating solder paste or silver paste and then curing the coated solder paste or silver paste. When the conductive adhesive material 60 is obtained by curing the solder paste, the first chip 20 and the first base island 11 can be soldered together, and the second chip 30 and the second base island 12 can be soldered together through a reflow process.

[0044] In one embodiment, Figure 2 and Figure 4As shown, the semiconductor structure further includes a conductive adhesive material 70 located between the second surface 22 of the first chip 20 and the conductive connection part 40, and a conductive adhesive material 70 located between the fourth surface 32 of the second chip 30 and the conductive connection part 40. The conductive adhesive material 70 located between the second surface 22 of the first chip 20 and the conductive connection part 40 can make the first chip 20 and the conductive connection part 40 bonded more firmly, and at the same time, the second electrode disposed on the second surface 22 of the first chip 20 can be electrically connected to the conductive connection part 40 through the conductive adhesive material 70; the conductive adhesive material 70 located between the fourth surface 32 of the second chip 30 and the conductive connection part 40 can make the second chip 30 and the conductive connection part 40 bonded more firmly, and at the same time, the fourth electrode disposed on the fourth surface 32 of the second chip 30 can be electrically connected to the conductive connection part 40 through the conductive adhesive material 70.

[0045] In one embodiment, the conductive adhesive material 70 can be obtained by coating solder paste or silver paste and then curing the coated solder paste or silver paste. When the conductive adhesive material 70 is obtained by curing the solder paste, the first chip 20 and the second chip 30 can be soldered together with the conductive connection part 40 through a reflow process.

[0046] In one embodiment, Figure 1 and Figure 2 As shown, the lead frame 10 also includes a pin 13 located on the side of the first base island 11, and the conductive connection part 40 is connected to the pin 13. The first electrode and the third electrode are positive electrodes, and the second electrode and the fourth electrode are negative electrodes; or, the first electrode and the third electrode are negative electrodes, and the second electrode and the fourth electrode are positive electrodes. In this way, the first chip 20 and the second chip 30 are connected in parallel, and the semiconductor structure can be used in a DC power supply circuit to protect the DC power supply circuit from overvoltage. When the semiconductor structure is connected to the external structure, the first base island 11 and the second base island 12 are both connected to the high-level power supply terminal, and the pin 13 is connected to the low-level power supply terminal. For example, the first base island 11 and the second base island 12 can be connected to the high-level power supply terminals of different DC circuits respectively, and the pin 13 is connected to the ground terminal.

[0047] Furthermore, if Figure 2 As shown, the surface of the pin 13 away from the conductive connection part 40, the surface of the first base island 11 away from the conductive connection part 40, and the surface of the second base island 12 away from the conductive connection part 40 are in the same plane. In this way, the surface of the pin 13 away from the conductive connection part 40, the surface of the first base island 11 away from the conductive connection part 40, and the surface of the second base island 12 away from the conductive connection part 40 can all be exposed from the plastic packaging layer 50, so that they can be electrically connected to an external structure, such as a circuit board.

[0048] Furthermore, if Figure 2 As shown, the semiconductor structure further includes a conductive adhesive material 70 located between the pin 13 and the conductive connection portion 40. The conductive adhesive material 70 located between the pin 13 and the conductive connection portion 40 can make the pin 13 and the conductive connection portion 40 bonded more firmly, and at the same time, the pin 13 can be electrically connected to the conductive connection portion 40 through the conductive adhesive material 70.

[0049] In one embodiment, Figure 3 and Figure 4 In the semiconductor structure shown, the first electrode and the fourth electrode are positive electrodes, and the second electrode and the third electrode are negative electrodes; or, the first electrode and the fourth electrode are negative electrodes, and the second electrode and the third electrode are positive electrodes. In this way, the first chip 20 and the second chip 30 are connected in series, and the semiconductor structure can be used in an AC power supply circuit to perform overvoltage protection on the AC power supply circuit. When the semiconductor structure is connected to an external structure, one of the first base island 11 and the second base island 12 is connected to a high-level power terminal, and the other is connected to a low-level power terminal, for example, the first base island 11 is connected to a high-level power terminal, and the second base island 12 is connected to a low-level power terminal. In this way, the lead frame 10 does not need to be provided with pins, which can improve the utilization rate of the lead frame 10.

[0050] In one embodiment, Figure 2 and Figure 4 As shown, a groove 41 is provided on the surface of the conductive connection portion 40 facing the lead frame 10; a portion of the orthographic projection of at least one of the grooves 41 on the plane where the second surface 22 is located falls within the second surface 22, and a gap exists between the surface of the groove 41 facing the lead frame 10 and the second surface 22; a portion of the orthographic projection of at least one of the grooves 41 on the plane where the fourth surface 32 is located falls within the fourth surface 32, and a gap exists between the surface of the groove 41 facing the lead frame 10 and the fourth surface 32. With such a configuration, during the process of curing the conductive adhesive material 70, the conductive adhesive material 70 can enter the groove 41, preventing the conductive adhesive material 70 from flowing to the side of the first chip 20 before curing, thereby causing the first electrode located on the first surface 21 and the second electrode located on the second surface 22 to be electrically connected through the conductive adhesive material flowing to the side of the first chip 20, thereby causing a short circuit; it can also prevent the conductive adhesive material 70 from flowing to the side of the second chip 30 before curing, thereby causing the third electrode located on the third surface 31 and the fourth electrode located on the fourth surface 32 to be electrically connected through the conductive adhesive material flowing to the side of the second chip 30, thereby causing a short circuit, which helps to improve the yield of the semiconductor structure. Figure 2In the illustrated embodiment, a portion of the orthographic projection of one of the grooves 41 on the plane where the second surface 22 is located falls within the second surface 22, and a portion of the orthographic projection on the plane where the fourth surface 32 is located falls within the fourth surface 32; a portion of the orthographic projection of another groove on the plane where the second surface 22 is located falls within the second surface 22, and another portion falls outside the second surface 22.

[0051] In one embodiment, the conductive connection part is a metal conductive sheet. For example, the conductive connection part may be a copper sheet. The resistivity of copper is relatively low, which can make the impedance of the conductive connection part small.

[0052] In one embodiment, Figure 1 and Figure 3 As shown, the lead frame 10 also includes a plurality of connecting portions 14. The sides of the first base island 11 and the second base island 12 are respectively provided with a plurality of connecting portions 14. Before the semiconductor structure is prepared, the lead frame 10 also includes a frame. The connecting portions 14 are connected to the frame, that is, the lead frame 10 is initially a whole. This can prevent different structures of the lead frame 10 from moving relative to each other during the preparation of the semiconductor structure, thereby affecting the quality of the semiconductor structure.

[0053] In one embodiment, Figure 1 As shown, when the lead frame 10 includes the pins 13 , the side of the pins 13 is provided with a connecting portion 14 .

[0054] The present application provides a method for manufacturing a semiconductor structure. Figure 5 As shown, the method for manufacturing the semiconductor structure includes the following steps 110 to 140.

[0055] In step 110 , a lead frame is provided, wherein the lead frame includes a first base island and a second base island arranged in parallel.

[0056] In one embodiment, the lead frame includes a frame, the frame includes a plurality of sub-regions arranged at intervals, the lead frame also includes a plurality of first base islands and a plurality of second base islands, each sub-region is provided with a first base island and a second base island, and the first base island and the second base island are respectively connected to the frame.

[0057] In one embodiment, the lead frame further includes a plurality of pins, one pin is provided in each sub-region, and the pins are connected to the frame.

[0058] In step 120, a first chip is mounted on the first base island, and a second chip is mounted on the second base island; the first chip includes a first surface facing the first base island and a second surface opposite to the first surface, the first surface is provided with a first electrode, the second surface is provided with a second electrode, and the first electrode is electrically connected to the first base island; the second chip includes a third surface facing the second base island and a fourth surface opposite to the third surface, the third surface is provided with a third electrode, the fourth surface is provided with a fourth electrode, and the third electrode is electrically connected to the second base island.

[0059] In one embodiment, before the step of mounting the first chip on the first base island and mounting the second chip on the second base island, the method for manufacturing the semiconductor structure further includes: coating the surfaces of the first base island and the second base island with a conductive adhesive material. The conductive adhesive material may be coated on the surfaces of the first base island and the second base island using a dispensing process. The first chip is adhered to and electrically connected to the first base island through the conductive adhesive material coated on the surface of the first base island, and the second chip is adhered to and electrically connected to the second base island through the conductive adhesive material coated on the surface of the second base island.

[0060] In step 130, conductive connection portions are provided on the second surface and the fourth surface, and the conductive connection portions are electrically connected to the second electrode and the fourth electrode, respectively.

[0061] In one embodiment, after the step of mounting the first chip on the first base island and mounting the second chip on the second base island, and before step 130, the method for manufacturing the semiconductor structure further includes: coating the second surface and the fourth surface with a conductive adhesive material. The conductive adhesive material may be coated on the second surface and the fourth surface using a dispensing process. The conductive connection portion is adhered to and electrically connected to the first chip through the conductive adhesive material coated on the second surface, and the conductive connection portion is adhered to and electrically connected to the second chip through the conductive adhesive material coated on the fourth surface.

[0062] In one embodiment, after the step of providing the conductive connection portion on the second surface and the fourth surface, the method for manufacturing the semiconductor structure further comprises: curing the conductive adhesive material. In some embodiments, when the conductive adhesive material is solder paste, a reflow process can be used to cure the conductive adhesive material.

[0063] In step 140 , a plastic encapsulation layer is formed, wherein the plastic encapsulation layer encapsulates the lead frame, the first chip, the second chip, and the conductive connection portion, and the conductive connection portion is away from a surface of the lead frame to expose the plastic encapsulation layer.

[0064] In one embodiment, before the step of forming the plastic encapsulation layer, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the first chip, the second chip, the lead frame and the conductive connector, so that the plastic encapsulation layer and the first chip, the second chip, the lead frame and the conductive connector can be more closely connected without delamination or cracking.

[0065] In one embodiment, the material of the plastic encapsulation layer may be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer may be a resin with a filler, wherein the filler may be an inorganic particle. The plastic encapsulation layer may be formed by injection molding, compression molding, or transfer molding.

[0066] In one embodiment, the first electrode and the fourth electrode are positive electrodes, and the second electrode and the third electrode are negative electrodes; or, the first electrode and the fourth electrode are negative electrodes, and the second electrode and the third electrode are positive electrodes.

[0067] In one embodiment, the lead frame also includes a pin located on the side of the first base island, and the conductive connection portion is connected to the pin; the first electrode and the third electrode are positive electrodes, and the second electrode and the fourth electrode are negative electrodes; or, the first electrode and the third electrode are negative electrodes, and the second electrode and the fourth electrode are positive electrodes.

[0068] The manufacturing method of the semiconductor structure provided in the embodiment of the present application has a simple manufacturing process and can be performed using automated equipment without the need for manual intervention or with reduced manual intervention, which helps to improve the efficiency of manufacturing the semiconductor structure.

[0069] The embodiment of the method for manufacturing a semiconductor structure provided in the embodiment of the present application and the embodiment of the semiconductor structure belong to the same inventive concept, and the description of relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0070] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0071] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0072] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: A lead frame, comprising a first base island and a second base island arranged in parallel; A first chip is mounted on the first base island; the first chip comprises a first surface facing the first base island and a second surface opposite to the first surface, the first surface is provided with a first electrode, the second surface is provided with a second electrode, and the first electrode is electrically connected to the first base island; a second chip mounted on the second base island; the second chip comprises a third surface facing the second base island and a fourth surface opposite to the third surface, the third surface is provided with a third electrode, the fourth surface is provided with a fourth electrode, and the third electrode is electrically connected to the second base island; A conductive connection portion, located on the second surface and the fourth surface, and electrically connected to the second electrode and the fourth electrode respectively; the conductive connection portion is an integral structure; A plastic encapsulation layer encapsulates the lead frame, the first chip, the second chip and the conductive connection portion, and the conductive connection portion is away from a surface of the lead frame to expose the plastic encapsulation layer.

2. The semiconductor structure according to claim 1, characterized in that: The first electrode and the fourth electrode are positive electrodes, and the second electrode and the third electrode are negative electrodes; or, the first electrode and the fourth electrode are negative electrodes, and the second electrode and the third electrode are positive electrodes.

3. The semiconductor structure according to claim 1, characterized in that: The lead frame also includes a pin located on the side of the first base island, and the conductive connecting part is connected to the pin; the first electrode and the third electrode are positive electrodes, and the second electrode and the fourth electrode are negative electrodes; or, the first electrode and the third electrode are negative electrodes, and the second electrode and the fourth electrode are positive electrodes.

4. The semiconductor structure according to claim 3, characterized in that: A surface of the pin facing away from the conductive connection portion, a surface of the first base island facing away from the conductive connection portion, and a surface of the second base island facing away from the conductive connection portion are in the same plane.

5. The semiconductor structure according to claim 1, characterized in that: The surface of the first base island away from the conductive connecting portion and the surface of the second base island away from the conductive connecting portion are exposed from the plastic packaging layer.

6. The semiconductor structure according to claim 1, characterized in that A surface of the conductive connection portion facing the lead frame is provided with a groove; a portion of an orthographic projection of at least one of the grooves on the plane where the second surface is located falls within the second surface, and a gap exists between a surface of the groove facing the lead frame and the second surface; A portion of the orthographic projection of at least one of the grooves on the plane where the fourth surface is located falls within the fourth surface, and a gap exists between a surface of the groove facing the lead frame and the fourth surface.

7. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: Providing a lead frame, the lead frame comprising a first base island and a second base island arranged in parallel; Mounting a first chip on the first base island, and mounting a second chip on the second base island; the first chip comprises a first surface facing the first base island and a second surface opposite to the first surface, the first surface is provided with a first electrode, the second surface is provided with a second electrode, and the first electrode is electrically connected to the first base island; the second chip comprises a third surface facing the second base island and a fourth surface opposite to the third surface, the third surface is provided with a third electrode, the fourth surface is provided with a fourth electrode, and the third electrode is electrically connected to the second base island; Disposing a conductive connection portion on the second surface and the fourth surface, wherein the conductive connection portion is electrically connected to the second electrode and the fourth electrode respectively; A plastic encapsulation layer is formed, wherein the plastic encapsulation layer encapsulates the lead frame, the first chip, the second chip and the conductive connection portion, and the conductive connection portion is away from a surface of the lead frame to expose the plastic encapsulation layer.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The first electrode and the fourth electrode are positive electrodes, and the second electrode and the third electrode are negative electrodes; or, the first electrode and the fourth electrode are negative electrodes, and the second electrode and the third electrode are positive electrodes.

9. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The lead frame also includes a pin located on the side of the first base island, and the conductive connecting part is connected to the pin; the first electrode and the third electrode are positive electrodes, and the second electrode and the fourth electrode are negative electrodes; or, the first electrode and the third electrode are negative electrodes, and the second electrode and the fourth electrode are positive electrodes.

10. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: Before mounting the first chip on the first base island and mounting the second chip on the second base island, the method for manufacturing the semiconductor structure further comprises: coating a conductive adhesive material on the surfaces of the first base island and the second base island; After mounting the first chip on the first base island and mounting the second chip on the second base island, the method for manufacturing the semiconductor structure further includes: coating a conductive adhesive material on the second surface and the fourth surface; After providing the conductive connection parts on the second surface and the fourth surface, the method for manufacturing the semiconductor structure further includes: curing the conductive adhesive material.

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