Semiconductor structure and manufacturing method of semiconductor structure

Abstract

The invention provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a chip, an electrical connecting piece, a plurality of bonding wires, an insulating part and a plastic packaging layer. A plurality of welding pads are arranged on the front face of the chip. The electrical connecting piece comprises a bearing part and a plurality of pins positioned on the side part of the bearing part; the chip is attached to one side of the bearing part, and the back face of the chip faces the bearing part. The bonding wire is used for electrically connecting the welding pads with the pins or electrically connecting the two welding pads; the plurality of bonding wires comprise a first bonding wire and a second bonding wire, and the first bonding wire is adjacent to the second bonding wire. And the insulating part covers at least part of at least one of the first bonding wire and the second bonding wire. The plastic packaging layer packages the chip, the electrical connecting piece, the insulating part and the bonding wire; and at least parts of the pins are exposed out of the plastic packaging layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] Common semiconductor packaging technologies, such as chip packaging technology, usually include the following process: first, the chip is mounted on a lead frame, and the pins of the lead frame are located on one side of the chip; then, bonding wires are used to electrically connect the chip's pads to the pins, or to connect two pads; then a plastic encapsulation layer is formed, which encapsulates the chip, lead frame and bonding wires.

[0003] In the above packaging technology, during the process of forming the plastic packaging layer, the plastic packaging material impacts the bonding wires, which easily causes adjacent bonding wires to contact and cause a short circuit. That is, the yield rate of semiconductor products manufactured by the above packaging technology is low. Summary of the invention

[0004] Embodiments of the present application provide a semiconductor structure and a method for manufacturing the semiconductor structure.

[0005] According to a first aspect of an embodiment of the present application, a semiconductor structure is provided. The semiconductor structure comprises:

[0006] A chip, the chip comprising a chip front side and a chip back side opposite to the chip front side; a plurality of pads are provided on the chip front side;

[0007] An electrical connector, the electrical connector comprising a carrier and a plurality of pins located on a side of the carrier; the chip is mounted on one side of the carrier, and the back of the chip faces the carrier;

[0008] A plurality of bonding wires, the bonding wires electrically connecting the pad to the pin, or electrically connecting two pads; the plurality of bonding wires include a first bonding wire and a second bonding wire, the first bonding wire is adjacent to the second bonding wire;

[0009] an insulating portion covering at least a portion of at least one of the first bonding wire and the second bonding wire;

[0010] A plastic encapsulation layer encapsulates the chip, the electrical connector, the insulating portion and the bonding wire; and at least a portion of the pin is exposed from the plastic encapsulation layer.

[0011] In one embodiment, in a direction perpendicular to the plane where the chip front side is located, the first bonding wire is adjacent to the second bonding wire, and the orthographic projection of a portion of the first bonding wire away from the chip front side on the plane where the chip front side is located overlaps with the orthographic projection of a portion of the second bonding wire away from the chip front side on the plane; the portion of the second bonding wire away from the chip front side is located on a side of the first bonding wire away from the supporting portion; the insulating portion is located on the chip front side, and the insulating portion at least covers the portion of the first bonding wire away from the chip front side.

[0012] In one embodiment, the insulating portion completely covers the first bonding wire and the second bonding wire; and / or,

[0013] In a direction perpendicular to the plane where the chip front side is located, a distance between a portion of the first bonding wire away from the chip front side and a portion of the second bonding wire away from the chip front side is greater than an outer diameter of the bonding wire.

[0014] In one embodiment, in the direction of the plane where the chip front surface is located, the first bonding wire is adjacent to the second bonding wire;

[0015] The multiple pads include a first pad connected to the first bonding wire and a second pad connected to the second bonding wire, and the first pad is adjacent to the second pad; the multiple pins include a first pin connected to the first bonding wire and a second pin connected to the second bonding wire, and the first pin is adjacent to the second pin; the distance between the first pad and the second pad is smaller than the distance between the first pin and the second pin; the insulating portion at least covers the end of the first bonding wire connected to the first pad and the end of the second bonding wire connected to the second pad.

[0016] In one embodiment, the temperature at which the insulating portion is transformed from a solid state to a molten state is higher than the solidification temperature of the material of the plastic encapsulation layer.

[0017] In one embodiment, the insulating portion covers the chip front surface and an area of ​​the carrier portion not covered by the chip.

[0018] In one embodiment, the electrical connector is a lead frame, and the bearing portion is spaced apart from the lead; or,

[0019] The electrical connector is a circuit board, which includes a main body, the pins are located on the main body, and the bearing portion is a part of the main body.

[0020] According to a second aspect of an embodiment of the present application, a method for manufacturing a semiconductor structure is provided, comprising:

[0021] A chip and an electrical connector are provided; the chip comprises a chip front side and a chip back side opposite to the chip front side; a plurality of pads are arranged on the chip front side; the electrical connector comprises a bearing portion and a plurality of pins located on the side of the bearing portion;

[0022] The chip is mounted on one side of the carrier; the back of the chip faces the carrier, and the plurality of pins of the electrical connector are located on the side of the chip;

[0023] Providing a plurality of bonding wires, wherein the bonding wires electrically connect the pad to the pin, or electrically connect two pads; the plurality of bonding wires include a first bonding wire and a second bonding wire, wherein the first bonding wire is adjacent to the second bonding wire;

[0024] forming an insulating portion, the insulating portion covering at least a portion of at least one of the first bonding wire and the second bonding wire;

[0025] A plastic encapsulation layer is formed, wherein the plastic encapsulation layer encapsulates the chip, the electrical connector, the insulating portion and the bonding wire; and at least a portion of the pin is exposed from the plastic encapsulation layer.

[0026] In one embodiment, forming the insulating portion includes:

[0027] A fluid insulating material is dripped onto the front surface of the chip and / or the exposed surface of the carrier portion, and the insulating material is solidified to form an insulating portion.

[0028] In one embodiment, the orthographic projection of the dripping track of the insulating material on the plane where the front side of the chip is located does not overlap with the orthographic projection of the first bonding wire on the plane, and does not overlap with the orthographic projection of the second bonding wire on the plane; and / or,

[0029] The angle between the dripping track of the insulating material and the orthographic projection on the plane where the front surface of the chip is located is an acute angle.

[0030] In one embodiment, in a direction perpendicular to the plane where the chip front side is located, the first bonding wire is adjacent to the second bonding wire, and the orthographic projection of the portion of the first bonding wire away from the chip front side on the plane where the chip front side is located overlaps with the orthographic projection of the portion of the second bonding wire away from the chip front side on the plane; the portion of the second bonding wire away from the chip front side is located on a side of the first bonding wire away from the carrier portion; the insulating portion is located on the chip front side, and the insulating portion at least covers the portion of the first bonding wire away from the chip front side; or,

[0031] In the direction of the plane where the front side of the chip is located, the first bonding wire is adjacent to the second bonding wire; the multiple pads include a first bonding pad connected to the first bonding wire and a second bonding pad connected to the second bonding wire, and the first bonding pad is adjacent to the second bonding pad; the multiple pins include a first pin connected to the first bonding wire and a second pin connected to the second bonding wire, and the first pin is adjacent to the second pin; the distance between the first bonding pad and the second bonding pad is smaller than the distance between the first pin and the second pin; the insulating part at least covers the end of the first bonding wire connected to the first bonding pad and the end of the second bonding wire connected to the second bonding pad.

[0032] The main technical effects achieved by the embodiments of the present application are:

[0033] The semiconductor structure and the method for manufacturing the semiconductor structure provided by the embodiments of the present application, by providing an insulating portion, and at least a portion of at least one of the adjacent first bonding wires and the second bonding wires is covered by the insulating portion. Therefore, even if the plastic encapsulation material impacts the first bonding wire and the second bonding wire during the process of forming the plastic encapsulation layer, the first bonding wire and the second bonding wire will not contact each other, which can avoid the situation where the adjacent first bonding wire and the second bonding wire contact and cause a short circuit, thereby improving the yield of the semiconductor structure; by providing an electrical connector including a bearing portion, the chip and the electrical connector can be fixed together, preventing the chip and the electrical connector from moving relative to each other during the process of forming the plastic encapsulation layer, which affects the reliability of the electrical connection between the pad and the pin, and helps to improve the yield of the semiconductor structure; the insulating portion is a non-conductive structure and does not affect the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a partial structural schematic diagram of a semiconductor structure provided by an exemplary embodiment of the present application;

[0035] Figure 2 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0036] Figure 3 is a partial structural schematic diagram of a semiconductor structure provided by another exemplary embodiment of the present application;

[0037] Figure 4 is a flow chart of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application. Specific embodiments

[0038] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0039] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0040] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0041] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0042] The present application embodiment provides a semiconductor structure. Figure 1 and Figure 2 As shown, the semiconductor structure includes a chip 10 , an electrical connector 20 , a plurality of bonding wires 30 , an insulating portion 40 and a plastic encapsulation layer 50 .

[0043] The chip 10 includes a chip front, a chip back opposite to the chip front, and a plurality of chip side surfaces connecting the chip front and the chip back; the chip front is provided with a plurality of pads 11. The electrical connector 20 includes a carrier 21 and a plurality of pins 22 located at the side of the carrier 21. The pins 22 located at the side of the carrier 21 means that the pins 22 are not part of the carrier 21, and there may be a gap between the pins 22 and the side of the carrier 21. The chip 10 is mounted on one side of the carrier 21, and the back of the chip faces the carrier 21. The bonding wire 30 electrically connects the pad 11 with the pin 22, or electrically connects two pads 11. The plurality of bonding wires 30 include a first bonding wire 31 and a second bonding wire 32, and the first bonding wire 31 is adjacent to the second bonding wire 32. The first bonding wire 31 is adjacent to the second bonding wire 32, which means that there is no other bonding wire between them. The insulating portion 40 covers at least a portion of at least one of the first bonding wire 31 and the second bonding wire 32. The plastic encapsulation layer 50 encapsulates the chip 10, the electrical connector 20, the insulating portion 40 and the bonding wire 30, and at least a portion of the pin 22 is exposed from the plastic encapsulation layer 50.

[0044] The semiconductor structure provided by the embodiment of the present application is provided with an insulating part, and at least one of the adjacent first bonding wires and the second bonding wires is at least partially covered by the insulating part. Therefore, even if the plastic encapsulation material impacts the first bonding wire and the second bonding wire in the process of forming the plastic encapsulation layer, the first bonding wire and the second bonding wire will not contact each other, which can avoid the situation where the adjacent first bonding wire and the second bonding wire contact and cause a short circuit, thereby improving the yield of the semiconductor structure; by providing an electrical connector including a bearing part, the chip and the electrical connector can be fixed together, preventing the chip and the electrical connector from relative movement during the process of forming the plastic encapsulation layer, which affects the reliability of the electrical connection between the pad and the pin, and helps to improve the yield of the semiconductor structure; the insulating part is a non-conductive structure and does not affect the electrical performance of the semiconductor structure.

[0045] In one embodiment, the plurality of bonding wires 30 may include two or more first bonding wires 31 and second bonding wires 32 adjacent to each first bonding wire 31. For each first bonding wire 31 and the second bonding wire 32 adjacent thereto, the insulating portion 40 covers at least a portion of at least one of them.

[0046] In one embodiment, the semiconductor structure includes two or more chips 10 , and the bonding wires 30 can connect the pads 11 of different chips 10 . Figure 1In the illustrated embodiment, the semiconductor structure includes two chips 10 , a first bonding wire 31 connects two pads 11 , and the two pads 11 belong to different chips 10 ; a second bonding wire 32 connects the two pads 11 , and the two pads 11 belong to different chips 10 .

[0047] In another embodiment, the semiconductor structure includes a chip 10 , and a bonding wire 30 can connect two pads 11 of the chip 10 .

[0048] In one embodiment, Figure 1 As shown, the plurality of pins 22 of the electrical connector 20 are arranged around the bearing portion 21 . Figure 1 Only some of the pins 22 are shown to be connected to the pads 11 . In practice, each pin 22 can be electrically connected to a pad 11 of the chip 10 through a bonding wire 30 .

[0049] In one embodiment, Figure 2 As shown, the chip 10 can be mounted on one side of the carrier 21 by means of an adhesive 60. In some embodiments, the adhesive 60 can be a conductive adhesive, for example, the adhesive 60 can be obtained by curing a silver paste. Alternatively, the adhesive 60 can be a non-conductive adhesive.

[0050] In one embodiment, Figure 1 and Figure 2 As shown, the electrical connector 20 is a lead frame. The bearing portion 21 is a base island of the lead frame. The bearing portion 21 is spaced apart from the pin 22. In other embodiments, the electrical connector may be a circuit board. The circuit board includes a main body, and the pins are arranged on the main body. The bearing portion is a part of the main body, and the part is not provided with other components such as pins.

[0051] In one embodiment, Figure 1 and 2As shown, in a direction perpendicular to the plane where the chip front is located, the first bonding wire 31 is adjacent to the second bonding wire 32, and the orthographic projection of the portion 311 of the first bonding wire 31 away from the chip front on the plane where the chip front is located overlaps with the orthographic projection of the portion 321 of the second bonding wire 32 away from the chip front on the plane; the portion 321 of the second bonding wire 32 away from the chip front is located on the side of the first bonding wire 31 away from the carrier 21; the insulating portion 40 covers the chip 10, and the insulating portion 40 at least covers the portion 311 of the first bonding wire 31 away from the chip front. When forming the insulating portion 40, the distance from the surface of the insulating portion 40 away from the carrier 21 to the carrier 21 can be controlled so that the insulating portion 40 at least covers the portion 311 of the first bonding wire 31 closer to the carrier 21 away from the chip front. In this way, a portion of the insulating part 40 is located between a portion 311 of the first bonding wire 31 away from the front side of the chip and a portion 321 of the second bonding wire 32 away from the front side of the chip, and the insulating part 40 is at least connected to the portion 311 of the first bonding wire 31 away from the front side of the chip, which can effectively avoid the impact of the molding material during the formation of the molding layer causing the first bonding wire 31 to contact the second bonding wire 32.

[0052] Furthermore, if Figure 2 As shown, the insulating portion 40 completely covers the first bonding wire 31 and the second bonding wire 32. In this way, during the process of forming the plastic encapsulation layer, even under the impact of the plastic encapsulation material, the first bonding wire 31 and the second bonding wire 32 will not move, which can more effectively avoid the first bonding wire 31 and the second bonding wire 32 from contacting each other.

[0053] Further, in a direction perpendicular to the plane where the chip front is located, the distance between the portion 311 of the first bonding wire 31 away from the chip front and the portion 321 of the second bonding wire 32 away from the chip front is greater than the outer diameter of the bonding wire 30. In this way, there is a certain distance between the portion 311 of the first bonding wire 31 away from the chip front and the portion 321 of the second bonding wire 32 away from the chip front, which helps to avoid the impact of the insulating material on the first bonding wire 31 and the second bonding wire 32 during the formation of the insulating portion 40, so that the two are in contact. In some embodiments, in a direction perpendicular to the plane where the chip front is located, the distance between the portion 311 of the first bonding wire 31 away from the chip front and the portion 321 of the second bonding wire 32 away from the chip front is greater than twice the outer diameter of the bonding wire 30. In this way, the impact of the insulating material on the first bonding wire 31 and the second bonding wire 32, so that the two are in contact, can be more effectively avoided.

[0054] In one embodiment, Figure 3As shown, in the direction of the plane where the front side of the chip is located, the first bonding wire 31 is adjacent to the second bonding wire 32. The plurality of pads 11 include a first pad 111 connected to the first bonding wire 31 and a second pad 112 connected to the second bonding wire 32, and the first pad 111 is adjacent to the second pad 112; the plurality of pins 22 include a first pin 221 connected to the first bonding wire 31 and a second pin 222 connected to the second bonding wire 32, and the first pin 221 is adjacent to the second pin 222; the distance between the first pad 111 and the second pad 112 is smaller than the distance between the first pin 221 and the second pin 222; the insulating portion 40 at least covers the end of the first bonding wire 31 connected to the first pad 111 and the end of the second bonding wire 32 connected to the second pad 112. The distance between the end of the first bonding wire 31 connected to the first pad 111 and the end of the second bonding wire 32 connected to the second pad 112 is small, and the two are more likely to contact each other after being impacted by the plastic packaging material. Therefore, the insulating part 40 covers the end of the first bonding wire 31 connected to the first pad 111 and the end of the second bonding wire 32 connected to the second pad 112, which can effectively prevent the first bonding wire 31 from contacting the second bonding wire 32 and causing a short circuit. Figure 3 In the illustrated embodiment, the insulating portion 40 only covers the end portion of the first bonding wire 31 connected to the first pad 111 and the end portion of the second bonding wire 32 connected to the second pad 112. In other embodiments, the insulating portion 40 may cover the entire first bonding wire 31 and the second bonding wire 32.

[0055] In one embodiment, the insulating portion 40 covers each bonding wire 30. In this way, the provision of the insulating portion 40 can effectively prevent any two adjacent bonding wires 30 from contacting each other and causing a short circuit during the process of forming the plastic encapsulation layer; at the same time, it can prevent the bonding wires from being impacted by the plastic encapsulation material and collapsing during the process of forming the plastic encapsulation layer, and the collapsed part of the bonding wires from contacting the conductive structure on the surface of the chip and causing a short circuit.

[0056] In one embodiment, the insulating portion 40 covers the entire chip front surface of the chip 10. In this way, the insulating portion 40 can protect the pad 11 disposed on the chip front surface.

[0057] Furthermore, the insulating portion 40 covers the front side of the chip and the area of ​​the carrier portion not covered by the chip. Thus, the insulating portion 40 can fix the chip 10 on the carrier portion 21 more firmly, and further prevent the chip 10 from moving relative to the carrier portion 21.

[0058] In one embodiment, Figure 2 and Figure 3As shown, the insulating portion 40 does not cover the lead 22. In other embodiments, the insulating portion 40 may cover at least a portion of the lead 22. During the process of forming the insulating portion 40, if the insulating material has good fluidity, the insulating material may flow to the surface of the lead 22 facing the bonding wire 30, so that the finally formed insulating portion 40 covers at least a portion of the surface of the lead 22.

[0059] In one embodiment, the material of the insulating portion 40 is acrylic hot melt adhesive (AD glue). In this way, the material cost of the insulating portion 40 is relatively low, and the preparation cost of the semiconductor structure will not be significantly increased. In other embodiments, the material of the insulating portion 40 may be other materials that can be converted from a fluid state to a solid state.

[0060] In one embodiment, the temperature at which the insulating portion 40 is transformed from a solid state to a molten state is higher than the curing temperature of the material of the plastic encapsulation layer 30. The plastic encapsulation layer 30 is formed after the insulating portion 40. By setting the temperature at which the insulating portion 40 is transformed from a solid state to a molten state to be higher than the curing temperature of the material of the plastic encapsulation layer 30, it is possible to avoid the insulating portion 40 being transformed into a molten state during the curing process of the plastic encapsulation layer, resulting in the insulating portion 40 no longer covering the bonding wires covered before it melts, thereby causing adjacent bonding wires to contact.

[0061] In one embodiment, the insulating portion 40 covers the front side of the chip 10, and the material of the insulating portion 40 is a material with very low transmittance, for example, the material of the insulating portion 40 may be black. In this way, the structure of the chip 10 cannot be directly observed, which can increase the difficulty of technical cracking of the semiconductor structure.

[0062] In one embodiment, Figure 2 As shown, the surface of the pin 22 facing away from the front of the chip exposes the plastic layer 50. In other embodiments, the end of the pin 22 away from the chip may expose the plastic layer 50. The portion of the pin 22 exposed from the plastic layer may be electrically connected to an external component.

[0063] In one embodiment, the material of the plastic encapsulation layer 50 may be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer 50 may be a resin with a filler, wherein the filler may be an inorganic particle. The plastic encapsulation layer 50 may be formed by injection molding, compression molding, or transfer molding.

[0064] The present application also provides a method for manufacturing a semiconductor structure. Figure 4 As shown, the method for manufacturing the semiconductor structure includes the following steps 110 to 150 .

[0065] In step 110, a chip and an electrical connector are provided; the chip includes a chip front side, a chip back side opposite to the chip front side, and a plurality of chip side sides connecting the chip front side and the chip back side; a plurality of solder pads are provided on the chip front side; the electrical connector includes a carrier portion and a plurality of pins located on the side of the carrier portion.

[0066] In step 120, the chip is mounted on one side of the carrier; the back side of the chip faces the carrier, and the plurality of pins of the electrical connector are located on the side of the chip.

[0067] In one embodiment, the step of attaching the chip to one side of the carrier may include the following process:

[0068] First, silver paste is applied on one side of the carrier;

[0069] Subsequently, the chip is placed on the silver paste;

[0070] Subsequently, the silver paste is cured, and after the silver paste is cured, the chip is fixed on the carrier through the cured silver paste.

[0071] In step 130, a plurality of bonding wires are provided, wherein the bonding wires electrically connect the pad to the pin, or electrically connect two pads; the plurality of bonding wires include a first bonding wire and a second bonding wire, wherein the first bonding wire is adjacent to the second bonding wire.

[0072] In one embodiment, the two ends of the bonding wire may be bonded to the conductive portion and the pad respectively by wire bonding, or the two ends of the bonding wire may be bonded to the two pads respectively by wire bonding, wherein wire bonding refers to a method of tightly welding two structures by using heat, pressure, or ultrasonic energy.

[0073] In step 140 , an insulating portion is formed, wherein the insulating portion covers at least a portion of at least one of the first bonding wire and the second bonding wire.

[0074] In one embodiment, the step of forming the insulating portion may include the following process: dripping a fluid insulating material onto the surface of the chip front and / or the exposed surface of the carrier, and solidifying the insulating material to form the insulating portion. As the amount of insulating material dripped onto the chip front and the surface of the carrier that is not covered by the chip gradually increases, the height of the insulating material increases, so that the insulating material can cover at least one of the first bonding wire and the second bonding wire. The insulating portion finally formed can cover the chip front, and can also cover the area of ​​the carrier that is not covered by the chip.

[0075] In one embodiment, the orthographic projection of the dripping track of the insulating material on the plane where the front surface of the chip is located does not overlap with the orthographic projection of the first bonding wire on the plane, and does not overlap with the orthographic projection of the second bonding wire on the plane. The insulating material drips under the action of gravity, and its dripping track is a straight line. This arrangement can prevent the insulating material from dripping directly on the first bonding wire or the second bonding wire, causing the first bonding wire or the second bonding wire to deform and contact each other.

[0076] In one embodiment, the orthographic projection of the dripping track of the insulating material on the plane where the front surface of the chip is located does not overlap with the orthographic projection of each bonding wire on the plane. This arrangement can prevent the insulating material from dripping directly on the bonding wire, causing the bonding wire to collapse, and the collapsed part of the bonding wire to contact the conductive structure on the surface of the chip and cause a short circuit.

[0077] In one embodiment, the angle between the dripping track of the insulating material and the plane where the front of the chip is located is an acute angle. Such a configuration helps to reduce the impact force of the insulating material on the bonding wire, improve the short circuit of adjacent bonding wires caused by the impact of the bonding wire, and the short circuit caused by the collapse of the bonding wire after the impact and contact with the conductive structure on the surface of the chip. When dripping the insulating material onto the front of the chip or the surface of the carrier that is not covered by the front of the chip, the structure including the chip, electrical connectors and bonding wires can be tilted to form a certain angle with the horizontal direction, and then the insulating material can be dripped, so that the angle between the dripping track of the insulating material and the plane where the front of the chip is located is an acute angle.

[0078] In some embodiments, the dripping speed of the insulating material can be controlled to reduce the impact of the insulating material on the bonding wire.

[0079] In step 150, a plastic encapsulation layer is formed, wherein the plastic encapsulation layer encapsulates the chip, the electrical connector, the insulating portion, and the bonding wire; and at least a portion of the pin is exposed from the plastic encapsulation layer.

[0080] In one embodiment, before forming the plastic encapsulation layer, some pre-processing steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the chip, electrical connectors and insulating parts, so that the plastic encapsulation layer can be more closely connected to the chip, electrical connectors and insulating parts without delamination or cracking.

[0081] In one embodiment, the material of the plastic encapsulation layer may be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer may be a resin with a filler, wherein the filler may be an inorganic particle. The plastic encapsulation layer may be formed by injection molding, compression molding, or transfer molding.

[0082] In one embodiment, in a direction perpendicular to the plane where the front side of the chip is located, the first bonding wire is adjacent to the second bonding wire, and the orthographic projection of a portion of the first bonding wire away from the front side of the chip on the plane where the front side of the chip is located overlaps with the orthographic projection of a portion of the second bonding wire away from the front side of the chip on the plane; the portion of the second bonding wire away from the front side of the chip is located on a side of the first bonding wire away from the supporting portion; the insulating portion covers the chip, and the insulating portion at least covers the portion of the first bonding wire away from the front side of the chip.

[0083] In one embodiment, in the direction of the plane where the front side of the chip is located, the first bonding wire is adjacent to the second bonding wire; the multiple pads include a first bonding pad connected to the first bonding wire and a second bonding pad connected to the second bonding wire, and the first bonding pad is adjacent to the second bonding pad; the multiple pins include a first pin connected to the first bonding wire and a second pin connected to the second bonding wire, and the first pin is adjacent to the second pin; the distance between the first bonding pad and the second bonding pad is smaller than the distance between the first pin and the second pin; the insulating portion at least covers the end of the first bonding wire connected to the first bonding pad and the end of the second bonding wire connected to the second bonding pad.

[0084] The embodiment of the semiconductor structure provided in the embodiment of the present application and the embodiment of the method for preparing the semiconductor structure belong to the same inventive concept, and the description of the relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0085] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0086] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0087] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: A chip, the chip comprising a chip front side and a chip back side opposite to the chip front side; a plurality of pads are provided on the chip front side; An electrical connector, the electrical connector comprising a carrier and a plurality of pins located on a side of the carrier; the chip is mounted on one side of the carrier, and the back of the chip faces the carrier; A plurality of bonding wires, the bonding wires electrically connecting the pad to the pin, or electrically connecting two pads; the plurality of bonding wires include a first bonding wire and a second bonding wire, the first bonding wire is adjacent to the second bonding wire; an insulating portion covering at least a portion of at least one of the first bonding wire and the second bonding wire; A plastic encapsulation layer encapsulates the chip, the electrical connector, the insulating portion and the bonding wire; and at least a portion of the pin is exposed from the plastic encapsulation layer.

2. The semiconductor structure according to claim 1, characterized in that: In a direction perpendicular to the plane where the chip front surface is located, the first bonding wire is adjacent to the second bonding wire, and an orthographic projection of a portion of the first bonding wire away from the chip front surface on the plane where the chip front surface is located overlaps with an orthographic projection of a portion of the second bonding wire away from the chip front surface on the plane; The portion of the second bonding wire away from the front surface of the chip is located on a side of the first bonding wire away from the carrying portion; The insulating portion is located on the front side of the chip, and the insulating portion at least covers a portion of the first bonding wire away from the front side of the chip.

3. The semiconductor structure according to claim 2, characterized in that: The insulating portion completely covers the first bonding wire and the second bonding wire; and / or, In a direction perpendicular to the plane where the chip front side is located, a distance between a portion of the first bonding wire away from the chip front side and a portion of the second bonding wire away from the chip front side is greater than an outer diameter of the bonding wire.

4. The semiconductor structure according to claim 1, characterized in that: In the direction of the plane where the front surface of the chip is located, the first bonding wire is adjacent to the second bonding wire; The multiple pads include a first pad connected to the first bonding wire and a second pad connected to the second bonding wire, and the first pad is adjacent to the second pad; the multiple pins include a first pin connected to the first bonding wire and a second pin connected to the second bonding wire, and the first pin is adjacent to the second pin; the distance between the first pad and the second pad is smaller than the distance between the first pin and the second pin; the insulating portion at least covers the end of the first bonding wire connected to the first pad and the end of the second bonding wire connected to the second pad.

5. The semiconductor structure according to claim 1, characterized in that: The temperature at which the insulating portion is transformed from a solid state to a molten state is higher than the solidification temperature of the material of the plastic packaging layer.

6. The semiconductor structure according to claim 1, characterized in that The insulating portion covers the chip front surface and an area of ​​the carrier portion not covered by the chip.

7. The semiconductor structure according to claim 1, characterized in that: The electrical connector is a lead frame, and the bearing portion is spaced apart from the lead; or, The electrical connector is a circuit board, which includes a main body, the pins are located on the main body, and the bearing portion is a part of the main body.

8. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a chip and an electrical connector; the chip comprises a chip front side and a chip back side opposite to the chip front side; The front side of the chip is provided with a plurality of pads; the electrical connector comprises a bearing portion and a plurality of pins located on the side of the bearing portion; The chip is mounted on one side of the carrier; the back of the chip faces the carrier, and the plurality of pins of the electrical connector are located on the side of the chip; Providing a plurality of bonding wires, wherein the bonding wires electrically connect the pad to the pin, or electrically connect two pads; the plurality of bonding wires include a first bonding wire and a second bonding wire, wherein the first bonding wire is adjacent to the second bonding wire; forming an insulating portion, the insulating portion covering at least a portion of at least one of the first bonding wire and the second bonding wire; A plastic encapsulation layer is formed, wherein the plastic encapsulation layer encapsulates the chip, the electrical connector, the insulating portion and the bonding wire; and at least a portion of the pin is exposed from the plastic encapsulation layer.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The forming of the insulating portion comprises: A fluid insulating material is dripped onto the front surface of the chip and / or the exposed surface of the carrier portion, and the insulating material is solidified to form an insulating portion.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The orthographic projection of the dripping track of the insulating material on the plane where the front surface of the chip is located does not overlap with the orthographic projection of the first bonding wire on the plane, and does not overlap with the orthographic projection of the second bonding wire on the plane; and / or, The angle between the dripping track of the insulating material and the orthographic projection on the plane where the front surface of the chip is located is an acute angle.

11. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: In a direction perpendicular to the plane where the chip front surface is located, the first bonding wire is adjacent to the second bonding wire, and an orthographic projection of a portion of the first bonding wire away from the chip front surface on the plane where the chip front surface is located overlaps with an orthographic projection of a portion of the second bonding wire away from the chip front surface on the plane; The portion of the second bonding wire away from the front surface of the chip is located on a side of the first bonding wire away from the carrying portion; The insulating portion is located on the front side of the chip, and the insulating portion at least covers a portion of the first bonding wire away from the front side of the chip; or, In the direction of the plane where the front side of the chip is located, the first bonding wire is adjacent to the second bonding wire; the multiple pads include a first bonding pad connected to the first bonding wire and a second bonding pad connected to the second bonding wire, and the first bonding pad is adjacent to the second bonding pad; the multiple pins include a first pin connected to the first bonding wire and a second pin connected to the second bonding wire, and the first pin is adjacent to the second pin; the distance between the first bonding pad and the second bonding pad is smaller than the distance between the first pin and the second pin; the insulating part at least covers the end of the first bonding wire connected to the first bonding pad and the end of the second bonding wire connected to the second bonding pad.

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