Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprising: a substrate; an interlayer dielectric layer formed on the substrate; a metal interconnection structure formed in the interlayer dielectric layer, the metal interconnection structure comprising two layers of metal layers and a via plug, each of the metal layers comprising at least one metal line, each of the metal lines comprising a plurality of sub-metal lines, the sub-metal lines in the metal lines of adjacent layers being staggered, and the sub-metal lines in the metal lines of adjacent layers being electrically connected through the via plug. The technical scheme of the application can significantly reduce the parasitic capacitance of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In practical applications, semiconductor devices (such as MOS transistors) have certain parasitic capacitances, which have certain influences on the performance of circuits, cause additional charge and voltage fluctuation of the semiconductor devices when switching, and thus affect the response speed of the circuit. In addition, due to the consumption of additional power when switching, the parasitic capacitance also causes the power consumption of the semiconductor device to increase, and meanwhile introduces additional interference signals and increases the noise of the circuit.

[0003] In order to reduce the parasitic capacitance, the existing process generally uses a material with low dielectric constant (k) or an air gap as an interlayer dielectric layer, but this method needs to use additional materials or processes.

[0004] Therefore, how to significantly reduce the parasitic capacitance of the semiconductor device is a problem to be solved at present. SUMMARY

[0005] The present application aims to provide a semiconductor device and a manufacturing method thereof, which can significantly reduce the parasitic capacitance of the semiconductor device.

[0006] To achieve the above-mentioned purpose, the present application provides a semiconductor device, comprising:

[0007] a substrate;

[0008] an interlayer dielectric layer formed on the substrate;

[0009] a metal interconnection structure formed in the interlayer dielectric layer, the metal interconnection structure comprising two layers of metal layers and a via plug, each of the metal layers comprising at least one metal line, each of the metal lines comprising a plurality of sub-metal lines, the sub-metal lines in the metal lines of adjacent layers being staggered in arrangement, and the sub-metal lines in the metal lines of adjacent layers being electrically connected through the via plug.

[0010] Optionally, each of the metal layers comprises at least two metal lines; in each of the metal layers, the sub-metal lines in adjacent two metal lines are staggered in arrangement.

[0011] Optionally, the semiconductor device further comprises:

[0012] a shallow trench isolation structure formed in the substrate, the shallow trench isolation structure defining an active region;

[0013] a gate structure formed on the active region;

[0014] a source region and a drain region formed in the active region;

[0015] The metal interconnection structure further comprises a contact plug, the bottommost metal layer is electrically connected with the source region or the drain region through the contact plug.

[0016] Optionally, the sub-metal lines in the metal lines of adjacent layers are electrically connected through at least two via plugs.

[0017] Optionally, the semiconductor device further comprises a dummy gate located on both sides of the gate structure.

[0018] Optionally, the metal interconnection structure comprises a first metal layer and a second metal layer, wherein the second metal layer further comprises a metal block, the metal lines extend in a first direction, the metal block extends in a second direction, the metal block is located at both ends of the metal lines, and each metal block is connected with the source region or the drain region.

[0019] The present application further provides a manufacturing method of a semiconductor device, comprising:

[0020] providing a substrate;

[0021] forming an interlayer dielectric layer and a metal interconnection structure, the interlayer dielectric layer is formed on the substrate, and the metal interconnection structure is formed in the interlayer dielectric layer; the metal interconnection structure comprises two metal layers and a via plug, each metal layer comprises at least one metal line, each metal line comprises a plurality of sub-metal lines, the sub-metal lines in the metal lines of adjacent layers are staggered, and the sub-metal lines in the metal lines of adjacent layers are electrically connected through the via plug.

[0022] Optionally, each metal layer comprises at least two metal lines; in each metal layer, the sub-metal lines in adjacent two metal lines are staggered.

[0023] Optionally, before forming the interlayer dielectric layer and the metal interconnection structure, the manufacturing method of the semiconductor device further comprises:

[0024] forming a shallow trench isolation structure in the substrate, the shallow trench isolation structure defines an active region;

[0025] forming a gate structure on the active region;

[0026] forming a source region and a drain region in the active region;

[0027] The metal interconnection structure further comprises a contact plug, the bottommost metal layer is electrically connected with the source region or the drain region through the contact plug.

[0028] Optionally, the sub-metal lines in the metal lines of adjacent layers are electrically connected through at least two of the via plugs.

[0029] Optionally, the metal interconnection structure comprises a first metal layer and a second metal layer, wherein the second metal layer further comprises metal blocks, the metal lines extend in a first direction, the metal blocks extend in a second direction, and the metal blocks are located at both ends of the metal lines, and each of the metal blocks is connected to the source region or the drain region.

[0030] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0031] 1. The semiconductor device of the present application, since the metal interconnection structure comprises two metal layers and via plugs, each of the metal layers comprises at least one metal line, each of the metal lines comprises a plurality of sub-metal lines, the sub-metal lines in the metal lines of adjacent layers are staggered, and the sub-metal lines in the metal lines of adjacent layers are electrically connected through the via plugs, so that the parasitic capacitance of the semiconductor device can be significantly reduced.

[0032] 2. The manufacturing method of the semiconductor device of the present application, by forming an interlayer dielectric layer on a substrate and a metal interconnection structure in the interlayer dielectric layer, the metal interconnection structure comprises two metal layers and via plugs, each of the metal layers comprises at least one metal line, each of the metal lines comprises a plurality of sub-metal lines, the sub-metal lines in the metal lines of adjacent layers are staggered, and the sub-metal lines in the metal lines of adjacent layers are electrically connected through the via plugs, so that the parasitic capacitance of the semiconductor device can be significantly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a top view schematic diagram of a semiconductor device of an embodiment of the present application;

[0034] Figure 2a is a longitudinal sectional view schematic diagram of a metal interconnection structure of an embodiment of the present application;

[0035] Figure 2b is Figure 1 is a longitudinal sectional view schematic diagram of the semiconductor device shown along the AA' direction;

[0036] Figure 3 is Figure 1 is a longitudinal sectional view schematic diagram of the semiconductor device shown along the BB' direction;

[0037] Figure 4 is a flow chart of a manufacturing method of a semiconductor device of an embodiment of the present application.

[0038] Wherein, the attached Figures 1 to 4 The reference signs in the drawings are explained as follows:

[0039] 10 - substrate; 101 - shallow trench isolation structure; 11 - interlayer dielectric layer; 121a - first sub-metal line; 121b - first connection layer; 121c - second connection layer; 122 - second metal layer; 122a - second sub-metal line; 122b - metal block; 131 - via plug; 132 - contact plug; 14 - gate structure; 15 - dummy gate. DETAILED DESCRIPTION

[0040] To make the objects, advantages and features of the present application more clear, the semiconductor device and the manufacturing method thereof proposed by the present application are further described in detail below in combination with the drawings. It should be noted that all the drawings are in a very simplified form and all use non-precise proportions, only to facilitate, clearly assist the purpose of explaining the embodiments of the present application.

[0041] An embodiment of the present application provides a semiconductor device, comprising: a substrate; an interlayer dielectric layer formed on the substrate; a metal interconnection structure formed in the interlayer dielectric layer, the metal interconnection structure comprising two metal layers and a via plug, each of the metal layers comprising at least one metal line, each of the metal lines comprising a plurality of sub-metal lines, the sub-metal lines in the metal lines of adjacent layers being staggered, the sub-metal lines in the metal lines of adjacent layers being electrically connected through the via plug.

[0042] Reference will be made to Figures 1 to 3 The semiconductor device provided by the embodiment is described in more detail, Figure 1 The shallow trench isolation structure 101 and the interlayer dielectric layer 11 are not shown in the figure.

[0043] The substrate 10 can be a single-layer structure or a multi-layer structure composed of the same or different materials. The substrate 10 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors, etc., can also include a layered substrate such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI) or silicon-on-silicon germanium, and can also include other materials other than semiconductor materials, which are not limited by the present application.

[0044] The interlayer dielectric layer 11 is formed on the substrate 10.

[0045] The interlayer dielectric layer 11 can include a plurality of stacked insulating layers.

[0046] The metal interconnection structure is formed in the interlayer dielectric layer 11, and includes two metal layers (i.e., a first metal layer and a second metal layer 122) and a via plug 131, each of the metal layers includes at least one metal line, each of the metal lines includes a plurality of sub-metal lines; in the two adjacent metal layers, the sub-metal lines in the metal lines of the adjacent layers are staggered, and the sub-metal lines in the metal lines of the adjacent layers are electrically connected by the via plug 131. Wherein, the sub-metal lines in the metal lines of the adjacent layers are staggered in the direction perpendicular to the surface of the substrate 10, as shown in Figure 2a the first sub-metal line 121a in the first metal layer and the second sub-metal line 122a in the second metal layer are staggered and electrically connected by the via plug 131 in the direction.

[0047] Wherein, in the two adjacent metal layers, the projections of the sub-metal lines in the metal lines of the adjacent layers in the direction perpendicular to the surface of the substrate 10 only overlap at the ends, the regions of the sub-metal lines in the metal lines of the adjacent layers other than the ends do not overlap in the direction perpendicular to the surface of the substrate 10, the via plug 131 is located between the ends of the sub-metal lines in the metal lines of the adjacent layers, and each of the sub-metal lines in the metal lines of the adjacent layers is connected in turn by the via plug 131 to realize the electrical connection between the metal lines of the adjacent layers.

[0048] Because the projections of the sub-metal lines in the metal lines of the adjacent layers in the direction perpendicular to the surface of the substrate 10 are staggered, the overlapping area between the projections of the metal lines of the adjacent layers in the direction perpendicular to the surface of the substrate 10 is significantly reduced, and further the overlapping area (i.e., the opposite area of the metal layer) between the projections of the metal layers of the adjacent layers in the direction perpendicular to the surface of the substrate 10 is significantly reduced, thereby significantly reducing the parasitic capacitance formed by the metal layers of the adjacent layers and the interlayer dielectric layer 11 therebetween, i.e., significantly reducing the parasitic capacitance of the semiconductor device.

[0049] In one embodiment, each of the metal layers includes at least two metal lines, and preferably, in each of the metal layers, the sub-metal lines in the two adjacent metal lines are staggered. Wherein, the sub-metal lines in the two adjacent metal lines are staggered in the direction perpendicular to the extension direction of the metal lines, as shown in Figure 1As shown, in the same metal layer, the first sub-metal line 121a of one metal line is staggered from the first sub-metal line 121a of the adjacent metal line. In each metal layer, the ends of the sub-metal lines of two adjacent metal lines may overlap or not overlap in the direction perpendicular to the extension of the metal line, and the areas other than the ends of the sub-metal lines of two adjacent metal lines do not overlap in the direction perpendicular to the extension of the metal line.

[0050] Because the sub-metal lines of two adjacent metal lines are staggered in the direction perpendicular to the extension of the metal lines in each metal layer, the overlapping area (i.e. the area facing each other) of two adjacent metal lines in the direction perpendicular to the extension of the metal lines in each metal layer is significantly reduced. This significantly reduces the parasitic capacitance formed by the two adjacent metal lines and the interlayer dielectric layer 11 between them in each metal layer, thereby further significantly reducing the parasitic capacitance of the semiconductor device.

[0051] In one embodiment, the second metal layer 122 further includes a metal block 122b. The metal wire can extend in a first direction, and the metal block 122b can extend in a second direction. The metal block 122b can be located at both ends of the metal wire. One end of the metal wire in the second metal layer 122 is connected to one of the metal blocks 122b, and the other end of the metal wire in the second metal layer 122 is not connected to the other metal block 122b. The first direction and the second direction are different; in one embodiment, the first direction is perpendicular to the second direction.

[0052] The two metal blocks 122b are arranged opposite each other, and all the metal wires are arranged sequentially and at intervals between the two metal blocks 122b along the second direction.

[0053] In one embodiment, the second metal layer 122 includes two comb-shaped structures arranged opposite to each other. Each comb-shaped structure includes multiple comb teeth arranged in sequence and a comb back located at the same end of each comb tooth. The comb backs of the two comb-shaped structures are parallel to each other, and the comb teeth are perpendicular to the comb backs. The comb teeth and the comb backs can be connected. The metal wire serves as the comb teeth, and the metal block 122b serves as the comb back.

[0054] like Figure 1 to 3As shown, the metal interconnection structure includes a first metal layer and a second metal layer 122 located above the first metal layer; the first metal layer includes a plurality of first metal lines extending in a first direction Y, the first metal lines are arranged in a second direction X with intervals, each of the first metal lines includes a plurality of first sub-metal lines 121a, the first sub-metal lines 121a in adjacent two of the first metal lines are arranged in the second direction X with intervals; the second metal layer 122 includes two oppositely arranged comb-shaped structures, each of the comb-shaped structures includes a plurality of second metal lines extending in the first direction Y and a metal block 122b extending in the second direction X, each of the second metal lines includes a plurality of second sub-metal lines 122a, the second sub-metal line 122a closest to the metal block 122b in each of the comb-shaped structures is connected to the metal block 122b, the second metal lines in the two comb-shaped structures are arranged in an interpenetrating manner, and the second sub-metal lines 122a in adjacent two of the second metal lines are arranged in the second direction X with intervals; the first sub-metal lines 121a in the first metal lines and the second sub-metal lines 122a in the second metal lines are arranged in a projection direction perpendicular to the surface of the substrate 10 with intervals, and each of the first sub-metal lines 121a and each of the second sub-metal lines 122a are sequentially and alternately electrically connected by the via plug 131. The first direction Y is perpendicular to the second direction X.

[0055] The semiconductor device further includes:

[0056] A shallow trench isolation structure 101 formed in the substrate 10, the shallow trench isolation structure 101 defining an active region;

[0057] A gate structure 14 formed on the active region. In an embodiment, the gate structure 14 can also extend from the active region to the shallow trench isolation structure 101;

[0058] A source region (not shown) and a drain region (not shown) formed in the active region.

[0059] Each of the metal blocks 122b in the second metal layer 122 is electrically connected to the source region or the drain region, i.e., each of the comb-shaped structures is electrically connected to the source region or the drain region.

[0060] As Figure 1 and Figure 2bAs shown, the semiconductor device further comprises: a first connection layer 121b and a second connection layer 121c extending in the second direction X, the first connection layer 121b and the second connection layer 121c are both in the same layer as the first metal layer, and the first connection layer 121b and the second connection layer 121c are respectively located at both ends of the first metal line, the first sub-metal line 121a closest to the first connection layer 121b is not connected with the first connection layer 121b, and the first sub-metal line 121a closest to the second connection layer 121c is not connected with the second connection layer 121c; the projection of the first connection layer 121b and one of the metal blocks 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10 is staggered, and the projection of the second connection layer 121c and the other metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10 is overlapped.

[0061] Preferably, the projections of the first connection layer 121b and the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 are respectively staggered with the projections of the metal blocks 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10, so that the overlapping area between the projections of the first connection layer 121b and the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 and the projections of the metal blocks 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10 (i.e. the facing area between the first connection layer 121b and the second connection layer 121c and the metal blocks 122b in the second metal layer 122 respectively) is significantly reduced, and further the parasitic capacitance formed by the first connection layer 121b, the metal blocks 122b and the interlayer dielectric layer 11 therebetween and the parasitic capacitance formed by the second connection layer 121c, the metal blocks 122b and the interlayer dielectric layer 11 therebetween are significantly reduced, thereby further significantly reducing the parasitic capacitance of the semiconductor device. In other embodiments, the projections of the first connection layer 121b and the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 can be overlapped with the projections of the metal blocks 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10 respectively.

[0062] In one embodiment, the semiconductor device further includes dummy gates 15 located on both sides of the gate structure 14. The dummy gates 15 do not need to be electrically connected to the metal layer; that is, the dummy gates 15 are not electrically led out. The dummy gates 15 are used for optical proximity correction during exposure, ensuring that the pattern of the formed gate structure 14 is not distorted. Furthermore, during the planarization of the device surface using a chemical mechanical polishing process, the dummy gates 15 can also be used to reduce the impact of the process itself on the gate structure 14.

[0063] The metal interconnect structure also includes a contact plug 132, through which the first metal layer is electrically connected to the source region or the drain region respectively.

[0064] The active region can also form a volumetric contact region (not shown).

[0065] by Figure 1 Taking the structure shown as an example, the gate structure 14 is an H-type structure. The "-" portion of the H-type structure extends in the first direction Y. The projection of the "-" portion of the H-type structure in the direction perpendicular to the surface of the substrate 10 is located between the projections of adjacent first metal lines in the direction perpendicular to the surface of the substrate 10 or between the projections of adjacent second metal lines in the direction perpendicular to the surface of the substrate 10. The "|" portion of the H-type structure extends in the second direction X. One end of multiple "-" portions of the H-type structure extends from the active region to the shallow trench isolation structure 101. Both ends of one "|" portion of the H-type structure extend from the active region to the shallow trench isolation structure 101. The other "|" portion of the H-type structure is located on the shallow trench isolation structure 101. The source region and the drain region are respectively formed in the "-" portion of the H-type structure. In the active regions on both sides of the H-shaped structure, the body contact region is formed in the active region on the side of the "|" portion away from the "—" portion of the H-shaped structure; the first connecting layer 121b and one of the metal blocks 122b are located above the shallow trench isolation structure 101, the second connecting layer 121c is located above the body contact region, and another metal block 122b extends from above the body contact region to above the shallow trench isolation structure 101; the first sub-metal line 121a in the first metal line is electrically connected to the source region and the drain region respectively through the contact plug 132, the first connecting layer 121b is electrically connected to the gate structure 14 (the "|" portion of the H-shaped structure) extending to the shallow trench isolation structure 101 through the contact plug 132, and the second connecting layer 121c is electrically connected to the body contact region through the contact plug 132. In other embodiments, the gate structure 14 can be a T-shaped structure.

[0066] Preferably, each segment of the sub-metal wire in the first metal layer is electrically connected to the source region or drain region through at least two contact plugs 132 to improve the effectiveness of the connection. For example, if one of the contact plugs 132 is disconnected or fails, the other contact plugs 132 can still keep the circuit connected and prevent the entire circuit from being disconnected.

[0067] Preferably, the sub-metal wires in the metal wires of adjacent layers are electrically connected by at least two through-hole plugs 131 to improve the effectiveness of the connection. For example, if a first sub-metal wire in the first metal layer is electrically connected to a second sub-metal wire in the second metal layer 122 by at least two through-hole plugs 131, if one of the through-hole plugs 131 is disconnected or fails, the other through-hole plugs 131 can still keep the circuit connected and prevent the entire circuit from being disconnected.

[0068] In addition, the semiconductor device further includes: a conductive interconnect structure (not shown) electrically connected to the metal interconnect structure, the first connection layer 121b and the second connection layer 121c respectively. The conductive interconnect structure is used to electrically lead out the metal interconnect structure, the first connection layer 121b and the second connection layer 121c respectively, and then correspondingly electrically lead out the source region, the drain region, the gate structure 14 and the body contact region respectively.

[0069] In summary, the semiconductor device provided by the present invention includes: a substrate; an interlayer dielectric layer formed on the substrate; and a metal interconnect structure formed in the interlayer dielectric layer. The metal interconnect structure includes two metal layers and via plugs. Each metal layer includes at least one metal line, and each metal line includes multiple sub-metal lines. The sub-metal lines in adjacent metal lines are staggered and electrically connected to each other through the via plugs. The semiconductor device of the present invention enables a significant reduction in parasitic capacitance of the semiconductor device.

[0070] One embodiment of the present invention provides a method for manufacturing a semiconductor device, see reference. Figure 4 , Figure 4 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method comprising:

[0071] Step S1: Provide a substrate;

[0072] Step S2: Form an interlayer dielectric layer and a metal interconnect structure. The interlayer dielectric layer is formed on the substrate, and the metal interconnect structure is formed in the interlayer dielectric layer. The metal interconnect structure includes two metal layers and via plugs. Each metal layer includes at least one metal line, and each metal line includes multiple sub-metal lines. The sub-metal lines in adjacent metal lines are staggered and electrically connected to each other through the via plugs.

[0073] See below. Figures 1 to 3 The manufacturing method of the semiconductor device provided in this embodiment will be described in more detail. Figure 1 The shallow trench isolation structure 101 and the interlayer medium layer 11 are not shown in the diagram.

[0074] According to step S1, a substrate 10 is provided.

[0075] The substrate 10 can be a single-layer structure or a multilayer structure composed of the same or different materials. The substrate 10 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors, or a layered substrate such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. It can also include other materials besides semiconductor materials, which are not limited in this application.

[0076] According to step S2, an interlayer dielectric layer 11 and a metal interconnect structure are formed. The interlayer dielectric layer 11 is formed on the substrate 10, and the metal interconnect structure is formed in the interlayer dielectric layer 11. The metal interconnect structure includes two metal layers (i.e., a first metal layer and a second metal layer 122) and a via plug 131. Each metal layer includes at least one metal line, and each metal line includes multiple sub-metal lines. In two adjacent metal layers, the sub-metal lines in the metal lines of the adjacent layers are staggered, and the sub-metal lines in the metal lines of the adjacent layers are electrically connected through the via plug 131.

[0077] The staggered arrangement of the sub-metal lines in adjacent layers refers to the staggered arrangement of the projections of the sub-metal lines in adjacent layers in a direction perpendicular to the surface of the substrate 10, such as... Figure 2a As shown, in this direction, the first sub-metal line 121a in the first metal layer and the second sub-metal line 122a in the second metal layer are staggered and electrically connected through a through-hole plug 131. The interlayer dielectric layer 11 may include multiple stacked insulating layers.

[0078] In one embodiment, the first insulating layer is deposited first, and then the first metal layer is formed by depositing a metal material on the first insulating layer and etching the metal material. Then, the second insulating layer is deposited on the first insulating layer and the first metal layer, and the via and the recess are formed by etching the second insulating layer. The top surface of the first metal layer is exposed at the bottom of the via, and the recess is located at the top of the via. The metal material in the via serves as the via plug 131, and the metal material in the recess serves as the second metal layer. Thus, the interlayer dielectric layer 11 and the metal interconnection structure are formed.

[0079] In the adjacent two layers of the metal layers, the projections of the sub-metal lines in the metal lines of the adjacent layers in the direction perpendicular to the surface of the substrate 10 only overlap at the ends, and the regions other than the ends of the sub-metal lines in the metal lines of the adjacent layers do not overlap in the projection in the direction perpendicular to the surface of the substrate 10. The via plug 131 is located between the ends of the sub-metal lines in the metal lines of the adjacent layers, and each of the sub-metal lines in the metal lines of the adjacent layers is connected in turn through the via plug 131 to realize the electrical connection between the metal lines of the adjacent layers.

[0080] Due to the staggered arrangement of the projections of the sub-metal lines in the metal lines of the adjacent layers in the direction perpendicular to the surface of the substrate 10, the overlapping area between the projections of the metal lines of the adjacent layers in the direction perpendicular to the surface of the substrate 10 is significantly reduced, and the overlapping area (i.e., the opposite area of the metal layer) between the projections of the metal layers of the adjacent layers in the direction perpendicular to the surface of the substrate 10 is significantly reduced, thereby significantly reducing the parasitic capacitance formed by the metal layers of the adjacent layers and the interlayer dielectric layer 11 therebetween, i.e., the parasitic capacitance of the semiconductor device is significantly reduced.

[0081] In one embodiment, each of the metal layers includes at least two metal lines, and preferably, the sub-metal lines in the adjacent two metal lines are staggered in each of the metal layers. The staggered arrangement of the sub-metal lines in the adjacent two metal lines refers to the staggered arrangement in the direction perpendicular to the extension direction of the metal lines, as shown in FIG. 1C, in which the first sub-metal line 121a in one metal line is staggered with the first sub-metal line 121a in the adjacent metal line. Figure 1 In each of the metal layers, the ends of the sub-metal lines in the adjacent two metal lines can overlap or not overlap in the direction perpendicular to the extension direction of the metal lines, and the regions other than the ends of the sub-metal lines in the adjacent two metal lines do not overlap in the direction perpendicular to the extension direction of the metal lines.

[0082] Due to the staggered arrangement between the sub-metal wires in the two adjacent metal wires in each of the metal layers in a direction perpendicular to the extending direction of the metal wires, the overlapping area of the two adjacent metal wires in each of the metal layers in a direction perpendicular to the extending direction of the metal wires (i.e. the facing area of the two adjacent metal wires) is significantly reduced, and the parasitic capacitance formed by the two adjacent metal wires in each of the metal layers and the interlayer dielectric layer 11 therebetween is also significantly reduced, thereby further significantly reducing the parasitic capacitance of the semiconductor device.

[0083] In an embodiment, the second metal layer 122 further comprises metal blocks 122b, the metal wires can extend in a first direction, the metal blocks 122b can extend in a second direction, the metal blocks 122b can be located at both ends of the metal wires, one end of the metal wire in the second metal layer 122 is connected with one of the metal blocks 122b, and the other end of the metal wire in the second metal layer 122 is not connected with the other metal block 122b. Wherein, the first direction is different from the second direction; in an embodiment, the first direction is perpendicular to the second direction.

[0084] Wherein, the two metal blocks 122b are oppositely arranged, and all the metal wires are sequentially and spacedly arranged between the two metal blocks 122b along the second direction.

[0085] In an embodiment, the second metal layer 122 comprises two oppositely staggered comb structures, each of the comb structures comprises a plurality of sequentially arranged comb teeth and a comb back located at the same end of each comb tooth, the comb backs of the two comb structures are parallel to each other, and the comb teeth are perpendicular to the comb backs, the comb teeth and the comb backs can be connected, the metal wires are the comb teeth, and the metal blocks 122b are the comb backs.

[0086] As Figures 1 to 3As shown, the metal interconnection structure includes a first metal layer and a second metal layer 122 located above the first metal layer; the first metal layer includes a plurality of first metal lines extending in a first direction Y, the first metal lines being spaced apart in a second direction X, each of the first metal lines including a plurality of first sub-metal lines 121a, the first sub-metal lines 121a in adjacent two of the first metal lines being staggered in the second direction X; the second metal layer 122 includes two oppositely staggered comb-shaped structures, each of the comb-shaped structures including a plurality of second metal lines extending in the first direction Y and a metal block 122b extending in the second direction X, each of the second metal lines including a plurality of second sub-metal lines 122a, the second sub-metal lines 122a closest to the metal block 122b in each of the comb-shaped structures being connected to the metal block 122b, the second metal lines in the two comb-shaped structures being staggered and interpenetrated, the second sub-metal lines 122a in adjacent two of the second metal lines being staggered in the second direction X; the first sub-metal lines 121a in the first metal lines and the second sub-metal lines 122a in the second metal lines being staggered in a direction perpendicular to a surface of the substrate 10, each of the first sub-metal lines 121a and each of the second sub-metal lines 122a being electrically connected in sequence by the via plug 131. The first direction Y is perpendicular to the second direction X.

[0087] Before forming the interlayer dielectric layer 11 and the metal interconnection structure, the method for manufacturing the semiconductor device further includes:

[0088] forming a shallow trench isolation structure 101 in the substrate 10, the shallow trench isolation structure 101 defining an active region;

[0089] forming a gate structure 14 on the active region; in an embodiment, the gate structure 14 can also extend from the active region to the shallow trench isolation structure 101;

[0090] forming a source region (not shown), a drain region (not shown) and a body contact region (not shown) in the active region.

[0091] each of the metal blocks 122b in the second metal layer 122 is electrically connected to the source region or the drain region, i.e., each of the comb-shaped structures is electrically connected to the source region or the drain region.

[0092] As Figure 1 and Figure 2bAs shown, the method for manufacturing the semiconductor device further comprises: forming a first connection layer 121b and a second connection layer 121c extending in the second direction X, the first connection layer 121b and the second connection layer 121c are both formed simultaneously with the first metal layer, the first connection layer 121b and the second connection layer 121c are both located in the same layer as the first metal layer, and the first connection layer 121b and the second connection layer 121c are respectively located at both ends of the first metal line, the first sub-metal line 121a closest to the first connection layer 121b is not connected with the first connection layer 121b, and the first sub-metal line 121a closest to the second connection layer 121c is not connected with the second connection layer 121c; the projection of the first connection layer 121b in the direction perpendicular to the surface of the substrate 10 is staggered with the projection of one of the metal blocks 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10, and the projection of the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 overlaps with the projection of the other metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10.

[0093] Preferably, the projection of the first connection layer 121b in the direction perpendicular to the surface of the substrate 10 is staggered with the projection of the metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10, and the projection of the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 is staggered with the projection of the metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10, so that the overlapping area between the projection of the first connection layer 121b in the direction perpendicular to the surface of the substrate 10 and the projection of the metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10 (i.e. the facing area between the first connection layer 121b and the metal block 122b in the second metal layer 122) and the overlapping area between the projection of the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 and the projection of the metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10 (i.e. the facing area between the second connection layer 121c and the metal block 122b in the second metal layer 122) are significantly reduced, thereby significantly reducing the parasitic capacitance formed by the first connection layer 121b, the metal block 122b and the interlayer dielectric layer 11 therebetween and the parasitic capacitance formed by the second connection layer 121c, the metal block 122b and the interlayer dielectric layer 11 therebetween, and further significantly reducing the parasitic capacitance of the semiconductor device. In other embodiments, the projection of the first connection layer 121b in the direction perpendicular to the surface of the substrate 10 can overlap with the projection of the metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10, and the projection of the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 can overlap with the projection of the metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10.

[0094] In one embodiment, the method for manufacturing the semiconductor device further comprises forming dummy gates 15 on both sides of the gate structure 14. The dummy gates 15 can be formed simultaneously with the gate structure 14. The dummy gates 15 do not need to be electrically connected to the metal layer, i.e. the dummy gates 15 are not electrically led out. The dummy gates 15 are used for optical proximity correction during exposure, so that the pattern of the formed gate structure 14 is not distorted; and in the process of planarizing the device surface using a chemical mechanical polishing process, the dummy gates 15 are also used to reduce the impact of the process itself on the gate structure 14.

[0095] The metal interconnection structure further comprises a contact plug 132, and the first metal layer is electrically connected to the source region or the drain region through the contact plug 132.

[0096] After the formation of the bottommost insulating layer and before the formation of the first insulating layer, a contact hole can be formed by etching the bottommost insulating layer, and the contact plug 132 can be formed by filling the contact hole with a metal material.

[0097] In one embodiment, the method for manufacturing the semiconductor device further comprises forming dummy gates 15 on both sides of the gate structure 14. The dummy gates 15 can be formed simultaneously with the gate structure 14. The dummy gates 15 do not need to be electrically connected to the metal layer, i.e. the dummy gates 15 are not electrically led out. The dummy gates 15 are used for optical proximity correction during exposure, so that the pattern of the formed gate structure 14 is not distorted; and in the process of planarizing the device surface using a chemical mechanical polishing process, the dummy gates 15 are also used to reduce the impact of the process itself on the gate structure 14. Figure 1As shown in the structure, the gate structure 14 is an H-shaped structure, the “—” part of the H-shaped structure extends in the first direction Y, the projection of the “—” part of the H-shaped structure in the direction perpendicular to the surface of the substrate 10 is located between the projections of adjacent first metal lines in the direction perpendicular to the surface of the substrate 10 or between the projections of adjacent second metal lines in the direction perpendicular to the surface of the substrate 10, the “|” part of the H-shaped structure extends in the second direction X, one end of the plurality of “—” parts of the H-shaped structure extends from the active region to the shallow trench isolation structure 101, both ends of one of the “|” parts of the H-shaped structure extend from the active region to the shallow trench isolation structure 101, and the other “|” part of the H-shaped structure is located on the shallow trench isolation structure 101; the source region and the drain region are respectively formed in the active regions on both sides of the “—” part of the H-shaped structure, and the body contact region is formed in the active region on the side of the “|” part of the H-shaped structure away from the “—” part of the H-shaped structure; the first connection layer 121b and one of the metal blocks 122b are located above the shallow trench isolation structure 101, the second connection layer 121c is located above the body contact region, and the other metal block 122b extends from above the body contact region to above the shallow trench isolation structure 101; the first sub-metal line 121a in the first metal line is electrically connected to the source region and the drain region through the contact plug 132, the first connection layer 121b is electrically connected to the gate structure 14 (the “|” part of the H-shaped structure) extending to the shallow trench isolation structure 101 through the contact plug 132, and the second connection layer 121c is electrically connected to the body contact region through the contact plug 132. In other embodiments, the gate structure 14 can be a T-shaped structure.

[0098] Preferably, each sub-metal line in the first metal layer is electrically connected to the source region or the drain region through at least two contact plugs 132, so as to improve the effectiveness of the connection, for example, if one of the contact plugs 132 is disconnected or fails, the other contact plugs 132 can still keep the circuit connected, avoiding the disconnection of the entire circuit.

[0099] Preferably, the sub-metal lines in the metal lines of adjacent layers are electrically connected through at least two via plugs 131, so as to improve the effectiveness of the connection, for example, if a first sub-metal line in the first metal layer and a second sub-metal line in the second metal layer 122 are electrically connected through at least two via plugs 131, if one of the via plugs 131 is disconnected or fails, the other via plugs 131 can still keep the circuit connected, avoiding the disconnection of the entire circuit.

[0100] In addition, the manufacturing method of the semiconductor device further includes forming conductive interconnection structures (not shown) electrically connected with the metal interconnection structures, the first connection layer 121b and the second connection layer 121c respectively, the conductive interconnection structures being used for electrically leading out the metal interconnection structures, the first connection layer 121b and the second connection layer 121c respectively, and further corresponding to electrically leading out the source region, the drain region, the gate structure 14 and the body contact region respectively.

[0101] In summary, the manufacturing method of the semiconductor device provided by the present application includes: providing a substrate; forming an interlayer dielectric layer and a metal interconnection structure, the interlayer dielectric layer being formed on the substrate, and the metal interconnection structure being formed in the interlayer dielectric layer; the metal interconnection structure including two layers of metal layers and a via plug, each of the metal layers including at least one metal line, each of the metal lines including a plurality of sub-metal lines, the sub-metal lines in the metal lines of adjacent layers being staggered, and the sub-metal lines in the metal lines of adjacent layers being electrically connected through the via plug. The manufacturing method of the semiconductor device provided by the present application can significantly reduce the parasitic capacitance of the semiconductor device.

[0102] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any modification or change made by a person of ordinary skill in the art according to the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; a shallow trench isolation structure formed in the substrate, the shallow trench isolation structure defining an active region; a gate structure formed on the active region; a source region, a drain region and a body contact region formed in the active region; an interlayer dielectric layer formed on the substrate; a metal interconnection structure formed in the interlayer dielectric layer, the metal interconnection structure comprising two metal layers and via plugs, each metal layer comprising at least one metal line, each metal line comprising a plurality of sub-metal lines, the sub-metal lines in the metal lines of adjacent layers being staggered, the sub-metal lines in the metal lines of adjacent layers being electrically connected by the via plugs; wherein the metal interconnection structure comprises a first metal layer and a second metal layer, the second metal layer further comprising metal blocks, the semiconductor device further comprising a connection layer at the same layer as the first metal layer, each metal block being connected to the source region or the drain region, each connection layer being connected to the gate structure or the body contact region, the projection of the connection layer in the direction perpendicular to the substrate surface being staggered with the projection of the metal block in the direction perpendicular to the substrate surface.

2. The semiconductor device of claim 1, wherein, Each metal layer comprises at least two metal lines; in each metal layer, the sub-metal lines in adjacent two metal lines are staggered.

3. The semiconductor device of claim 1, wherein, The semiconductor device further comprises: The metal interconnection structure further comprises a contact plug, the bottommost metal layer being electrically connected to the source region, the drain region or the body contact region through the contact plug.

4. The semiconductor device of claim 1, wherein, The sub-metal lines in the metal lines of adjacent layers are electrically connected by at least two via plugs.

5. The semiconductor device of claim 3, wherein, The semiconductor device further comprises: a dummy gate, the dummy gate being located on both sides of the gate structure.

6. The semiconductor device of claim 3, wherein, The metal lines extend in a first direction, the metal blocks extend in a second direction, and the metal blocks are located at both ends of the metal lines.

7. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises: providing a substrate; forming a shallow trench isolation structure in the substrate, the shallow trench isolation structure defining an active region; forming a gate structure on the active region; forming a source region, a drain region and a body contact region in the active region; forming an interlayer dielectric layer and a metal interconnection structure, the interlayer dielectric layer being formed on the substrate, the metal interconnection structure being formed in the interlayer dielectric layer; the metal interconnection structure comprising two metal layers and via plugs, each metal layer comprising at least one metal line, each metal line comprising a plurality of sub-metal lines, the sub-metal lines in the metal lines of adjacent layers being staggered, the sub-metal lines in the metal lines of adjacent layers being electrically connected by the via plugs; The metal interconnection structure comprises a first metal layer and a second metal layer, wherein the second metal layer further comprises metal blocks, the semiconductor device further comprises connecting layers in the same layer as the first metal layer, each of the metal blocks is connected to the source region or the drain region, each of the connecting layers is connected to the gate structure or the body contact region, and a projection of the connecting layer in a direction perpendicular to the substrate surface is staggered with a projection of the metal block in the direction perpendicular to the substrate surface.

8. The method of manufacturing a semiconductor device according to Claim 7, wherein Each of the metal layers comprises at least two metal lines; in each of the metal layers, the sub-metal lines in two adjacent metal lines are arranged staggeredly.

9. The method according to claim 7, wherein The metal interconnection structure further comprises a contact plug, and the bottommost metal layer is electrically connected to the source region, the drain region or the body contact region through the contact plug.

10. The method of manufacturing a semiconductor device according to Claim 7, wherein The sub-metal lines in the metal lines of adjacent layers are electrically connected through at least two via plugs.

11. The method of manufacturing a semiconductor device according to Claim 9, wherein The metal lines extend in a first direction, and the metal blocks extend in a second direction, and the metal blocks are located at two ends of the metal lines.

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