Semiconductor LDD extension width test structure and its formation method and calculation method

Abstract

A semiconductor LDD extension width test structure and a formation method and calculation method thereof, comprising: determining the width of the test structure, the width of the test structure being determined based on the width of the first well and / or the width of the first LDD; testing the first well to obtain the measured resistance of the first well; testing the first LDD to obtain the measured resistance of the first LDD; testing the semiconductor channel to obtain the measured resistance of the semiconductor channel; and obtaining the actual width of the semiconductor channel based on the measured resistance of the first well, the measured resistance of the first LDD, the measured resistance of the semiconductor channel, and the width of the test structure. The embodiment of the present invention is conducive to obtaining the semiconductor LDD extension width.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor LDD extension width test structure and a forming method and a calculation method thereof. Background Art

[0002] In semiconductor technology, in order to suppress the generation of leakage current between the source and drain caused by the reduction of the conductive channel length, a lightly doped drain LDD (Lightly Doped Drain: LDD) injection process is usually introduced, that is, before the heavy doping of the source and drain, shallow junction injection is performed with ions with a larger molecular weight. In the LDD process, the injection energy needs to be low, the junction depth is shallow, and the block resistance after injection should be as small as possible. While the industry's process personnel are developing how to form a shallow junction LDD doping layer, they also need to obtain the extension width of the LDD doping layer extending under the gate layer, that is, to obtain the LDD extension width, in order to judge the performance of the semiconductor device.

[0003] However, the existing technology has the problem of being unable to obtain the LDD expansion width. Specifically, since the impurity concentration distribution of ion implantation is usually Gaussian, there is doping within a certain range in the substrate, resulting in the expansion width of the doped ions often having a certain range, and it is difficult to determine an accurate value through theoretical calculation.

[0004] Therefore, how to provide a technical solution to obtain the LDD expansion width has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] The technical problem solved by the present invention is to obtain the LDD extension width by providing a semiconductor LDD extension width test structure and a forming method and a calculation method thereof.

[0006] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor LDD extended width test structure, comprising: providing a substrate, the substrate comprising a first region, a second region adjacent to the first region, and a third region adjacent to the second region; performing doping treatment on the substrate to form a first well located in the first region, a second well in the second region, and a third well in the third region; doping to form a first LDD in the second well, and doping to form a pair of second LDDs in the third well in a direction parallel to the carrier flow, wherein there is a gap between each pair of second LDDs, and a side of each pair of second LDDs away from another second LDD is flush with an edge of the third well; forming a gate layer, the gate layer covering the pair of second LDDs and the third well between them.

[0007] Optionally, the forming method further includes:

[0008] forming a well region test terminal coupled to the first well in the first region;

[0009] forming an LDD test terminal coupled to the first LDD in the second region;

[0010] forming a comprehensive test terminal in the third region, the comprehensive test terminal being coupled to the second LDD and to a third well located between the paired second LDDs;

[0011] Wherein, the well region test terminal, the LDD test terminal and the integrated test terminal are formed in the same process step.

[0012] Optionally, before forming the well region test terminal, the LDD test terminal and the integrated test terminal, and after forming the gate layer, the forming method further includes:

[0013] forming a dielectric layer covering the substrate;

[0014] Etching the dielectric layer to form a through-well region via located on the first well, a through-LDD via located on the first LDD, and a through-comprehensive via located on the second LDD in the dielectric layer;

[0015] The well region via hole, the LDD via hole and the integrated via hole are filled with a connection layer material to form a connection plug.

[0016] Optionally, the first well includes a P-type well or an N-type well, the second well includes a P-type well or an N-type well, and the third well includes a P-type well or an N-type well;

[0017] The first LDD includes a P-type LDD or an N-type LDD, and the second LDD includes a P-type LDD or an N-type LDD;

[0018] The material of the gate layer includes: polysilicon or amorphous silicon;

[0019] The material of the well region test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide;

[0020] The material of the LDD test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide;

[0021] The material of the comprehensive test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide;

[0022] The connection layer material includes: one or more combinations of copper, aluminum, tungsten and titanium.

[0023] Correspondingly, an embodiment of the present invention also provides a semiconductor LDD extended width test structure, comprising: a substrate, the substrate comprising a first region, a second region adjacent to the first region, and a third region adjacent to the second region; a first well, located in the first region; a second well, located in the second region; a third well, located in the third region; a first LDD, located in the second well; paired second LDDs, located in the third well, with a gap between each pair of second LDDs, and a side of each pair of second LDDs away from the other second LDD is flush with an edge of the third well; a gate layer, located in the third region, the gate layer covering the paired second LDDs and the third well between them.

[0024] Optionally, the test structure further includes: a well region via, an LDD via, and a comprehensive via, wherein the comprehensive via includes a first comprehensive via and a second comprehensive via, wherein the second comprehensive via runs through the gate layer, and the second comprehensive via spans the second LDD and the third well;

[0025] Well test terminal, LDD test terminal, comprehensive test terminal;

[0026] A connection layer is located in the well region via, the LDD via and the integrated via;

[0027] The well region test terminal is coupled to the first well through the connection layer in the well region via hole to form a well resistance test structure for testing the first well resistance;

[0028] The LDD test terminal is coupled to the first LDD via the connection layer in the LDD via hole to form an LDD resistance test structure for testing the first LDD resistance;

[0029] The integrated test terminal is coupled to the second LDDs on both sides of the third well through the connection layer in the first integrated via hole, and is also coupled to the second LDD and the third well through the connection layer in the second integrated via hole, forming an integrated resistance test structure for testing semiconductor channel resistance;

[0030] The first LDD resistance is the resistance after the first LDD contacts the second well;

[0031] The semiconductor channel resistance is the resistance of the second LDDs on both sides of the third well and the resistance of the third well between the second LDDs in parallel;

[0032] The connection layer is insulated and connected to the gate layer.

[0033] Optionally, the first well includes a P-type well or an N-type well, the second well includes a P-type well or an N-type well, and the third well includes a P-type well or an N-type well;

[0034] The first LDD includes a P-type LDD or an N-type LDD, and the second LDD includes a P-type LDD or an N-type LDD;

[0035] The material of the gate layer includes: polysilicon or amorphous silicon;

[0036] The material of the well region test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide;

[0037] The material of the LDD test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide;

[0038] The material of the comprehensive test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide;

[0039] The connection layer material includes: one or more combinations of copper, aluminum, tungsten and titanium.

[0040] Optionally, the number of the well region vias is greater than or equal to 2, and the number of the well region test terminals is at least 2, wherein one well region test terminal is connected to one end of the first well via a connection layer in the well region via, and another well region test terminal is connected to the other end of the first well via a connection layer in the well region via;

[0041] The number of the LDD vias is greater than or equal to 2, and the number of the LDD test terminals is at least 2, wherein one LDD test terminal is connected to one end of the first LDD via the connection layer in the LDD via, and the other LDD test terminal is connected to the other end of the first LDD via the connection layer in the LDD via;

[0042] The number of the integrated vias is greater than or equal to 8, and the number of the integrated test terminals is at least 2, wherein one integrated test terminal is respectively connected to the second LDD at one end of the third well through the connection layers in at least 2 integrated vias, and is also simultaneously coupled to the second LDD and the third well at one end of the third well through the connection layers in at least 2 integrated vias, and another integrated test terminal is respectively connected to the second LDD at the other end of the third well through the connection layers in at least 2 integrated vias, and is also simultaneously coupled to the second LDD and the third well at the other end of the third well through the connection layers in at least 2 integrated vias.

[0043] Optionally, the well region via, LDD via, and integrated via are of the same shape and size.

[0044] Optionally, along a direction parallel to the carrier flow direction, the theoretical widths of the first well, the second well, the third well, and the first LDD are equal, and the theoretical width of the gate layer is smaller than the theoretical width of the first well;

[0045] The sum of the theoretical widths of the second LDD and the third well located between the second LDD is equal to the theoretical width of the first well;

[0046] In a direction perpendicular to the carrier flow direction, the theoretical lengths of the first well, the second well, the third well, the first LDD, and the second LDD are equal;

[0047] The well region test terminal, the LDD test terminal and the integrated test terminal have the same shape and area.

[0048] Correspondingly, an embodiment of the present invention also provides a method for calculating the expansion width of a semiconductor LDD, comprising: being applied to a test structure as described in any of the foregoing, comprising: determining the width of the test structure, wherein the width of the test structure is determined based on the width of the first well and / or the width of the first LDD; testing the first well to obtain the measured resistance of the first well; testing the first LDD to obtain the measured resistance of the first LDD; testing the semiconductor channel to obtain the measured resistance of the semiconductor channel; and deriving the actual width of the semiconductor channel based on the measured resistance of the first well, the measured resistance of the first LDD, the measured resistance of the semiconductor channel, and the width of the test structure.

[0049] Optionally, determining the width of the test structure includes one or more of the following:

[0050] Determine the measured width W1 of the first well in a direction parallel to the carrier flow direction;

[0051] Determine the measured width W2 of the first LDD in a direction parallel to the carrier flow direction;

[0052] The measured width W1 of the first well and the measured width W2 of the first LDD are determined parallel to the carrier flow direction, and then the average value of W1 and W2 is determined as W ;

[0053] Determine a length of a test structure, wherein the length of the test structure is determined based on a length of the first well and / or a length of the first LDD, wherein determining the length of the test structure comprises one or more of the following:

[0054] Determine the measured length L1 of the first well along a direction parallel to the substrate surface and perpendicular to the carrier flow direction;

[0055] Determine the measured length L2 of the first LDD along a direction parallel to the substrate surface and perpendicular to the carrier flow direction;

[0056] The measured length L1 of the first well and the measured length L2 of the first LDD are determined along a direction parallel to the substrate surface and perpendicular to the carrier flow direction, and then the average value of L1 and L2 is determined as L0;

[0057] Determine the thickness of the test structure, the thickness of the test structure including the thickness of the first well and the thickness of the first LDD; determine the measured thickness D1 of the first well along a direction perpendicular to the surface of the substrate; determine the measured thickness D2 of the first LDD along a direction perpendicular to the surface of the substrate;

[0058] Determine the measured width of the gate layer parallel to the direction of carrier flow L .

[0059] Optionally, use the following formula:

[0060] , according to the measured resistance of the first well is R 1. The measured resistance of the first LDD is R 2 and the measured resistance of the semiconductor channel is R 3. Obtain the actual width of the semiconductor channel W C .

[0061] Optionally, use the following formula:

[0062] , according to the width of the gate layer L and the actual width of the semiconductor channel W C , the semiconductor LDD expansion width is obtained x .

[0063] Optionally, the measured resistance of the first well, the measured resistance of the first LDD, and the measured resistance of the semiconductor channel are tested by a resistance tester.

[0064] Optionally, the measured thickness D1 of the first well, the measured thickness D2 of the first LDD, the measured width W1 of the first well, the measured width W2 of the first LDD, the measured length L1 of the first well, the measured length L2 of the first LDD, and the measured width of the gate layer are measured by an optical interferometer. L .

[0065] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0066] An embodiment of the present invention provides a semiconductor LDD extended width test structure, comprising: forming the first well, the second well adjacent to the first well, and the third well adjacent to the second well on the substrate; forming a first LDD in the second well, and forming a paired second LDD in the third well.

[0067] The width of the test structure is determined, the first well is tested to obtain the measured resistance of the first well, the first LDD is tested to obtain the measured resistance of the first LDD, and the semiconductor channel is tested to obtain the measured resistance of the semiconductor channel. Compared with the prior art in which it is difficult to obtain the actual LDD expansion width through theoretical calculation, the solution of the embodiment of the present invention is adopted to obtain the actual width of the semiconductor channel according to the measured resistance of the first well, the measured resistance of the first LDD, the measured resistance of the semiconductor channel and the width of the test structure, and then the actual LDD expansion width can be obtained according to the obtained actual width of the semiconductor channel, thereby effectively improving the accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0069] Figure 1 It is a partial schematic diagram of a semiconductor structure;

[0070] Figures 2 to 9 It is a schematic diagram of the structures corresponding to each step in a method for forming a semiconductor LDD extension width test structure according to an embodiment of the present invention;

[0071] Fig.10 It is a flowchart of a method for calculating a semiconductor LDD extension width according to an embodiment of the present invention. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0073] As can be seen from the background technology, there is a problem of low accuracy of the obtained LDD extension width, the specific reasons are as follows:

[0074] refer to Figure 1, is a partial schematic diagram of a semiconductor structure, the semiconductor structure comprising: a substrate 10; a source 11, a drain 12, and a gate layer 13 located on the substrate 10; an LDD lightly doped source 14 in contact with the source 11, and an LDD lightly doped drain 15 in contact with the drain 12; when the LDD lightly doped source 14 is doped, a part of the region 16 of the LDD lightly doped source 14 will diffuse to the bottom of the gate layer 13, and when the LDD lightly doped drain 15 is doped, a part of the region 17 of the LDD lightly doped drain 15 will also diffuse to the bottom of the gate layer 13, and the region 16 and the region 18 between the regions are semiconductor channels. Along the direction parallel to the carrier movement direction F, the width of the region 16 or the region 17 is called the LDD extension width, that is, the width of the LDD lightly doped source 14 overlapping with the gate layer 13, or the width of the LDD lightly doped drain 15 overlapping with the gate layer 13. It should be noted that the carrier movement direction F is the direction from the LDD lightly doped source 14 vertically to the LDD lightly doped drain 15 .

[0075] The above test technology cannot obtain the LDD expansion width for the following reasons:

[0076] First, because the LDD lightly doped source 14 and the LDD lightly doped drain 15 are formed by a light doping process, the color distinction between region 16 and region 17 and region 18 is not obvious. During the semiconductor manufacturing process, along the direction F parallel to the carrier movement direction, the existing testing equipment cannot obtain the LDD expansion width, that is, it cannot obtain the width of the semiconductor channel in region 16, region 17, and also cannot obtain the width of the semiconductor channel in region 18.

[0077] Second, with the continuous advancement of complementary metal oxide semiconductor transistor technology, the integration level is getting higher and higher, and the width of the LDD lightly doped source 14, the LDD lightly doped drain 15 and the semiconductor channel is also constantly decreasing. In the semiconductor manufacturing process, along the direction F parallel to the carrier movement direction, the existing testing equipment cannot obtain the LDD expansion width, that is, it cannot obtain the width of the semiconductor channel in area 16, area 17, and also cannot obtain the width of the semiconductor channel in area 18.

[0078] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor LDD extension width test structure, the forming method comprising: providing a substrate, the substrate comprising a first region, a second region adjacent to the first region, and a third region adjacent to the second region; performing doping treatment on the substrate to form a first well located in the first region, a second well in the second region, and a third well in the third region; doping to form a first LDD in the second well, and doping to form a pair of second LDDs in the third well in parallel to the carrier flow direction, wherein each pair of second LDDs has a gap between them, and the side of each pair of second LDDs away from the other second LDD is flush with the edge of the third well; forming a gate layer, the gate layer covering the pair of second LDDs and the third well between them. The test structure formed by the forming method of the embodiment of the present invention can obtain the LDD extension width.

[0079] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0080] Figures 2 to 9 It is a schematic diagram of the structures corresponding to the steps in the method for forming a semiconductor LDD extension width test structure according to an embodiment of the present invention.

[0081] It should be noted that Figure 3 include Figure 3 Part a of Figure 3 Part b of Figure 3 Part c of Figure 3 The d part of Figure 3 Part a in the figure is a top view of the base. Figure 3 Part b in Figure 3 The cross-sectional view along A1A2 in part a of FIG. Figure 3 The c part of Figure 3 The cross-sectional view along A3A4 in part a of FIG. Figure 3 The d part in Figure 3 A cross-sectional view along A5A6 in part a of FIG. Figure 4 include Figure 4 Part a of Figure 4 Part b of Figure 4 Part c of Figure 4 The d part of Figure 4 Part a in the figure is a top view of the base. Figure 4 Part b in Figure 4 The cross-sectional view along B1B2 in part a of FIG. Figure 4 The c part of Figure 4 The cross-sectional view along B3B4 in part a of FIG. Figure 4 The d part in Figure 4 A cross-sectional view along B5B6 in part a; Figure 5 include Figure 5 Part a of Figure 5 Part b of Figure 5 Part c of Figure 5 The d part of Figure 5 Part a in the figure is a top view of the base. Figure 5 Part b in Figure 5 The cross-sectional view along C1C2 in part a of FIG. Figure 5 The c part of Figure 5 The cross-sectional view along C3C4 in part a of FIG. Figure 5 The d part in Figure 5 The cross-sectional view along C5C6 in part a; Figure 6 include Figure 6 Part a of Figure 6 Part b of Figure 6 Part c of Figure 6 The d part of Figure 6 Part a in the figure is a top view of the base. Figure 6 Part b in Figure 6 The cross-sectional view along D1D2 in part a of FIG. Figure 6 The c part of Figure 6 The cross-sectional view along D3D4 in part a of FIG. Figure 6 The d part in Figure 6 A cross-sectional view along D5D6 in part a; Figure 7 include Figure 7 Part a of Figure 7 Part b of Figure 7 Part c of Figure 7 The d part of Figure 7 Part a in the figure is a top view of the base. Figure 7 Part b in Figure 7 The cross-sectional view along E1E2 in part a of FIG. Figure 7 The c part of Figure 7 The cross-sectional view along E3E4 in part a of FIG. Figure 7 The d part in Figure 7 The cross-section along E5E6 in part a; Figure 8 include Figure 8 Part a of Figure 8 Part b of Figure 8 Part c of Figure 8 The d part of Figure 8 Part a in the figure is a top view of the substrate. Figure 8Part b in Figure 8 The cross-sectional view along F1F2 in part a of FIG. Figure 8 The c part of Figure 8 The cross-sectional view along F3F4 in part a of FIG. Figure 8 The d part in Figure 8 Cross-sectional view along F5F6 in part a.

[0082] refer to Figure 2 , providing a substrate 100.

[0083] The substrate 100 is used to provide a process platform for forming a semiconductor LDD extended width test structure.

[0084] In this embodiment, the substrate 100 is a silicon substrate 100, and the material of the substrate 100 is single crystal silicon. In other embodiments, the material of the substrate 100 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium, and the substrate 100 can also be a silicon substrate 100 on an insulator or a germanium substrate 100 on an insulator. Other types of substrates 100. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 100 can also be formed on the surface of the substrate 100 to improve the quality of pattern transfer.

[0085] It should be noted that Figure 2 This is a schematic diagram, and does not depict the entire structure of the substrate 100. For example, in the process of forming the substrate 100, it may also include: forming other appropriate regions, such as an insulating layer, for example: a well region formed in the substrate 100, the well region being located above the insulating layer.

[0086] Continue to refer Figure 2 The substrate 100 includes a first region 101 , a second region 102 adjacent to the first region 101 , and a third region 103 adjacent to the second region.

[0087] The first area 101 is used to reserve a position space for forming a first well; the second area is used to reserve a position space for forming a second well; and the third area is used to reserve a position space for forming a third well.

[0088] refer to Figure 3 , the substrate 100 is doped to form a first well 200 located in the first area 101 , a second well 201 in the second area 102 , and a third well 202 in the third area 103 .

[0089] The first well 200 is used to test the resistance of the first well 200; the second well 201 is used to provide a position space for the subsequent formation of the first LDD; and the third well 202 is used to provide a position space for the subsequent formation of the semiconductor channel and the second LDD.

[0090] The first well 200 includes a P-type well or an N-type well, the second well 201 includes a P-type well or an N-type well, and the third well 202 includes a P-type well or an N-type well; in this embodiment, the first well 200, the second well 201 and the third well 202 are all P-type wells.

[0091] In this embodiment, the specific process steps for forming the first well 200, the second well 201 and the third well 202 include:

[0092] In the same process step, the first well 200 , the second well 201 and the third well 202 are formed.

[0093] By using photoresist and / or hard mask (not shown), a first well region is defined in the first region 101 , a second well region is defined in the second region 102 , and a third well region is defined in the third region 103 on the substrate 100 .

[0094] An ion implantation process, such as implanting boron ions, is used to perform a doping process and an annealing process on the defined first well region, the second well region, and the third well region, so as to form a first well 200 in the first well region, a second well 201 in the second well region, and a third well 202 in the third well region. In other embodiments, the doping process may be an ion extension process.

[0095] It should be noted that the types of doping ions defined in the first well region, the second well region and the third well region depend on the conductivity types required by the first well 200 , the second well 201 and the third well 202 , which will not be elaborated in this application.

[0096] The doping process includes light doping and heavy doping. In this embodiment, heavy doping is used to form the first well 200, the second well 201 and the third well 202.

[0097] refer to Figure 4 , a first LDD 203 is doped in the second well 201 , and a pair of second LDDs 204 are doped in the third well 202 in a direction parallel to the carrier flow direction.

[0098] The first LDD 203 is used to test the resistance of the first LDD 203 ; the second LDD 204 is used to form a lightly doped layer of a semiconductor channel.

[0099] In this embodiment, a pair of second LDDs 204 are formed by doping in the third well 202 , including a second LDD 2040 and a second LDD 2041 .

[0100] In this embodiment, the specific process steps for forming the first LDD 203 and the second LDD 204 include:

[0101] In the same process step, the first LDD 203 and the second LDD 204 are formed.

[0102] The first LDD 203 includes a P-type LDD or an N-type LDD, and the second LDD 204 includes a P-type LDD or an N-type LDD. In this embodiment, both the first LDD 203 and the second LDD 204 are N-type.

[0103] A first LDD region is defined on the second well 201 , and a second LDD region is defined on the third well 202 by using a photoresist and / or a hard mask (not shown).

[0104] The first LDD region and the second LDD region are doped and annealed by an ion implantation process, such as implanting phosphorus ions, to form a first LDD 203 in the first LDD region and a second LDD 204 in the second LDD region. In other embodiments, the doping process may be an ion extension process.

[0105] It should be noted that the types of doping ions defined in the first LDD region and the second LDD region depend on the conductivity types required by the first LDD 203 and the second LDD 204 , which will not be elaborated in this application.

[0106] The doping process includes light doping and heavy doping. In this embodiment, light doping is used to form the first LDD 203 and the second LDD 204.

[0107] Continue to refer Figure 4 There is a gap between each pair of second LDDs 204, and one side of each pair of second LDDs 204 away from another second LDD 204 is flush with the edge of the third well 202, so that the expansion widths of the second LDDs 204 are the same or close to each other, so as to improve the accuracy of obtaining the LDD expansion width.

[0108] In this embodiment, the second LDD204 is a pair, namely a second LDD2040 and a second LDD2041; a side 2042 of the second LDD2040 away from the second LDD2041 is flush with the edge 2020 of the third well 202, and a side 2043 of the second LDD2041 away from the second LDD2040 is flush with the edge 2021 of the third well 202.

[0109] refer to Figure 5 , forming a gate layer 205, wherein the gate layer 205 covers the pair of second LDDs 204 and the third well 202 therebetween.

[0110] The material of the gate layer 205 includes: polysilicon or amorphous silicon. In this embodiment, the material of the gate layer 205 is polysilicon.

[0111] In this embodiment, the main process steps for forming the gate layer 205 include:

[0112] A material layer of the gate layer 205 is formed on the substrate 100 by, for example, a chemical vapor deposition process;

[0113] The gate layer 205 is formed by exposure, development and etching processes.

[0114] Continue to refer Figure 5 The gate layer 205 covers the paired second LDDs 204 and the third well 202 therebetween. In this embodiment, that is, the gate layer 205 covers the second LDDs 2040 and the second LDDs 2041 and the third well 202 therebetween.

[0115] refer to Figure 6 Before forming the well area test terminal, the LDD test terminal and the integrated test terminal, and after forming the gate layer 205, the formation method also includes: forming a dielectric layer 206 covering the substrate 100 to provide a process basis for the subsequent formation of the well area via, the LDD via and the integrated via.

[0116] The material of the dielectric layer 206 includes: one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the dielectric layer 206 is silicon nitride.

[0117] In this embodiment, the main process steps for forming the dielectric layer 206 covering the substrate 100 include:

[0118] A dielectric layer 206 is formed on the substrate 100 by, for example, a chemical vapor deposition process.

[0119] Continue to refer Figure 6 , the dielectric layer 206 is etched, and a through well region via 207 located on the first well 200, a through LDD via 208 located on the first LDD 203, and a through integrated via 209 located on the second LDD 204 are formed in the dielectric layer 206, providing a process basis for the subsequent formation of the connection layer 210. The integrated via 209 includes a first integrated via 2090 and a second integrated via 2091.

[0120] In this embodiment, the main process steps for forming the well region via 207, the LDD via 208 and the integrated via 209 include:

[0121] A hard mask (not shown) is formed on the substrate 100 , and the hard mask includes a first opening (not shown), a second opening (not shown), and a third opening (not shown).

[0122] The dielectric layer 206 is subjected to an exposure, development and etching process to form a through well region via 207 located on the first well 200 in the dielectric layer 206 at the first opening, a through LDD via 208 located on the first LDD 203 at the second opening, and a through integrated via 209 located on the second LDD 204 at the third opening. The integrated via 209 is also located on the third well 202 between the paired second LDDs 204.

[0123] refer to Figure 7 , combined with Figure 6 , the connection layer 210 material is filled in the well area via 207, the LDD via 208 and the integrated via 209 to form a connection plug for connecting the well area test terminal to the first well 200, connecting the LDD test terminal to the first LDD 203, connecting the integrated test terminal to the second LDD 204, and connecting to the third well 202 located between the paired second LDDs 204.

[0124] The material of the connection layer 210 includes: one or more combinations of copper, aluminum, tungsten, and titanium. In this embodiment, the material of the connection layer 210 is tungsten.

[0125] In this embodiment, the main process steps of filling the connection layer 210 material in the well region via 207, the LDD via 208 and the integrated via 209 include:

[0126] The connection layer 210 material is formed on the substrate 100 by using a physical vapor deposition process.

[0127] Through exposure, development and etching processes, the connection layer 210 material is filled in the well region via hole 207, the LDD via hole 208 and the integrated via hole 209 to form a connection plug.

[0128] Continue to refer Figure 6 Before forming the connection layer 210, after forming the well region via 207, the LDD via 208 and the integrated via 209, an isolation layer 500 is formed on the sidewall of the second integrated via 2091, that is, the isolation layer 500 covers the sidewall of the dielectric layer 206 and the sidewall of the gate layer 205 in the second integrated via 2091. The isolation layer 500 is used to insulate and connect the connection layer formed subsequently with the gate layer 205, so as to prevent the gate layer 205 from affecting the accuracy of obtaining the LDD expansion width.

[0129] refer to Figure 8, the formation method also includes: forming a well region test terminal 211 coupled to the first well 200 in the first region 101; forming an LDD test terminal 212 coupled to the first LDD203 in the second region 102; forming an integrated test terminal 213 in the third region 103, the integrated test terminal 213 is coupled to the second LDD204, and is coupled to the third well 202 located between the paired second LDD204.

[0130] The material of the well region test terminal 211 includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide; the material of the LDD test terminal 212 includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide; the material of the integrated test terminal 213 includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide; in this embodiment, the material of the well region test terminal 211 is indium tin oxide, the material of the LDD test terminal 212 is indium tin oxide, and the material of the integrated test terminal 213 is indium tin oxide, and the indium tin oxide is a transparent material.

[0131] For the convenience of description, in this embodiment, the well test terminal 211, the LDD test terminal 212 and the integrated test terminal 213 are all referred to as test terminals.

[0132] It should be noted that the test terminal described in this application is made of transparent material. Figure 8 In part a of FIG. 1 , the relevant film structure visible below the test terminal is shown.

[0133] In this embodiment, the well region test terminal 211, the LDD test terminal 212 and the integrated test terminal 213 are formed in the same process step, and the main process steps include:

[0134] Using a physical vapor deposition process to form a material for the test terminal on the substrate 100;

[0135] Through exposure, development and etching processes, a well region test terminal 211 coupled to the first well 200 is formed in the first region 101; an LDD test terminal 212 coupled to the first LDD203 is formed in the second region; and a comprehensive test terminal 213 is formed in the third region, and the comprehensive test terminal 213 is coupled to the second LDD204 and to the third well 202 located between the paired second LDD204.

[0136] The well region test terminal 211 is coupled to the first well 200 through the connection layer 210 in the well region via 207 .

[0137] The LDD test terminal 212 is coupled to the first LDD 203 through the connection layer 210 in the LDD via 208 .

[0138] The integrated test terminal 213 is coupled to the second LDD 204 through the connection layer 210 in the integrated via 209 , and is coupled to the third well 202 located between the paired second LDDs 204 . In this embodiment, that is, the integrated test terminal 213 is also coupled to the third well 202 between the second LDD 2040 and the second LDD 2041 .

[0139] In order to solve the technical problem, the present invention also provides a semiconductor LDD extension width test structure accordingly. Figure 8 It is a schematic diagram of a semiconductor LDD extension width test structure according to an embodiment of the present invention.

[0140] It should be noted that the direction of the LDD extension width is parallel to the direction of carrier movement.

[0141] refer to Figure 8 The semiconductor LDD extension width test structure comprises: a substrate 100, the substrate

[0142] The bottom 100 includes a first region 101, a second region 102 adjacent to the first region 101, and a third region 103 adjacent to the second region 102; a first well 200 located in the first region 101; a second well 201 located in the second region 102; a third well 202 located in the third region 103; a first LDD 203 located in the second well 201; a pair of second LDDs 204 located in the third well 202, and each pair of second LDDs 204 has a gap between them, and one side of each pair of second LDDs 204 away from another second LDD 204 is flush with an edge of the third well 202; a gate layer 205 located in the third region 103, and the gate layer 205 covers the pair of second LDDs 204 and the third well 202 therebetween. The LDD extension width can be obtained by using the test structure of the embodiment of the present invention.

[0143] refer to Figure 8 The substrate 100 is used to provide a process platform for forming a semiconductor LDD extended width test structure.

[0144] In this embodiment, the substrate 100 is a silicon substrate 100, and the material of the substrate 100 is single crystal silicon. In other embodiments, the material of the substrate 100 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium, and the substrate 100 can also be a silicon substrate 100 on an insulator or a germanium substrate 100 on an insulator. Other types of substrates 100. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 100 can also be formed on the surface of the substrate 100 to improve the quality of pattern transfer.

[0145] It should be noted that Figure 8 This is a schematic diagram, and does not depict the entire structure of the substrate 100. For example, in the process of forming the substrate 100, it may also include: forming other appropriate regions, such as an insulating layer, for example: a well region formed in the substrate 100, the well region being located above the insulating layer.

[0146] Continue to refer Figure 8 The substrate 100 includes a first region 101 , a second region 102 adjacent to the first region 101 , and a third region 103 adjacent to the second region 102 .

[0147] The first region 101 is used to reserve a position space for forming a first well 200 ; the second region 102 is used to reserve a position space for forming a second well 201 ; and the third region 103 is used to reserve a position space for forming a third well 202 .

[0148] The first well 200 is located in the first region 101 and is used to provide a test basis for testing the resistance of the first well 200 .

[0149] The second well 201 , located in the second region 102 , is used to provide a space for forming the first LDD 203 .

[0150] The third well 202 is located in the third region 103 and is used to provide a space for forming a semiconductor channel and a second LDD 204 .

[0151] The first LDD 203 is located in the second well 201 and is used to provide a test basis for testing the resistance of the first LDD 203 .

[0152] The first well 200 includes a P-type well or an N-type well, the second well 201 includes a P-type well or an N-type well, and the third well 202 includes a P-type well or an N-type well; in this embodiment, the first well 200, the second well 201 and the third well 202 are all P-type wells.

[0153] It should be noted that, along the direction parallel to the carrier flow, the theoretical widths of the first well 200, the second well 201, the third well 202, and the first LDD 203 are equal, so that the actual widths of the first well 200, the second well 201, the third well 202, and the first LDD 203 formed on the substrate 100 are close to or equal, which facilitates the subsequent calculation of the LDD expansion width.

[0154] Continue to refer Figure 8 , the paired second LDDs 204 are located in the third well 202, and there is a gap between each pair of second LDDs 204, and the side of each pair of second LDDs 204 away from the other second LDD 204 is flush with an edge of the third well 202. In this embodiment, the second LDDs 204 are a pair, namely, a second LDD 2040 and a second LDD 2041; the side 2042 of the second LDD 2040 away from the second LDD 2041 is flush with the edge 2020 of the third well 202, and the side 2043 of the second LDD 2041 away from the second LDD 2040 is flush with the edge 2021 of the third well 202, so as to prevent the width of the second LDD 204 from becoming smaller along the direction of carrier movement, and ensure that the subsequent integrated via 209 can be formed on the second LDD 204.

[0155] The first LDD 203 includes a P-type LDD or an N-type LDD, and the second LDD 204 includes a P-type LDD or an N-type LDD. In this embodiment, both the first LDD 203 and the second LDD 204 are N-type.

[0156] It should be noted that, along the direction parallel to the carrier flow, the sum of the theoretical widths of the second LDD204 and the third well 202 located between the second LDD204 is equal to the theoretical width of the first well 200, so that the sum of the measured widths of the second LDD204 and the third well 202 located between the second LDD204 is equal to the measured width of the first well 200, which facilitates the subsequent calculation of the LDD expansion width.

[0157] It should be noted that, along the direction perpendicular to the carrier flow, the theoretical lengths of the first well 200, the second well 201, the third well 202, the first LDD 203, and the second LDD 204 are equal, so that the actual lengths of the first well 200, the second well 201, the third well 202, the first LDD 203, and the second LDD 204 formed on the substrate 100 are close to or equal, ensuring that the integrated via 209 can be formed on the second LDD 204.

[0158] Continue to refer Figure 8The test structure includes: a gate layer 205 located in the third region 103, and the gate layer 205 covers the paired second LDDs 204 and the third well 202 therebetween. In this embodiment, that is, the gate layer 205 covers the second LDD 204 and the second LDD 204 and the third well 202 therebetween.

[0159] The material of the gate layer 205 includes: polysilicon or amorphous silicon. In this embodiment, the material of the gate layer 205 is polysilicon.

[0160] It should be noted that, along the direction parallel to the carrier flow, the theoretical width of the gate layer 205 is smaller than the theoretical width of the first well 200, so that the measured width of the gate layer 205 is smaller than the measured width of the first well 200, which is convenient for subsequent calculation of the LDD expansion width.

[0161] Continue to refer Figure 8 , combined with Figure 6 The test structure includes: a well region via 207, an LDD via 208, and an integrated via 209. The integrated via 209 includes a first integrated via 2090 and a second integrated via 2091. The second integrated via 2091 penetrates the gate layer 205. The second integrated via 2091 spans the second LDD 204 and the third well 202 to prevent the first integrated via 2090 from having poor contact with the second LDD 204, resulting in no test signal on the second LDD 204.

[0162] It should be noted that the well region via 207 , the LDD via 208 , and the integrated via 209 have the same shape and size, which reduces the resistance difference caused by the vias and improves the accuracy of obtaining the LDD expansion width.

[0163] In this embodiment, the via holes are in the shape of squares of the same size.

[0164] Continue to refer Figure 8 The test structure includes: a connection layer 210 located in the well region via 207 , the LDD via 208 and the integrated via 209 .

[0165] The material of the connection layer 210 includes: a combination of one or more of copper, aluminum, tungsten, and titanium. In this embodiment, the material of the connection layer 210 is copper.

[0166] Continue to refer Figure 8 , combined with Figure 6 The test structure includes: a well region test terminal 211, an LDD test terminal 212, and a comprehensive test terminal 213.

[0167] In this embodiment, the well region test terminal 211 is coupled to the first well 200 through the connection layer 210 in the well region via 207 to form a well resistance test structure for testing the resistance of the first well 200. The test signal for testing the resistance of the first well 200 is transmitted to the well resistance test structure through the well region test terminal 211.

[0168] The LDD test terminal 212 is coupled to the first LDD 203 through the connection layer 210 in the LDD via 208 to form an LDD resistance test structure for testing the resistance of the first LDD 203 . The test signal for testing the resistance of the first LDD 203 is transmitted to the LDD resistance test structure through the LDD test terminal 212 .

[0169] The integrated test terminal 213 is coupled to the second LDD 204 on both sides of the third well 202 through the connection layer 210 in the first integrated via 2090, and is also coupled to the second LDD 204 and the third well 202 through the connection layer 210 in the second integrated via 2091, forming an integrated resistance test structure for testing the semiconductor channel resistance. The test signal for testing the semiconductor channel resistance is transmitted to the integrated resistance test structure through the integrated test terminal 213.

[0170] It should be noted that the resistance of the first LDD 203 is the resistance after the first LDD 203 contacts the second well 201. The resistance of the semiconductor channel is the resistance of the second LDD 204 on both sides of the third well 202 and the resistance of the third well 202 between the second LDD 204 in parallel.

[0171] It should be noted that the connection layer 210 is insulated from the gate layer 205 to prevent the integrated test terminal 213 from short-circuiting with the gate layer 205, thereby affecting the accuracy of the integrated test terminal 213 in testing the semiconductor channel resistance, thereby improving the accuracy of obtaining the LDD expansion width.

[0172] like Figure 6 The d part and Figure 7 As shown in part d, the connection layer 210 is insulated and connected to the gate layer 205, that is, an isolation layer 500 is arranged between the connection layer 210 and the gate layer 205, and the isolation layer 500 covers the side wall of the second integrated via 2091, that is, the isolation layer 500 covers the side wall of the dielectric layer 206 and the side wall of the gate layer 205 in the second integrated via 2091.

[0173] The material of the well region test terminal 211 includes: one or more combinations of copper, aluminum, tungsten, titanium, and indium tin oxide; the material of the LDD test terminal 212 includes: one or more combinations of copper, aluminum, tungsten, titanium, and indium tin oxide; the material of the integrated test terminal 213 includes: one or more combinations of copper, aluminum, tungsten, titanium, and indium tin oxide; in this embodiment, the material of the well region test terminal 211 is indium tin oxide, the material of the LDD test terminal 212 is indium tin oxide, and the material of the integrated test terminal 213 is indium tin oxide. The indium tin oxide is a transparent material.

[0174] Continue to refer Figure 8 , combined with Figure 6 , the number of the well area vias is greater than or equal to 2, the number of the well area test terminals is at least 2, wherein one well area test terminal is connected to one end of the first well through the connection layer in the well area via, and the other well area test terminal is connected to the other end of the first well through the connection layer in the well area via. In this embodiment, the number of the well area vias 207 is equal to 8, and the number of the well area test terminals 211 is 2, namely well area test terminal 2110 and well area test terminal 2111, wherein the well area test terminal 2110 is connected to one end of the first well 200 through the connection layers 210 in 4 of the well area vias 207, and the well area test terminal 2111 is connected to the other end of the first well 200 through the connection layers 210 in 4 of the well area vias 207.

[0175] Continue to refer Figure 8 , combined with Figure 6 , the number of the LDD vias is greater than or equal to 2, the number of the LDD test terminals is at least 2, wherein one LDD test terminal is connected to one end of the first LDD via the connection layer in the LDD via, and the other LDD test terminal is connected to the other end of the first LDD via the connection layer in the LDD via. In this embodiment, the number of the LDD vias 208 is equal to 8, and the number of the LDD test terminals 212 is 2, namely LDD test terminal 2120 and LDD test terminal 2121, wherein the LDD test terminal 2120 is connected to one end of the first LDD 203 via the connection layers 210 in four of the LDD vias 208, and the LDD test terminal 2121 is connected to the other end of the first LDD 203 via the connection layers 210 in four of the LDD vias 208.

[0176] Continue to refer Figure 8 , combined with Figure 6, the number of the integrated vias is greater than or equal to 8, the number of the integrated test terminals is at least 2, wherein one integrated test terminal is respectively connected to the second LDD at one end of the third well through the connection layers in at least 2 integrated vias, and is also simultaneously coupled to the second LDD and the third well at one end of the third well through the connection layers in at least 2 integrated vias, and another integrated test terminal is respectively connected to the second LDD at the other end of the third well through the connection layers in at least 2 integrated vias, and is also simultaneously coupled to the second LDD and the third well at the other end of the third well through the connection layers in at least 2 integrated vias. In this embodiment, the number of the integrated vias 209 is equal to 8, and the number of the integrated test terminals 213 is 2, namely, the integrated test terminal 2130 and the integrated test terminal 2131, wherein the integrated test terminal 2130 is connected to the second LDD 204 at one end of the third well 202 through the connection layer 210 in the two integrated vias 209 (i.e., the first integrated via 2090), and is also connected to the second LDD 204 at one end of the third well 202 through the connection layer 210 in the two integrated vias 209 (i.e., the second integrated via 2091). The integrated test terminal 2131 is coupled to the second LDD 204 and the third well 202 at one end of the third well 202, and the integrated test terminal 2131 is respectively connected to the second LDD 204 at the other end of the third well 202 through the connection layer 210 in two integrated vias 209 (i.e., the first integrated via 2090), and is also coupled to the second LDD 204 and the third well 202 at the other end of the third well 202 through the connection layer 210 in two integrated vias 209 (i.e., the second integrated via 2091).

[0177] It should be noted that the well test terminal 211, LDD test terminal 212, and integrated test terminal 213 have the same shape and area, which prevents the resistance difference between the test terminals from affecting the accuracy of the integrated test terminal 213 in testing the semiconductor channel resistance, thereby improving the accuracy of obtaining the LDD expansion width.

[0178] In order to solve the technical problem, the present invention also provides a method for calculating the semiconductor LDD extension width corresponding to the test structure.

[0179] Fig.10 It is a flowchart of a method for calculating a semiconductor LDD extension width according to an embodiment of the present invention.

[0180] The method for calculating the semiconductor LDD extension width is applied to the test structure described in any of the above items, including: determining the width of the test structure, the width of the test structure is determined based on the width of the first well and / or the width of the first LDD; testing the first well to obtain the measured resistance of the first well; testing the first LDD to obtain the measured resistance of the first LDD; testing the semiconductor channel to obtain the measured resistance of the semiconductor channel; and deriving the actual width of the semiconductor channel based on the measured resistance of the first well, the measured resistance of the first LDD, the measured resistance of the semiconductor channel and the width of the test structure.

[0181] The test structure includes: the well resistance test structure, the LDD resistance test structure, and the integrated resistance test structure. For the relevant contents of the test structure, please refer to the detailed description of the corresponding parts above, which will not be repeated here.

[0182] like Fig.10 As shown, the method for calculating the semiconductor LDD extension width mainly comprises the following steps:

[0183] Step S11: testing the first well to obtain the measured resistance of the first well; testing the first LDD to obtain the measured resistance of the first LDD; testing the semiconductor channel to obtain the measured resistance of the semiconductor channel.

[0184] The measured resistance of the first well, the measured resistance of the first LDD, and the measured resistance of the semiconductor channel are tested by a resistance tester.

[0185] refer to Figure 8 and Fig. 9 , Fig. 9 include Fig. 9 Part a of Fig. 9 Part b of Fig. 9 Part c of Fig. 9 The a part in the figure is the resistance of the first well 200. R 1 Schematic diagram, Fig. 9 Part b in the figure is the resistance of the first LDD203 R 2 Schematic diagram, Fig. 9 The c part in the figure is the resistance of the semiconductor channel. R 3 Schematic diagram.

[0186] The resistance tester provides a test signal to the well region test terminal 211 to test the first well 200 and obtain the measured resistance of the first well 200. R 1.

[0187] A resistance tester is used to provide a test signal to the test terminal of the first LDD203, and the first LDD203 is tested to obtain the measured resistance of the first LDD203. R 2.

[0188] The resistance tester provides a test signal to the integrated test terminal 213 to test the semiconductor channel and obtain the measured resistance of the semiconductor channel. R 3.

[0189] In this embodiment, the measured resistance of the first well 200 is obtained by synchronous testing with a resistance tester. R 1. Measured resistance of the first LDD203 R 2. Measured resistance of semiconductor channel R 3. In other embodiments, the measured resistance of the first well 200 is obtained by testing respectively R 1. Measured resistance of the first LDD203 R 2. Measured resistance of semiconductor channel R 3.

[0190] The resistance tester includes a multimeter or a four-probe tester; in this embodiment, the resistance tester is a four-probe tester.

[0191] Step S12: determine the width of the test structure, determine the length of the test structure, determine the thickness of the test structure, and determine the width of the gate layer.

[0192] The measured thickness D1 of the first well, the measured thickness D2 of the first LDD, the measured width W1 of the first well, the measured width W2 of the first LDD, the measured length L1 of the first well, the measured length L2 of the first LDD, and the measured width of the gate layer are measured by an optical interferometer. L .

[0193] refer to Figure 8 , determining the width of the test structure, the width of the test structure being determined based on the width of the first well and / or the width of the first LDD; determining the width of the test structure, including one or more of the following: determining the measured width W1 of the first well 200 along a direction parallel to the carrier flow, determining the measured width W2 of the first LDD 203 along a direction parallel to the carrier flow, determining the measured width W1 of the first well 200 and the measured width W2 of the first LDD 203 along a direction parallel to the carrier flow, and then determining the average value of W1 and W2 as W， That is, the width of the test structure may be the measured width W1 of the first well 200, the measured width W2 of the first LDD 203, or the average of W1 and W2. W .

[0194] In this embodiment, the width of the test structure is W .

[0195] It should be noted that, along the direction parallel to the carrier flow, the theoretical widths of the first well 200, the second well 201, the third well 202, and the first LDD 203 are equal, so the measured width W1 of the first well 200, the measured width W2 of the first LDD 203, and the measured width W3 of the third well 202 can be equal, that is, W1=W2=W3= W .

[0196] In this embodiment, the measured width W1 of the first well 200 and the measured width W2 of the first LDD 203 are obtained by measuring in parallel to the carrier flow direction through an optical interferometer.

[0197] refer to Figure 8 , determine the length of the test structure, the length of the test structure is determined based on the length of the first well and / or the length of the first LDD, the length of the test structure is determined, including one or more of the following: along a direction parallel to the surface of the substrate 100 and perpendicular to the direction of carrier flow, determine the measured length L1 of the first well 200; along a direction parallel to the surface of the substrate 100 and perpendicular to the direction of carrier flow, determine the measured length L2 of the first LDD203; along a direction parallel to the surface of the substrate 100 and perpendicular to the direction of carrier flow, determine the measured length L1 of the first well 200 and the measured length L2 of the first LDD203, and then determine that the average value of L1 and L2 is L0, that is, the length of the test structure can be the measured length L1 of the first well 200, the measured length L2 of the first LDD203, or the average value of L1 and L2. L 0 。

[0198] In this embodiment, the length of the test structure is L 0.

[0199] It should be noted that, along the direction parallel to the carrier flow, the theoretical lengths of the first well 200, the second well 201, the third well 202, and the first LDD 203 are equal, so the measured length L1 of the first well 200, the measured length L2 of the first LDD 203, and the measured length L3 of the third well 202 can be equal, that is, L1=L2=L3= L 0.

[0200] In this embodiment, the measured length L1 of the first well 200 and the measured length L2 of the first LDD 203 are obtained by measuring with an optical interferometer along a direction parallel to the surface of the substrate 100 and perpendicular to the carrier flow direction.

[0201] Determine the thickness of the test structure, the thickness of the test structure including the thickness of the first well and the thickness of the first LDD; determine the measured thickness D1 of the first well along a direction perpendicular to the substrate surface; determine the measured thickness D2 of the first LDD along a direction perpendicular to the substrate surface.

[0202] refer to Figure 8 In this embodiment, the measured thickness D1 of the first well 200 and the measured thickness D2 of the first LDD 203 are obtained by measuring along a direction perpendicular to the surface of the substrate 100 using an optical interferometer.

[0203] refer to Figure 8 , determine the width of the gate layer 205, and obtain the measured width of the gate layer 205 by measuring the width of the gate layer 205 parallel to the carrier flow direction by optical interferometer L .

[0204] It should be noted that the present invention does not limit the test order of determining the width of the test structure, the length of the test structure, the thickness of the test structure, and the width of the gate layer 205 .

[0205] Step S13: deriving the actual width of the semiconductor channel according to the measured resistance of the first well, the measured resistance of the first LDD, the measured resistance of the semiconductor channel, and the width of the test structure.

[0206] The actual width of the semiconductor channel is obtained by using the following formula (3): W C .

[0207] According to the following formula (1):

[0208]

[0209] The actual resistivity of the first well 200 is obtained:

[0210]

[0211] According to the following formula (2):

[0212]

[0213] The actual resistivity of the first LDD203 is obtained:

[0214]

[0215] refer to Figure 8 and Fig. 9 , the measured resistance of the semiconductor channel R 3 is the parallel resistance of the second LDD2040 and the second LDD2041 R4 and the third well 202 resistance between the second LDD 2040 and the second LDD 2041 at the semiconductor channel R 5 resistors in parallel.

[0216] The following formula (3) is used:

[0217]

[0218] Bring in R 3. Get the actual width of the semiconductor channel W C :

[0219]

[0220] According to the measured resistance of the first well 200: R 1. The measured resistance of the first LDD203 is R 2 and the measured resistance of the semiconductor channel is R 3. Obtain the actual width of the semiconductor channel W C .

[0221] refer to Figure 8 It should be noted that, along the direction perpendicular to the substrate 100, the thickness of the third well 202 below the second LDD 204 is thinner than the thickness of the first well 200. In the calculation method of the present invention, the thickness of the third well 202 between the second LDD 2040 and the second LDD 2041 at the semiconductor channel is D1, but this is not a limitation to the present invention.

[0222] Step S14: Obtaining the semiconductor LDD extension width.

[0223] The following formula (4) is used:

[0224]

[0225] According to the width of the gate layer 205 L and the actual width of the semiconductor channel W C , the semiconductor LDD expansion width is obtained x .

[0226] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make possible changes, modifications and combinations to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming a semiconductor LDD extended width test structure, characterized in that: include: providing a substrate, the substrate comprising a first region, a second region adjacent to the first region, and a third region adjacent to the second region; Performing a doping process on the substrate to form a first well in the first region, a second well in the second region, and a third well in the third region; Doping a first LDD in the second well, and doping a pair of second LDDs in the third well in a direction parallel to the carrier flow direction, wherein there is a gap between each pair of second LDDs, and a side of each pair of second LDDs away from another second LDD is flush with an edge of the third well; forming a gate layer, the gate layer covering the pair of second LDDs and the third well therebetween; forming a well region test terminal coupled to the first well in the first region; forming an LDD test terminal coupled to the first LDD in the second region; forming a comprehensive test terminal in the third region, the comprehensive test terminal being coupled to the second LDD and to a third well located between the paired second LDDs; Wherein, the well region test terminal, the LDD test terminal and the integrated test terminal are formed in the same process step; Before forming the well region test terminal, the LDD test terminal and the integrated test terminal, and after forming the gate layer, the forming method further includes: forming a dielectric layer covering the substrate; Etching the dielectric layer to form a through-well region via located on the first well, a through-LDD via located on the first LDD, and a through-comprehensive via located on the second LDD in the dielectric layer; The well region via hole, the LDD via hole and the integrated via hole are filled with a connection layer material to form a connection plug.

2. The forming method according to claim 1, characterized in that: The first well includes a P-type well or an N-type well, the second well includes a P-type well or an N-type well, and the third well includes a P-type well or an N-type well; The first LDD includes a P-type LDD or an N-type LDD, and the second LDD includes a P-type LDD or an N-type LDD; The material of the gate layer includes: polysilicon or amorphous silicon; The material of the well region test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide; The material of the LDD test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide; The material of the comprehensive test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide; The connection layer material includes: one or more combinations of copper, aluminum, tungsten and titanium.

3. A semiconductor LDD extension width test structure, characterized in that: include: a substrate comprising a first region, a second region adjacent to the first region, and a third region adjacent to the second region; a first well located in the first region; a second well located in the second region; A third well, located in the third region; a first LDD, located in the second well; The paired second LDDs are located in the third well, and there is a gap between each pair of the second LDDs, and a side of each pair of the second LDDs away from another second LDD is flush with an edge of the third well; A gate layer, located in the third region, the gate layer covers the paired second LDDs and the third well therebetween; The test structure further includes: a well region via, an LDD via, and a comprehensive via, wherein the comprehensive via includes a first comprehensive via and a second comprehensive via, wherein the second comprehensive via penetrates the gate layer, and the second comprehensive via spans the second LDD and the third well; Well test terminal, LDD test terminal, comprehensive test terminal; A connection layer is located in the well region via, the LDD via and the integrated via; The well region test terminal is coupled to the first well through the connection layer in the well region via hole to form a well resistance test structure for testing the first well resistance; The LDD test terminal is coupled to the first LDD via the connection layer in the LDD via hole to form an LDD resistance test structure for testing the first LDD resistance; The integrated test terminal is coupled to the second LDDs on both sides of the third well through the connection layer in the first integrated via hole, and is also coupled to the second LDD and the third well through the connection layer in the second integrated via hole, forming an integrated resistance test structure for testing semiconductor channel resistance; The first LDD resistance is the resistance after the first LDD contacts the second well; The semiconductor channel resistance is the resistance of the second LDDs on both sides of the third well and the resistance of the third well between the second LDDs in parallel; The connection layer is insulated and connected to the gate layer.

4. The test structure according to claim 3, characterized in that: The first well includes a P-type well or an N-type well, the second well includes a P-type well or an N-type well, and the third well includes a P-type well or an N-type well; The first LDD includes a P-type LDD or an N-type LDD, and the second LDD includes a P-type LDD or an N-type LDD; The material of the gate layer includes: polysilicon or amorphous silicon; The material of the well region test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide; The material of the LDD test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide; The material of the comprehensive test terminal includes: a combination of one or more of copper, aluminum, tungsten, titanium, and indium tin oxide; The connection layer material includes: one or more combinations of copper, aluminum, tungsten and titanium.

5. The test structure according to claim 3, characterized in that: The number of the well area vias is greater than or equal to 2, and the number of the well area test terminals is at least 2, wherein one well area test terminal is connected to one end of the first well through the connection layer in the well area via, and the other well area test terminal is connected to the other end of the first well through the connection layer in the well area via; The number of the LDD vias is greater than or equal to 2, and the number of the LDD test terminals is at least 2, wherein one LDD test terminal is connected to one end of the first LDD via the connection layer in the LDD via, and the other LDD test terminal is connected to the other end of the first LDD via the connection layer in the LDD via; The number of the integrated vias is greater than or equal to 8, and the number of the integrated test terminals is at least 2, wherein one integrated test terminal is respectively connected to the second LDD at one end of the third well through the connection layers in at least 2 integrated vias, and is also simultaneously coupled to the second LDD and the third well at one end of the third well through the connection layers in at least 2 integrated vias, and another integrated test terminal is respectively connected to the second LDD at the other end of the third well through the connection layers in at least 2 integrated vias, and is also simultaneously coupled to the second LDD and the third well at the other end of the third well through the connection layers in at least 2 integrated vias.

6. The test structure according to claim 4, characterized in that: The well region vias, LDD vias and integrated vias have the same shape and size.

7. The test structure according to claim 3, characterized in that: In a direction parallel to the carrier flow direction, the theoretical widths of the first well, the second well, the third well, and the first LDD are equal, and the theoretical width of the gate layer is smaller than the theoretical width of the first well; The sum of the theoretical widths of the second LDD and the third well located between the second LDD is equal to the theoretical width of the first well; In a direction perpendicular to the carrier flow direction, the theoretical lengths of the first well, the second well, the third well, the first LDD, and the second LDD are equal; The well region test terminal, the LDD test terminal and the integrated test terminal have the same shape and area.

8. A method for calculating semiconductor LDD extension width, applied to the test structure according to any one of claims 3 to 7, characterized in that: include: Determining a width of a test structure, wherein the width of the test structure is determined based on a width of the first well and / or a width of a first LDD; Testing the first well to obtain a measured resistance of the first well; Testing the first LDD to obtain a measured resistance of the first LDD; Testing the semiconductor channel to obtain a measured resistance of the semiconductor channel; According to the measured resistance of the first well, the measured resistance of the first LDD, and the semiconductor channel The actual width of the semiconductor channel is obtained based on the measured resistance of the test structure and the width of the test structure.

9. The calculation method according to claim 8, characterized in that: Determining the width of the test structure includes one or more of the following: Determine the measured width W1 of the first well in a direction parallel to the carrier flow direction; Determine the measured width W2 of the first LDD in a direction parallel to the carrier flow direction; The measured width W1 of the first well and the measured width W2 of the first LDD are determined parallel to the carrier flow direction, and then the average value of W1 and W2 is determined as W ; Determine a length of a test structure, wherein the length of the test structure is determined based on a length of the first well and / or a length of the first LDD, wherein determining the length of the test structure comprises one or more of the following: Determine the measured length L1 of the first well along a direction parallel to the substrate surface and perpendicular to the carrier flow direction; Determine the measured length L2 of the first LDD along a direction parallel to the substrate surface and perpendicular to the carrier flow direction; The measured length L1 of the first well and the measured length L2 of the first LDD are determined along a direction parallel to the substrate surface and perpendicular to the carrier flow direction, and then the average value of L1 and L2 is determined as L 0; Determine the thickness of the test structure, the thickness of the test structure including the thickness of the first well and the thickness of the first LDD; determine the measured thickness D1 of the first well along a direction perpendicular to the surface of the substrate; determine the measured thickness D2 of the first LDD along a direction perpendicular to the surface of the substrate; Determine the measured width of the gate layer parallel to the direction of carrier flow L .

10. The calculation method according to claim 8, characterized in that: Use the following formula: , according to the measured resistance of the first well is R 1. The measured resistance of the first LDD is R 2 and the measured resistance of the semiconductor channel is R 3. Obtain the actual width of the semiconductor channel W C .

11. The calculation method according to claim 10, characterized in that: Use the following formula: , according to the width of the gate layer L and the actual width of the semiconductor channel W C , the semiconductor LDD expansion width is obtained x .

12. The calculation method according to claim 8, characterized in that: The measured resistance of the first well, the measured resistance of the first LDD, and the measured resistance of the semiconductor channel are tested by a resistance tester.

13. The calculation method according to claim 9, characterized in that: The measured thickness D1 of the first well, the measured thickness D2 of the first LDD, the measured width W1 of the first well, the measured width W2 of the first LDD, the measured length L1 of the first well, the measured length L2 of the first LDD, and the measured width of the gate layer are measured by an optical interferometer. L .

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