ESD protection circuit and electronic device including same

Abstract

The invention relates to an ESD protection circuit and an electronic device including the same. An electrostatic discharge (ESD) protection circuit includes: an ESD current discharge circuit including a first transistor, a second transistor, and a third transistor connected in series and between a pad and a ground voltage; an ESD detection circuit configured to turn on the third transistor when an ESD event occurs; and a bias generation circuit configured to provide a bias voltage for turning on the first transistor to a gate of the first transistor when an ESD event occurs.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0096425, filed on Jul. 24, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to an electrostatic discharge (ESD) protection circuit and an electronic device including the ESD protection circuit. Background Art

[0004] Recent system-on-chip (SoC) devices require high-speed interface circuits, which require low power supply voltage and high-speed operation. For this reason, a triple gate oxide (TGO) process has been applied, which uses a MOS transistor with a thin gate insulating layer for relatively low core voltage operation and a MOS transistor with two different thicknesses of thick gate insulating layers for relatively high input / output voltage operation. However, with the recent introduction of micromachining for semiconductor devices, a double gate oxide (DGO) process is being applied instead of a triple gate oxide (TGO) process with a very complicated manufacturing process. That is, as devices constituting a working circuit, a MOS transistor with a thin gate insulating layer for core voltage operation and a MOS transistor with a thick gate insulating layer for input / output voltage operation are used. For example, when a process below 28nm is applied, a MOS transistor including a thin gate insulating layer for 1.8V operation and a MOS transistor including a thick gate insulating layer for 2.5V or 3.3V operation are used.

[0005] However, when an electrostatic discharge (ESD) protection circuit is implemented using a MOS transistor, a voltage twice or three times higher than the operating voltage may be applied to the terminal of the MOS transistor. In this case, reliability issues may arise in the MOS transistor. In addition, to date, a method of using a parasitic bipolar junction transistor in a MOS transistor has been used as a mechanism for ESD protection operation. Recently, when a process below 7nm is applied, a method of releasing ESD current through the channel of a MOS transistor is adopted instead of turning on a parasitic bipolar junction transistor. Therefore, it is necessary to solve the reliability problem of the MOS transistor constituting the ESD protection circuit when an ESD event occurs. Summary of the invention

[0006] According to an embodiment of the present disclosure, an electrostatic discharge (ESD) protection circuit may include: an ESD current discharge circuit, which includes a first transistor, a second transistor, and a third transistor connected in series and connected between a pad and a ground voltage; an ESD detection circuit, configured to turn on the third transistor when an ESD event occurs; and a bias generation circuit, configured to provide a bias voltage to the gate of the first transistor for turning on the first transistor when an ESD event occurs.

[0007] An electronic device according to an embodiment of the present disclosure may include a pad, an internal circuit coupled to the pad, and an electrostatic discharge (ESD) protection circuit configured to protect the internal circuit when an ESD event occurs in which an ESD current flows into the pad. The ESD protection circuit may include: an ESD current discharge circuit including a first transistor, a second transistor, and a third transistor connected in series with each other and connected between the pad and a ground voltage; and a bias generation circuit configured to provide a bias voltage to the gate of the first transistor for turning on the first transistor when an ESD event occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating an electronic device including an electrostatic discharge (ESD) protection circuit according to an embodiment of the present disclosure.

[0009] Figure 2 is a circuit diagram showing an ESD protection circuit according to an embodiment of the present disclosure.

[0010] Figure 3 1 is a table of conditions under which the transistors constituting the ESD protection circuit according to the present disclosure can ensure reliability.

[0011] Figure 4 It shows that Figure 1 When the electronic device is performing normal operation Figure 2 Diagram of the operation of the ESD protection circuit.

[0012] Figure 5 It shows that Figure 1 When an ESD event occurs in an electronic device Figure 2 Diagram of the operation of the ESD protection circuit. DETAILED DESCRIPTION

[0013] In the description of the following embodiments, it should be understood that the terms "first" and "second" are intended to identify elements, and are not used to define a specific number or sequence of elements. In addition, when an element is referred to as being "on", "above", "above", "below" or "below" another element, it is intended to represent a relative positional relationship, and is not intended to limit certain situations where an element directly contacts another element or there is at least one intermediate element between two elements. Therefore, terms such as "on", "above", "above", "below", "below" and the like used herein are only for the purpose of describing specific embodiments, and are not intended to limit the scope of the present disclosure.

[0014] In addition, when an element is referred to as being "connected" or "coupled" to another element, the element may be directly electrically or mechanically connected or coupled to the other element, or may be indirectly electrically or mechanically connected or coupled to the other element with one or more additional elements between the two elements. In addition, when a parameter is referred to as being "predetermined," it may mean that the value of the parameter is determined before the parameter is used in a process or algorithm. The value of a parameter may be set at the beginning of a process or algorithm, or may be set during the execution of a process or algorithm.

[0015] Logical "high" level and logical "low" level are used to describe the logical level of an electrical signal. A signal with a logical "high" level is different from a signal with a logical "low" level. For example, when a signal with a first voltage corresponds to a signal with a logical "high" level, a signal with a second voltage may correspond to a signal with a logical "low" level. In an embodiment, the voltage level of the logical "high" level may be set to a voltage level higher than the voltage level of the logical "low" level. In addition, the logic level of the signal may be set to be different or opposite according to the embodiment. For example, a signal with a logical "high" level in one embodiment may be set to have a logical "low" level in another embodiment.

[0016] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0017] As used herein, "ESD" refers to electrostatic discharge. The strength of an electrostatic discharge that can or will damage an integrated circuit will depend on a variety of factors, including but not limited to the construction, materials, and packaging of the integrated circuit itself.

[0018] Figure 1 is a block diagram illustrating an electronic device 100 including an electrostatic discharge (ESD) protection circuit 130 according to an embodiment of the present disclosure.

[0019] refer to Figure 1, the electronic device 100 may include a pad 110, an internal circuit 120, and an ESD protection circuit 130. The electronic device 100 may also include a buffer 140. The pad 110 may allow the electronic device 100 to be electrically coupled to an external circuit, such as one or more other integrated circuits. That is, the electronic device 100 may receive a signal from the external circuit through the pad 110. The electronic device 100 may also send a signal to the external circuit through the pad 110. The pad 110 may also be coupled to the first voltage line 151.

[0020] The internal circuit 120 may perform various types of operations and functions, and may include logic devices and circuits, analog devices and circuits, and other types of devices and circuits. The internal circuit 120 may include transistors, diodes, preamplifiers, operational amplifiers, buffers, inverters, and / or other circuits. In addition, the internal circuit 120 may include a level shifter that is suitable for converting a voltage signal within a specific range into a voltage signal within another range. In addition, the internal circuit 120 may include a signal amplification circuit. The internal circuit 120 may include a volatile memory cell such as a DRAM cell or a non-volatile memory cell such as a NAND cell or a NOR cell.

[0021] The internal circuit 120 may be coupled to the second voltage line 152 and the third voltage line 153. A reference potential voltage VSS of a ground voltage or other magnitude is applied to the second voltage line 152. A power supply voltage VCCQ is applied to the third voltage line 153.

[0022] The internal circuit 120 may be electrically coupled to the buffer 140. In an embodiment, the buffer 140 may include a pull-up circuit or driver and a pull-down circuit or driver as input and output circuits of the buffer 140.

[0023] The buffer 140 may be coupled to the pad 110 through the first voltage line 151. A signal transmitted from the outside of the device 100 through the pad 110 may be transmitted to the internal circuit 120 through the first voltage line 151 and the buffer 140. A signal output from the internal circuit 120 may also be transmitted to the outside of the device 100 through the buffer 140, the first voltage line 151, and the pad 110.

[0024] The ESD protection circuit 130 may be positioned to be coupled to the first voltage line 151, the second voltage line 152, and the third voltage line 153. When an ESD event occurs in which an ESD current flows into the pad 110, the ESD protection circuit 130 may release the ESD current to the second voltage line 152 or the third voltage line 153, thereby preventing the internal circuit 120 from being damaged due to the ESD event. Therefore, the ESD protection circuit 130 may need a fast trigger function to perform an ESD protection operation before the ESD current flows into the internal circuit 120. In addition, the ESD protection circuit 130 may need to be designed to withstand high ESD voltages until the ESD current has been fully discharged. In addition, the ESD protection circuit 130 may need to be designed not to affect the signal transmitted between the pad 110 and the internal circuit 120 when the internal circuit 120 is operating normally.

[0025] Figure 2 1 is a circuit diagram showing an electrostatic discharge (ESD) protection circuit 130 according to an embodiment of the present disclosure. Figure 2 , the ESD protection circuit 130 may include an ESD current discharge circuit 131, an ESD detection circuit 132 and a bias generation circuit 133. Figure 1 As described above, when an ESD event occurs, the ESD protection circuit 130 can protect the internal circuit ( Figure 1 120) from ESD.

[0026] The ESD current discharge circuit 131 may be coupled to the pad 110 through a first voltage line 151 and coupled to a ground voltage VSS through a second voltage line 152. The ESD current discharge circuit 131 may include a first transistor NM1, a second transistor NM2, and a third transistor NM3. Figure 2As shown, the first transistor NM1, the second transistor NM2 and the third transistor NM3 are connected in series and are connected across the first voltage line 151 and the second voltage line 152 or between the first voltage line 151 and the second voltage line 152. Each of the first transistor NM1, the second transistor NM2 and the third transistor NM3 can be composed of an N-channel MOS (NMOS) transistor. Hereinafter, the first transistor NM1, the second transistor NM2 and the third transistor NM3 can be referred to as the first N-channel MOS (NMOS) transistor NM1, the second NMOS transistor NM2 and the third NMOS transistor NM3, respectively. When an ESD event occurs (a large, i.e., destructive positive voltage is introduced to the first voltage line 151 through the pad 110), the ESD current caused by the positive voltage can be shunted to the ground or the second voltage line 152 through the channels of the first NMOS transistor NM1, the second NMOS transistor NM2 and the third NMOS transistor NM3 connected in series, that is, discharged from the pad 110 to the ground voltage VSS. Similarly, when a large negative potential (i.e., less than ground potential) is introduced to the first voltage line 151 so that the potential of the first voltage line 151 drops sharply to below the potential of the second voltage line 152, the destructive current drawn from the second voltage line 152 can be shunted from the second voltage line 152 to the first voltage line 151, i.e., in the opposite path.

[0027] like Figure 2 As shown, the drain of the first NMOS transistor NM1 can be coupled to the pad 110 through the first voltage line 151. The source of the first NMOS transistor NM1 can be coupled to the drain of the second NMOS transistor NM2. The source of the second NMOS transistor NM2 can be coupled to the drain of the third NMOS transistor NM3. The source of the third NMOS transistor NM3 can be coupled to the ground voltage VSS through the second voltage line 152. The gate of the first NMOS transistor NM1 can be coupled to the bias generating circuit 133. The gate of the second NMOS transistor NM2 can be coupled to the drain of the second NMOS transistor NM2 and the source of the first NMOS transistor NM1. The gate of the third NMOS transistor NM3 can be coupled to the ESD detecting circuit 132.

[0028] The second NMOS transistor NM2 can be configured to provide a diode-connected MOSFET in which the gate and the drain are directly connected to each other. Therefore, the gate and drain of the second NMOS transistor NM2 can be coupled to the source of the first NMOS transistor NM1 in common. The source voltage of the first NMOS transistor NM1 can be applied to the gate and drain of the second NMOS transistor NM2 in common, and the gate-source voltage and the drain-source voltage of the second NMOS transistor NM2 can be increased or decreased together. Therefore, the drain-source voltage of the second NMOS transistor NM2 can always be greater than the value obtained by subtracting the threshold voltage of the second NMOS transistor NM2 from the gate-source voltage of the second NMOS transistor NM2, and as a result, the second NMOS transistor NM2 can always operate in the saturation region. The second NMOS transistor NM2 can be turned on at a time point when the gate-source voltage of the second NMOS transistor NM2 becomes greater than the threshold voltage of the second NMOS transistor NM2. To this end, the first NMOS transistor NM1 needs to be turned on to increase the source voltage of the first NMOS transistor NM1. That is, the second NMOS transistor NM2 may be turned on in a state in which the first NMOS transistor NM1 is turned on and the gate voltage and the drain voltage of the second NMOS transistor NM2 are increased.

[0029] The ESD detection circuit 132 may include a capacitor C and a first resistor R1. The capacitor C is connected between the first voltage line 151 and the first node NODE1. The first resistor R1 is connected between the first node NODE1 and the second voltage line 152. One electrode of the capacitor C may be coupled to the pad 110 through the first voltage line 151. The other electrode of the capacitor C may be coupled to the first node NODE1. One terminal of the first resistor R1 may be coupled to the first node NODE1. The other terminal of the first resistor R1 may be coupled to the ground voltage VSS through the second voltage line 152. The first node NODE1 of the ESD detection circuit 132 may be coupled to the gate of the third NMOS transistor NM3 of the ESD current discharge circuit 131.

[0030] The bias generating circuit 133 may include a second resistor R2 connected between the first voltage line 151 and the second node NODE2, a fourth transistor PM1 connected between the second node NODE2 and the third node NODE3, and a fifth transistor PM2 coupled to the third node NODE3 and the power supply voltage VCCQ. One terminal of the second resistor R2 may be coupled to the first voltage line 151. The other terminal of the second resistor R2 may be coupled to the second node NODE2. Each of the fourth transistor PM1 and the fifth transistor PM2 may be composed of a P-channel MOS (PMOS) transistor. Hereinafter, the fourth transistor PM1 and the fifth transistor PM2 will be referred to as the first PMOS transistor PM1 and the second PMOS transistor PM2, respectively.

[0031] The source of the first PMOS transistor PM1 may be coupled to the second node NODE2. The drain of the first PMOS transistor PM1 may be coupled to the third node NODE3. The gate of the first PMOS transistor PM1 may be coupled to the power supply voltage VCCQ. The drain of the second PMOS transistor PM2 may be coupled to the third node NODE3. The source of the second PMOS transistor PM2 may be coupled to the power supply voltage VCCQ. The gate of the second PMOS transistor PM2 may be coupled to the second node NODE2. The third node NODE3 of the bias generating circuit 133 may be coupled to the gate of the first NMOS transistor NM1 of the ESD current discharge circuit 131. In addition, the third node NODE3 of the bias generating circuit 133 may be coupled to the N-type well region of each of the first PMOS transistor PM1 and the second PMOS transistor PM2.

[0032] In one embodiment, the transistors constituting the ESD protection circuit 100, that is, the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 constituting the ESD current discharge circuit 131 and the first PMOS transistor PM1 and the second PMOS transistor PM2 constituting the bias generation circuit 133, can all be manufactured using the same semiconductor manufacturing process, an example of which is a process that produces a line width of less than 7nm. Using such a process, the transistors NM1-NM3 and PM1-PM2 constituting the ESD protection circuit 100 can be configured to operate at a nominal voltage of approximately 1.5V to 1.8V. However, depending on the internal circuit ( Figure 1 120 ) or a configuration of an external circuit coupled to the pad 110 , a high voltage (eg, a voltage of 3.3 V) may be applied to the pad 110 .

[0033] According to the ESD protection circuit 130 of the present disclosure, when the voltage of the pad 110 is triggered from the first voltage (e.g., 0V) to the higher second voltage (e.g., 3.3V) or vice versa, the reliability of the transistors NM1-NM3 and PM1-PM2 constituting the ESD protection circuit 130 may not be damaged. In addition, even when the voltage rises rapidly due to the ESD current flowing into the pad 110 during the ESD event, the reliability of the transistors NM1-NM3 and PM1-PM2 constituting the ESD protection circuit 130 may be maintained.

[0034] Figure 3 is a table of conditions for ensuring reliability of transistors constituting the ESD protection circuit 130 according to the present disclosure. Figure 3 The transistor 200 in the embodiment of the present invention takes an NMOS transistor as an example, but the same principle can also be applied to a PMOS transistor. The following description of the transistor 200 can be applied to the same manner as the Figure 2 Transistors NM1-NM3 and PM1-PM2 in.

[0035] refer to Figure 3 , for transistor 200 to ensure reliability, the gate-drain voltage Vgd, the gate-source voltage Vgs, and the drain-source voltage Vds all need to be no more than the level of the reliability guarantee voltage. In the present embodiment, the reliability guarantee voltage can be defined as the maximum voltage that can be applied between the terminals of the transistor 200 without destroying the gate insulating layer of the transistor 200. In the example, the reliability guarantee voltage of the transistor 200 can be set to about 110% of the operating voltage. For example, when the operating voltage of the transistor 200 is 1.8V, the reliability guarantee voltage can be set to 1.98V. In this case, the gate-drain voltage Vgd, the gate-source voltage Vgs, and the drain-source voltage Vds of the transistor 200 operating at 1.8V all need to be no more than 1.98V. When the gate-drain voltage Vgd or the gate-source voltage Vgs of the transistor 200 exceeds the reliability guarantee voltage, the gate insulating layer of the transistor 200 may be destroyed due to the strong electric field in the vertical direction of the gate insulating layer. When the drain-source voltage Vds of the transistor 200 exceeds the reliability guarantee voltage, hot carrier injection (HCL) may occur, and carriers such as electrons may be trapped in the gate insulating layer of the transistor 200. Therefore, the gate insulating layer of the transistor 200 may be broken.

[0036] Figure 4 It shows that Figure 1 When the electronic device 100 performs normal operation Figure 2 FIG. 1 is a diagram of the operation of the ESD protection circuit 130. Figure 4 In, with Figure 2 The same reference numerals in the drawings represent the same components.

[0037] Reference Figure 4 , when a normal voltage of 3.3V is applied to the pad 110, the voltage at the first node NODE1, that is, the first node voltage VN1 can be maintained at 0V. Because the first node voltage VN1 corresponds to the gate voltage of the third NMOS transistor NM3, the third NMOS transistor NM3 can remain in an off state. When the third NMOS transistor NM3 is turned off, no current flow path through the ESD current discharge circuit 131 exists regardless of whether the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on. That is, even when the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, the space between the first voltage line 151 and the second voltage line 152 can be in an open circuit state within the ESD current discharge circuit 131 due to the third NMOS transistor NM3 being turned off. Therefore, the voltage of 3.3V applied to the pad 110 can be applied to the electronic device ( Figure 1 100) of the buffer 140 input and output drivers. Figure 4 Although not shown in FIG. 1 , even when a voltage of 0 V is applied to the pad 110 , the third NMOS transistor NM3 may maintain its off state according to the same principle.

[0038] Figure 5 It shows that Figure 1 When an ESD event occurs in the electronic device 100 Figure 2 FIG. 1 is a diagram of the operation of the ESD protection circuit 130. Figure 4 In, with Figure 2 The same reference numerals in the drawings represent the same components.

[0039] Reference Figure 5 , when an ESD event occurs, the ESD current Iesd may flow into the pad 110 and begin to flow along the first voltage line 151. Therefore, the ESD voltage Vesd that increases over time may be applied to the pad 110 and the first voltage line 151. Since the ESD current Iesd has an alternating current (AC) form, until the ESD current Iesd reaches a steady state, the capacitor C of the ESD detection circuit 132 will conduct, that is, act as a short circuit. The voltage at the first node NODE1, that is, the first node voltage VN1, will therefore rise or increase from 0V.

[0040] When the first node voltage VN1 increases to a first voltage V1 that turns on the third NMOS transistor NM3 , the third NMOS transistor NM3 of the ESD current discharge circuit 131 may be “turned on”.

[0041] The ESD current Iesd may also flow through the second resistor R2 of the bias generating circuit 133. Therefore, when the voltage of the second node NODE2 (i.e., the second node voltage VN2) increases to the second voltage V2 that turns on the first PMOS transistor PM1, the first PMOS transistor PM1 may be turned on. The amplitude of the second voltage V2 may vary according to the amplitude of the power supply voltage VCCQ. In an example, the second voltage V2 may have an amplitude that satisfies the condition that the source-gate voltage V2-VCCQ of the first PMOS transistor PM1 is greater than the threshold voltage of the first PMOS transistor PM1. That is, the minimum value of the second voltage V2 may be less than the power supply voltage VCCQ by the threshold voltage of the first PMOS transistor PM1.

[0042] The first PMOS transistor PM1 of the bias generating circuit 133 may be turned on, and the second PMOS transistor PM2 may be turned off. Specifically, the second voltage V2 as the second node voltage VN2 may be applied to the gate of the second PMOS transistor PM2. Since the power supply voltage VCCQ as the source voltage of the second PMOS transistor PM2 is less than the second voltage V2 as the gate voltage, the second PMOS transistor PM2 may be turned off.

[0043] When the first PMOS transistor PM1 of the bias generating circuit 133 is turned on and the second PMOS transistor PM2 is turned off, the voltage at the third node NODE3, that is, the third node voltage VN3 may substantially become the second voltage V2. The third voltage V2 as the third node voltage VN3 may be provided to the gate of the first NMOS transistor NM1 of the ESD current discharge circuit 131, and the first NMOS transistor NM1 may be turned on accordingly. That is, the bias generating circuit 133 may be configured to provide the bias voltage for turning on the first NMOS transistor NM1, that is, the second voltage V2, to the gate of the first NMOS transistor NM1.

[0044] When the first NMOS transistor NM1 of the ESD current discharge circuit 131 is turned on, the source voltage of the first NMOS transistor NM1 may increase. The increased source voltage of the first NMOS transistor NM1 may be provided to the gate and drain of the second NMOS transistor NM2, and the second NMOS transistor NM2 may be turned on accordingly. Since the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 are all turned on, an ESD current discharge path may be formed from the first voltage line 151 to the second voltage line 152 in the ESD current discharge circuit 131. That is, the ESD current Iesd may be discharged from the first voltage line 151 to the second voltage line 152 through the channels of the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3.

[0045] After the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 of the ESD current discharge circuit 131 are all turned on, the first node voltage VN1 of the ESD detection circuit 132 may no longer increase. Therefore, the first node voltage VN1 applied to the gate of the third NMOS transistor NM3 may no longer increase. As a result, the gate-source voltage, the gate-drain voltage, and the drain-source voltage of the third NMOS transistor NM3 may all be maintained within the reliability guarantee voltage range.

[0046] After the first PMOS transistor PM1 of the bias generating circuit 133 is turned on, and the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 of the ESD current discharge circuit 131 are all turned on, the third node voltage VN3 may no longer increase. Therefore, the third node voltage VN3 applied to the gate of the first NMOS transistor NM1 may no longer increase. As a result, the gate-source voltage, the gate-drain voltage, and the drain-source voltage of the first NMOS transistor NM1 may all be maintained within the reliability guarantee voltage range. In addition, since the third node voltage VN3 no longer increases, the gate-source voltage, the gate-drain voltage, and the drain-source voltage of the first PMOS transistor PM1 and the second PMOS transistor PM2 may all be maintained within the reliability guarantee voltage range.

[0047] For illustrative purposes, a limited number of possible embodiments of this teaching have been given above. It will be appreciated by those skilled in the art that multiple modifications, additions and substitutions are possible. Although this patent document contains many details, these details should not be interpreted as limitations on the scope of this teaching or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular embodiment. Certain features described in this patent document with the case of separate embodiments may also be implemented in combination in a single embodiment. On the contrary, the various features described with the case of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. In addition, although the features may be described above as working with certain combinations, even initially claimed as such, in some cases, one or more features in the claimed combination may be deleted from the combination, and the claimed combination may be directed to a variant of a sub-combination or a sub-combination.

Claims

1. An ESD protection circuit, ESD stands for electrostatic discharge, and the ESD protection circuit comprises: An ESD current discharge circuit including a first transistor, a second transistor, and a third transistor connected in series and connected between a pad and a ground voltage; An ESD detection circuit, which: turns on the third transistor when an ESD event occurs; and A bias generating circuit is configured to provide a bias voltage to the gate of the first transistor for turning on the first transistor when the ESD event occurs.

2. The ESD protection circuit according to claim 1, wherein: The first transistor, the second transistor and the third transistor are respectively a first NMOS transistor, a second NMOS transistor and a third NMOS transistor, where NMOS represents an N-channel MOS.

3. The ESD protection circuit according to claim 2, in, The drain of the first NMOS transistor is coupled to the pad, The source of the first NMOS transistor is coupled to the drain of the second transistor. The gate of the first NMOS transistor is coupled to the bias generating circuit. The source of the second NMOS transistor is coupled to the drain of the third transistor. Wherein, the source of the third NMOS transistor is coupled to the ground voltage, and Wherein, a gate of the third NMOS transistor is coupled to the ESD detection circuit.

4. The ESD protection circuit according to claim 2, wherein: The second NMOS transistor is turned on by a source voltage of the first NMOS transistor.

5. The ESD protection circuit according to claim 4, wherein: A gate and a drain of the second NMOS transistor are commonly coupled to a source of the first NMOS transistor.

6. The ESD protection circuit according to claim 1, wherein: The ESD detection circuit includes a capacitor and a first resistor, which are connected in series with each other and connected between the pad and the ground voltage.

7. The ESD protection circuit according to claim 6, wherein: A first node between the capacitor and the first resistor is coupled to a gate of the third transistor.

8. The ESD protection circuit according to claim 1, wherein: The bias generating circuit includes: a second resistor connected between the pad and the second node, and The bias voltage has substantially the same magnitude as a voltage of the second node.

9. The ESD protection circuit according to claim 8, wherein: The bias generating circuit further includes a fourth transistor and a fifth transistor connected between the second node and a power supply voltage.

10. The ESD protection circuit according to claim 9, wherein: The fourth transistor and the fifth transistor are respectively a first PMOS transistor and a second PMOS transistor, where PMOS represents a P-channel MOS.

11. The ESD protection circuit according to claim 10, wherein: A gate of the first PMOS transistor is coupled to the power supply voltage.

12. The ESD protection circuit according to claim 10, wherein: A gate of the second PMOS transistor is coupled to the second node.

13. The ESD protection circuit according to claim 10, wherein: A third node between the first PMOS transistor and the second PMOS transistor is coupled to a gate of the first transistor.

14. The ESD protection circuit according to claim 13, wherein: The third node is coupled to an N-type well region of each of the first PMOS transistor and the second PMOS transistor.

15. The ESD protection circuit according to claim 10, in, A drain of the first PMOS transistor and a drain of the second PMOS transistor are coupled to a third node between the first PMOS transistor and the second PMOS transistor, wherein the source of the first PMOS transistor is coupled to the second node, and Wherein, a source of the second PMOS transistor is coupled to the power supply voltage.

16. An electronic device comprising: Solder pads; an internal circuit coupled to the pad; as well as An ESD protection circuit, which: protects the internal circuit when an ESD event occurs in which an ESD current flows into the pad, where ESD stands for electrostatic discharge, Wherein, the ESD protection circuit comprises: An ESD current discharge circuit comprising a first transistor, a second transistor and a third transistor connected in series with each other and connected between the pad and a ground voltage; An ESD detection circuit, which: turns on the third transistor when the ESD event occurs; and A bias generating circuit is configured to provide a bias voltage to the gate of the first transistor for turning on the first transistor when the ESD event occurs.

17. The electronic device according to claim 16, in, The first transistor, the second transistor and the third transistor are respectively a first NMOS transistor, a second NMOS transistor and a third NMOS transistor, NMOS represents an N-channel MOS, and The second NMOS transistor is triggered by a source voltage of the first NMOS transistor.

18. The electronic device according to claim 16, in, The ESD detection circuit comprises: a capacitor coupled to the pad and the first node; and a first resistor coupled to the first node and the ground voltage, and The first node is coupled to the gate of the third transistor.

19. The electronic device according to claim 16, wherein: The bias generating circuit comprises: a second resistor coupled to the pad and a second node to cause a voltage drop by the ESD current to provide the bias voltage; and The first PMOS transistor and the second PMOS transistor are coupled to the second node and a power supply voltage, respectively, and PMOS represents a P-channel MOS.

20. The electronic device according to claim 19, in, The drain of the first PMOS transistor and the drain of the second PMOS transistor are coupled to a third node, The source of the first PMOS transistor is coupled to the second node. wherein the source of the second PMOS transistor is coupled to the power supply voltage, wherein the gate of the second PMOS transistor is coupled to the second node, and The third node is coupled to the gate of the first transistor.

Images