Three-level fault-tolerant converter and control method thereof

Abstract

The invention belongs to the technical field of power electronic current transformation, and particularly provides a three-level fault-tolerant converter and a control method thereof.The three-level fault-tolerant converter comprises a direct-current circuit, a current transformation circuit, a detection circuit and a control unit, the direct-current circuit comprises a supporting capacitor FC1 and a supporting capacitor FC2, the current transformation circuit comprises three parallel three-level bridge arms, and the three-level bridge arms are connected in parallel. Comprising an A-phase level bridge arm, a B-phase level bridge arm and a C-phase level bridge arm, each level bridge arm comprises an upper bridge arm, a lower bridge arm and a third bridge arm, the upper bridge arm, the lower bridge arm and the third bridge arm respectively comprise two insulated gate bipolar transistors which are connected in series, and the control ends of the insulated gate bipolar transistors are connected to the output end of the control unit; by adding the third bridge arm in each level bridge arm and combining the reconstruction of the corresponding driving signal, when the power element breaks down, the converter can continue to operate or at least temporarily operate, and necessary buffer time is provided for overall shutdown of the system.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic conversion, and in particular relates to a three-level fault-tolerant converter and a control method thereof. Background Art

[0002] In the field of power electronics, traditional three-level converters have been widely used in energy storage, wind power, electrical transmission and other industries due to their significant advantages in handling high voltage and high power. This type of converter effectively achieves efficient conversion and control of electric energy through a three-level structure, meeting the needs of many high-voltage and high-power application scenarios. However, with the increasing complexity of the three-level converter structure and the increasingly close integration of power modules, its failure rate during operation has also increased.

[0003] The structural complexity of the three-level converter is not only reflected in the fine design of its internal circuit, but also in the tight integration and interdependence of each power module. This complexity makes the converter more susceptible to various factors during operation, such as component aging, external interference, etc., which can lead to failures. In addition, as the operating life of the converter increases, its potential failure probability also shows a trend of increasing significantly.

[0004] After a converter failure, how to ensure that the system can continue to operate or at least operate for a short period of time to provide the necessary buffer time for the overall shutdown has become a key issue that needs to be urgently resolved in the current industry. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a three-level fault-tolerant converter and a control method thereof to solve the above-mentioned technical problems.

[0006] In a first aspect, the present invention provides a three-level fault-tolerant converter, comprising a DC circuit, a conversion circuit, a detection circuit, a drive unit and a control unit, wherein the DC circuit comprises a support capacitor FC1 and a support capacitor FC2, the conversion circuit comprises three parallel three-level bridge arms, comprising an A-phase level bridge arm, a B-phase level bridge arm and a C-phase level bridge arm, each level bridge arm comprises an upper bridge arm, a lower bridge arm and a third bridge arm, the upper bridge arm, the lower bridge arm and the third bridge arm respectively comprise two insulated gate bipolar transistors arranged in series, the insulated gate bipolar transistors are connected to the control unit through the drive unit, the first end of the upper bridge arm is connected to a DC positive bus, the first end of the lower bridge arm is connected to a DC negative bus, the second end of the upper bridge arm is connected to a second end of the lower bridge arm, the second end of the upper bridge arm and the second end of the lower bridge arm are connected at a connection point to an output end of the three-level fault-tolerant converter, the first end of the third bridge arm is connected to a center point of the upper bridge arm, and the second end of the third bridge arm is connected to a center point of the lower bridge arm; A first end of the supporting capacitor FC1 is connected to the DC positive bus, a first end of the supporting capacitor FC2 is connected to the DC negative bus, and a second end of the supporting capacitor FC1 and a second end of the supporting capacitor FC2 are both connected to the center point of the third bridge arm; The detection circuit is arranged at the output end of the three-level fault-tolerant converter, and performs three-phase voltage and three-phase current detection on the A-phase level bridge arm, the B-phase level bridge arm and the C-phase level bridge arm respectively, and transmits the detected three-phase voltage and three-phase current data to the input end of the control unit. The driving unit is used to detect the voltage signal of each insulated gate bipolar transistor, and transmits the detected voltage signal of each insulated gate bipolar transistor to the control unit. The control unit determines whether there is a fault on the conversion circuit according to the received voltage signals of each insulated gate bipolar transistor, and reconstructs the driving signal according to the received three-phase voltage and three-phase current data when it is determined that there is a fault, and sends the reconstructed driving signal to the remaining intact corresponding insulated gate bipolar transistors through the driving unit to control them to be turned on; during normal operation, the insulated gate bipolar transistor on the third bridge arm is in a disconnected state.

[0007] A further improvement of the technical solution is that it also includes a filtering circuit, and the connection point between the second end of the upper bridge arm and the second end of the lower bridge arm is connected to the output end of the three-level fault-tolerant converter through the filtering circuit.

[0008] A further improvement of the technical solution is that the filter circuit includes a filter inductor Lf and a filter capacitor Cf, the first end of the filter inductor Lf is connected to the connection point of the second end of the upper bridge arm and the second end of the lower bridge arm, the second end of the filter inductor Lf and the first end of the filter capacitor Cf are both connected to the output end of the three-level fault-tolerant converter, and the second end of the filter capacitor Cf is star-connected.

[0009] A further improvement of the technical solution is that the detection circuit includes a voltage sensor TVS and a current sensor TAS, the first end of the voltage sensor TVS is connected to the second end of the filter inductor Lf, the second end of the voltage sensor TVS is star-connected, and the current sensor TAS is arranged on the connection line between the second end of the filter inductor Lf and the output end of the three-level fault-tolerant converter.

[0010] In a second aspect, the present invention provides a control method for a three-level fault-tolerant converter, comprising: The detection circuit detects the voltage and current of the A-phase level bridge arm, the B-phase level bridge arm and the C-phase level bridge arm respectively, and transmits the detected three-phase voltage and three-phase current data to the control unit; The driving unit detects the voltage signal of each insulated gate bipolar transistor, and transmits the detected voltage signal of each insulated gate bipolar transistor to the control unit; The control unit determines whether there is a fault in the converter circuit according to the received voltage signals of each insulated gate bipolar transistor; If yes, the control unit reconstructs the driving signal according to the received three-phase voltage and three-phase current data, and controls the remaining intact corresponding insulated gate bipolar transistors to turn on through the reconstructed driving signal.

[0011] A further improvement of the technical solution is that before the control unit reconstructs the driving signal, it also includes: The control unit determines the fault location according to the received voltage signals of each insulated gate bipolar transistor, and determines the corresponding relationship between the reconstructed driving signal and the remaining intact insulated gate bipolar transistors according to the fault location.

[0012] A further improvement of the technical solution is that the method for reconstructing the driving signal is: The control unit performs Clarke coordinate transformation and Park coordinate transformation on the received three-phase voltage and current data to obtain a dq rotating coordinate system, and obtains dq axis positive sequence voltage and current components and dq axis negative sequence voltage and current components under the dq rotating coordinate system; In the dq rotating coordinate system, the positive sequence dq axis voltage component is controlled by PI to obtain the locking phase angle Teta and the voltage and current values ​​in the dq axis coordinates; Perform PI positive and negative sequence control on the current to obtain the voltage command increment value and the symmetrical output current at the same time; Feed-forward control of voltage increment; Perform voltage coordinate inverse transformation on the voltage after feedforward control to obtain the voltage horizontal coordinate component in the stationary two-phase coordinate system and the ordinate component ; For the voltage abscissa component in the two-phase coordinate system and the ordinate component Perform space vector modulation, generate three-phase PWM drive waveform, and set dead time; Output symmetrical current and symmetrical voltage after space vector modulation.

[0013] A further improvement of the technical solution is that the formula for feedforward control is: ; in, is the d-axis component command of the positive sequence voltage after feedforward, is the q-axis component command of the positive sequence voltage after feedforward, is the q-axis component command of the positive sequence voltage after feedforward, is the q-axis component command of the negative sequence voltage after feedforward, is the voltage increment of the d-axis component of the positive sequence voltage, is the voltage increment of the q-axis component of the positive sequence voltage, is the voltage increment of the d-axis component of the negative sequence voltage, is the voltage increment of the q-axis component of the negative sequence voltage, is the d-axis component of the positive sequence current, is the q-axis component of the positive sequence current, is the d-axis component of the negative sequence current, is the q-axis component of the negative sequence current, is the synchronous angular velocity, is the inductance value of the filter inductor Lf.

[0014] A further improvement of the technical solution is that the voltage horizontal coordinate component in the two-phase coordinate system and the ordinate component Perform space vector modulation, generate a three-phase PWM drive waveform, and set the dead time, the steps specifically include: The voltage space vector is defined, and the space voltage base vector diagram is obtained according to the switching state of the insulated gate bipolar transistor on the level bridge arm of the three-level fault-tolerant converter; Determine the sector where the space voltage base vector is located, and calculate the action time of the vector voltage in each sector of the space voltage base vector diagram according to the equivalent principle; According to different sectors, the three-phase modulation waves TmA, TmB, and TmC are obtained by looking up the table; A three-phase PWM drive waveform is generated according to the three-phase modulation waves TmA, TmB, and TmC, and a dead time is set.

[0015] A further improvement of the technical solution is that the voltage space vector is defined as: ; Among them, α=ej2π / 3 is the rotation factor; Uan, Ubn and Ucn are the three-phase voltages at the output port of the three-level fault-tolerant converter.

[0016] The beneficial effect of the present invention is that, by adding a third bridge arm in each horizontal bridge arm and combining the reconstruction of the corresponding drive signal, the present invention enables the converter to continue to operate or at least operate briefly when a power element fails, providing the necessary buffer time for the overall shutdown of the system, that is, the design of the third bridge arm allows the third bridge arm of the non-fault phase bridge arm and the fault phase bridge arm to work together by reconfiguring the drive signal in the case of a fault, thereby maintaining the basic function of the system. In addition, the control method of the present invention adopts Clarke coordinate transformation and Park coordinate transformation to convert the three-phase voltage and current data into components under the dq rotating coordinate system, which is convenient for PI control and feedforward control. Through PI positive and negative sequence control and feedforward control, the system can realize the accurate calculation of the voltage command increment value, thereby generating a symmetrical output current and a symmetrical voltage after space vector modulation. The present invention performs space vector modulation so that the system can generate an efficient three-phase PWM drive waveform and set a reasonable dead time, further improving the performance and efficiency of the system.

[0017] In addition, the invention has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 This is the circuit schematic diagram of the three-level fault-tolerant converter.

[0020] Figure 2 Schematic diagram of the control method.

[0021] Figure 3 This is the reconstructed power tube driving diagram.

[0022] Figure 4 The flowchart of Clarke coordinate transformation and Park coordinate transformation for the collected three-phase voltage and current data is shown in FIG.

[0023] Figure 5 In order to perform PI positive and negative sequence control on the current, a flow chart of the voltage command increment is obtained.

[0024] Figure 6 This is a flow chart for inversely transforming the voltage coordinates after feedforward control.

[0025] Figure 7 is the spatial voltage base vector diagram.

[0026] Figure 8 It is the time distribution diagram of the vector voltage in each sector.

[0027] Fig. 9 The waveform diagram of the symmetrical voltage and symmetrical current of the output. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0030] The key terms appearing in the present invention are explained below.

[0031] SVPWM (Space Vector Pulse Width Modulation) mainly uses the ideal stator flux circle of a three-phase symmetrical motor when powered by a three-phase symmetrical sinusoidal voltage as a reference standard, and appropriately switches the different switching modes of the three-phase inverter to form a PWM wave, and uses the actual flux vector formed to track its accurate flux circle. The traditional SPWM method starts from the perspective of power supply to generate a sine wave power supply with adjustable frequency and voltage, while the SVPWM method considers the inverter system and asynchronous motor as a whole. The model is relatively simple and is also convenient for real-time control of the microprocessor.

[0032] PI (proportional integral) control is a type of linear control that forms a control deviation based on a given value and an actual output value, and uses a linear combination of the proportion and integral of the deviation to form a control quantity to control the controlled object.

[0033] like Figure 1As shown, the present invention provides a three-level fault-tolerant converter, including a DC circuit, a conversion circuit, a detection circuit, a drive unit and a control unit. The DC circuit includes a support capacitor FC1 and a support capacitor FC2. The conversion circuit includes three parallel three-level bridge arms, including an A-phase level bridge arm, a B-phase level bridge arm and a C-phase level bridge arm. Each level bridge arm includes an upper bridge arm, a lower bridge arm and a third bridge arm. The upper bridge arm, the lower bridge arm and the third bridge arm respectively include two insulated gate bipolar transistors arranged in series. The insulated gate bipolar transistors are connected to the control unit through the drive unit. The first end of the upper bridge arm is connected to the DC positive bus, the first end of the lower bridge arm is connected to the DC negative bus, the second end of the upper bridge arm is connected to the second end of the lower bridge arm, the second end of the upper bridge arm and the second end of the lower bridge arm are connected at a connection point to the output end of the three-level fault-tolerant converter, the first end of the third bridge arm is connected to the center point of the upper bridge arm, and the second end of the third bridge arm is connected to the center point of the lower bridge arm; the first end of the support capacitor FC1 is connected to the DC positive bus, the support capacitor F The first end of C2 is connected to the DC negative bus, and the second end of the supporting capacitor FC1 and the second end of the supporting capacitor FC2 are both connected to the center point of the third bridge arm; the detection circuit is arranged at the output end of the three-level fault-tolerant converter, and the three-phase voltage and three-phase current are detected for the A-phase level bridge arm, the B-phase level bridge arm and the C-phase level bridge arm respectively, and the detected three-phase voltage and three-phase current data are transmitted to the input end of the control unit; the driving unit is used to detect the voltage signals of each insulated gate bipolar transistor, and transmit the detected voltage signals of each insulated gate bipolar transistor to the control unit; the control unit determines whether there is a fault on the converter circuit according to the received voltage signals of each insulated gate bipolar transistor, and reconstructs the driving signal according to the received three-phase voltage and three-phase current data when it is determined that there is a fault, and sends the reconstructed driving signal to the remaining intact corresponding insulated gate bipolar transistors through the driving unit to control them to be turned on; during normal operation, the insulated gate bipolar transistor on the third bridge arm is in a disconnected state.

[0034] Specifically, the positive and negative bus bars connect insulated gate bipolar transistors (power tubes) QA1, QA2, QA3, QA4, QA5, QA6, QB1, QB2, QB3, QB4, QB5, QB6, QC1, QC2, QC3, QC4, QC5 and QC6.

[0035] When in use, the two insulated gate bipolar transistors connected in series on the upper bridge arm are packaged as one device, the two insulated gate bipolar transistors connected in series on the lower bridge arm are packaged as one device, and the two insulated gate bipolar transistors connected in series on the third bridge arm are packaged as one device; when any packaged device fails, the bridge arm will be in an open circuit state.

[0036] In order to improve the waveform quality of the output voltage, the present invention is provided with a filter circuit, and the second end of the upper bridge arm and the second end of the lower bridge arm are connected to the output end of the three-level fault-tolerant converter through the filter circuit. Specifically, the filter circuit includes a filter inductor Lf and a filter capacitor Cf, the first end of the filter inductor Lf is connected to the second end of the upper bridge arm and the second end of the lower bridge arm The connection point, the second end of the filter inductor Lf and the first end of the filter capacitor Cf are both connected to the output end of the three-level fault-tolerant converter, and the second end of the filter capacitor Cf is star-connected. The design of the filter circuit reduces the harmonic content and enhances the stability and reliability of the system.

[0037] Specifically, the detection circuit includes a voltage sensor TVS and a current sensor TAS, the first end of the voltage sensor TVS is connected to the second end of the filter inductor Lf, the second end of the voltage sensor TVS is star-connected, and the current sensor TAS is arranged on the line between the second end of the filter inductor Lf and the output end of the three-level fault-tolerant converter.

[0038] like Figure 2 As shown, the present invention provides a control method for a three-level fault-tolerant converter, comprising: Step 210, the detection circuit performs voltage and current detection on the A-phase level bridge arm, the B-phase level bridge arm, and the C-phase level bridge arm, respectively, and transmits the detected three-phase voltage and three-phase current data to the control unit; Step 220, the driving unit detects the voltage signal of each insulated gate bipolar transistor, and transmits the detected voltage signal of each insulated gate bipolar transistor to the control unit; Step 230, the control unit determines whether there is a fault in the converter circuit according to the received voltage signals of each insulated gate bipolar transistor; if so, go to step 240; Step 240: The control unit reconstructs the drive signal according to the received three-phase voltage and three-phase current data, and controls the remaining intact corresponding insulated gate bipolar transistors to turn on through the reconstructed drive signal.

[0039] In addition, before the control unit reconstructs the driving signal, it also includes: the control unit determines the fault location according to the received voltage signals of each insulated gate bipolar transistor, and determines the corresponding relationship between the reconstructed driving signal and the remaining intact insulated gate bipolar transistors according to the fault location. Among them, the driving unit can determine whether a short circuit fault occurs in the power tube by detecting the voltage between the main emitter and the auxiliary emitter of the power tube. Specifically, there is a parasitic inductance L of the power tube itself between the main emitter and the auxiliary emitter of the power tube. PE , the induced voltage U at both ends L =-L PE di / dt, if the power tube is short-circuited, it will cause a large induced voltage U L, when the induced voltage U L If it exceeds a certain threshold, it can be determined that the power tube is faulty, and the fault location corresponding to the faulty power tube can also be determined.

[0040] The remaining intact (available) insulated gate bipolar transistors (power tubes) are used to re-modulate SVPWM, so that the three-level fault-tolerant converter after the fault generates a symmetrically rotating three-phase voltage, ensuring that the three-level fault-tolerant converter can continue to operate or at least operate briefly. If the fault location in the three-level fault-tolerant converter is determined to be QC1 and QC2 on the upper bridge arm of the C-phase level bridge arm, the corresponding relationship between the drive signal and the corresponding insulated gate bipolar transistor (power tube) obtained by looking up Table 1 is obtained at the same time as Figure 3 The reconstructed power tube driver diagram is shown.

[0041] Table 1 is a table showing the corresponding relationship between the driving signal and each insulated gate bipolar transistor

[0042] Specifically, the method for reconstructing the driving signal is: S231, the control unit performs Clarke coordinate transformation and Park coordinate transformation on the received three-phase voltage and current data to obtain a dq rotating coordinate system, and obtains dq axis positive sequence voltage and current components and dq axis negative sequence voltage and current components under the dq rotating coordinate system; S232, in the dq rotating coordinate system, PI control is performed on the positive sequence dq axis voltage component to obtain the locking phase angle Teta and the voltage and current values ​​in the dq axis coordinates; S233, performing PI positive and negative sequence control on the current to obtain a voltage command increment value and a symmetrical output current; S234, performing feedforward control on the voltage increment; S235, perform voltage coordinate inverse transformation on the voltage after feedforward control to obtain the voltage horizontal coordinate component in the stationary two-phase coordinate system and the ordinate component ; S236, voltage horizontal coordinate component in two-phase coordinate system and the ordinate component Perform space vector modulation, generate three-phase PWM drive waveform, and set dead time; S237, output symmetrical current and symmetrical voltage after space vector modulation.

[0043] like Figure 4As shown, the collected three-phase voltage and current data are transformed by Clarke coordinates (3s / 2s) and Park coordinates (2s / 2d), and the dq axis positive sequence voltage and current components and the dq axis negative sequence voltage and current components under the dq rotating coordinates are obtained, which are Figure 4 In: is the d-axis component of the positive sequence voltage, is the q-axis component of the positive sequence voltage, is the d-axis component of the negative sequence voltage, is the q-axis component of the negative sequence voltage, is the d-axis component of the positive sequence current, is the q-axis component of the positive sequence current, is the d-axis component of the negative sequence current, is the q-axis component of the negative-sequence current; at the same time, in the dq rotating coordinate system, the positive-sequence dq-axis voltage component is controlled by PI to obtain the locked phase angle Teta (Teta is the angle between the stationary coordinate and the rotating coordinate) and the voltage and current values ​​under the dq-axis coordinates; among them, Kp_pll, ki_pll, and s in the PI control are the phase-locked proportional coefficient, integral coefficient, and Laplace operator, respectively; Mod is the remainder calculation, where ω is the synchronous angular velocity, and its value is 628rad / s.

[0044] In addition, in order to control in both positive and negative sequence dimensions, a notch filter is used. Gs (s) is a notch filter. ,in, ; where ωc is the center frequency, is the damping ratio; s is the Laplace operator.

[0045] Afterwards, if Figure 5 As shown, the current is controlled by PI positive and negative sequence to obtain the voltage command increment value and the symmetrical output current; Furthermore, the voltage increment is feedforward controlled, and the feedforward control formula is: ; in, is the d-axis component command of the positive sequence voltage after feedforward, is the q-axis component command of the positive sequence voltage after feedforward, is the q-axis component command of the positive sequence voltage after feedforward, is the q-axis component command of the negative sequence voltage after feedforward, is the voltage increment of the d-axis component of the positive sequence voltage, is the voltage increment of the q-axis component of the positive sequence voltage, is the voltage increment of the d-axis component of the negative sequence voltage, is the voltage increment of the q-axis component of the negative sequence voltage, is the d-axis component of the positive sequence current, is the q-axis component of the positive sequence current, is the d-axis component of the negative sequence current, is the q-axis component of the negative sequence current, is the synchronous angular velocity, is the inductance value of the filter inductor Lf.

[0046] Then, if Figure 6 As shown, the voltage coordinates are inversely transformed after feedforward control (2d / 2s is the inverse transformation of park) to obtain the voltage horizontal coordinate components in the stationary two-phase coordinate system. and the ordinate component .

[0047] Furthermore, for the voltage horizontal component in the two-phase coordinate system and the ordinate component Perform space vector modulation, generate a three-phase PWM drive waveform, and set the dead time, the steps specifically include: S2361, defining a voltage space vector, and obtaining a space voltage base vector diagram according to the switching state of the insulated gate bipolar transistor on the level bridge arm of the three-level fault-tolerant converter; S2362, determining the sector where the spatial voltage base vector is located, and calculating the action time of the vector voltage in each sector in the spatial voltage base vector diagram according to the equivalent principle; S2363, according to different sectors, look up the table to obtain three-phase modulation waves TmA, TmB, TmC; S2364. Generate a three-phase PWM drive waveform according to the three-phase modulation waves TmA, TmB, and TmC, and set the dead time.

[0048] Wherein, the voltage space vector is defined as: ; Among them, α=ej2π / 3 is the rotation factor; Uan, Ubn and Ucn are the three-phase voltages at the output port of the three-level fault-tolerant converter.

[0049] According to the fault location (the switching state of the insulated gate bipolar transistor on the level bridge arm of the three-level fault-tolerant converter), the available space voltage basis vectors V0-V7 are obtained, a total of 7, and the symmetric space voltage basis vectors are selected to construct the space voltage basis vector, such as Figure 7 As shown, Sa is 1, indicating that QA1 and QA2 are closed, and 0 indicates that QA3 and QA4 are closed; similarly, Sb is 1, indicating that QB1 and QB2 are closed, and 0 indicates that QB3 and QB4 are closed. Sc is 1, indicating that QC3 and QC4 are closed, and 0 indicates that QC5 and QC6 are closed (assuming that QC1 and QC2 are faulty). At the same time, the sector where the spatial voltage base vector is located is determined based on: >0 and >0, in sec1; >0 and <0, in sec3; <0 and >0, in sec4; <0 and >0, in sec2.

[0050] In addition, when the space voltage base vector is in different sectors, the action time of the vector voltage in each sector in the space voltage base vector is calculated according to the equivalent principle, such as Figure 8 shown.

[0051] Specifically, according to the principle of acting on adjacent vectors in the corresponding sector, the equivalent mode of base vector voltage action time is: ; In addition, according to the equivalent principle, T1 and T2 can be expressed as: Among them, U α , U β are the voltage instructions converted from A / B / C / to α and β coordinates, T1 / T2 is the action time of the vector voltage in each sector, T is a carrier cycle, VX and Vy are the base voltage vectors corresponding to the current sector, and Udc is the DC side voltage amplitude. In order to reduce the switching loss of the switch, a 5-segment symmetrical distribution method is adopted. The action time distribution of different vectors in the switching cycle is as follows: Figure 8 shown.

[0052] Afterwards, according to different sectors, three-phase modulation waves TmA, TmB, and TmC are obtained by looking up Table 2.

[0053] Table 2 is the corresponding relationship between different sectors and three-phase modulation waves based on the switching cycle Tpwm

[0054] Among them, numerically, the switching period Tpwm=T.

[0055] The formula for generating three-phase PWM drive waveforms (TA1, TA2, TB1, TB2, TC1, TC2) based on the three-phase modulation waves TmA, TmB, and TmC is: ; ; Among them, Tcarry is the triangle wave period; Dead_delay is the dead time setting function, which is realized by the counter in the control unit.

[0056] Specifically, the current is controlled by PI positive and negative sequence to obtain a symmetrical output current, and the method is as follows: Negative sequence current control command is 0: ; Positive sequence current control command calculation steps: ; ; Where S is the complex power; is the voltage component under the stationary α and β coordinates; i αβ is the current component in the stationary α and β coordinates; is the positive sequence voltage component of the dq coordinate axis; is the negative sequence voltage component of the dq coordinate axis; is the positive sequence current component of the dq coordinate axis; is the negative sequence current component of the dq coordinate axis; , are the positive sequence current instructions of dq axis respectively; p0* and q0* are the average active power value and the average reactive power value respectively; udp and uqp are the positive sequence current values ​​of dq axis.

[0057] Based on the above control method, the output is as follows Fig. 9 Symmetrical voltage and current (normalized) are shown.

[0058] Although the present invention has been described in detail with reference to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person of ordinary skill in the art may easily think of changes or substitutions within the technical scope disclosed by the present invention, and these shall be within the scope of protection of the present invention.

Claims

1. A three-level fault-tolerant converter, characterized in that: It comprises a direct current circuit, a current conversion circuit, a detection circuit, a drive unit and a control unit, wherein the direct current circuit comprises a support capacitor FC1 and a support capacitor FC2, the current conversion circuit comprises three parallel three-level bridge arms, comprising an A-phase level bridge arm, a B-phase level bridge arm and a C-phase level bridge arm, each level bridge arm comprises an upper bridge arm, a lower bridge arm and a third bridge arm, the upper bridge arm, the lower bridge arm and the third bridge arm respectively comprise two insulated gate bipolar transistors arranged in series, the insulated gate bipolar transistors are connected to the control unit through the drive unit, the first end of the upper bridge arm is connected to a direct current positive bus, the first end of the lower bridge arm is connected to a direct current negative bus, the second end of the upper bridge arm is connected to a second end of the lower bridge arm, the second end of the upper bridge arm and the second end of the lower bridge arm are connected at a connection point to an output end of the three-level fault-tolerant converter, the first end of the third bridge arm is connected to a central point of the upper bridge arm, and the second end of the third bridge arm is connected to a central point of the lower bridge arm; A first end of the supporting capacitor FC1 is connected to the DC positive bus, a first end of the supporting capacitor FC2 is connected to the DC negative bus, and a second end of the supporting capacitor FC1 and a second end of the supporting capacitor FC2 are both connected to the center point of the third bridge arm; The detection circuit is arranged at the output end of the three-level fault-tolerant converter, and performs three-phase voltage and three-phase current detection on the A-phase level bridge arm, the B-phase level bridge arm and the C-phase level bridge arm respectively, and transmits the detected three-phase voltage and three-phase current data to the input end of the control unit. The driving unit is used to detect the voltage signal of each insulated gate bipolar transistor, and transmits the detected voltage signal of each insulated gate bipolar transistor to the control unit. The control unit determines whether there is a fault on the converter circuit according to the received voltage signals of each insulated gate bipolar transistor, and reconstructs the driving signal according to the received three-phase voltage and three-phase current data when it is determined that there is a fault, and sends the reconstructed driving signal to the remaining intact corresponding insulated gate bipolar transistors through the driving unit to control them to be turned on; during normal operation, the insulated gate bipolar transistor on the third bridge arm is in a disconnected state.

2. The three-level fault-tolerant converter according to claim 1, characterized in that: It also includes a filtering circuit, and the connection point between the second end of the upper bridge arm and the second end of the lower bridge arm is connected to the output end of the three-level fault-tolerant converter through the filtering circuit.

3. The three-level fault-tolerant converter according to claim 2, characterized in that: The filtering circuit includes a filtering inductor Lf and a filtering capacitor Cf, wherein the first end of the filtering inductor Lf is connected to a connection point between the second end of the upper bridge arm and the second end of the lower bridge arm, the second end of the filtering inductor Lf and the first end of the filtering capacitor Cf are both connected to the output end of the three-level fault-tolerant converter, and the second end of the filtering capacitor Cf is star-connected.

4. The three-level fault-tolerant converter according to claim 3, characterized in that: The detection circuit includes a voltage sensor TVS and a current sensor TAS, the first end of the voltage sensor TVS is connected to the second end of the filter inductor Lf, the second end of the voltage sensor TVS is star-connected, and the current sensor TAS is arranged on the connection line between the second end of the filter inductor Lf and the output end of the three-level fault-tolerant converter.

5. A control method for a three-level fault-tolerant converter, characterized in that: include: The detection circuit detects the voltage and current of the A-phase level bridge arm, the B-phase level bridge arm and the C-phase level bridge arm respectively, and transmits the detected three-phase voltage and three-phase current data to the control unit; The driving unit detects the voltage signal of each insulated gate bipolar transistor, and transmits the detected voltage signal of each insulated gate bipolar transistor to the control unit; The control unit determines whether there is a fault in the converter circuit according to the received voltage signals of each insulated gate bipolar transistor; If yes, the control unit reconstructs the driving signal according to the received three-phase voltage and three-phase current data, and controls the remaining intact corresponding insulated gate bipolar transistors to turn on through the reconstructed driving signal.

6. The control method of the three-level fault-tolerant converter according to claim 5, characterized in that: Before the control unit reconstructs the driving signal, the following steps are also included: The control unit determines the fault location according to the received voltage signals of each insulated gate bipolar transistor, and determines the corresponding relationship between the reconstructed driving signal and the remaining intact insulated gate bipolar transistors according to the fault location.

7. The control method of the three-level fault-tolerant converter according to claim 6, characterized in that: The method to reconstruct the driving signal is: The control unit performs Clarke coordinate transformation and Park coordinate transformation on the received three-phase voltage and current data to obtain a dq rotating coordinate system, and obtains dq axis positive sequence voltage and current components and dq axis negative sequence voltage and current components under the dq rotating coordinate system; In the dq rotating coordinate system, the positive sequence dq axis voltage component is controlled by PI to obtain the locking phase angle Teta and the voltage and current values ​​in the dq axis coordinates; Perform PI positive and negative sequence control on the current to obtain the voltage command increment value and the symmetrical output current at the same time; Feed-forward control of voltage increment; Perform voltage coordinate inverse transformation on the voltage after feedforward control to obtain the voltage horizontal coordinate component in the stationary two-phase coordinate system and the ordinate component ; For the voltage horizontal component in the two-phase coordinate system and the ordinate component Perform space vector modulation, generate three-phase PWM drive waveform, and set dead time; Output symmetrical current and symmetrical voltage after space vector modulation.

8. The control method of the three-level fault-tolerant converter according to claim 7, characterized in that: The formula for feedforward control is: ； in, is the d-axis component command of the positive sequence voltage after feedforward, is the q-axis component command of the positive sequence voltage after feedforward, is the q-axis component command of the positive sequence voltage after feedforward, is the q-axis component command of the negative sequence voltage after feedforward, is the voltage increment of the d-axis component of the positive sequence voltage, is the voltage increment of the q-axis component of the positive sequence voltage, is the voltage increment of the d-axis component of the negative sequence voltage, is the voltage increment of the q-axis component of the negative sequence voltage, is the d-axis component of the positive sequence current, is the q-axis component of the positive sequence current, is the d-axis component of the negative sequence current, is the q-axis component of the negative sequence current, is the synchronous angular velocity, is the inductance value of the filter inductor Lf.

9. The control method of the three-level fault-tolerant converter according to claim 7, characterized in that: For the voltage horizontal component in the two-phase coordinate system and the ordinate component Perform space vector modulation, generate a three-phase PWM drive waveform, and set the dead time, the steps specifically include: The voltage space vector is defined, and the space voltage base vector diagram is obtained according to the switching state of the insulated gate bipolar transistor on the level bridge arm of the three-level fault-tolerant converter; Determine the sector where the space voltage base vector is located, and calculate the action time of the vector voltage in each sector of the space voltage base vector diagram according to the equivalent principle; According to different sectors, the three-phase modulation waves TmA, TmB, and TmC are obtained by looking up the table; A three-phase PWM drive waveform is generated according to the three-phase modulation waves TmA, TmB, and TmC, and a dead time is set.

10. The control method of the three-level fault-tolerant converter according to claim 9, characterized in that: The voltage space vector is defined as: ； Among them, α=ej2π / 3 is the rotation factor; Uan, Ubn and Ucn are the three-phase voltages at the output port of the three-level fault-tolerant converter.

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