Voltage conversion circuit

Abstract

The invention relates to a voltage conversion circuit. The voltage conversion circuit comprises a first type voltage converter, a second type voltage converter and a controller, the controller is connected to the output end of the first type voltage converter and the output end of the second type voltage converter. The voltage conversion circuit can operate in different modes (modes). In the standby mode, the controller takes a voltage conversion signal level output by a voltage converter as an output signal level of the voltage conversion circuit. In the non-standby mode, the controller takes the voltage conversion signal level output by the second-type voltage converter as the output signal level of the voltage conversion circuit.

Description

Technical Field

[0001] The present invention relates to a level shifting circuit, and more particularly to a level shifting circuit capable of operating in different modes. Background Art

[0002] Generally speaking, there are different power domains in an IC chip, and the circuits in different power domains receive different power voltages. For example, the power voltage of the first power domain is Vdd1, and the power voltage of the second power domain is Vdd2, and the power voltage Vdd1 is different from the power voltage Vdd2. Furthermore, the signals between different power domains need to be converted using a level shifter so that the circuits in different power domains can communicate normally.

[0003] For example, in the first power domain, the logic high level (logic hilevel) of the signals of all circuit operations is the power voltage Vdd1, and the logic low level (logic low level) is the ground voltage GND. In the second power domain, the logic high level of the signals of all circuit operations is the power voltage Vdd2, and the logic low level is the ground voltage GND.

[0004] Furthermore, the voltage converter can convert the logic high level (ie, Vdd1) in the first power domain into the logic high level (ie, Vdd2) in the second power domain. The voltage converter can also convert the logic low level (ie, GND) in the first power domain into the logic low level (ie, GND) in the second power domain.

[0005] In addition, in order to reduce the power consumption of the IC chip, the IC chip can provide various mode signals to set different modes according to its operating conditions. For example, a standby signal is a mode signal. When the standby signal is at a first logic level, the IC chip is in a standby mode. When the standby signal is at a second logic level, the IC chip is in a non-standby mode, or a chip enable mode.

[0006] In the standby mode, the standby signal is at the first logic level. At this time, only a small part of the circuits in the power domain with the lower power voltage Vdd1 operate. Furthermore, the voltage converter transmits the standby signal to the power domain with the higher power voltage Vdd2, so that the circuits in the power domain stop operating.

[0007] In non-standby mode, the standby signal is at the second logic level. At this time, the circuits in the power domain with the lower power supply voltage Vdd1 operate normally. Furthermore, the voltage converter transmits the standby signal to the power domain with the higher power supply voltage Vdd2, so that the circuits in the power domain operate normally. Summary of the invention

[0008] The present invention relates to a voltage conversion circuit having a first input terminal and a first output terminal, wherein the first input terminal of the voltage conversion circuit receives a first mode signal of a first power domain, and the first output terminal of the voltage conversion circuit outputs a converted first mode signal of a second power domain, wherein the first power domain is different from the second power domain, and the voltage conversion circuit comprises: a first type one voltage converter, wherein an input terminal of the first type one voltage converter is coupled to the first input terminal of the voltage conversion circuit; wherein the input terminal of the first type one voltage converter receives the first mode signal, and an output terminal of the first type one voltage converter outputs a first converted signal of the second power domain; and a first type two voltage converter, wherein an input terminal of the first type two voltage converter is coupled to the first input terminal of the voltage conversion circuit; wherein the input terminal of the first type two voltage converter receives the first mode signal, and an output terminal of the first type two voltage converter outputs a second converted signal of the second power domain; wherein the first type two voltage converter comprises a first a bias circuit, and the first bias circuit receives at least one bias voltage for normal operation; and a controller coupled to the output end of the first type one converter and the output end of the first type two converter; wherein, in a standby mode, the first mode signal is a first logic level; the controller disables the first type two converter, and the controller does not provide the at least one bias voltage to the first bias circuit of the first type two converter; and, according to the first conversion signal of the first logic level, the controller outputs the conversion first mode signal of the first logic level; wherein, in a non-standby mode, the first mode signal is a second logic level; the controller ignores the first conversion signal output by the first type one converter; the controller provides the at least one bias voltage to the first bias circuit of the first type two converter; and, according to the second conversion signal of the second logic level, the controller outputs the conversion first mode signal of the second logic level.

[0009] In order to better understand the above and other aspects of the present invention, the following is a detailed description of preferred embodiments with reference to the accompanying drawings as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is an example of a type 1 converter;

[0011] Figure 2AAnother example of a type 1 converter;

[0012] Figure 2B for Figure 2A A schematic diagram of related signals of a type 1 converter;

[0013] Figure 3 It is an example of a type 2 converter;

[0014] Figure 4 Another example of a type 2 converter;

[0015] Figure 5A The voltage conversion circuit of the first embodiment of the present invention;

[0016] Figure 5B This is a schematic diagram of related signals of the voltage conversion circuit of the first embodiment;

[0017] Fig. 6A The voltage conversion circuit of the second embodiment of the present invention;

[0018] Figure 6B is a schematic diagram of related signals of a voltage conversion circuit according to a second embodiment of the present invention; and

[0019] Figure 7 This is the third embodiment of the voltage conversion circuit of the present invention.

[0020]

Explanation of symbols

[0021] 100, 200: Type-1 Converter

[0022] 105: Inverter

[0023] 300, 400: Type 2 transformer

[0024] 310, 410: Bias circuit

[0025] 500, 600: Converter circuit

[0026] 510: Type 1 - Transformer

[0027] 520: Type I Dual Converter

[0028] 530, 630: Latch

[0029] 540, 640: OR gate

[0030] 550: Bias voltage generator

[0031] 560: Delay element

[0032] 590, 690, 790: Controller

[0033] 610: Second Type - Transformer

[0034] 620: Type II Dual Converter

[0035] 750: AND Gate DETAILED DESCRIPTION

[0036] The present invention proposes a voltage conversion circuit that can operate in different modes. The voltage conversion circuit includes at least two different types of voltage converters (level shifters). The first type of voltage converter (first-type level shifter) does not include a bias circuit inside, while the second type of voltage converter (second-type level shifter) includes a bias circuit inside. The various voltage converters are first introduced below.

[0037] Please refer to Figure 1 , which is an example of a type 1 converter. This type 1 converter 100 can convert an input signal IN and an inverted input signal ZIN whose signal range is between a voltage Vdd1 and GND into an output signal OUT and an inverted output signal ZOUT whose signal range is between a voltage Vdd2 and GND. Wherein, Vdd1 is a power supply voltage, Vdd2 is another power supply voltage, and GND is a ground voltage. For example, the power supply voltage Vdd1 is greater than the power supply voltage Vdd2, the power supply voltage Vdd1 is 1V, the power supply voltage Vdd2 is 5V, and the ground voltage GND is 0V. Furthermore, the input signal IN and the inverted input signal ZIN are complementary signals, and the output signal OUT and the inverted output signal ZOUT are complementary signals.

[0038] The type-one converter 100 includes an inverter 105, a P-type transistor MP1, a P-type transistor MP2, an N-type transistor MN1, and an N-type transistor MN2. Furthermore, the type-one converter 100 has at least an input terminal and an output terminal. The input terminal of the type-one converter 100 receives an input signal IN, and the output terminal of the type-one converter 100 can generate an output signal OUT.

[0039] The inverter 105 is connected to a power supply voltage Vdd1 and a ground voltage GND. An input terminal of the inverter 105 is connected to an input terminal of the type-one converter 100 to receive an input signal IN. An output terminal of the inverter 105 generates an inverted input signal ZIN.

[0040] The source of the P-type transistor MP1 receives the power supply voltage Vdd2, the drain is connected to the node a, and the gate is connected to the node b. In addition, the source of the P-type transistor MP2 receives the power supply voltage Vdd2, the drain is connected to the node b, and the gate is connected to the node a.

[0041] The drain of the N-type transistor MN1 is connected to the node a, the source receives the ground voltage GND, and the gate receives the input signal IN. In addition, the drain of the N-type transistor MN2 is connected to the node b, the source receives the ground voltage GND, and the gate receives the inverted input signal ZIN. Among them, the node b is connected to the output terminal of the type-one converter 100, which can generate the output signal OUT. In addition, the node a can also be used as another output terminal of the type-one converter 100 to generate the inverted output signal ZOUT.

[0042] When the input signal IN of the type-one converter 100 is at a logic high level (i.e., the power supply voltage Vdd1) and the inverting input signal ZIN is at a logic low level (i.e., 0V), the N-type transistor MN1 and the P-type transistor MP2 are turned on, and the N-type transistor MN2 and the P-type transistor MP1 are turned off. Therefore, the output signal OUT is at a logic high level (i.e., the power supply voltage Vdd2), and the inverting output signal ZOUT is at a logic low level (i.e., 0V).

[0043] When the input signal IN of the type-one converter 100 is at a logic low level (i.e., 0V) and the inverting input signal ZIN is at a logic high level (i.e., the power supply voltage Vdd1), the N-type transistor MN1 and the P-type transistor MP2 are turned off, and the N-type transistor MN2 and the P-type transistor MP1 are turned on. Therefore, the output signal OUT is at a logic low level (i.e., 0V), and the inverting output signal ZOUT is at a logic high level (i.e., the power supply voltage Vdd2).

[0044] From the above description, it can be known that the type 1 converter 100 can convert the logic high level of the power supply voltage Vdd1 into the logic high level of the power supply voltage Vdd2. The type 1 converter 100 can convert the logic low level of the ground voltage GND into the logic low level of the ground voltage. In other words, the output signal OUT is the shifted signal of the input signal IN.

[0045] Please refer to Figure 2A, which is another example of a type-one converter. The type-one converter 200 includes: an inverter 105, a P-type transistor MP1, a P-type transistor MP2, a P-type transistor MP3, a P-type transistor MP4, an N-type transistor MN1, and an N-type transistor MN2. Furthermore, the type-one converter 200 has at least an input terminal and an output terminal. The input terminal of the type-one converter 200 receives an input signal IN, and the output terminal of the type-one converter 200 generates an output signal OUT.

[0046] The inverter 105 is connected to a power supply voltage Vdd1 and a ground voltage GND. An input terminal of the inverter 105 is connected to an input terminal of the type-one converter 200 to receive an input signal IN. An output terminal of the inverter 105 generates an inverted input signal ZIN.

[0047] The source of the P-type transistor MP1 receives the power supply voltage Vdd2, the drain is connected to the node a, and the gate is connected to the node d. The source of the P-type transistor MP2 receives the power supply voltage Vdd2, the drain is connected to the node b, and the gate is connected to the node c. The source of the P-type transistor MP3 is connected to the node a, the drain is connected to the node c, and the gate receives the input signal IN. The source of the P-type transistor MP4 is connected to the node b, the drain is connected to the node d, and the gate receives the inverted input signal ZIN.

[0048] Furthermore, the drain of the N-type transistor MN1 is connected to the node c, the source receives the ground voltage GND, and the gate receives the input signal IN. The drain of the N-type transistor MN2 is connected to the node d, the source receives the ground voltage GND, and the gate receives the inverted input signal ZIN. The node d is connected to the output terminal of the type-one converter 200 to generate the output signal OUT. In addition, the node c can also be used as another output terminal of the type-one converter 200 to generate the inverted output signal ZOUT.

[0049] When the input signal IN of the type-one converter 200 is at a logic high level (i.e., the power supply voltage Vdd1) and the inverting input signal ZIN is at a logic low level (i.e., 0V), the N-type transistor MN1, the P-type transistor MP2, and the P-type transistor MP4 are turned on, and the N-type transistor MN2, the P-type transistor MP1, and the P-type transistor MP3 are turned off. Therefore, the output signal OUT is at a logic high level (i.e., the power supply voltage Vdd2), and the inverting output signal ZOUT is at a logic low level (i.e., 0V).

[0050] When the input signal IN of the type 1 converter 200 is a logic low level (i.e., 0V) and the inverted input signal ZIN is a logic high level (i.e., power supply voltage Vdd1), the N-type transistor MN1, the P-type transistor MP2, and the P-type transistor MP4 are turned off, and the N-type transistor MN2, the P-type transistor MP1, and the P-type transistor MP3 are turned on. Therefore, the output signal OUT is a logic low level (i.e., 0V), and the inverted output signal ZOUT is a logic high level (i.e., power supply voltage Vdd2). In other words, the output signal OUT is a shifted signal of the input signal IN.

[0051] Generally speaking, today's CMOS process can provide different processes for the voltage operating range of transistors. For example, the medium voltage device (MV device) process can be used to manufacture transistors that can withstand higher voltage stress, and the threshold voltage of the transistor has a larger magnitude, and the manufactured transistor is suitable for medium voltage operation. In addition, the low voltage device (LV device) process can be used to manufacture transistors that can withstand lower voltage stress, and the threshold voltage of the transistor has a smaller magnitude, and the manufactured transistor is suitable for low voltage operation. For example, the voltage stress range that the transistor of the medium voltage device can withstand is approximately between 3.0V and 10V. The voltage stress range that the transistor of the low voltage device can withstand is approximately between 0.8V and 2.0V.

[0052] by Figure 2A The type-to-type converter 200 is used as an example. When the N-type transistor MN1 is turned off, the drain and source of the N-type transistor MN1 will be subjected to the voltage stress of the power supply voltage Vdd2 (i.e., 5V). Similarly, when the N-type transistor MN2 is turned off, the drain and source of the N-type transistor MN2 will be subjected to the voltage stress of the power supply voltage Vdd2 (i.e., 5V). In other words, in the design Figure 2A When the type-1 converter 200 is used, the two N-type transistors MN1 and MN2 need to be designed as medium-voltage devices to withstand higher voltage stress, and the four P-type transistors MP1 to MP4 are also medium-voltage devices. Figure 1The two N-type transistors MN1 and MN2 and the two P-type transistors MP1 and MP2 in the type 1 converter 100 also need to be designed as medium voltage devices capable of withstanding higher voltage stress.

[0053] However, when the power supply voltage Vdd1 is set to a relatively low voltage and close to the threshold voltage of the N-type transistors MN1 and MN2, the converter designed with medium voltage components may cause malfunction. Figure 2B , which is shown as Figure 2A Schematic diagram of related signals of a type 1 converter. In the type 1 converter 200, the logic high level of the first power domain is Vdd1 (1V), and the two N-type transistors MN1 and MN2 are medium voltage devices, which have a higher threshold voltage Vt1, such as 0.9V. In other words, the logic high level of the first power domain (Vdd, 1V) is only slightly greater than the threshold voltage (Vt1, 0.9V) of the N-type transistor MN1.

[0054] like Figure 2B As shown, at time point t A When the gate of the N-type transistor MN1 receives the input signal IN of the logic high level (Vdd1), the source receives the ground voltage GND (0V), and the gate-source voltage (gate-source voltage, V GS ) is 1V (ie, 1V-0V), which is greater than the threshold voltage Vt1 (0.9V), so that the N-type transistor MN1 is turned on and the output signal OUT is a logic high level (Vdd2).

[0055] At time point t B When the gate of the N-type transistor MN1 receives the input signal IN of the logic low level (0V), the gate-source voltage V GS is 0V (ie, 0V-0V), which is less than the threshold voltage Vt1 (0.9V), so that the N-type transistor MN1 is turned off and the output signal OUT is a logic low level (0V).

[0056] However, when the total current generated during the operation of the IC chip is large, it may cause disturbance of the ground voltage GND. Figure 2B As shown, at time point t C Afterwards, the gate of the N-type transistor MN1 receives the input signal IN of a logic high level (Vdd1). Theoretically, the output signal OUT should be a logic high level (Vdd2).

[0057] However, at time t C To time point t ZA ground voltage GND disturbance occurs between t and t, and the ground voltage GND changes up and down, for example, between 0V and 0.2V. For example, at time point t D With time point t E The ground voltage GND rises by more than 0.1V, causing the gate-source voltage V GS When the voltage is less than 0.9V, that is, lower than the threshold voltage (Vt1, 0.9V), the N-type transistor MN1 is turned off, causing the node c to become floating and possibly coupled to a high voltage level through other signals, thereby affecting the output signal OUT, causing the output signal OUT to be coupled to a logic low level. E With time point t F The ground voltage GND is lower than 0.1V, so that the gate-source voltage V GS When the voltage is greater than 0.9V, that is, greater than the threshold voltage (Vt1, 0.9V), the N-type transistor MN1 is turned on and the output signal OUT becomes a logic high level. Figure 2B As shown, at time point t C To time point t Z In the meantime, a glitch may be generated in the output signal OUT, causing the type-one converter 200 to malfunction.

[0058] Since the N-type transistors MN1 and MN2 in the above-mentioned type 1 converter 100 and 200 are medium voltage components with a relatively high threshold voltage, the type 1 converter 100 and 200 can operate normally when there is no ground voltage GND disturbance inside the IC chip. However, when there is a ground voltage GND disturbance inside the IC chip, the type 1 converter 100 and 200 may not operate normally.

[0059] In order to solve the above problem, a low-voltage element with a lower threshold voltage can be used to design the voltage converter. For example, the N-type transistor MN1 and the N-type transistor MN2 are low-voltage elements, and their threshold voltages are, for example, 0.5V. When the N-type transistor MN1 receives a logic high level (for example, 1V) and a ground voltage GND disturbance occurs, although the gate-source voltage V GS will change, but the gate-source voltage V GS It is still greater than the threshold voltage (0.5V) of the N-type transistor MN1. Therefore, it can be ensured that the malfunction described in the above-mentioned type 1 converter will not occur. However, low-voltage components cannot withstand high voltage stress, so a bias circuit needs to be designed in the converter to prevent the low-voltage components from being damaged by excessive voltage stress.

[0060] Please refer to Figure 3, which is illustrated as an example of a type-2 converter. This type-2 converter 300 can convert an input signal IN and an inverted input signal ZIN whose signal range is between the voltage Vdd1 and GND into an output signal OUT and an inverted output signal ZOUT whose signal range is between the voltage Vdd2 and GND. Among them, Vdd1 is a power supply voltage (e.g., 1V), Vdd2 is another power supply voltage (e.g., 5V), and GND is a ground voltage (e.g., 0V). Furthermore, the type-2 converter 300 receives an initial signal (INI). According to the initial signal INI, the initial state of the type-2 converter 300 before operation can be controlled. The signal range of the initial signal INI is between the power supply voltage Vdd2 and the ground voltage GND.

[0061] The type-two converter 300 includes an inverter 105, a P-type transistor MP1, a P-type transistor MP2, a P-type transistor MPc, an N-type transistor MN1, an N-type transistor MN2, and a bias circuit 310. Among them, the P-type transistor MP1, the P-type transistor MP2, and the P-type transistor MPc are medium-voltage devices, and the N-type transistor MN1 and the N-type transistor MN2 are low-voltage devices with a lower threshold voltage. Figure 1 and Figure 2A The N-type transistors MN1 and MN2 in the type-1 converters 100 and 200 are Figure 3 The N-type transistors MN1 and MN2 in the type-two converter 300 generally have a relatively low input impedance. Furthermore, the type-two converter 300 has at least an initial end, an input end, and an output end. The initial end of the type-two converter 300 receives the initial signal INI, the input end of the type-two converter 300 receives the input signal IN, and the output end of the type-two converter 300 generates the output signal OUT.

[0062] The inverter 105 is connected to a power supply voltage Vdd1 and a ground voltage GND. An input terminal of the inverter 105 is connected to an input terminal of the type-two converter 300 to receive an input signal IN. An output terminal of the inverter 105 generates an inverted input signal ZIN.

[0063] The source of the P-type transistor MP1 receives the power supply voltage Vdd2, the drain is connected to the node a, and the gate is connected to the node b. The source of the P-type transistor MP2 receives the power supply voltage Vdd2, the drain is connected to the node b, and the gate is connected to the node a. The source of the P-type transistor MPc receives the power supply voltage Vdd2, the drain is connected to the node a, and the gate receives the initial signal INI. Among them, the node b is connected to the output end of the type-two converter 300 to generate the output signal OUT. In addition, the node a can also be used as another output end of the type-two converter 300 to generate the inverted output signal ZOUT.

[0064] The drain of the N-type transistor MN1 is connected to the node c, the source receives the ground voltage GND, and the gate receives the input signal IN. In addition, the drain of the N-type transistor MN2 is connected to the node d, the source receives the ground voltage GND, and the gate receives the inverted input signal ZIN.

[0065] The bias circuit 310 is coupled between the node a and the node c, and the bias circuit 310 is coupled between the node b and the node d. The bias circuit 310 includes an N-type transistor MN3 and an N-type transistor MN4. The drain of the N-type transistor MN3 is connected to the node a, the source is connected to the node c, and the gate receives a bias voltage Vb1. In addition, the drain of the N-type transistor MN4 is connected to the node b, the source is connected to the node d, and the gate receives the bias voltage Vb1.

[0066] According to an embodiment of the present invention, the bias voltage Vb1 is between the power voltage Vdd1 and the power voltage Vdd2. When the type-2 converter 300 does not receive the bias voltage Vb1, the N-type transistor MN3 and the N-type transistor MN4 are turned off, and the type-2 converter 300 cannot operate. When the type-2 converter 300 receives the bias voltage Vb1, the type-1 converter 200 operates. For example, the bias voltage Vb1 is 2.0V.

[0067] During normal operation, the bias voltage Vb1 can maintain the N-type transistor MN3 and the N-type transistor MN4 in a conducting state, and limit the maximum voltage of the node c and the node d to (Vb1-Vt3). Wherein, Vt3 is the threshold voltage of the N-type transistor MN3 and the N-type transistor MN4, for example, 0.9V. Therefore, when the type-2 converter 300 operates normally, the maximum voltage of the node c and the node d will be controlled at about 1.1V (2.0V-0.9V). And this maximum voltage (1.1V) is the voltage stress that the N-type transistor MN1 and the N-type transistor MN2 can withstand, which can ensure that the N-type transistor MN1 and the N-type transistor MN2 will not be damaged, and the type-2 converter 300 will not malfunction.

[0068] like Figure 3 As shown, when the initial signal INI is at a logic low level, it means that the initial signal INI is activated, the type-two converter 300 is disabled, and the P-type transistor MPc is turned on. At this time, no matter how the input signal IN and the inverted input signal ZIN change, the type-two converter 300 remains in the initial state, the output signal OUT remains at a logic low level, and the inverted output signal ZOUT remains at a logic high level. In other words, according to the initial signal INI, in the initial state before the type-two converter 300 is activated (enabled), the output signal OUT and the inverted output signal ZOUT can be controlled.

[0069] When the enable signal EN is at a logic high level, it means that the initial signal INI is inactivated, and the P-type transistor MPc is turned off. At this time, the type-2 converter 300 can be regarded as enabled and can operate. The output signal OUT and the inverted output signal ZOUT of the type-2 converter 300 change according to the changes of the input signal IN and the inverted input signal ZIN. In other words, the type-2 converter 300 needs to receive the bias voltage Vb1 and be enabled (that is, the initial signal INI is inactivated) before the type-2 converter 300 can operate normally.

[0070] When the input signal IN of the type-two converter 300 is at a logic high level (i.e., the power supply voltage Vdd1) and the inverting input signal ZIN is at a logic low level (i.e., 0V), the N-type transistor MN1 and the P-type transistor MP2 are turned on, the N-type transistor MN2 and the P-type transistor MP1 are turned off, the bias circuit 310 is in a conducting state, the node a is coupled to the node c via the bias circuit 310, and the node b is coupled to the node d via the bias circuit 310. Therefore, the output signal OUT is at a logic high level (i.e., the power supply voltage Vdd2), and the inverting output signal ZOUT is at a logic low level (i.e., 0V).

[0071] When the input signal IN of the type-two converter 300 is a logic low level (i.e., 0V) and the inverted input signal ZIN is a logic high level (i.e., the power supply voltage Vdd1), the N-type transistor MN1 and the P-type transistor MP2 are turned off, the N-type transistor MN2 and the P-type transistor MP1 are turned on, the bias circuit 310 is in a conducting state, the node a is coupled to the node c via the bias circuit 310, and the node b is coupled to the node d via the bias circuit 310. Therefore, the output signal OUT is a logic low level (i.e., 0V), and the inverted output signal ZOUT is a logic high level (i.e., the power supply voltage Vdd2). In other words, the output signal OUT is a shifted signal of the input signal IN.

[0072] Of course, the type-two converter 300 can also be modified so that in the initial state of the type-two converter 300, the output signal OUT is a logic high level and the inverted output signal ZOUT is a logic low level. Figure 3 The connection relationship of the P-type transistor MPc in the embodiment. The source of the P-type transistor MPc receives the power supply voltage Vdd2, the drain is connected to the node b, and the gate receives the initial signal INI. Therefore, when the initial signal INI is activated, the output signal OUT of the type-two converter 300 is maintained at a logic high level, and the inverted output signal ZOUT is maintained at a logic low level.

[0073] Please refer to Figure 4 , which shows another example of a type II converter. Figure 3 The difference between the two converters 300 is Figure 4 The structure of the bias circuit 410 in the type-2 converter 400. Furthermore, the operation principle of the type-2 converter 300 is similar to that of the type-2 converter 400, and only the structure of the bias circuit 410 is described below, and the rest is not repeated.

[0074] The bias circuit 410 is coupled between the node a and the node c, and the bias circuit 410 is coupled between the node b and the node d. The bias circuit 410 includes an N-type transistor MN3, an N-type transistor MN4, an N-type transistor MN5, and an N-type transistor MN6. The drain of the N-type transistor MN3 is connected to the node e, the source is connected to the node c, and the gate receives a bias voltage Vb1. The drain of the N-type transistor MN4 is connected to the node f, the source is connected to the node d, and the gate receives the bias voltage Vb1. The drain of the N-type transistor MN5 is connected to the node a, the source is connected to the node e, and the gate receives a bias voltage Vb2. The drain of the N-type transistor MN6 is connected to the node b, the source is connected to the node f, and the gate receives the bias voltage Vb2.

[0075] Among them, the bias voltages Vb1 and Vb2 are between the power supply voltage Vdd1 and the power supply voltage Vdd2, and Vb2 is greater than Vb1. For example, the bias voltage Vb2 is 3.0V and the bias voltage Vb1 is 2.0V. Similarly, when the type-two converter 400 operates normally, the bias voltage Vb1 can keep the N-type transistor MN3 and the N-type transistor MN4 in the on state, and the bias voltage Vb2 can keep the N-type transistor MN5 and the N-type transistor MN6 in the on state. At the same time, the bias circuit 410 can control the maximum voltage of the node c and the node d to (Vb1-Vt3). In this way, it can be ensured that the N-type transistor MN1 and the N-type transistor MN2 will not be damaged, and the type-two converter 400 will not malfunction.

[0076] Depend on Figure 3 and Figure 4 It can be seen from the type-2 converters 300 and 400 that bias circuits 310 and 410 need to be designed inside the type-2 converters 300 and 400. In order for the type-2 converters 300 and 400 to operate normally, a bias voltage generator needs to be designed in the IC chip and continuously provide bias voltages Vb1 and Vb2 to the bias circuits 310 and 410, which will cause additional energy consumption of the IC chip. For example, the bias voltage generator can be a low dropout regulator (LDO) or a voltage divider connected to the power supply voltage Vdd2. When the bias voltage generator is enabled, the bias voltage generator can output bias voltages Vb1 and Vb2 that are lower than the power supply voltage Vdd2.

[0077] Please refer to Figure 5A , which illustrates a voltage conversion circuit according to a first embodiment of the present invention. Figure 5B FIG. 1 is a schematic diagram of related signals of the voltage conversion circuit of the first embodiment.

[0078] Basically, when the IC chip is in standby mode, most of the circuits stop operating, so the total current generated inside the IC chip is very small, and no ground voltage GND disturbance occurs. On the contrary, when it is in non-standby mode, most of the circuits in the IC chip are operating, so the total current generated inside the IC chip is larger, and ground voltage GND disturbance may occur. Therefore, the present invention designs the converter circuit 500 according to the characteristics of different types of converters, so that the converter circuit 500 can operate in different modes.

[0079] The voltage conversion circuit 500 of the present invention is designed in an IC chip. According to a mode signal, the voltage conversion circuit 500 can operate in one of two modes. Furthermore, the voltage conversion circuit 500 receives a mode signal and outputs a shifted mode signal. For example, the mode signal is a standby signal. When the standby signal is a first logic level (e.g., a logic low level), the IC chip is in a standby mode. When the standby signal is a second logic level (e.g., a logic high level), the IC chip is in a non-standby mode, or a chip enable mode.

[0080] The voltage conversion circuit 500 includes: a first type 1 voltage converter 510, a first type 2 voltage converter 520 and a controller 590. The voltage conversion circuit 500 includes an input terminal and an output terminal. The input terminal receives a standby signal (STB DD1 ), the output end can output a shifted standby signal (shifted standby signal, STB DD2 ). The voltage conversion circuit 500 can convert the standby signal STB of the first power domain into DD1 Converted to the second power domain voltage standby signal STB DD2 In addition, Figure 5A and Figure 5B Among the signals, the signal subscript DD1 represents a signal belonging to the first power domain, and the signal subscript DD2 represents a signal belonging to the second power domain.

[0081] In the voltage conversion circuit 500, the first type of voltage converter 510 can be Figure 1 or Figure 2A The first type of transformer 520 can be realized by the first type of transformer 100, 200. Figure 3 or Figure 4 In addition, the first type of two-phase converter 520 further has a bias circuit and an initial terminal.

[0082] According to the first embodiment of the present invention, the input terminals of the first type 1 converter 510 and the first type 2 converter 520 receive the standby signal STB. DD1 The output terminal of the first type-transformer 510 outputs a first transducer signal S1. DD2 The output terminal of the first type second converter 520 outputs a second converted signal S2 DD2The controller 590 is coupled to the output ends of the first type one transformer 510 and the first type two transformer 520 .

[0083] In standby mode, the standby signal STB DD1 is a first logic level (eg, logic low level), the controller 590 disables the first type binary converter 520 and does not provide the bias voltage Vb1 to the first type binary converter 520. Furthermore, according to the first conversion signal S1 of the first logic level DD2 , the controller 590 outputs a first logic level voltage-converting standby signal STB DD2 .

[0084] In addition, when in non-standby mode, the standby signal STB DD1 is a second logic level (eg, a logic high level), the controller 590 ignores the first conversion signal S1 output by the first type-1 converter 510. DD2 Furthermore, the controller 590 enables the first type binary converter 520 and provides the bias voltage Vb1 to the first type binary converter 520. In addition, according to the second conversion signal S2 of the second logic level DD2 , the controller 590 outputs a second logic level voltage conversion standby signal STB DD2 .

[0085] like Figure 5A As shown, the controller 590 includes: a latch 530, an OR gate 540, a bias voltage generator 550 and a delay element 560. Furthermore, the controller 590 belongs to the circuit of the second power domain. That is, the latch 530, the OR gate 540, the bias voltage generator 550 and the delay element 560 belong to the circuit of the second power domain. The detailed connection relationship and operation principle of the voltage conversion circuit 500 are described in detail below.

[0086] The input terminal of the first type-one converter 510 is coupled to the input terminal of the converter circuit 500 to receive the standby signal STB. DD1 The input terminal of the first type two converter 520 is coupled to the input terminal of the converter circuit 500 to receive the standby signal STB. DD1The input end of the latch 530 is coupled to the output end of the first type one converter 510, and the reset end (Reset) of the latch 530 is coupled to the output end of the delay element 560. The first input end of the OR gate 540 is coupled to the output end of the latch 530, the second input end of the OR gate 540 is coupled to the output end of the first type two converter 520, the output end of the OR gate 540 is coupled to the initial end INI of the first type two converter 520, and the output end of the OR gate 540 is used as the output end of the converter circuit 500, which can output the converter standby signal STB. DD2 Furthermore, the input terminal of the delay element 560 is coupled to the output terminal of the OR gate 540, and the output terminal of the delay element 560 is coupled to the reset terminal (Reset) of the latch 530. The enable terminal EN of the bias voltage generator 550 is coupled to the output terminal of the OR gate 540, and the bias voltage generator 550 can output at least one bias voltage Vb1 to the first type two converter 520.

[0087] Of course, if the structure of the first type second converter 520 is similar to Figure 4 For the first type two converter 400 , the bias voltage generator 550 can provide two bias voltages Vb1 and Vb2 to the first type two converter 520 .

[0088] According to the first embodiment of the present invention, the latch 530 is implemented by a D-type flip-flop. The clock input terminal CK of the D-type flip-flop serves as the input terminal of the latch 530, and the output terminal Q of the D-type flip-flop serves as the output terminal of the latch 530. In addition, the data terminal D of the D-type flip-flop receives a logic high level (Vdd2), and the reset terminal (Reset) of the D-type flip-flop is coupled to the output terminal of the delay element 560.

[0089] Of course, in other embodiments, the latch 530 may also be implemented by other circuits. For example, the latch 530 is implemented by an RS flip-flop. The clock input terminal CK of the RS flip-flop serves as the input terminal of the latch 530, and the output terminal Q of the RS flip-flop serves as the output terminal of the latch 530. In addition, the S terminal of the RS flip-flop receives a logic high level (Vdd2), the R terminal of the RS flip-flop receives a logic low level (GND), and the reset terminal (Reset) of the RS flip-flop is coupled to the output terminal of the delay element 560. Alternatively, the latch 530 may also be implemented by a JK flip-flop. The clock input terminal CK of the JK flip-flop serves as the input terminal of the latch 530, and the output terminal Q of the JK flip-flop serves as the output terminal of the latch 530. In addition, the J terminal of the JK type flip-flop receives a logic high level (Vdd2), the K terminal of the JK type flip-flop receives a logic low level (GND), and the reset terminal (Reset) of the JK type flip-flop is coupled to the output terminal of the delay element 560 .

[0090] For example, the standby signal STB DD1 And the standby signal STB DD2 When it is logic low, the IC chip is in standby mode. Standby signal STB DD1 And the standby signal STB DD2 When it is logic high, the IC chip is not in standby mode.

[0091] like Figure 5B As shown, at time point t 1 Before, the IC chip is in standby mode, and the standby signal STB received at the input end of the voltage conversion circuit 500 DD1 is a logic low level, the first type-1 converter 510 outputs the first conversion signal S1 DD2 Furthermore, the first type two-phase converter 520 is disabled and maintained in the initial state, so that the second voltage conversion signal S2 output by the first type two-phase converter 520 is DD2 Therefore, the voltage conversion standby signal STB at the output end of the voltage conversion circuit 500 (ie, the output end of the OR gate 540) is DD2 is a logic low level.

[0092] Furthermore, due to the conversion of the standby signal STB DD2 is a logic low level, the bias voltage generator 550 is disabled and cannot provide the bias voltage Vb1. Furthermore, the first type two-phase converter 520 is disabled and maintained in the initial state, that is, the first type two-phase converter 520 outputs the second voltage conversion signal S2 DD2 In addition, the delay output signal (DO DD2 ) is at a logic low level, so the latch 530 is not reset and operates normally. The latch output signal (Latch output signal, LO1) outputted from the output terminal Q of the latch 530 is DD2 ) is a logic low level.

[0093] At time point t 1 , the standby mode switches to non-standby mode, the standby signal STB DD1 The first type-one converter 510 outputs the first converted signal S1 from the logic low level to the logic high level. DD2 The logic level switches from a low level to a high level, so that the latch 530 is activated, and the latch output signal LO1 outputted from the output terminal Q of the latch 530 is DD2The logic level is switched from a low level to a high level and is latched at a high level. Furthermore, the voltage conversion standby signal STB at the output end of the voltage conversion circuit 500 (ie, the output end of the OR gate 540) DD2 The logic level is switched from a logic low level to a logic high level, so that the first type two converter 520 and the bias voltage generator 550 are enabled.

[0094] Furthermore, since the bias voltage generator 550 is enabled, the bias voltage generator 550 starts to provide the bias voltage Vb1. In addition, the delayed output signal DO output by the delay element 560 is DD2 is a logic low level, so the latch 530 is not reset and still operates normally. The latch output signal LO1 outputted from the output terminal Q of the latch 530 is DD2 is a logic high level.

[0095] like Figure 5B As shown, after the bias voltage generator 550 is enabled, a start-up time (start-up time, T startup ) can provide a stable bias voltage Vb1, such as 2V, so that the first type two-converter 520 starts to operate. Therefore, the present invention designs a delay element 560, whose delay time (delay time, T delay ) is greater than or equal to the start time T startup To ensure that the voltage conversion standby signal STB at the output end of the voltage conversion circuit 500 DD2 No glitch or malfunction will occur.

[0096] That is, at time t 1 After the start time T startup At the next time point t 2 , the bias voltage generator 550 provides a stable bias voltage Vb1 to the first type two-phase converter 520. Therefore, the first type two-phase converter 520 starts to operate, and the first type two-phase converter 520 outputs a second conversion signal S2 DD2 Switches from logic low to logic high.

[0097] In addition, at time t 1 After the delay time T delay At the next time point t 3 , the delayed output signal DO output by the delay element 560 DD2 The latch 530 is reset because the logic low level is switched to the logic high level. The latch output signal LO1 outputted from the output terminal Q of the latch 530 is reset. DD2 = is a logic low level. Since the second voltage conversion signal S2 output by the first type second voltage converter 520DD2 is a logic high level, so the voltage conversion standby signal STB at the output end of the voltage conversion circuit 500 (ie, the output end of the OR gate 540) is DD2 Still maintained at logic high level.

[0098] At time point t 4 , the IC chip switches from non-standby mode to standby mode, the standby signal STB DD1 The first type-one converter 510 outputs the first converted signal S1 from the logic high level to the logic low level. DD2 The delayed output signal DO DD2 The latch 530 is still at a logic high level, so the latch output signal LO1 is still reset. DD2 Still at a logic low level. Furthermore, the second voltage conversion signal S2 output by the first type second voltage converter 520 is DD2 Therefore, the voltage conversion standby signal STB at the output end of the voltage conversion circuit 500 (ie, the output end of the OR gate 540) is DD2 Switches from logic high level to logic low level. In addition, due to the voltage conversion standby signal STB DD2 is a logic low level, the first type two converter 520 is disabled and returns to the initial state, and the bias voltage generator 550 is also disabled, and the bias voltage generator 550 stops providing the bias voltage Vb1.

[0099] After the delay time T delay At the next time point t 5 , the delayed output signal DO output by the delay element 560 DD2 Since the logic high level is switched to the logic low level, the latch 530 is not reset. The latch 530 can operate normally and wait for the next first voltage conversion signal S1. DD2 Switching logic level. Of course, in other embodiments, the delay element 560 can also be modified according to actual design requirements. For example, when the IC chip is at time point t 4 When switching from the non-standby mode to the standby mode, the delayed output signal DO output by the delay element 560 DD2 It is also possible to skip the delay time T delay At time t 5 , and at time point t 4 The delayed output signal DO DD2 Switches to logic low.

[0100] When the IC chip enters the non-standby mode, a ground voltage GND disturbance may occur, causing the first type-one converter 510 to output the first converted signal S1 DD2Generate glitch. Figure 5B As shown, at time point t 2 To time point t 3 , the first voltage conversion signal S1 DD1 A glitch is generated. Since the latch output signal LO1 of the latch 530 DD2 Latched at logic high level, converting to standby signal STB DD2 No glitch will be generated. At time point t 3 To time point t 4 , the first voltage conversion signal S1 DD2 A glitch occurs. Since the latch 530 has been reset, the latch output signal LO1 of the latch 530 DD2 Maintain at logic low level, convert to standby signal STB DD2 That is, when in the non-standby mode, the latch 530 in the controller 590 ignores the first voltage conversion signal S1 output by the first type-one voltage converter 510. DD2 , so that the voltage conversion standby signal STB output by the voltage conversion circuit 500 DD2 No glitches will be generated.

[0101] In addition, since the first type dual converter 520 is not operated and the bias voltage generator 550 is not enabled in the standby mode, the bias voltage Vb1 is not provided. Therefore, in the standby mode, the power consumption of the IC chip can be reduced.

[0102] Using similar concepts, the present invention can design multiple mode signals so that the voltage conversion circuit in the IC chip can operate in more modes. For example, two mode signals are used to distinguish three modes, and the voltage conversion circuit receives two mode signals and outputs two shifted mode signals.

[0103] In the following embodiments, the two mode signals are a deep standby signal and a standby signal. A variety of modes can be determined using the deep standby signal and the standby signal. When the deep standby signal and the standby signal are both at a first logic level (e.g., a logic low level), the IC chip is in a deep standby mode. When the deep standby signal is at a second logic level (e.g., a logic high level) and the standby signal is at a first logic level (e.g., a logic low level), the IC chip is in standby mode. When the deep standby signal and the standby signal are both at a second logic level (e.g., a logic high level), the IC chip is in a non-standby mode, or a chip enable mode.

[0104] Please refer to Fig. 6A , which illustrates a voltage conversion circuit according to a second embodiment of the present invention. Figure 6B The voltage conversion circuit 600 includes: a first type one voltage converter 510 , a second type one voltage converter 610 , a first type two voltage converter 520 , a second type two voltage converter 620 and a controller 690 .

[0105] The voltage conversion circuit 600 includes two input terminals and two output terminals. The first input terminal receives the standby signal STB. DD1 The first output terminal outputs a voltage conversion standby signal STB DD2 The second input terminal receives a deep standby signal (DSTB DD1 ), the second output terminal outputs a shifted deep standby signal (DSTB DD2 ). The voltage conversion circuit 600 converts the standby signal STB of the first power domain into DD1 Converted to the second power domain voltage standby signal STB DD2 , and the voltage conversion circuit 600 converts the deep standby signal DSTB of the first power domain DD1 Converted to the deep standby signal DSTB of the second power domain DD2 .

[0106] Similarly, the first type-transformer 510 and the second type-transformer 610 can be Figure 1 or Figure 2A The disclosed type 1 transformer 100, 200 is implemented. The first type 2 transformer 520 and the second type 2 transformer 620 can be Figure 3 or Figure 4The disclosed two-type converter 300, 400 is implemented. In addition, the first type two-type converter 520 and the second type two-type converter 620 further include a bias circuit and an initial terminal.

[0107] According to the second embodiment of the present invention, the input terminals of the first type 1 converter 510 and the first type 2 converter 520 receive the standby signal STB. DD1 The output terminals of the first type 1 converter 510 and the first type 2 converter 520 respectively output the first converted signal S1 DD2 and the second voltage conversion signal S2 DD2 The input terminals of the second type 1 converter 610 and the second type 2 converter 620 receive the deep standby signal DSTB. DD1 The output terminals of the second type one transformer 610 and the second type two transformer 620 respectively output the third transformer signal S3 DD2 and the fourth voltage conversion signal S4 DD2 The controller 690 is coupled to the output terminals of the two type 1 converters 510 , 610 and the two type 2 converters 520 , 620 .

[0108] In deep standby mode, the standby signal STB DD1 With deep standby signal DSTB DD1 is a first logic level (eg, logic low level), the controller 690 disables the two type two converters 520, 620, and the controller 690 does not provide the bias voltage Vb1 to the two type two converters 520, 620. Furthermore, according to the first conversion signal S1 of the first logic level DD2 and the third voltage conversion signal S3 DD2 , the controller 690 outputs a first logic level voltage-shifted standby signal STB DD2 And the deep standby signal DSTB DD2 .

[0109] In addition, in standby mode, the deep standby signal DSTB DD1 is a second logic level (eg, a logic high level), the standby signal STB DD1 is the first logic level, the controller 690 disables the two type-two converters 520, 620 and does not provide the bias voltage Vb1 to the two type-two converters 520, 620. Furthermore, according to the third conversion signal S3 of the second logic level DD2 , the controller 690 outputs a second logic level deep standby signal DSTB DD2 According to the first conversion signal S1 of the first logic level DD2 , the controller 690 outputs a first logic level voltage-shifted standby signal STB DD2 .

[0110] When not in standby mode, the standby signal STB DD1 The second logic level and the deep standby signal DSTB DD1 The controller 590 ignores the first conversion signal S1 output by the two type-1 converters 510 and 610. DD2 and the third voltage conversion signal S3 DD2 Furthermore, the controller 690 enables the two type-two converters 520 and 620 and provides the bias voltage Vb1 to the two type-two converters 520 and 620. In addition, according to the fourth conversion signal S4 of the second logic level DD2 , the controller 690 outputs a second logic level deep standby signal DSTB DD2 According to the second conversion signal S2 of the second logic level DD2 , the controller 690 outputs a second logic level voltage conversion standby signal STB DD2 .

[0111] Compared to Figure 5A The controller 590, Fig. 6A The controller 690 further includes: a latch 630 and an OR gate 640. The controller 690 belongs to the circuit of the second power domain. The following only introduces the connection relationship and operation principle of the latch 630 and the OR gate 640, and the rest will not be repeated.

[0112] The input terminal of the latch 630 is coupled to the output terminal of the second type one converter 610, and the reset terminal (Reset) of the latch 630 is coupled to the output terminal of the delay element 560. The first input terminal of the OR gate 640 is coupled to the output terminal of the latch 630, the second input terminal of the OR gate 640 is coupled to the output terminal of the second type two converter 620, and the output terminal of the OR gate 640 is connected to the second output terminal of the converter circuit 600, which can output the converted deep standby signal DSTB. DD2 Furthermore, the initial terminal INI of the second type binary converter 620 is coupled to the output terminal of the OR gate 540 , and the bias voltage generator 550 can output at least one bias voltage Vb1 to the second type binary converter 620 .

[0113] Furthermore, the latch 630 can be implemented by a D flip-flop, an RS flip-flop, or a JK flip-flop.

[0114] like Figure 6B As shown, at time point t 0 The IC chip is in deep standby mode before, and the standby signal STB received by the input end of the voltage conversion circuit 600 DD1 With deep standby signal DSTB DD1is a logic low level, the first type-1 converter 510 outputs the first conversion signal S1 DD2 is a logic low level, the third voltage conversion signal S3 output by the second type one voltage converter 610 DD2 Furthermore, the two type-2 converters 520 and 620 are disabled and maintained in the initial state, and the output second conversion signal S2 DD2 and the fourth voltage conversion signal S4 DD2 Therefore, the voltage conversion standby signal STB at the first output terminal of the voltage conversion circuit 600 (ie, the output terminal of the OR gate 540) is DD2 is a logic low level, the deep standby signal DSTB at the second output terminal of the voltage conversion circuit 600 (ie, the output terminal of the OR gate 640) is DD2 is a logic low level.

[0115] Furthermore, due to the conversion of the standby signal STB DD2 is a logic low level, the bias voltage generator 550 is disabled and cannot provide the bias voltage Vb1. Furthermore, the two type-two converters 520 and 620 are disabled and maintained in the initial state, that is, the second conversion signal S2 output by the two type-two converters 520 and 620 is DD1 and the fourth voltage conversion signal S4 DD1 is a logic low level. In addition, the delay output signal (delay output signal, DO DD2 ) is a logic low level, so the two latches 530 and 630 are not reset and operate normally. The latch output signal LO1 outputted from the output terminal Q of the two latches 530 and 630 is DD2 LO2 DD2 All are logic low.

[0116] At time point t 1 Afterwards, the signal change of the voltage conversion circuit 600 is similar to Figure 5B In addition, at time t 1 , the second type of converter 620 is enabled. At time point t 2 , the stable bias voltage Vb1 is provided to the second type second converter 620, so that the fourth conversion signal S4 DD2 Switches from logic low level to logic high level. At time t 3 , the latch 630 is reset. 4 , deep standby signal DSTB DD1 With standby signal STB DD1 , switches to logic low and returns to deep standby mode.

[0117] When the IC chip enters the non-standby mode, a ground voltage GND disturbance may occur, causing the first conversion signal S1 output by the two type-one converters 510 and 610 to be DD1 and the third voltage conversion signal S3 DD1 Generate glitch. Similarly, Figure 6B As shown, in the non-standby mode, the latch 530 in the controller 690 can ignore the first voltage conversion signal S1 output by the first type-one voltage converter 510. DD2 The latch 630 may ignore the third voltage conversion signal S3 output by the second type one voltage converter 610. DD2 The voltage conversion circuit 600 outputs a voltage conversion standby signal STB DD2 And the deep standby signal DSTB DD2 No glitches will be generated.

[0118] From the above description, it can be seen that the present invention proposes a voltage conversion circuit that can operate in different modes. In the deep standby mode and the standby mode, the controller uses the voltage conversion signal level output by the type 1 voltage converter as the output signal level of the voltage conversion circuit. In the non-standby mode, the controller uses the voltage conversion signal level output by the type 2 voltage converter as the output signal level of the voltage conversion circuit.

[0119] Furthermore, the present invention does not limit the connection relationship of the circuit elements of the controllers 590 and 690. Of course, the present invention does not limit the first logic level and the second logic level. For example, the first logic level may be a logic high level, and the second logic level may be a logic low level. Those skilled in the art can also simply modify the connection relationship of the circuit elements in the controller to complete the present invention.

[0120] For example, Figure 7 This is the third embodiment of the voltage conversion circuit of the present invention. Fig. 6A The voltage conversion circuit 600, Figure 7 An AND gate 750 is added to the controller 790 of the voltage conversion circuit 700, so that the output end of the delay element 560 is coupled to the reset end (Reset) of the two latches 530 and 630 via the AND gate 750. Furthermore, a first input end of the AND gate 750 is connected to the output end of the delay element 560, a second input end of the AND gate 750 is connected to the output end of the OR gate 640, and the output end of the AND gate 750 is connected to the reset end (Reset) of the two latches 530 and 630. Basically, the signal relationship between the voltage conversion circuit 600 of the second embodiment and the voltage conversion circuit 700 of the third embodiment is the same, and at the time point t 3 The two latches 530 and 630 are reset at the same time.

[0121] In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the definition of the attached claims.

Claims

1. A voltage conversion circuit having a first input terminal and a first output terminal, wherein the first input terminal of the voltage conversion circuit receives a first mode signal of a first power domain, and the first output terminal of the voltage conversion circuit outputs a converted first mode signal of a second power domain, wherein the first power domain is different from the second power domain, and the voltage conversion circuit comprises: A first type-type converter, an input end of the first type-type converter is coupled to the first input end of the converter circuit; wherein the input end of the first type-type converter receives the first mode signal, and an output end of the first type-type converter outputs a first conversion signal of the second power domain; a first type two-converter, an input end of the first type two-converter is coupled to the first input end of the voltage conversion circuit; wherein the input end of the first type two-converter receives the first mode signal, and an output end of the first type two-converter outputs a second voltage conversion signal of the second power domain; wherein the first type two-converter includes a first bias circuit, and the first bias circuit receives at least one bias voltage for normal operation; and A controller coupled to the output end of the first type one converter and the output end of the first type two converter; Wherein, in a standby mode, the first mode signal is a first logic level; the controller disables the first type two-converter, and the controller does not provide the at least one bias voltage to the first bias circuit of the first type two-converter; and, according to the first conversion signal of the first logic level, the controller outputs the conversion first mode signal of the first logic level; Wherein, in a non-standby mode, the first mode signal is a second logic level; the controller ignores the first conversion signal output by the first type one converter; the controller provides the at least one bias voltage to the first bias circuit of the first type two converter; and, according to the second conversion signal of the second logic level, the controller outputs the conversion first mode signal of the second logic level.

2. The voltage conversion circuit as claimed in claim 1, wherein the controller comprises: a delay element having an output terminal and an input terminal; a first latch, an input terminal of the first latch being coupled to the output terminal of the first type-one converter, and a reset terminal of the first latch being coupled to the output terminal of the delay element; a first OR gate, a first input terminal of the first OR gate coupled to an output terminal of the first latch, a second input terminal of the first OR gate coupled to the output terminal of the first type two converter, an output terminal of the first OR gate coupled to the input terminal of the delay element, and the output terminal of the first OR gate serving as the first output terminal of the converter circuit; as well as a bias voltage generator, wherein an enable terminal of the bias voltage generator is coupled to the output terminal of the first OR gate; When the bias voltage generator is enabled, the bias voltage generator provides the at least one bias voltage to the first bias circuit of the first type two-converter; when the bias voltage generator is disabled, the bias voltage generator does not provide the at least one bias voltage to the first bias circuit of the first type two-converter.

3. The converter circuit as described in claim 2, wherein in the standby mode, the first latch outputs a first latch output signal of the second power domain, and the first latch output signal is the first logic level; the first OR gate outputs the converter first mode signal of the first logic level; the delay element outputs a delayed output signal of the first logic level so that the first latch is not reset; and, according to the converter first mode signal of the first logic level, the first type two converter and the bias voltage generator are disabled.

4. The voltage conversion circuit as described in claim 1, wherein when the standby mode is switched to the non-standby mode, the first mode signal is switched from the first logic level to the second logic level, the first voltage conversion signal is switched from the first logic level to the second logic level, the first latch output signal is switched from the first logic level to the second logic level, and the voltage conversion first mode signal is switched from the first logic level to the second logic level.

5. The converter circuit as claimed in claim 4, wherein according to the converter first mode signal of the second logic level, the first type two converter and the bias voltage generator are enabled, so that the bias voltage generator provides the at least one bias voltage to the first bias circuit of the first type two converter after a start-up time; According to the converted first mode signal of the second logic level, the delay element outputs the delayed output signal of the second level to the first latch after a delay time to reset the first latch; And, the delay time is greater than or equal to the start time.

6. The converter circuit as described in claim 5, wherein after the delay time of switching from the standby mode to the non-standby mode, the first type two converter outputs the second converted signal of the second logic level, and the first OR gate outputs the converted first mode signal of the second logic level.

7. The voltage conversion circuit as described in claim 2, wherein the first latch is a D-type flip-flop, a reset terminal of the D-type flip-flop serves as the reset terminal of the first latch, a clock input terminal of the D-type flip-flop serves as the input terminal of the first latch, an output terminal of the D-type flip-flop serves as the output terminal of the first latch, and a data terminal of the D-type flip-flop receives a logic high level of the second power domain.

8. The voltage conversion circuit as described in claim 1, wherein the first logic level of the first mode signal is a ground voltage, and the second logic level of the first mode signal is a first power supply voltage; and the first logic level of the converted first mode signal is the ground voltage, and the second logic level of the converted first mode signal is a second power supply voltage.

9. The voltage converter circuit as claimed in claim 8, wherein the first type-one voltage converter comprises: a first P-type transistor, a source of the first P-type transistor receiving the second power supply voltage, a drain of the first P-type transistor connected to a first node, and a gate of the first P-type transistor connected to a second node; a second P-type transistor, a source of the second P-type transistor receiving the second power supply voltage, a drain of the second P-type transistor connected to a third node, and a gate of the second P-type transistor connected to a fourth node; an inverter, an input terminal of the inverter is connected to the input terminal of the first type-one converter; a third P-type transistor, a source of the third P-type transistor being connected to the first node, a drain of the third P-type transistor being connected to the fourth node, and a gate of the third P-type transistor being connected to the input terminal of the inverter; a fourth P-type transistor, a source of the fourth P-type transistor being connected to the third node, a drain of the fourth P-type transistor being connected to the second node, and a gate of the fourth P-type transistor being connected to an output terminal of the inverter; a first N-type transistor, a drain of the first N-type transistor being connected to the fourth node, a source of the first N-type transistor receiving the ground voltage, and a gate of the first N-type transistor being connected to the input terminal of the inverter; and a second N-type transistor, a drain of the second N-type transistor being connected to the second node, a source of the second N-type transistor receiving the ground voltage, and a gate of the second N-type transistor being connected to the output terminal of the inverter; The second node is connected to the output end of the first type-one converter. 10 . The voltage conversion circuit as claimed in claim 9 , wherein the first N-type transistor and the second N-type transistor are medium voltage devices.

11. The voltage converter circuit as claimed in claim 8, wherein the first type two-converter comprises: a first P-type transistor, a source of the first P-type transistor receiving the second power supply voltage, a drain of the first P-type transistor connected to a first node, and a gate of the first P-type transistor connected to a second node; a second P-type transistor, a source of the second P-type transistor receiving the second power supply voltage, a drain of the second P-type transistor connected to the second node, and a gate of the second P-type transistor connected to a first node; an inverter, an input terminal of the inverter being connected to the input terminal of the first type two-phase converter; a first N-type transistor, a drain of the first N-type transistor being connected to a third node, a source of the first N-type transistor receiving the ground voltage, and a gate of the first N-type transistor being connected to the input terminal of the inverter; a second N-type transistor, a drain of the second N-type transistor being connected to a fourth node, a source of the second N-type transistor receiving the ground voltage, and a gate of the second N-type transistor being connected to the output terminal of the inverter; a third N-type transistor, a drain of the third N-type transistor being connected to the first node, a source of the third N-type transistor being connected to the third node, and a gate of the third N-type transistor receiving the at least one bias voltage; a fourth N-type transistor, a drain of the fourth N-type transistor being connected to the second node, a source of the fourth N-type transistor being connected to the fourth node, and a gate of the fourth N-type transistor receiving the at least one bias voltage; The second node is connected to the output end of the first type two-phase converter, and the third N-type transistor and the fourth N-type transistor form the first bias circuit of the first type two-phase converter.

12. The voltage conversion circuit as claimed in claim 11, further comprising: A third P-type transistor, a source of the third P-type transistor receives the second power supply voltage, a drain of the third P-type transistor is connected to the first node or the second node, and a gate of the third P-type transistor serves as an initial end of the type-two converter. 13 . The voltage conversion circuit as claimed in claim 11 , wherein the first N-type transistor and the second N-type transistor are low voltage devices.

14. The voltage conversion circuit as claimed in claim 1, further comprising a second input terminal and a second output terminal, wherein the second input terminal of the voltage conversion circuit receives a second mode signal of the first power domain, and the second output terminal of the voltage conversion circuit outputs a converted second mode signal of the second power domain, and the voltage conversion circuit further comprises: a second type-one voltage converter, an input end of the second type-one voltage converter is coupled to the second input end of the voltage converter circuit; wherein the input end of the second type-one voltage converter receives the second mode signal, and an output end of the second type-one voltage converter outputs a third voltage conversion signal of the second power domain; a second type two-converter, an input end of the second type two-converter is coupled to the second input end of the voltage conversion circuit; wherein the input end of the second type two-converter receives the second mode signal, and an output end of the second type two-converter outputs a fourth voltage conversion signal of the second power domain; wherein the second type two-converter includes a second bias circuit, and the second bias circuit receives the at least one bias voltage; and The controller is coupled to the output end of the second type one transformer and the output end of the second type two transformer; Wherein, in a deep standby mode, the first mode signal and the second mode signal are at the first logic level; the controller disables the first type two-converter and the second type two-converter, and the controller does not provide the at least one bias voltage to the first type two-converter and the second type two-converter; according to the first conversion signal of the first logic level, the controller outputs the conversion first mode signal of the first logic level; and, according to the third conversion signal of the first logic level, the controller outputs the conversion second mode signal of the first logic level; Wherein, in the standby mode, the second mode signal is the second logic level; the controller disables the second type two-converter, and the controller does not provide the at least one bias voltage to the second type two-converter; and, according to the third conversion signal of the second logic level, the controller outputs the conversion second mode signal of the second logic level; Wherein, in the non-standby mode, the second mode signal is the second logic level; the controller ignores the third conversion signal output by the second type one converter; the controller enables the second type two converter and provides the at least one bias voltage to the second type two converter; and, according to the fourth conversion signal of the second logic level, the controller outputs the conversion second mode signal of the second logic level.

15. The voltage conversion circuit as claimed in claim 14, wherein the controller comprises: a delay element having an output terminal and an input terminal; a first latch, an input terminal of the first latch being coupled to the output terminal of the first type-one converter, and a reset terminal of the first latch being coupled to the output terminal of the delay element; a first OR gate, a first input terminal of the first OR gate coupled to an output terminal of the first latch, a second input terminal of the first OR gate coupled to the output terminal of the first type two converter, an output terminal of the first OR gate coupled to the input terminal of the delay element, and the output terminal of the first OR gate serving as the first output terminal of the converter circuit; and a bias voltage generator, wherein an enable terminal of the bias voltage generator is coupled to the output terminal of the first OR gate; a second latch, an input terminal of the second latch being coupled to the output terminal of the second type-1 converter, and a reset terminal of the second latch being coupled to the output terminal of the delay element; a second OR gate, a first input terminal of the second OR gate coupled to an output terminal of the second latch, a second input terminal of the second OR gate coupled to the output terminal of the second type two-converter, and an output terminal of the second OR gate connected to the second output terminal of the converter circuit; When the bias voltage generator is enabled, the bias voltage generator provides the at least one bias voltage to the first bias circuit of the first type two-type converter and the second bias circuit of the second type two-type converter; when the bias voltage generator is disabled, the bias voltage generator does not provide the at least one bias voltage to the first bias circuit of the first type two-type converter and the second bias circuit of the second type two-type converter.

16. A voltage conversion circuit as described in claim 15, wherein the output end of the delay element is coupled to the reset ends of the first latch and the second latch via an AND gate; and a first input end of the AND gate is connected to the output end of the delay element, a second input end of the AND gate is connected to the output end of the second OR gate, and an output end of the AND gate is connected to the reset ends of the first latch and the second latch.

17. The converter circuit as described in claim 16, wherein in the deep standby mode, the first latch outputs a first latch output signal of the first logic level, the first OR gate outputs the converter first mode signal of the first logic level, the second latch outputs a second latch output signal of the first logic level, and the second OR gate outputs the converter second mode signal of the first logic level; the delay element outputs a delayed output signal of the first logic level so that the first latch and the second latch are not reset; and, according to the converter first mode signal of the first logic level, the first type two converter, the second type two converter and the bias voltage generator are disabled.

18. The voltage conversion circuit as described in claim 17, wherein when the deep standby mode is switched to the standby mode, the second mode signal is switched from the first logic level to the second logic level, the third voltage conversion signal is switched from the first logic level to the second logic level, the second latch output signal is switched from the first logic level to the second logic level, and the voltage conversion second mode signal is switched from the first logic level to the second logic level.

19. The voltage conversion circuit as described in claim 18, wherein when the standby mode is switched to the non-standby mode, the first mode signal is switched from the first logic level to the second logic level, the first voltage conversion signal is switched from the first logic level to the second logic level, the first latch output signal is switched from the first logic level to the second logic level, and the voltage conversion first mode signal is switched from the first logic level to the second logic level.

20. The converter circuit as described in claim 19, wherein according to the converter first mode signal of the second logic level, the first type two converter, the second type two converter and the bias voltage generator are enabled, so that the bias voltage generator provides the at least one bias voltage to the first type two converter and the second type two converter after a start time; according to the converter first mode signal of the second logic level, the delay element outputs the delayed output signal of the second level to the first latch and the second latch after a delay time to reset the first latch and the second latch; and the delay time is greater than or equal to the start time.

21. The voltage conversion circuit as described in claim 14, wherein the first logic level of the first mode signal and the second mode signal is a ground voltage, and the second logic level of the first mode signal and the second mode signal is a first power supply voltage; and the first logic level of the converted first mode signal and the converted second mode signal is the ground voltage, and the second logic level of the converted first mode signal and the converted second mode signal is a second power supply voltage.

Images