Power conversion device

Abstract

Provided is a power conversion device. The rectifier circuit (20) converts AC power source power into DC power. The inverter circuit (40) has a plurality of switching elements (41a-46a) and converts direct current into alternating current. A capacitor (31) is connected in parallel with each circuit between the rectifier circuit and the inverter circuit, permits a variation in the output voltage of the rectifier circuit, and absorbs a variation in the output voltage of the inverter circuit caused by the switching operation. A control circuit (60) controls the inverter circuit. When the inverter circuit stops supplying power to the load, the control circuit executes conduction control for turning on at least one of the plurality of switching elements so that the absolute value of the average output power of the inverter circuit is smaller than that when all of the plurality of switching elements are turned off. The conduction control is implemented such that the output power of the inverter circuit is switched to be positive or negative during the switching period of the switching element, and the average output power of the inverter circuit during each switching period is substantially zero.

Description

[0001] This invention patent application is a divisional application of the invention patent application with the invention name of “Power Conversion Device”, the international application date of January 30, 2020, the international application number of “PCT / JP2020 / 003504”, and the national application number of “202080011606.9”. Technical Field

[0002] The present disclosure relates to a power conversion device. Background Art

[0003] The power conversion device is provided between an AC power source and a load, and supplies a predetermined AC power to the load. Patent Document 1 discloses a technique related to the power conversion device.

[0004] The power conversion device of Patent Document 1 includes a rectifier circuit, a smoothing capacitor, a brake circuit, and an inverter circuit.

[0005] Patent Document 1: International Publication No. 2017 / 098836 Summary of the invention

[0006] -Technical problem to be solved by the invention-

[0007] Generally, there is a demand to reduce the capacitance of a smoothing capacitor in a power conversion device such as that of Patent Document 1 mentioned above.

[0008] An object of the present disclosure is to reduce the capacitance of a smoothing capacitor.

[0009] -Technical solutions to solve technical problems-

[0010] The first aspect of the present invention is a power conversion device, characterized in that it includes a rectifier circuit 20, an inverter circuit 40, a capacitor 31, an overvoltage protection circuit 50 and control circuits 60 and 70, wherein the rectifier circuit 20 converts the AC power output from the AC power supply 1 into DC power; the inverter circuit 40 has a plurality of switching elements 41a to 46a, converts the DC power into AC power and supplies it to a load; the capacitor 31 is connected in parallel with the rectifier circuit 20 and the inverter circuit 40 between the rectifier circuit 20 and the inverter circuit 40, respectively, allows the output voltage of the rectifier circuit 20 to change, and absorbs the output voltage of the inverter circuit 40 caused by the switching operation. The overvoltage protection circuit 50 has a resistor 51 and a semiconductor element 52 connected in series with each other, is connected in parallel with the capacitor 31, and protects the inverter circuit 40 from being damaged by the overvoltage applied to the inverter circuit 40; the control circuits 60 and 70 control the inverter circuit 40 and the overvoltage protection circuit 50.

[0011] Here, the capacitance of the capacitor 31 is small enough to allow the output voltage fluctuation of the rectifier circuit 20 and absorb the output voltage fluctuation of the inverter circuit 40 caused by the switching operation. In addition, the power tolerance of the resistor 51 and the semiconductor element 52 constituting the overvoltage protection circuit 50 is small enough to consume the magnetic energy stored in the inductance component of the load. Therefore, the capacitor 31 and the overvoltage protection circuit 50 can be miniaturized.

[0012] The second invention of the present disclosure is based on the first invention and is characterized in that the capacitance of the capacitor 31 is set to suppress the voltage variation of the capacitor 31 during the switching cycle of the switching elements 41a~46a to less than 1 / 10 of the average value of the voltage of the capacitor 31.

[0013] The third aspect of the invention disclosed in the present invention is based on the first aspect of the invention or the second aspect of the invention, and is characterized in that: when the capacitance of the capacitor 31 is set to C, the breakdown voltage of the capacitor 31 is set to Vc1, the peak voltage of the capacitor 31 in the switching operation is set to Vc2, and the maximum magnetic energy stored in the load is set to E, the following equation holds.

[0014] C(Vc1 2 -Vc2 2 ) / 2<E

[0015] The fourth invention of the present disclosure is based on any one of the first to third inventions, and is characterized in that the rectifier circuit 20, the inverter circuit 40, the overvoltage protection circuit 50 and the control circuits 60 and 70 are installed on the same substrate.

[0016] A fifth aspect of the present disclosure is based on any one of the first to fourth aspects of the present disclosure, and is characterized in that at least the inverter circuit 40 and the overvoltage protection circuit 50 are housed in the same package P1.

[0017] The resistor 51 and the semiconductor element 52 with small power tolerances are also small in size. As a result, the overvoltage protection circuit 50 can be housed together with the inverter circuit 40 in the same package P1, and the overvoltage protection circuit 50 can be cooled simultaneously with the inverter circuit 40.

[0018] The sixth invention of the present disclosure is based on any one of the first to fifth inventions, and is characterized in that the capacitance C of the capacitor (31) is determined so as to satisfy the following equation based on the power supply voltage Vac of the power supply and the maximum power Pmax of the alternating current:

[0019] [Formula 1]

[0020]

[0021] The seventh invention of the present disclosure is based on any one of the first to sixth inventions, and is characterized in that the control circuit 60, 70 operates the overvoltage protection circuit 50 when the inverter circuit 40 stops supplying power to the load.

[0022] The eighth invention of the present disclosure is based on any one of the first to seventh inventions, and is characterized in that the control circuit 60, 70 operates the overvoltage protection circuit 50 during a part of the period during which the capacitor 31 is charged just after the voltage of the AC power supply 1 rises sharply.

[0023] The ninth invention of the present disclosure is based on any one of the first to eighth inventions, and is characterized in that the control circuit 60, 70 operates the overvoltage protection circuit 50 during a portion of the period during which the circuit including the capacitor 31 generates resonance.

[0024] The tenth invention of the present disclosure is based on any one of the first to ninth inventions, and is characterized in that: when the input voltage applied to the inverter circuit 40 via the capacitor 31 becomes greater than a first specified value, the control circuit 60, 70 turns on the semiconductor element 52 to operate the overvoltage protection circuit 50, and when the input voltage applied to the inverter circuit 40 becomes less than a second specified value after the overvoltage protection circuit 50 starts to work, the semiconductor element 52 is disconnected to stop the overvoltage protection circuit 50, and the second specified value is set to be smaller than the first specified value.

[0025] The input voltage applied to the inverter circuit 40 is reduced due to the operation of the overvoltage protection circuit 50 .

[0026] The eleventh invention of the present disclosure is based on any one of the first to ninth inventions, and is characterized in that: when the input voltage applied to the inverter circuit 40 via the capacitor 31 becomes greater than a third specified value, the control circuit 60, 70 turns on the semiconductor element 52, so that the overvoltage protection circuit 50 starts to work. When a specified time has passed after the overvoltage protection circuit 50 starts to work, the control circuit 60, 70 turns off the semiconductor element 52, so that the overvoltage protection circuit 50 stops working.

[0027] The input voltage applied to the inverter circuit 40 is reduced due to the operation of the overvoltage protection circuit 50 .

[0028] The twelfth invention of the present disclosure is based on any one of the first to ninth inventions, and is characterized in that: when the input voltage applied to the inverter circuit 40 in the state of stopping the switching operation via the capacitor 31 becomes greater than a fourth specified value, the control circuit 60, 70 turns on the semiconductor element 52 to operate the overvoltage protection circuit 50, and after the overvoltage protection circuit 50 starts to work, at least one of the multiple switching elements 41a~46a of the inverter circuit 40 in the state of stopping the switching operation is switched from disconnection to conduction.

[0029] The input voltage applied to the inverter circuit 40 in which the switching operation is stopped is reduced by the operation of the overvoltage protection circuit 50. After the overvoltage protection circuit 50 starts to operate, the switching elements 41a to 46a are turned on, thereby reducing the burden of the overvoltage protection circuit 50. Elements with smaller power tolerance values ​​can be selected as the resistor 51 and the semiconductor element 52.

[0030] The thirteenth invention of the present disclosure is based on the twelfth invention and is characterized in that: after the control circuit 60, 70 turns on at least one of the switching elements 41a~46a, it disconnects the semiconductor element 52 of the overvoltage protection circuit 50 to stop the overvoltage protection circuit 50.

[0031] The power allowable value of the overvoltage protection circuit 50 can be further reduced.

[0032] The fourteenth invention of the present disclosure is based on any one of the first to thirteenth inventions, and is characterized in that: during the operation of the overvoltage protection circuit 50, the control circuit 60, 70 performs conduction control to turn on at least one of the multiple switching elements 41a~46a, so that the absolute value of the average output power of the inverter circuit 40 is smaller than the case where all of the multiple switching elements 41a~46a are disconnected.

[0033] During the operation of the overvoltage protection circuit 50 , the absolute value of the power output by the inverter circuit 40 decreases, thereby reducing the amount of electric energy transferred from the load 2 to the capacitor 31 and reducing the capacitance of the capacitor 31 .

[0034] A fifteenth invention of the present disclosure is based on the fourteenth invention, and is characterized in that the conduction control is implemented in such a way that the average output power of the inverter circuit 40 is substantially zero.

[0035] A sixteenth invention of the present disclosure is based on the fourteenth invention or the fifteenth invention, and is characterized in that the conduction control is to make the inverter circuit 40 a zero vector state.

[0036] The seventeenth invention of the present disclosure is based on the fourteenth invention or the fifteenth invention, and is characterized in that the conduction control is implemented in a manner that the output power of the inverter circuit 40 is switched to positive or negative in the switching cycle of the switching elements 41a~46a, and the average output power of the inverter circuit 40 in each switching cycle is approximately zero.

[0037] The eighteenth invention of the present disclosure is based on the fourteenth invention or the fifteenth invention, and is characterized in that the conduction control is implemented in a manner that the output power of the inverter circuit 40 is switched to positive or negative within multiple consecutive switching cycles of the switching elements 41a~46a, and the average output power of the inverter circuit 40 within the multiple consecutive switching cycles is approximately zero.

[0038] The nineteenth invention of the present disclosure is based on any one of the fourteenth to eighteenth inventions, and is characterized in that the conduction control controls the switching signal for controlling the switching elements 41a~46a based on at least one of the current flowing from the inverter circuit 40 to the capacitor 31 and the voltage of the capacitor 31.

[0039] The twentieth invention of the present disclosure is based on any one of the fourteenth to nineteenth inventions, and is characterized in that the switching cycle of the switching elements 41a~46a in the conduction control is set to be shorter than the switching cycle in supplying power to the load.

[0040] The twenty-first invention of the present disclosure is based on any one of the fourteenth to twentieth inventions, and is characterized in that: the load is a permanent magnet motor, and the conduction control is implemented so that when the d-axis current of the load in the conduction control is set to Id, the q-axis current of the load is set to Iq, the minimum value of the d-axis current causing irreversible demagnetization of the magnet of the load is set to Im, the magnetic flux of the magnet is set to Φm, and the d-axis inductance of the load is set to Ld, the following equation holds.

[0041] (Id+Φm / Ld) 2 +Iq 2 <Im 2

[0042] The twenty-second invention of the present disclosure is based on any one of the fourteenth to twentieth inventions, and is characterized in that: the conduction control is implemented so that when the magnitude of the dq-axis current vector of the load in the conduction control is set to Idq, the minimum value of the magnitude of the d-axis current causing irreversible demagnetization in the magnet of the load is set to Im, the magnetic flux of the magnet is set to Φm, and the d-axis inductance of the load is set to Ld, the following equation holds.

[0043] Idq<Im-Φm / Ld

[0044] The twenty-third invention of the present disclosure is based on any one of the first to twenty-second inventions, and is characterized in that the switching elements 41a to 46a are elements whose main material is a wide bandgap semiconductor including silicon carbide, gallium nitride or diamond.

[0045] The chip area of ​​the elements constituting the inverter circuit 40 can be reduced.

[0046] The twenty-fourth invention of the present disclosure is based on any one of the first to twenty-third inventions, and is characterized in that the semiconductor element 52 is an element whose main material is a wide bandgap semiconductor including silicon carbide, gallium nitride or diamond.

[0047] The chip area of ​​the elements constituting the overvoltage protection circuit 50 can be reduced.

[0048] The twenty-fifth invention of the present disclosure is a power conversion device, including an inverter circuit 40 and an overvoltage protection circuit 50, wherein the inverter circuit 40 has a plurality of switching elements 41a~46a, which convert direct current into alternating current and supply it to a load; the overvoltage protection circuit 50 has a resistor 51 and a semiconductor element 52 connected in series with each other, which are connected in parallel with the DC part of the inverter circuit 40 to protect the inverter circuit 40 from being damaged by an overvoltage applied to the inverter circuit 40, and the inverter circuit 40 and the overvoltage protection circuit 50 are housed in the same package P1.

[0049] When the inverter circuit 40 is cooled, the overvoltage protection circuit 50 can also be cooled at the same time.

[0050] The twenty-sixth invention of the present disclosure is based on the twenty-fifth invention and is characterized in that the switching elements 41a~46a are elements whose main material is a wide bandgap semiconductor including silicon carbide, gallium nitride or diamond.

[0051] The chip area of ​​the elements constituting the inverter circuit 40 can be reduced.

[0052] The twenty-seventh invention of the present disclosure is based on the twenty-fifth invention or the twenty-sixth invention, and is characterized in that the semiconductor element 52 is an element whose main material is a wide bandgap semiconductor including silicon carbide, gallium nitride or diamond.

[0053] The chip area of ​​the elements constituting the overvoltage protection circuit 50 can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is a circuit diagram of a power conversion device according to a first embodiment;

[0055] Figure 2 is a timing chart showing the operation of each circuit in the first embodiment;

[0056] Figure 3 is a circuit diagram of a power conversion device according to a second embodiment;

[0057] Figure 4 is a timing chart showing the operation of each circuit in the second embodiment;

[0058] Figure 5 is a circuit diagram of a power conversion device according to a third embodiment;

[0059] Figure 6 is a timing chart showing the operation of each circuit in the third embodiment;

[0060] Figure 7 is a circuit diagram of a power conversion device according to a fourth embodiment;

[0061] Figure 8 is a timing chart showing the operation of each circuit before and after the power supply is turned on in the fourth embodiment;

[0062] Fig. 9 is a timing chart showing the operation of each circuit before and after an abnormality occurs in the load in the fourth embodiment;

[0063] Fig.10 is a circuit diagram of a power conversion device according to a fifth embodiment;

[0064] Fig.11 is a timing chart showing the operation of each circuit in the fifth embodiment;

[0065] Fig.12 is a circuit diagram illustrating a state of an inverter circuit during conduction control in the sixth embodiment;

[0066] Fig.13 This is an illustration of the eight vectors used in the inverter circuit.

[0067] Fig.14is a timing chart showing the operation of each circuit in the eighth embodiment;

[0068] Fig.15 is a timing chart showing the operation of each circuit in the first modification of the eighth embodiment;

[0069] Fig.16 is a functional block diagram showing a structure for realizing a control function of a first control unit on a switch signal;

[0070] Fig.17 is a timing chart showing the operation of each circuit in the ninth embodiment;

[0071] Fig.18 is a timing chart showing the operation of each circuit in the tenth embodiment;

[0072] Fig.19 It is a timing chart showing the operation of each circuit in the modification of the tenth embodiment.

[0073] - Explanation of symbols -

[0074] 10 Power conversion device

[0075] 20 Rectification circuit

[0076] 31 Capacitor

[0077] 40 Inverter Circuit

[0078] 41a~43a upper branch side switch element

[0079] 44a~46a Lower branch side switch element

[0080] 50 Overvoltage protection circuit

[0081] 51 Resistors

[0082] 52 Semiconductor components

[0083] 60 first control unit (control circuit)

[0084] 70 second control unit (control circuit)

[0085] 80 substrate

[0086] Vdc DC link voltage (input voltage) DETAILED DESCRIPTION

[0087] (First Embodiment)

[0088] <Outline>

[0089] Figure 11 is a circuit diagram of a power conversion device 10 according to the first embodiment. The power conversion device 10 is connected to an AC power source 1 and a load 2 .

[0090] Figure 1 The example in which the AC power source 1 is a three-phase AC power source is shown. In the first embodiment, the load 2 is a permanent magnet motor of a compressor in a refrigerant circuit of an air conditioner. It should be noted that a motor or a transformer of a system that does not require regenerative braking can be used as the load 2.

[0091] Three-phase AC power is input from the AC power source 1 to the power conversion device 10. The power conversion device 10 converts the power into AC power having a desired frequency and a desired voltage, and supplies the AC power to the load 2. As a result, the load 2 operates.

[0092] <Structure>

[0093] like Figure 1 As shown, the power conversion device 10 includes a rectifier circuit 20 , a DC link unit 30 , an inverter circuit 40 , an overvoltage protection circuit 50 , a first control unit 60 as a control circuit, and a second control unit 70 .

[0094] (Rectifier circuit)

[0095] The rectifier circuit 20 includes a plurality of semiconductor elements and converts the power output from the AC power source 1 into DC power.

[0096] In the first embodiment, the case where the rectifier circuit 20 is a full-wave rectifier circuit is exemplified. The rectifier circuit 20 includes six diodes 21 to 26 as a plurality of semiconductor elements. The six diodes 21 to 26 are connected in a bridge shape.

[0097] (DC link part)

[0098] The DC link unit 30 is located between the rectifier circuit 20 and the inverter circuit 40 and includes a capacitor 31. The capacitor 31 is connected between a pair of output nodes of the rectifier circuit 20 and is connected in parallel with the rectifier circuit 20 and the inverter circuit 40, respectively.

[0099] A DC voltage corresponding to the DC power is inputted from the rectifying circuit 20 to the capacitor 31. The capacitor 31 generates a DC link voltage Vdc using the DC voltage. The DC link voltage Vdc pulsates at a frequency of the power supply voltage Vac corresponding to the power supply power.

[0100] The reason why the DC link voltage Vdc includes a pulsating component corresponding to the frequency of the power supply voltage Vac is described. The capacitance value of the capacitor 31 is set so that the output voltage of the rectifier circuit 20 can be almost smoothed but the ripple voltage caused by the switching operation of the inverter circuit 40 can be suppressed. The ripple voltage is a voltage fluctuation corresponding to the switching frequency of the switching elements 41a to 46a.

[0101] In short, the capacitor 31 allows the output voltage of the rectifier circuit 20 to fluctuate, and absorbs the output voltage of the inverter circuit 40 fluctuating due to the switching operation. Specifically, the capacitance of the capacitor 31 is set so that the voltage fluctuation of the capacitor 31 during the switching cycle is suppressed to less than 1 / 10 of the average value of the voltage of the capacitor 31. Therefore, the minimum capacitance required of the capacitor 31 is determined by the switching frequency and the load current flowing between the load 2 and the capacitor 31.

[0102] By setting the capacitance C of the capacitor 31 to satisfy the following formula (A), the voltage variation of the capacitor 31 during the switching cycle can be suppressed to less than 1 / 10 of the average value of the voltage of the capacitor 31. In the formula (A), the output voltage variation of the rectifier circuit 20 superimposed on the DC link voltage Vdc is ignored, the average value of the DC link voltage Vdc is set to VAdc, the peak value of the load current when the AC power is the maximum power is set to Imax, and the switching cycle is set to Ts.

[0103] C≥(10·Imax·Ts) / VAdc……(A)

[0104] Here, the switching cycle is a cycle in which the switching elements 41a to 46a repeatedly turn on and off. In the first embodiment, the switching elements 41a to 46a are controlled by PWM (pulse width modulation) control, so the switching cycle is a carrier cycle of the carrier.

[0105] Furthermore, the capacitance value C of the capacitor 31 is determined so as to satisfy the following equation (1) based on the power supply voltage Vac and the maximum power Pmax of the AC power output by the inverter circuit 40 .

[0106] [Formula 1]

[0107]

[0108] Furthermore, when the capacitance of the capacitor 31 is set to C, the breakdown voltage of the capacitor 31 is set to Vc1, the peak voltage of the capacitor 31 during the switching operation is set to Vc2, and the maximum magnetic energy stored in the inductance component of the load 2 is set to E, the following equation (2) holds.

[0109] C(Vc1 2 -Vc2 2) / 2<E……(2)

[0110] In a general power conversion device, an electrolytic capacitor is used as a smoothing capacitor for smoothing the output voltage of the rectifier circuit 20. On the other hand, the capacitance value of the capacitor 31 of this embodiment is about 0.01 times that of the smoothing capacitor, which is actually about several tens of μF. As an example, the capacitor 31 is composed of a film capacitor.

[0111] Since the capacitance of the capacitor 31 is small, the output voltage of the rectifier circuit 20 is hardly smoothed in the DC link unit 30. As a result, a pulsating component corresponding to the frequency of the power supply voltage Vac remains in the DC link voltage Vdc. In the case of the first embodiment, the AC power supply 1 is a three-phase power supply, so the pulsating component corresponding to the frequency of the power supply voltage Vac is six times the frequency of the power supply voltage.

[0112] The DC link unit 30 further includes a voltage detection unit 32. The voltage detection unit 32 is a sensor located near the capacitor 31, and detects the DC link voltage Vdc.

[0113] (Inverter circuit)

[0114] A pair of input nodes of the inverter circuit 40 are connected to both ends of the capacitor 31. The inverter circuit 40 has a plurality of switch elements 41a to 46a and return diodes 41b to 46b. The plurality of switch elements 41a to 46a respectively include a plurality of upper branch switch elements 41a to 43a and a plurality of lower branch switch elements 44a to 46a. The upper branch switch elements 41a to 43a are respectively connected in series with the corresponding lower branch switch elements 44a to 46a. The midpoints of the upper branch switch elements 41a to 43a and the lower branch switch elements 44a to 46a are respectively connected to the respective phase windings (U phase, V phase, W phase windings) of the load 2, forming the output nodes of the inverter circuit 40. In the following, the output current of the inverter circuit 40 of the U phase flowing from the inverter circuit 40 to the load 2 is called the U phase current Iu, the output current of the inverter circuit 40 of the V phase flowing from the inverter circuit 40 to the load 2 is called the V phase current Iv, and the output current of the inverter circuit 40 of the W phase flowing from the inverter circuit 40 to the load 2 is called the W phase current Iw.

[0115] The DC link voltage Vdc is applied as an input voltage to the inverter circuit 40. The inverter circuit 40 converts DC power corresponding to the DC link voltage Vdc into AC power by switching operation and supplies it to the load 2. Here, the switching operation of the inverter circuit 40 refers to the operation of turning on / off the switching elements 41a to 46a.

[0116] The switching elements 41 a to 46 a are elements whose main material is a wide bandgap semiconductor including silicon carbide (SiC), gallium nitride (GaN), or diamond (C).

[0117] (Overvoltage protection circuit)

[0118] The overvoltage protection circuit 50 is connected in parallel with the rectifier circuit 20 and the capacitor 31 between the rectifier circuit 20 and the DC link unit 30. The overvoltage protection circuit 50 includes a resistor 51 and a semiconductor element 52. The resistor 51 and the semiconductor element 52 are connected in series with each other.

[0119] When the DC link voltage Vdc, which becomes an overvoltage, is applied to the inverter circuit 40 , the overvoltage protection circuit 50 protects the inverter circuit 40 .

[0120] The resistance value of the resistor 51 is set smaller than that of the brake circuit of International Publication No. 2017 / 098836. The resistance value is determined by the current flowing back to the inverter circuit 40 of the load 2 during the switching stop, in other words, by the magnetic energy stored in the inductance component of the load 2.

[0121] The semiconductor element 52 is a switching element and is an element whose main material is a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond (C).

[0122] Wide bandgap semiconductors can also operate at a high temperature of about 200 degrees. Although the overvoltage protection circuit 50 is small in size, it can convert the energy of overvoltage into heat.

[0123] (First Control Unit)

[0124] The first control unit 60 is composed of various elements, a microcomputer, a memory, etc. The output terminal of the first control unit 60 is connected to the gate terminal of each of the switching elements 41 a to 46 a in the inverter circuit 40 .

[0125] The first control unit 60 outputs a control signal G_INV to the inverter circuit 40 to control the switching operation of each switch element 41a~46a. This control includes control to make the rotation speed of the load 2 close to the desired rotation speed. The first control unit 60 performs PWM (pulse width modulation) control of multiple switch elements 41a~46a according to the switching signal corresponding to the comparison result of the modulation wave of each phase and the prescribed triangular wave, that is, the carrier. In detail, if the modulation wave is greater than the carrier, the upper branch switch elements 41a~43a are turned on and the lower branch switch elements 44a~46a are turned off. On the other hand, if the modulation wave is less than the carrier, the upper branch switch elements 41a~43a are turned off and the lower branch switch elements 44a~46a are turned on.

[0126] (Second Control Unit)

[0127] The second control unit 70 has one input terminal. The DC link voltage Vdc detected by the voltage detection unit 32 is input to the input terminal.

[0128] The second control unit 70 has one output terminal. The output terminal is connected to the input terminal of the semiconductor element 52 in the overvoltage protection circuit 50. The second control unit 70 controls the overvoltage protection circuit 50.

[0129] The second control unit 70 includes two setters 72 and 73 , two comparators 74 and 75 , and a determiner 76 .

[0130] The setter 72 sets and stores a first prescribed value. The setter 73 sets and stores a second prescribed value. The first prescribed value and the second prescribed value are threshold values ​​of voltage and are used to control the operation of the semiconductor element 52. The second prescribed value is set to be smaller than the first prescribed value.

[0131] The comparator 74 has two input terminals. One input terminal is connected to the setter 72, and the other input terminal is connected to the voltage detector 32. The comparator 74 compares the first predetermined value with the detection result of the voltage detector 32, that is, the DC link voltage Vdc.

[0132] The comparator 75 has two input terminals. One input terminal is connected to the setter 73, and the other input terminal is connected to the voltage detection unit 32. The comparator 75 compares the second predetermined value with the DC link voltage Vdc.

[0133] The judgement device 76 has two input terminals. The two input terminals are connected to the output terminals of the comparators 74 and 75, respectively. The judgement device 76 performs a logic operation using the output signals from the comparators 74 and 75. The output terminal of the judgement device 76 is connected to the input terminal of the semiconductor element 52, and the operation signal G_OVDPOR output by the judgement device 76 is applied to the semiconductor element 52. The semiconductor element 52 is turned on or off, and the overvoltage protection circuit 50 works or stops working.

[0134] <Work Status>

[0135] Reference Figure 2 The timing diagram illustrates the working conditions of each circuit included in the power conversion device 10. Figure 2 The diagram shows how the DC link voltage Vdc, the operation of the inverter circuit 40 , the output signals of the comparators 74 , 75 , and the operation of the overvoltage protection circuit 50 change over time.

[0136] During the period from time t0 to time t1, the inverter circuit 40 performs a switching operation. During this period, the DC link voltage Vdc applied to the inverter circuit 40 is a value less than the second predetermined value and is stable. During this period, the output signals of the two comparators 74 and 75 are all "off". Therefore, the operation signal G_OVDPOR output by the determiner 76 is "off", and the overvoltage protection circuit 50 stops operating.

[0137] Assume that at time t1, the first control unit 60 switches the control signal G_INV from "ON" to "OFF" to stop the switching operation of the inverter circuit 40. In the first embodiment, when the switching operation is stopped, all the switching elements 41a to 46a of the inverter circuit 40 are turned off. The DC link voltage Vdc starts to rise due to the regeneration of magnetic energy of the load 2.

[0138] Assuming that the DC link voltage Vdc exceeds the second predetermined value at time t2, the comparator 75 switches the output signal from "off" to "on".

[0139] Assuming that the DC link voltage Vdc further continues to rise, and as a result, at time t3, the DC link voltage Vdc becomes equal to or higher than the first predetermined value, the comparator 74 switches the output signal from "off" to "on".

[0140] At time t3, the output signals input to the judgement device 76 from the comparators 74 and 75 are all "ON". The judgement device 76 switches the operation signal G_OVDPOR from "OFF" to "ON". After receiving the operation signal G_OVDPOR, the semiconductor element 52 is turned on, and the overvoltage protection circuit 50 starts to operate. The DC link voltage Vdc starts to drop.

[0141] As described above, the energy regenerated in the DC link unit 30 is only the magnetic energy stored in the load 2 , so during the operation of the overvoltage protection circuit 50 , the loss consumed by the resistor 51 is smaller than that of the brake circuit of International Publication No. 2017 / 098836.

[0142] Assuming that at time t4 after time t3, the decreasing DC link voltage Vdc reaches a value that is not more than the first predetermined value and greater than the second predetermined value, only the output signal of the comparator 74 switches from "ON" to "OFF".

[0143] However, the judgement device 76 does not switch the working signal G_OVDPOR only because the output signal of the comparator 74 is switched to "off". The judgement device 76 switches the working signal G_OVDPOR because the output signal of the comparator 74 and the output signal of the comparator 75 are both turned "off". This is to reduce the DC link voltage Vdc as much as possible. Even if the output signal of the comparator 74 is switched to "off" at time t4, the judgement device 76 continues to maintain the working signal G_OVDPOR "on" from time t3. The overvoltage protection circuit 50 also works after time t4, and the DC link voltage Vdc continues to drop.

[0144] Assume that at time t5, the DC link voltage Vdc becomes less than the second specified value. The comparator 75 switches the output signal from "on" to "off". Since the output signals of the two comparators 74 and 75 are both "off", the determiner 76 switches the working signal G_OVDPOR from "on" to "off". After receiving the working signal G_OVDPOR, the semiconductor element 52 is turned off, and the overvoltage protection circuit 50 stops working. The DC link voltage Vdc stops decreasing and remains below the second specified value.

[0145] Thus, during the period when the inverter circuit 40 stops switching operation, the DC link voltage Vdc can be suppressed from rising due to the regeneration of the magnetic energy stored in the inductance component of the load 2, and the diodes 21 to 26 of the rectifier circuit 20 and the switching elements 41a to 46a of the inverter circuit 40 are destroyed. The period from time t3 to time t5, that is, the operation time of the overvoltage protection circuit 50 is short, and the energy consumed by the overvoltage protection circuit 50 is also small. Therefore, the resistor 51 and the semiconductor element 52 can be selected as elements with a small allowable value of power.

[0146] <Single-unit packaging>

[0147] like Figure 1 As shown, the inverter circuit 40 and the overvoltage protection circuit 50 are housed in the same package P1.

[0148] In addition, the rectifier circuit 20 , the capacitor 31 , the inverter circuit 40 , the overvoltage protection circuit 50 , and the control circuits 60 and 70 are mounted on the same substrate 80 .

[0149] International Publication No. 2017 / 098836 cites a document for the purpose of implementing regenerative braking of a motor. In order to consume all the regenerative energy of load 2, it is necessary to select an element with a large power tolerance as a component constituting the braking circuit.

[0150] In the first embodiment, as described above, a component with a small power tolerance can be selected as the resistor 51. The operating time of the overvoltage protection circuit 50 is also short, and the loss is small. In the first embodiment, a component with a small size can be selected as the resistor 51.

[0151] Furthermore, the semiconductor element 52 in the overvoltage protection circuit 50 and the switch elements 41a to 46a in the inverter circuit 40 are elements whose main materials are wide bandgap semiconductors. The chip area of ​​the elements constituting the inverter circuit 40 can be reduced. Even if the semiconductor element 52 is made to have a size that can withstand a large current, the chip area of ​​the elements constituting the overvoltage protection circuit 50 can be reduced.

[0152] Therefore, in the first embodiment, it is easy to accommodate the inverter circuit 40 and the overvoltage protection circuit 50 in the same package P1.

[0153] The switching elements 41a to 46a generate heat due to the switching operation, and therefore need to be cooled. The resistor 51 also generates heat due to the flow of current. In the first embodiment, the inverter circuit 40 and the overvoltage protection circuit 50 are housed in the same package P1, so when the switching elements 41a to 46a are cooled, the resistor 51 is also cooled. There is no need to provide a cooling mechanism for the switching elements 41a to 46a and a cooling mechanism for the resistor 51 separately.

[0154] <Effect>

[0155] In the first embodiment, the magnetic energy of the inductance component stored in the load 2 can be consumed by the overvoltage protection circuit 50 , so the capacitance of the capacitor 31 can be reduced.

[0156] The capacitance of the capacitor 31 is small enough to allow the variation of the output voltage of the rectifier circuit 20 and absorb the variation of the output voltage of the inverter circuit 40 caused by the switching operation. The power consumed by the overvoltage protection circuit 50 only needs to be the energy stored in the inductance of the load 2. Therefore, compared with the case where the overvoltage protection circuit 50 consumes power for the purpose of regenerative braking of the load 2, elements with smaller power tolerance values ​​can be selected as the resistor 51 and the semiconductor element 52 included in the overvoltage protection circuit 50.

[0157] The resistor 51 and the semiconductor element 52 have smaller power tolerance values ​​and smaller element sizes. As a result, the overvoltage protection circuit 50 can be easily housed together with the inverter circuit 40 in the same package P1, and when the inverter circuit 40 is cooled, the overvoltage protection circuit 50 can also be cooled at the same time. Therefore, the inverter circuit 40 and the overvoltage protection circuit 50 can share a heat dissipation mechanism with good performance, so the device can be miniaturized and the cost can be reduced. In addition, since the overvoltage protection circuit 50 is cooled by a heat dissipation mechanism with good performance, the elements constituting the overvoltage protection circuit 50 can also be miniaturized. It should be noted that when the rectifier circuit 20 is further housed in the same package P1, the device can be further miniaturized.

[0158] The switching elements 41a to 46a and the semiconductor element 52 are elements mainly made of wide bandgap semiconductors such as silicon carbide, gallium nitride, or diamond, so that the chip area of ​​the elements constituting the inverter circuit 40 and the overvoltage protection circuit 50 can be reduced.

[0159] In addition, since the overvoltage protection circuit 50 is composed of the resistor 51 and the semiconductor element 52, the overvoltage protection circuit 50 can consume energy at any time. Therefore, compared with the case where the overvoltage protection circuit 50 is composed of a nonlinear resistor or a Zener diode, by extending the energy consumption time and reducing the energy consumption per unit time, that is, the power consumption, the components constituting the overvoltage protection circuit 50 can be further miniaturized.

[0160] Furthermore, since the overvoltage protection circuit 50 uses the resistor 51 having a heat resistance temperature generally higher than that of a nonlinear resistor or a Zener diode, the overvoltage protection circuit 50 can be easily miniaturized compared with a case where the overvoltage protection circuit 50 is composed of a nonlinear resistor or a Zener diode.

[0161] In addition, since the electric energy that the capacitor 31 can retain until the voltage of the capacitor 31 exceeds the rated operating voltage and reaches the breakdown voltage is smaller than the maximum magnetic energy stored in the load 2, if there is no overvoltage protection circuit 50, when the inverter circuit 40 stops the switching operation, the magnetic energy of the load 2 will be absorbed by the capacitor 31, and the voltage of the capacitor 31 will exceed its breakdown voltage. However, in the first embodiment, since the overvoltage protection circuit 50 is provided, the power absorbed by the capacitor 31 can be reduced, and the voltage of the capacitor 31 can be prevented from exceeding its breakdown voltage without increasing the static capacitance and breakdown voltage of the capacitor 31. Therefore, the capacitor 31 can be miniaturized and the cost of the capacitor 31 can be reduced.

[0162] (Second Embodiment)

[0163] Reference Figure 3 and Figure 4 A power conversion device 10 according to the second embodiment will be described.

[0164] <Structure>

[0165] In the second embodiment, the configuration of the second control unit 70 is different from that of the first embodiment. Figure 3 The power conversion device 10 in the embodiment of the present invention is composed of Figure 1 Next, the second control unit 70 will be described.

[0166] (Second Control Unit)

[0167] As in the first embodiment, one input terminal of the second control unit 70 is connected to the voltage detection unit 32. One output terminal of the second control unit 70 is connected to an input terminal of the semiconductor element 52 of the overvoltage protection circuit 50. The second control unit 70 controls the overvoltage protection circuit 50.

[0168] Different from the first embodiment, the second control unit 70 includes two setters 72 and 81 , one comparator 74 , and one determiner 82 .

[0169] The third prescribed value is set and stored by the setter 72 of the two setters 72 and 81 .

[0170] The comparator 74 compares the third predetermined value with the DC link voltage Vdc which is the detection result of the voltage detection unit 32 .

[0171] The other setting device 81 stores a predetermined time set in advance. Hereinafter, in order to distinguish it from the setting device 72, the setting device 81 is referred to as an on-time setting device.

[0172] The on-time setter 81 has an input terminal and an output terminal. The input terminal of the on-time setter 81 is connected to the output terminal of the comparator 74. The output terminal of the on-time setter 81 is connected to the input terminal of the determiner 82.

[0173] The on-time setting device 81 determines whether a DC link voltage Vdc greater than or equal to a third predetermined value is applied to the inverter circuit 40 based on the output signal of the comparator 74. The on-time setting device 81 sets the output signal to "on" during the period from when the DC link voltage Vdc greater than or equal to the third predetermined value is applied to the inverter circuit 40 until a predetermined time has passed.

[0174] The predetermined time is set in advance based on the limit values ​​of the heat amounts of the resistor 51 and the semiconductor element 52 of the overvoltage protection circuit 50. In the second embodiment, the predetermined time is a fixed value.

[0175] The output signal from the comparator 74 and the output signal from the on-time setter 81 are input to the determiner 82. The determiner 82 performs a logic operation on these signals. The operation signal G_OVDPOR outputted from the determiner 82 is applied to the semiconductor element 52. The semiconductor element 52 is turned on or off.

[0176] <Work Status>

[0177] Figure 4 2 shows the time-dependent changes of the DC link voltage Vdc, the operation of the inverter circuit 40, the output signal of the comparator 74, the output signal of the conduction time setter 81, and the operation of the overvoltage protection circuit 50.

[0178] During the period from time t0 to time t1, the inverter circuit 40 performs a switching operation. During this period, the DC link voltage Vdc is less than the third specified value and is stable. The output signals of the comparator 74 and the conduction time setter 81 and the operation signal G_OVDPOR are both "off", and the overvoltage protection circuit 50 stops working.

[0179] Assume that at time t1, the first control unit 60 stops the switching operation of the inverter circuit 40. The DC link voltage Vdc starts to rise due to the recirculation of the inductive energy of the load 2.

[0180] Assuming that the DC link voltage Vdc exceeds the third predetermined value at time t2, the comparator 74 switches the output signal from "off" to "on".

[0181] After receiving the output signal of the comparator 74, the on-time setter 81 switches its own output signal from "off" to "on" at the same time as the switching timing of the output signal of the comparator 74. The on-time setter 81 starts counting the time from when its own output signal is switched to "on".

[0182] At time t2, all output signals input to the determiner 82 become "ON", so the determiner 82 switches the operation signal G_OVDPOR from "OFF" to "ON". After receiving the operation signal G_OVDPOR, the semiconductor element 52 is turned on, and the overvoltage protection circuit 50 starts to operate. The DC link voltage Vdc starts to drop.

[0183] Assuming that at time t3, the decreasing DC link voltage Vdc is lower than the third predetermined value, only the output signal of the comparator 74 switches from "ON" to "OFF". The on-time setter 81 and the determiner 82 maintain the output signal of "ON".

[0184] Assume that at time t4, the time counted by the on-time setter 81 from time t2 reaches the prescribed time. The on-time setter 81 switches the output signal from "on" to "off". Since the output signal of the comparator 74 and the output signal of the on-time setter 81 are both "off", the determiner 82 switches the operating signal G_OVDPOR from "on" to "off". After receiving the operating signal G_OVDPOR, the semiconductor element 52 is turned off, and the overvoltage protection circuit 50 stops operating. The DC link voltage Vdc stops decreasing and remains below the third prescribed value.

[0185] Therefore, similarly to the first embodiment, during the time when the inverter circuit 40 stops switching operation, the DC link voltage Vdc can be suppressed from rising due to the regeneration of the energy stored in the inductance component of the load 2, and the diodes 20 to 26 of the rectifier circuit 20 and the switching elements 41a to 46a of the inverter circuit 40 are destroyed. The time from time t2 to time t4, that is, the operation time of the overvoltage protection circuit 50 is short, and the energy consumed by the overvoltage protection circuit 50 is also small. Elements with a small power tolerance value can be selected as the resistor 51 and the semiconductor element 52.

[0186] As in the first embodiment, the semiconductor element 52 in the overvoltage protection circuit 50 and the switching elements 41a to 46a in the inverter circuit 40 are elements mainly made of wide bandgap semiconductors. The chip area of ​​the elements constituting the inverter circuit 40 and the overvoltage protection circuit 50 can be reduced.

[0187] Therefore, it becomes easy to accommodate the inverter circuit 40 and the overvoltage protection circuit 50 in the same package P1. When the switching elements 41a to 46a are cooled, the resistor 51 is also cooled.

[0188] <Effect>

[0189] Unlike the first embodiment, in the second embodiment, when the DC link voltage Vdc applied to the inverter circuit 40 becomes equal to or greater than the third predetermined value, the second control unit 70 starts the operation of the overvoltage protection circuit 50. When a predetermined time has passed after the overvoltage protection circuit 50 starts to operate, the second control unit 70 stops the operation of the overvoltage protection circuit 50. The DC link voltage Vdc decreases due to the operation of the overvoltage protection circuit 50. The optimal power capacity of the components of the overvoltage protection circuit 50 can be selected based on the third predetermined value and the predetermined time, and the device can be miniaturized and cost-effective.

[0190] (Third Embodiment)

[0191] Reference Figure 5 and Figure 6 A power conversion device 10 according to the third embodiment will be described.

[0192] <Structure>

[0193] The power conversion device 10 of the third embodiment is different from the first embodiment described above. Figure 1 In addition, the first control unit 60 further includes a wiring L1 connecting the first control unit 60 and the second control unit 70. Figure 1 In addition to the structure of the first embodiment, the second control unit 70 further has two input terminals and one output terminal. Figure 1 Based on the structure, it also has an input terminal and an "AND" operator 78.

[0194] Figure 5 The first control unit 60 in the embodiment has two input terminals. An operation signal G_OVDPOR, which is an output of the second control unit 70, is input to one input terminal. A DC link voltage Vdc detected by the voltage detection unit 32 is input to the other input terminal.

[0195] The first control unit 60 performs switching operation on the switching elements 41 a to 46 a of the inverter circuit 40 in the switching stop state, using the output signal G_OVDPOR of the second control unit 70 and the DC link voltage Vdc.

[0196] One output terminal of the first control unit 60 outputs a control signal ES1 for controlling the output of the determiner 76 to be turned off. In addition, one input terminal of the second control unit 70 is connected to one output terminal of the first control unit 60 via the wiring L1, and receives the control signal ES1. One input terminal of the second control unit 70 is connected to the input of the AND operator 78. The AND operator 78 calculates the logical product of the control signal ES1 and the output signal of the determiner 76. The output signal of the AND operator 78 becomes the output signal G_OVDPOR of the control unit 70.

[0197] The fifth prescribed value is set and stored by the setter 73 in the second control unit 70. The fourth prescribed value is set and stored by the setter 72. The fourth prescribed value and the fifth prescribed value are threshold values ​​of voltage and are used to control the operation of the semiconductor element 52. The fifth prescribed value is set to be smaller than the fourth prescribed value.

[0198] The first control unit 60 stores a sixth predetermined value. The sixth predetermined value is a voltage threshold value and is used to control the control signal ES1. The sixth predetermined value is set to be smaller than the fourth predetermined value and larger than the fifth predetermined value.

[0199] The comparator 74 compares the fourth predetermined value with the DC link voltage Vdc. The comparator 75 compares the fifth predetermined value with the DC link voltage Vdc.

[0200] Except for the above, the configuration of the power conversion device 10 of the third embodiment is the same as Figure 1 same.

[0201] <Work Status>

[0202] Figure 6 The diagram shows how the DC link voltage Vdc, the operation of the inverter circuit 40 , the output signal ES1 of the first controller 60 , the output signals of the comparators 74 , 75 , and the operation of the overvoltage protection circuit 50 change over time.

[0203] During the period from time t0 to time t1, the inverter circuit 40 performs a switching operation. During this period, the DC link voltage Vdc is less than the fifth specified value and is stable. The control signal ES1 and the output signals of the two comparators 74 and 75 and the operation signal G_OVDPOR are all "off", and the overvoltage protection circuit 50 stops working.

[0204] Assume that at time t1, the first control unit 60 stops the switching operation of the inverter circuit 40. At this time, the control signal ES1 of the first control unit 60 is switched from "off" to "on". The control signal ES1 indicates the stop of the switching operation. After time t1, the DC link voltage Vdc starts to rise due to the regeneration of the inductance component energy stored in the load 2.

[0205] Assuming that the DC link voltage Vdc exceeds the fifth predetermined value at time t2, the comparator 75 switches the output signal from "off" to "on".

[0206] Assuming that the DC link voltage Vdc further continues to rise, and as a result, the DC link voltage Vdc becomes equal to or higher than the fourth predetermined value at time t3, the comparator 74 switches the output signal from "off" to "on".

[0207] At time t3, the output signals inputted to the judgement unit 76 from the comparators 74 and 75 all become "ON". The judgement unit 76 switches the output signal from "OFF" to "ON". At this time, the input signals of the AND operator 78 all become "ON". The AND operator 78 switches the operation signal G_OVDPOR from "OFF" to "ON". After receiving the operation signal G_OVDPOR, the semiconductor element 52 turns on, and the overvoltage protection circuit 50 starts to operate. The DC link voltage Vdc starts to drop.

[0208] Assume that at time t4 after time t3, the DC link voltage Vdc that is decreasing becomes a value that is less than the fourth predetermined value and greater than the fifth predetermined value. Only the output signal of the comparator 74 is switched from "on" to "off", but the output signal of the determiner 76 continues to be "on" from time t3, and the operation signal G_OVDPOR also remains "on". This is to reduce the DC link voltage Vdc as much as possible. The overvoltage protection circuit 50 also operates after time t4, and the DC link voltage Vdc continues to decrease.

[0209] Assume that at time t5, the DC link voltage Vdc becomes less than the sixth predetermined value. After receiving the DC link voltage Vdc less than the sixth predetermined value and the operation signal G_OVDPOR in the "on" state, the first control unit 60 outputs a control signal G_INV for turning on (switching) at least one of the plurality of switching elements 41a to 46a of the inverter circuit 40 in which the switching operation is stopped to the inverter circuit 40. In addition, after turning on at least one of the plurality of switching elements 41a to 46a, the first control unit 60 switches the control signal ES1 from "on" to "off".

[0210] The AND operator 78 is switched to “OFF” by the control signal ES1, and the output signal is switched to “OFF”. The operating signal G_OVDPOR is thereby switched from “ON” to “OFF”.

[0211] The semiconductor element 52 in the overvoltage protection circuit 50 is turned off, and the overvoltage protection circuit 50 stops operating. The DC link voltage Vdc is maintained below the sixth prescribed value.

[0212] In the third embodiment, the first control unit 60 generates the control signal ES1 for indicating the state of the switch operation of the switch elements 41a to 46a, but a circuit for generating the same signal using the control signal G_INV may be separately provided. For example, by calculating the logical sum of the drive signals of all the switch elements 41a to 46a and inverting the calculation result, a signal identical to the control signal ES1 can be obtained.

[0213] As in the first and second embodiments, during the period when the inverter circuit 40 stops switching operation, the DC link voltage Vdc can be suppressed from rising due to the regeneration of the energy stored in the inductance component of the load 2, and the diodes 20 to 26 of the rectifier circuit 20 and the switching elements 41a to 46a of the inverter circuit 40 are destroyed. The period from time t3 to time t6, that is, the operating time of the overvoltage protection circuit 50 is short, and the energy consumed by the overvoltage protection circuit 50 is also small.

[0214] Furthermore, in the third embodiment, the first control unit 60 and the second control unit 70 stop the overvoltage protection circuit 50 after turning on (switching) at least one of the switching elements 41a to 46a, thereby reducing the burden on the overvoltage protection circuit 50. Elements with a smaller power tolerance can be selected as the resistor 51 and the semiconductor element 52, and the heating of the resistor 51 can be further suppressed.

[0215] Assume that the switch elements 41a to 46a are turned on after the overvoltage protection circuit 50 stops operating. If the DC link voltage Vdc is greater than the voltage allowable value of the switch elements 41a to 46a after the switch elements 41a to 46a are turned on, the switch elements 41a to 46a may be damaged. In contrast, in the third embodiment, at least one of the switch elements 41a to 46a is turned on before the overvoltage protection circuit 50 stops operating. Thereafter, the overvoltage protection circuit 50 stops operating. This can prevent the switch elements 41a to 46a from being damaged.

[0216] As in the first and second embodiments, the semiconductor element 52 in the overvoltage protection circuit 50 and the switch elements 41a to 46a in the inverter circuit 40 are elements mainly made of wide bandgap semiconductors. The chip area of ​​the elements constituting the inverter circuit 40 and the overvoltage protection circuit 50 can be reduced.

[0217] Therefore, it becomes easy to accommodate the inverter circuit 40 and the overvoltage protection circuit 50 in the same package P1. When the switching elements 41a to 46a are cooled, the resistor 51 is also cooled.

[0218] <Effect>

[0219] Unlike the first and second embodiments, in the third embodiment, when the DC link voltage Vdc applied to the inverter circuit 40 in which the switching operation is stopped becomes equal to or greater than the fourth predetermined value, the second control unit 70 operates the overvoltage protection circuit 50. The DC link voltage Vdc is reduced by the operation of the overvoltage protection circuit 50. After the overvoltage protection circuit 50 starts to operate, the first control unit 60 turns on (switches) at least one of the plurality of switching elements 41a to 46a of the inverter circuit 40 in which the switching operation is stopped. Since the burden of the overvoltage protection circuit 50 is reduced, elements with a smaller power tolerance can be selected as the resistor 51 and the semiconductor element 52.

[0220] Furthermore, the second control unit 70 turns on at least one of the switching elements 41a to 46a and then stops the operation of the overvoltage protection circuit 50. This can prevent the switching elements 41a to 46a from being damaged.

[0221] (Fourth Embodiment)

[0222] Reference Figure 7 A power conversion device 10 according to the fourth embodiment will be described.

[0223] <Structure>

[0224] In the fourth embodiment, based on the structure of the third embodiment, an input terminal and an output terminal are provided in the first control unit 60, two input terminals, a conduction time setter 79 and an "OR" circuit 77 are provided in the second control unit 70, and a wiring L2 connecting the first control unit 60 and the second control unit 70 is provided.

[0225] The first control unit 60, based on the configuration of the third embodiment, further includes an input terminal for inputting an abnormality stop signal ABS indicating whether or not an abnormality has occurred in the load 2. The input terminal is connected with wiring for receiving the abnormality stop signal ABS from an external control device (not shown). If the abnormality stop signal ABS changes from a state indicating that no abnormality has occurred to a state indicating that an abnormality has occurred during the switching operation, the first control unit 60 stops supplying AC power to the load 2 by stopping the switching operation of each switching element 41a to 46a at the same time. The abnormality of the load 2 is, for example, an overcurrent flowing to the load 2.

[0226] The first control unit 60, based on the configuration of the third embodiment, further includes an output terminal for outputting a control signal ES2 for controlling the output signal G_OVDPOR of the second control unit 70 to be turned on or off. The first control unit 60 identifies whether it is a charging period in which the capacitor 31 is charged just after the voltage of the AC power source 1 input to the power conversion device 10 rises sharply. The first control unit 60 can identify whether it is in the charging period based on the DC link voltage Vdc detected by the voltage detection unit 32. When it has been identified that it is in the charging process, the control signal ES2 selects "on" or "off" based on the seventh prescribed value and the eighth prescribed value. The seventh prescribed value and the eighth prescribed value are comparison values ​​with the DC link voltage Vdc, and are stored in the first control unit 60. The seventh prescribed value is approximately the voltage peak value of the AC power source 1 in normal conditions, and the eighth prescribed value is greater than the seventh prescribed value.

[0227] Examples of situations where the voltage of the AC power source 1 input to the power conversion device 10 rises suddenly include powering on the power conversion device 10, recovery of the AC power source 1 from a momentary power failure, and recovery of the AC power source 1 from a momentary voltage drop. In the fourth embodiment, the example is when the power source is turned on.

[0228] The second control unit 70 further includes an input terminal for inputting the control signal ES2 based on the configuration of the third embodiment. The input terminal is connected to the output terminal of the first control unit 60 that outputs the control signal ES2 through the wiring L2. The control signal ES2 is input to the OR circuit 77, so that after the voltage of the AC power source rises sharply, the overvoltage protection circuit 50 operates.

[0229] The second control unit 70 further includes an input terminal for inputting an abnormal stop signal ABS indicating whether an abnormality has occurred in the load 2. A wiring for receiving the abnormal stop signal ABS is connected to the input terminal. The abnormal stop signal ABS is input to the conduction time setter 79, and the output signal of the conduction time setter 79 is input to the OR circuit 77. When the abnormal stop occurs, the overvoltage protection circuit 50 is operated.

[0230] The OR circuit 77 outputs a logical sum of the output signal of the AND operator 78 , the control signal ES2 from the first control unit 60 , and the output signal of the on-time setter 79 .

[0231] <Work Status>

[0232] Figure 8 The diagram shows how the DC link voltage Vdc, the operation of the inverter circuit 40, the control signal ES2, the abnormal stop signal ABS, and the operation of the overvoltage protection circuit 50 change over time before and after the AC power source 1 is turned on.

[0233] During the period from time t0 to time t1, AC power is not input from the AC power source 1 to the power conversion device 10. During this period, the inverter circuit 40 stops the switching operation.

[0234] At time t1, AC power starts to be input from AC power source 1 to power conversion device 10. Thus, during the period from time t1 to time t2, that is, from the start of AC power input from AC power source 1, capacitor 31 is charged and DC link voltage Vdc increases.

[0235] Assuming that at time t2, the DC link voltage Vdc exceeds the seventh predetermined value. The first control unit 60 switches the control signal ES2 from "off" to "on". The control signal ES2 becomes "on", thereby the operation signal G_OVDPOR of the overvoltage protection circuit 50 becomes "on", the semiconductor element 52 is turned on, and the overvoltage protection circuit 50 starts to operate.

[0236] The semiconductor element 52 is turned on, so that part of the charge stored in the capacitor 31 flows to the resistor 51 and the semiconductor element 52, and the DC link voltage Vdc rises slowly. The DC link voltage Vdc starts to drop soon and becomes equal to or less than the eighth predetermined value at time t3.

[0237] At time t3, the first control unit 60 switches the control signal ES2 from "ON" to "OFF". The control signal ES2 becomes "OFF", and the operation signal G_OVDPOR of the overvoltage protection circuit 50 becomes "OFF", the semiconductor element 52 is turned off, and the overvoltage protection circuit 50 stops operating. As described above, the overvoltage protection circuit 50 operates during the period immediately after the DC link voltage Vdc becomes equal to or higher than the seventh predetermined value during the charging period.

[0238] Fig. 9 The diagram shows the time-dependent changes of the DC link voltage Vdc, the operation of the inverter circuit 40, the control signal ES2, the abnormal stop signal ABS, the operation of the overvoltage protection circuit 50, and the output signal of the on-time setter 79 before and after the load 2 becomes abnormal.

[0239] During the period from time t4 to time t5, the inverter circuit 40 performs a switching operation.

[0240] At time t5, an abnormality such as overcurrent flowing to the load 2 occurs, and the abnormal stop signal ABS changes from a state indicating that no abnormality has occurred to a state indicating that an abnormality has occurred. The on-time setter 79 thus switches the output signal from "off" to "on". The output signal of the on-time setter 79 becomes "on", and the operation signal G_OVDPOR of the overvoltage protection circuit 50 thus becomes "on", the semiconductor element 52 is turned on, and the overvoltage protection circuit 50 starts to work.

[0241] The semiconductor element 52 is turned on, and part of the current flowing to the load 2 flows to the resistor 51 and the semiconductor element 52 , so that the rise of the DC link voltage Vdc also becomes slow, and the DC link voltage Vdc starts to drop after a while.

[0242] At time t5 after the time set by the on-time setter 79 has passed, the on-time setter 79 switches the output signal from "on" to "off". The output signal of the on-time setter 79 becomes "off", and the operation signal G_OVDPOR of the overvoltage protection circuit 50 becomes "off", the semiconductor element 52 is turned off, and the overvoltage protection circuit 50 stops working.

[0243] It should be noted that, during normal stop not based on the abnormal stop signal ABS, as shown in the first embodiment, the overvoltage protection circuit 50 operates according to the DC link voltage Vdc. Alternatively, during normal stop, the first control unit 60 turns the control signal ES2 “ON” for a predetermined time to operate the overvoltage protection circuit 50.

[0244] <Effect>

[0245] According to the fourth embodiment, when the DC link voltage Vdc becomes equal to or greater than the first predetermined value during the charging process of the capacitor 31, the overvoltage protection circuit 50 is operated, so that the voltage of the capacitor 31 can be prevented from greatly exceeding the seventh predetermined value due to the resonance of the resonance circuit composed of the inductance component L of the charging path and the capacitor 31. When the overvoltage protection circuit 50 is not operated, the voltage of the capacitor 31 rises to twice the peak value of the voltage of the AC power source 1 due to the resonance of the resonance circuit composed of the inductance component L of the charging path and the capacitor 31. However, by setting the first predetermined value to the peak value of the voltage of the AC power source 1, a part of the component of the inductance component L flowing to the charging path during the charging process of the capacitor 31 can flow into the voltage protection circuit 50, thereby suppressing the voltage rise of the capacitor 31. Therefore, the breakdown voltage of the capacitor 31 can be reduced, and the capacitor 31 can be miniaturized and reduced in cost.

[0246] In addition, when the switching elements 41a to 46a stop switching operations due to an abnormality in the load 2, the overvoltage protection circuit 50 is operated, and the inductance energy stored in the load 2 until then is consumed by the resistor, and the voltage rise of the capacitor 31 can be suppressed accordingly. Therefore, the breakdown voltage of the capacitor 31 can be reduced, and the capacitor 31 can be miniaturized and the cost can be reduced.

[0247] It should be noted that in the fourth embodiment, the first control unit 60 stops the switching operation of the switch elements 41a~46a in order to stop supplying AC power to the load 2 when an abnormality occurs during the charging period. However, it is also possible to stop the switching operation of only all the upper branch switch elements 44b~46b or only all the lower branch switch elements 44a~46a.

[0248] (Fifth Embodiment)

[0249] Reference Fig.10 A power conversion device 10 according to the fifth embodiment will be described.

[0250] <Structure>

[0251] In the fifth embodiment, the rectifier circuit 20 further includes a current detection unit 27 that detects the output current of the rectifier circuit 20 in addition to the configuration of the fourth embodiment.

[0252] In addition, the second control unit 70 includes the following components in addition to the configuration of the fourth embodiment: Fig.10 The resonance estimation circuit 90 shown in FIG. 1 includes a differentiation circuit 91 , a threshold value setter 92 , a threshold value exceeding determination device 93 , a zero crossing determination device 94 , and an on-time setting device 95 .

[0253] The differentiating circuit 91 outputs a waveform obtained by differentiating the current detected by the current detecting unit 27 .

[0254] The threshold value setter 92 sets and stores a predetermined threshold value of the current differential value.

[0255] When the output waveform of the differentiating circuit 91 exceeds the threshold value set by the threshold value setter 92, the threshold value excess judgement unit 93 outputs a "high" level as a threshold value excess signal.

[0256] The zero-crossing determiner 94 determines whether the output waveform of the differentiating circuit 91 is zero.

[0257] The on-time setter 95 makes the output "high" level, starts counting the time, and switches the threshold-exceeding signal to "low" level, when the output waveform of the differentiating circuit 91 becomes zero in the state where the threshold-exceeding signal is at "high" level, based on the judgment result of the zero-crossing judgement device 94. In addition, when the counted time reaches the on-time, the on-time setter 95 makes the output "low" level.

[0258] Furthermore, the OR circuit 77 outputs a logical sum of the output signal from the AND operator 78 , the output signal from the on-time setter 79 , the abnormal stop signal ABS, the control signal ES2 , and the output signal from the on-time setter 95 .

[0259] <Work Status>

[0260] Reference Fig.11 The timing diagram illustrates the working conditions of each circuit included in the power conversion device 10. Fig.11 The time-dependent changes of the DC link voltage Vdc, the output current of the rectifier circuit 20, the differential of the output current of the rectifier circuit 20, the threshold value exceeding signal, the output signal of the conduction time setter 95, and the operation status of the overvoltage protection circuit 50 are shown.

[0261] At time t1, the waveform of the differential value of the output current of the rectifier circuit 20 exceeds the threshold value, and the threshold-exceeding signal becomes a "high" level.

[0262] Next, at time t2, the waveform of the differential value of the output current of the rectifier circuit 20 becomes zero, and the on-time setting device 95 sets its output signal to "high" level to start counting time, and sets the threshold-exceeding signal to "low" level.

[0263] At time t3 when the on-time has elapsed from time t2 , the on-time setting device 95 sets its output signal to a “low” level.

[0264] The overvoltage protection circuit 50 operates during the period from time t2 to time t3, that is, during the period when the output signal of the on-time setting device 95 is at the "high" level.

[0265] <Effect>

[0266] In the fifth embodiment, the overvoltage protection circuit 50 is operated during a portion of the period during which the resonance circuit formed by the inductance component L of the charging path and the capacitor 31 resonates, so that a portion of the component flowing to the inductance component L flows into the overvoltage protection circuit 50, thereby suppressing the voltage rise of the capacitor 31.

[0267] It should be noted that the semiconductor element 52 can also be repeatedly turned on / off at a predetermined duty cycle during the operation period of the overvoltage protection circuit 50, that is, when the working signal G_OVDPOR is "on". By reducing the duty cycle during the on period, the actual resistance value of the overvoltage protection circuit 50 can be increased, and an appropriate current can flow into the overvoltage protection circuit 50 according to resonance.

[0268] (Sixth Embodiment)

[0269] <Structure>

[0270] In the sixth embodiment, if Figure 1 As shown by the double-dotted arrow in , the first control unit 60 receives the working signal G_OVDPOR output by the second control unit 70. Moreover, when the working signal G_OVDPOR is "on", the first control unit 60 performs a conduction control to turn on one or two switching elements 41a~46a in a manner that the output nodes of the three phases of the inverter circuit 40 are connected to the common electrode of the capacitor 31. Here, the switching elements 41a~46a that are turned on are two phases with the same direction of the output current of the inverter circuit 40 or phases with a different direction of the output current of the inverter circuit 40 from the other two phases. The switching period in the conduction control is set to be equal to the switching period in the process of supplying power to the load 2.

[0271] <Work Status>

[0272] For example, in Figure 2 At time t3 of the flowchart of FIG. 1 , when the working signal G_OVDPOR switches from “off” to “on”, the first control unit 60 performs conduction control to turn on one or two switching elements 41a to 46a in a manner that the output nodes of the three phases of the inverter circuit 40 are connected to the common electrode of the capacitor 31. For example, Fig.12As shown, when the U-phase current Iu is a positive value and the V-phase current Iv and the W-phase current Iw are negative values ​​in the output current of the inverter circuit 40, by turning on the lower branch switch elements 45a and 46a of the V-phase and W-phase, the output nodes of all three phases of the inverter circuit 40 can be made the negative electrode potential of the capacitor 31, and the voltage between the output nodes of the inverter circuit 40 can be made substantially zero. Therefore, the output power of the inverter circuit 40 is substantially zero, and the average output power of the inverter circuit 40 in the conduction control is also substantially zero. Here, "the voltage between the output nodes of the inverter circuit 40 is substantially zero" also includes the case where the voltage between the output nodes of the inverter circuit 40 has an error between zero and zero corresponding to the voltage drop of the return diodes 41b~46b and the switch elements 41a~46a. In addition, “the output power of the inverter circuit 40 is substantially zero” also includes a situation where the output power of the inverter circuit 40 is different from zero due to power consumption in the resistance component of the reflux diodes 41b to 46b, the switching elements 41a to 46a, the load 2, and the iron loss of the load 2.

[0273] The other structures and operations are the same as those of the first embodiment, and thus detailed descriptions thereof are omitted.

[0274] <Effect>

[0275] Therefore, in the sixth embodiment, the power output by the inverter circuit 40 during the operation of the overvoltage protection circuit 50 is substantially zero, so the amount of electric energy transferred from the load 2 to the capacitor 31 can be substantially zero, and the capacitance of the capacitor 31 can be reduced.

[0276] (Seventh Embodiment)

[0277] <Inverter circuit vector>

[0278] like Fig.13 As shown, the two-level three-phase voltage inverter can take eight vector states V0 to V7. Fig.13In (), the numbers in () represent the connection status of the output nodes of the U, V, and W phases and the capacitor 31 (DC link unit 30) from the left, "1" is the state where the output node is connected to the positive electrode of the capacitor 31, and "0" is the state where the output node is connected to the negative electrode of the capacitor 31. That is, "1" indicates that the upper branch switch elements 41a~43a are turned on and the lower branch switch elements 44a~46a are turned off, and "0" indicates that the upper branch switch elements 41a~43a are turned off and the lower branch switch elements 44a~46a are turned on. Vectors V1~V6 are called basic vectors. The size of the vector changes with the ratio of the time output within the carrier period of the carrier. When the output is 1 / 2 of the time of the carrier period, the size of the vector is 1 / 2. V0 is when all the lower branch switch elements 44a~46a are turned on, and V7 is when all the upper branch switch elements 41a~43a are turned on. They are all called zero vectors because their output voltage is zero.

[0279] <Structure>

[0280] In the seventh embodiment, when the operation signal G_OVDPOR is "ON", the first control unit 60 performs an operation of setting the inverter circuit 40 to a zero vector state as the conduction control. That is, the state of vector V0 is set to turn on all the lower branch switch elements 44a to 46a and turn off all the upper branch switch elements 41a to 43a, or the state of vector V7 is set to turn on all the upper branch switch elements 41a to 43a and turn off all the lower branch switch elements 44a to 46a.

[0281] <Work Status>

[0282] For example, when Figure 2 At time t3 in the timing diagram of , when the working signal G_OVDPOR switches from "off" to "on", the first control unit 60 makes the inverter circuit 40 a zero vector state. As a result, the output nodes of all three phases of the inverter circuit 40 can be the negative electrode potential or the positive electrode potential of the capacitor 31, and the voltage between the output nodes of the inverter circuit 40 can be made substantially zero. Therefore, the output power of the inverter circuit 40 is substantially zero, and the average output power of the inverter circuit 40 in the on control is also substantially zero.

[0283] The other structures and working conditions are the same as those of the sixth embodiment, so their detailed description is omitted.

[0284] In the seventh embodiment, the inverter circuit 40 is set to either the state of vector V0 or the state of vector V7 during the conduction control. However, two periods of the state of vector V0 and the state of vector V7 may be provided during the conduction control.

[0285] (Eighth Embodiment)

[0286] <Structure>

[0287] In the eighth embodiment, when the operation signal G_OVDPOR is "ON", the first control unit 60 performs control as ON control to switch the output power of the inverter circuit 40 to positive or negative in such a manner that the average output power of the inverter circuit 40 in each switching cycle of the switching elements 41a to 46a is substantially zero. Specifically, Fig.14 As shown in FIG. 1 , the control of changing the state of the inverter circuit 40 in the manner of vector V7 → vector V6 → vector V0 → vector V1 → vector V7 in each carrier cycle, i.e., each switching cycle, is performed as the conduction control. It should be noted that when each switching element 41a to 46a is turned on / off, a dead time is set to actually turn off both the upper branch switching elements 41a to 43a and the lower branch switching elements 44a to 46a, but in Fig.14 In the figure, the dead time is omitted. Fig.14 For the sake of explanation, the changes in the DC link voltage Vdc and the output current of the inverter circuit 40 within the carrier cycle are omitted. The period during which the inverter circuit 40 is in the state of the vectors V1 and V6 in the conduction control is set so that the capacitor 31 does not exceed the breakdown voltage.

[0288] In addition, the conduction control is implemented in such a manner that the following equation (3) holds true when the d-axis current of the load 2 in the conduction control is Id, the q-axis current of the load 2 is Iq, the minimum value of the d-axis current causing irreversible demagnetization of the magnet of the load 2 is Im, the magnetic flux of the magnet is Φm, and the d-axis inductance of the load 2 is Ld. Thus, the irreversible demagnetization of the magnet of the load 2 can be prevented.

[0289] (Id+Φm / Ld) 2 +Iq 2 <Im 2 ……(3)

[0290] <Work Status>

[0291] Generally speaking, the input current of the inverter circuit 40 corresponds to the voltage vector and the output current of the inverter circuit 40. Fig.14 In the example, among the output currents of the inverter circuit 40, the U-phase current Iu is positive, and the V-phase current Iv and the W-phase current Iw are both negative. In this case, when the state of the inverter circuit 40 is vector V6, the input current of the inverter circuit 40 becomes a current with the sign of the W-phase current Iw reversed, when the state of the inverter circuit 40 is vector V1, it becomes the W-phase current Iw, and when the state of the inverter circuit 40 is vector V0 or V7, it becomes zero ampere. The appearance time of the vector V6 and the vector V1 in each carrier cycle is equal, so as Fig.13As shown by the double-dotted line, the magnitude of vector V6 is equal to that of vector V1. When the circuit loss is ignored, the output power of the inverter circuit 40 is equal to the input power of the inverter circuit 40. Fig.14 In the figure, the input power (output power) of the inverter circuit 40 is the product of the DC link voltage Vdc and the input current of the inverter circuit 40. When the inverter circuit 40 is in the state of vectors V6 and V1, the absolute value of the time product (power amount) is equal, but the polarity is different. In addition, when the inverter circuit 40 is in the state of vectors V0 and V7, the output power is zero. Therefore, the average output power (time average) is zero. The above relationship is established regardless of the combination of phase current polarities.

[0292] The other structures and working conditions are the same as those of the sixth embodiment, so their detailed description is omitted.

[0293] (First Modification of the Eighth Embodiment)

[0294] <Structure>

[0295] In the first modification of the eighth embodiment, as Fig.15 As shown, the first control unit 60 performs control as on-control to change the state of the inverter circuit 40 in the manner of vector V7 → vector V6 → vector V2 → vector V0 → vector V1 → vector V5 → vector V7 in each carrier cycle, that is, each switching cycle. Fig.15 In the figure, the dead time and the change of the DC link voltage Vdc and the output current of the inverter circuit 40 in the carrier cycle are omitted. The period during which the inverter circuit 40 is in the state of the vectors V1, V2, V5, and V6 in the conduction control is set so that the capacitor 31 does not exceed the breakdown voltage.

[0296] <Work Status>

[0297] exist Fig.15 In the example, in the output current of the inverter circuit 40, the U-phase current Iu is a positive value, and the V-phase current Iv and the W-phase current Iw are both negative values. In this case, the input current of the inverter circuit 40 becomes a current with the sign of the W-phase current Iw reversed when the state of the inverter circuit 40 is vector V6, becomes the V-phase current Iv when the state of the inverter circuit 40 is vector V2, becomes the W-phase current Iw when the state of the inverter circuit 40 is vector V1, becomes the V-phase current Iv when the state of the inverter circuit 40 is vector V5, becomes the V-phase current Iv with the sign reversed when the state of the inverter circuit 40 is vector V5, and becomes zero ampere when the state of the inverter circuit 40 is vector V0 or V7. The appearance time of vector V6 and vector V1 in each carrier cycle is equal, and the appearance time of vector V2 and vector V5 is equal, so as shown in FIG. Fig.13As shown by the double-dotted line in the figure, vector V6 is equal to vector V1 in magnitude, and as Fig.13 As shown by the dotted line in , the magnitude of vector V2 is equal to that of vector V5. When the circuit loss is ignored, the output power of the inverter circuit 40 is equal to the input power of the inverter circuit 40. Therefore, the average output power (time average) is zero. The above relationship is established regardless of the polarity of the phase current.

[0298] The other structures and working conditions are the same as those of the eighth embodiment, so their detailed description is omitted.

[0299] (Second Modification of Eighth Embodiment)

[0300] <Structure>

[0301] In the second variation of the eighth embodiment, when the working signal G_OVDPOR is “on” and is in the state of either of a pair of vectors with opposite directions, the first control unit 60 Fig.16 As shown in FIG. 1 , based on the DC link voltage Vdc detected by the voltage detection unit 32 and the DC link voltage command, the switching signals for controlling the switching elements 41a to 46a are controlled. Specifically, Fig.16 As shown in the block diagram of , the first control unit 60 has a PI controller 61. In the state of either the vector V6 or the vector V1, the first control unit 60 adds the command value correction amount calculated by the PI controller 61 to the modulation waves of the U phase, the V phase, and the W phase based on the deviation between the DC link voltage Vdc and the DC link voltage command.

[0302] It should be noted that in this second variant, the input of the PI controller 61 can be made to be the deviation between the average value of the current flowing between the inverter circuit 40 and the capacitor 31 between the switching cycles and the average current command. The average current command is set in such a way that the DC link voltage Vdc does not become an overvoltage. As a method for achieving such a setting, a PI controller that uses this PI controller 61 as a DC link voltage Vdc of a local loop can be constructed. The DC link voltage command is set to a value below the overvoltage. As a current detector for detecting the input current of the inverter circuit 40, an inexpensive current detector having a shunt resistor provided in the DC section can be used. In addition, all switching elements 41a to 46a can be disconnected when the output current of the inverter circuit 40 detected by the current detector becomes zero.

[0303] (Third Modification of Eighth Embodiment)

[0304] <Structure>

[0305] In the third modified example of the eighth embodiment, the power conversion device 10 includes a current detector (not shown) for detecting the output current of the inverter circuit 40, that is, the current flowing between the inverter circuit 40 and the capacitor 31. In addition, the first control unit 60 calculates the output power of the inverter circuit 40 based on the current detected by the current detector and the DC link voltage Vdc detected by the voltage detection unit 32, and calculates the command value correction amount so that the output power approaches zero in the next switching cycle (carrier cycle). In addition, the modulated waves of the U phase, the V phase, and the W phase are added to the command value correction amount. As the current detector, a low-cost current detector provided in the DC section and having a shunt resistor can be used.

[0306] (Ninth Embodiment)

[0307] <Structure>

[0308] In the ninth embodiment, when the working signal G_OVDPOR is "on", the first control unit 60 performs control as on control to switch the output power of the inverter circuit 40 to positive or negative in two consecutive switching cycles (carrier cycles) of the switching elements 41a to 46a so that the average output power of the inverter circuit 40 is substantially zero. Specifically, Fig.17 As shown, the control of changing the state of the inverter circuit 40 in the manner of vector V7 → vector V6 → vector V2 → vector V0 → vector V2 → vector V6 → vector V7 in the first switching cycle of two consecutive switching cycles and changing the state of the inverter circuit 40 in the manner of vector V7 → vector V5 → vector V1 → vector V0 → vector V1 → vector V5 → vector V7 in the second switching cycle is performed as the conduction control. The period during which the states of the inverter circuit 40 are vectors V1, V2, V5, and V6 in the conduction control is set so that the capacitor 31 does not exceed the breakdown voltage.

[0309] <Work Status>

[0310] Fig.17In the example, among the output currents of the inverter circuit 40, the U-phase current Iu is a positive value, and the V-phase current Iv and the W-phase current Iw are both negative values. In this case, the input current of the inverter circuit 40 becomes a current with the sign of the W-phase current Iw reversed when the state of the inverter circuit 40 is vector V6, becomes the V-phase current Iv when the state of the inverter circuit 40 is vector V2, becomes the W-phase current Iw when the state of the inverter circuit 40 is vector V1, becomes the V-phase current Iv when the state of the inverter circuit 40 is vector V5, becomes the current with the sign of the V-phase current Iv reversed when the state of the inverter circuit 40 is vector V5, and becomes zero ampere when the state of the inverter circuit 40 is vector V0 or V7. The appearance time of vector V6 in one switching cycle is equal to the appearance time of vector V1 in another switching cycle, and the appearance time of vector V2 in one switching cycle is equal to the appearance time of vector V5 in another switching cycle, so as shown in FIG. Fig.13 As shown by the double-dotted line, the magnitude of vector V6 is equal to that of vector V1. Fig.13 As shown by the dotted line, the magnitude of vector V2 is equal to that of vector V5. Therefore, when the state of the inverter circuit 40 is vector V6 or V1, the absolute value of the time product (power amount) of the output power (input power) of the inverter circuit 40 is equal, but the polarity is different. In addition, when the state of the inverter circuit 40 is vector V2 or V5, the absolute value of the time product (power amount) of the output power (input power) of the inverter circuit 40 is equal, but the polarity is different. In addition, when the state of the inverter circuit 40 is vector V0 or V7, the output power is zero. Therefore, the average output power (time average) in two switching cycles is zero.

[0311] The other structures and working conditions are the same as those of the eighth embodiment, so their detailed description is omitted.

[0312] In the ninth embodiment, the first control unit 60 implements on-control in such a manner that the average output power of the inverter circuit 40 within two consecutive switching cycles is substantially zero, but it may also implement on-control in such a manner that the average output power of the inverter circuit 40 within three or more consecutive switching cycles is substantially zero.

[0313] (Tenth Embodiment)

[0314] <Structure>

[0315] In the tenth embodiment, if Fig.18 As shown, the first control unit 60 makes the switching period in the conduction control longer than the switching period in supplying power to the load 2 .

[0316] The other structures and working conditions are the same as those of the first variant of the eighth embodiment, so their detailed description is omitted.

[0317] <Effect>

[0318] Therefore, in the tenth embodiment, since the switching cycle in the conduction control is made larger than the switching cycle in the power supply to the load 2, the ripple of the DC link voltage Vdc can be reduced compared to the case where the switching cycle in the power supply to the load 2 is the same, and the voltage rise of the capacitor 31 can be more reliably suppressed in the conduction control.

[0319] It should be noted that in the eighth embodiment, the second and third variations of the eighth embodiment, and the ninth embodiment, the first control unit 60 may make the switching period in the conduction control longer than the switching period in supplying power to the load 2 .

[0320] (Variation of the Tenth Embodiment)

[0321] <Structure>

[0322] In a modified example of the tenth embodiment, Fig.19 As shown, between the load driving period for supplying power to the load 2 and the period in which the output power for conducting the on-control is substantially zero, a total switch-off period for turning off all the switching elements 41a to 46a of the inverter circuit 40 is provided. The length of the total switch-off period is set so that the DC link voltage Vdc does not exceed the breakdown voltage of the element connected to the DC link unit 30.

[0323] During the load driving period and the period when the output power is substantially zero, the DC link voltage Vdc fluctuates in the same manner as during the period when all switches are off, but Fig.19 The fluctuations are omitted in the figure and the average values ​​are shown.

[0324] The other structures and working conditions are the same as those of the tenth embodiment, so their detailed description is omitted.

[0325] (Other embodiments)

[0326] The AC power supply 1 can be a single-phase power supply instead of a three-phase power supply. In the case of a single-phase power supply, the pulsating component of the DC link voltage Vdc corresponding to the frequency of the power supply voltage Vac is a frequency approximately twice the frequency of the power supply voltage Vac. In this case, the DC link voltage Vdc pulsates in such a way that its maximum value is more than twice its minimum value.

[0327] The capacitance of the capacitor 31 does not have to satisfy the above formula (1).

[0328] The switching elements 41 a to 46 a of the inverter circuit 40 may be elements other than elements whose main material is a wide bandgap semiconductor.

[0329] The semiconductor element 52 in the overvoltage protection circuit 50 may be an element other than an element using a wide bandgap semiconductor as a main material.

[0330] It is not essential to house only the inverter circuit 40 and the overvoltage protection circuit 50 in the same package P1. Other circuits may be housed in the same package P1 together with the inverter circuit 40 and the overvoltage protection circuit 50.

[0331] In the sixth embodiment, an inverter circuit 40 having a different configuration from that of the sixth embodiment may be used to allow the current from the load 2 to flow back through the semiconductor element included in the inverter circuit 40 instead of the capacitor 31, thereby making the output power of the inverter circuit 40 substantially zero. An example of an inverter circuit having a different configuration is a multi-level inverter.

[0332] In the first to tenth embodiments and their variations, the switching signals for controlling the switching elements 41a to 46a are generated by PWM control, but they can also be generated by delaying the pulse signals supplied from a common pulse signal source by different phases for each phase.

[0333] In the eighth to tenth embodiments and their variations, the conduction control is implemented in a manner satisfying equation (3), but it may be implemented in a manner satisfying equation (4) below instead. In equation (4), Idq is the magnitude of the dq axis current vector of the load in the conduction control.

[0334] Idq<Im-Φm / Ld……(4)

[0335] This makes it possible to reliably prevent the irreversible demagnetization of the magnet of the load 2 even when the position of the rotor cannot be accurately known, such as when the motor is out of control.

[0336] As a method for obtaining the magnitude of the dq axis current vector, the square root of the sum of the squares of the phase currents Iu, Iv, and Iw of the inverter circuit 40 can be calculated. It is difficult to obtain the d axis current Id and the q axis current Iq when the rotor position cannot be accurately known. In contrast, the method for calculating the phase currents of the inverter circuit 40 can be realized using only the detected value of the current, and the value equal to the magnitude of the dq axis current vector can be obtained through the calculation. By outputting a voltage vector other than the zero vector, the phase current on the output side of the inverter circuit 40 can be detected on the input side of the inverter circuit 40.

[0337] In the sixth to tenth embodiments and their variations, the first control unit 60 performs conduction control so that the average output power of the inverter circuit 40 is substantially zero. However, the first control unit 60 may perform other control as conduction control to turn on at least one of the plurality of switching elements 41a to 46a so that the absolute value of the average output power of the inverter circuit 40 becomes smaller than when all the plurality of switching elements 41a to 46a are turned off.

[0338] In addition, in the sixth to tenth embodiments and their variations, when the operating signal G_OVDROR is "on", the average output power of the inverter circuit 40 is substantially zero, but the average output power of the inverter circuit 40 may be substantially zero when the power supply to the load 2 is stopped. Thus, the chances of stopping the operation of the load 2 without operating the overvoltage protection circuit 50 increase, and the life of the overvoltage protection circuit 50 can be extended.

[0339] Although the embodiments are described above, it should be understood that various changes in form and details can be made without departing from the spirit and scope of the claims. The above embodiments and modifications may be appropriately combined or replaced as long as the functions of the objects of the present disclosure are not impaired.

[0340] The present disclosure is useful as a power conversion device.

Claims

1. A power conversion device, characterized in that: The invention comprises a rectifier circuit (20), an inverter circuit (40), a capacitor (31) and a control circuit (60), The rectifier circuit (20) converts the AC power output from the AC power source (1) into DC power; The inverter circuit (40) has a plurality of switch elements (41a-46a) for converting the direct current into alternating current and supplying it to a load; The capacitor (31) is connected in parallel with the rectifier circuit (20) and the inverter circuit (40) respectively between the rectifier circuit (20) and the inverter circuit (40), allowing the output voltage of the rectifier circuit (20) to change and absorbing the output voltage of the inverter circuit (40) caused by the switching operation. The control circuit (60) controls the inverter circuit (40). The control circuit (60) performs conduction control to turn on at least one of the plurality of switch elements (41a-46a) when the inverter circuit (40) stops supplying power to the load, so that the absolute value of the average output power of the inverter circuit (40) is smaller than that in a case where all the plurality of switch elements (41a-46a) are turned off. The conduction control is implemented in such a way that the output power of the inverter circuit (40) is switched to positive or negative in the switching cycle of the switching elements (41a to 46a) and the average output power of the inverter circuit (40) in each switching cycle is substantially zero.

2. A power conversion device, characterized in that: The invention comprises a rectifier circuit (20), an inverter circuit (40), a capacitor (31) and a control circuit (60), The rectifier circuit (20) converts the AC power output from the AC power source (1) into DC power; The inverter circuit (40) has a plurality of switch elements (41a-46a) for converting the direct current into alternating current and supplying it to a load; The capacitor (31) is connected in parallel with the rectifier circuit (20) and the inverter circuit (40) respectively between the rectifier circuit (20) and the inverter circuit (40), allowing the output voltage of the rectifier circuit (20) to change and absorbing the output voltage of the inverter circuit (40) caused by the switching operation. The control circuit (60) controls the inverter circuit (40). The control circuit (60) performs conduction control to turn on at least one of the plurality of switch elements (41a-46a) when the inverter circuit (40) stops supplying power to the load, so that the absolute value of the average output power of the inverter circuit (40) is smaller than that in a case where all the plurality of switch elements (41a-46a) are turned off. The conduction control is implemented in such a way that the output power of the inverter circuit (40) is switched to positive or negative in a plurality of consecutive switching cycles of the switching elements (41a to 46a), and the average output power of the inverter circuit (40) in the plurality of consecutive switching cycles is substantially zero.

3. The power conversion device according to claim 1 or 2, characterized in that: The conduction control controls a switching signal for controlling the switching elements (41a to 46a) based on at least one of a current flowing from the inverter circuit (40) to the capacitor (31) and a voltage of the capacitor (31).

4. The power conversion device according to any one of claims 1 to 3, characterized in that: The switching cycle of the switching elements (41a-46a) in the conduction control is set to be shorter than the switching cycle in supplying power to the load.

5. The power conversion device according to any one of claims 1 to 4, characterized in that: The load is a permanent magnet motor, The conduction control is implemented so that when the d-axis current of the load in the conduction control is set to Id, the q-axis current of the load is set to Iq, the minimum value of the magnitude of the d-axis current that causes irreversible demagnetization in the magnet of the load is set to Im, the magnetic flux of the magnet is set to Φm, and the d-axis inductance of the load is set to Ld, the following equation holds: (Id+Φm / Ld) 2 +Iq 2 <Im 2 。 6. The power conversion device according to any one of claims 1 to 4, characterized in that: The conduction control is implemented so that when the magnitude of the dq-axis current vector of the load in the conduction control is set to Idq, the minimum value of the magnitude of the d-axis current that causes irreversible demagnetization in the magnet of the load is set to Im, the magnetic flux of the magnet is set to Φm, and the d-axis inductance of the load is set to Ld, the following equation holds: Idq<Im-Φm / Ld.

7. The power conversion device according to any one of claims 1 to 6, characterized in that: The switch elements (41a-46a) are elements whose main material is a wide bandgap semiconductor including silicon carbide, gallium nitride or diamond.

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