Circuit for improving average efficiency of fallback interval of power amplifier and design method thereof

Abstract

The invention discloses a circuit for improving the average efficiency of a fallback interval of a power amplifier and a design method of the circuit. Compared with a traditional asymmetric Doherty structure and a traditional three-stage Doherty structure, the three-stage Doherty structure disclosed by the invention has higher average efficiency in an output power back-off interval. The power amplifier structurally comprises a power divider, a phase shifter, a main power amplifier (M1), auxiliary power amplifiers (A1 and A2), balanced power amplifiers (B1 and B2), two quarter-wavelength lines (ML1 and ML2), a combiner, four quarter-wavelength impedance conversion lines (TL1, TL2, TL3 and TL4), an isolation resistor Rios, an input coupler, an output coupler and a post-matching network. According to the design, the three-stage Doherty power amplifier is used as a control power amplifier of the load balancing power amplifier, so that the power amplifier has four efficiency peak values in a power rollback interval, and the efficiency of the power amplifier in an output power rollback range can be remarkably improved. In addition, corresponding power backoff points can be flexibly set according to system requirements, and high system adaptability is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power amplifiers, and in particular relates to a circuit for improving the average efficiency of a power amplifier in a back-off interval and a design method thereof. Background Art

[0002] As people's demand for high-speed wireless communication continues to rise, the peak-to-average ratio of the modulated signal in the wireless communication system is required to continue to increase. This requires the power amplifier (PA) in the transmitter to operate in the power back-off range for a long time. As the component with the largest energy consumption in the system, the efficiency of the PA in the large back-off range becomes the key to affecting the energy consumption of the entire wireless communication system.

[0003] Traditional Doherty power amplifiers have two efficiency peaks and can maintain high efficiency within a power back-off range of 6 to 8 dB. However, the peak-to-average ratio of the modulated signal in the current wireless communication system can exceed 12 dB at most, and the traditional Doherty power amplifier can no longer meet the requirements. Therefore, it is necessary to increase the output power back-off range of the power amplifier to meet the development needs of future wireless communication systems. A common method is to use an asymmetric Doherty power amplifier, or use a sequential load modulation balanced power amplifier structure SLMBA, that is, to replace the auxiliary power amplifier in the Doherty power amplifier with a balanced power amplifier. Since the balanced power amplifier has two transistors, the back-off range can be increased to 10 dB; although the above two technologies can improve the back-off range to a certain extent, they only have two peaks in the entire back-off range. When the back-off range increases, there is an obvious efficiency trough between the two peaks, resulting in a significant decrease in the average efficiency of the power amplifier in the back-off range, which cannot meet the energy consumption requirements of the current wireless communication system.

[0004] The three-stage Doherty power amplifier (3-stage Doherty), or the recent Chinese invention patent with the announcement number CN116599469B, entitled "A load-modulated power amplifier structure capable of improving the average efficiency in the back-off region", is the traditional symmetrical Doherty plus LMBA architecture, which can achieve three efficiency peaks in the back-off interval, which can alleviate the above problems to a certain extent. However, as the back-off interval increases further, the valley between adjacent efficiency peaks will continue to increase, reducing the average efficiency in the back-off interval. With the continuous development of wireless communication systems, the peak-to-average ratio of signals will continue to increase. Therefore, improving the average efficiency of the power amplifier back-off interval is crucial to solving the energy consumption problem of the new generation of wireless communication systems. Summary of the invention

[0005] In order to improve the average efficiency within the back-off range of the power amplifier output power, the present invention provides a circuit and a design method for improving the average efficiency of the power amplifier back-off range. The circuit has four efficiency peaks and can provide a high-efficiency working state in a larger back-off range compared to the traditional asymmetric Doherty structure and the three-stage Doherty structure.

[0006] The present invention provides a structure for improving the average efficiency of a power amplifier back-off interval and a design method thereof, wherein the structure comprises: a power divider, a phase shifter, a main power amplifier M1, auxiliary power amplifiers A1 and A2, balanced power amplifiers B1 and B2, two quarter-wavelength lines ML1 and ML2, four quarter-wavelength impedance transformation lines TL1, TL2, TL3 and TL4, an isolation resistor R ios , input coupler, output coupler and post-matching network.

[0007] Furthermore, the power divider can be composed of a cascade of power dividers or a cascade of couplers, the input end is connected to the RF signal input, the first port of the output end of the power divider is connected to the input end of the quarter-wavelength line ML1 cascade main power amplifier M1, the second port of the output end is connected to the input end of the auxiliary power amplifier A1, the third port of the output end is connected to the input end of the quarter-wavelength line ML2 cascade auxiliary power amplifier A2, and the fourth port of the output end is connected to the input end of the phase shifter.

[0008] Furthermore, the input end of the input coupler is connected to the output port of the phase shifter, and the isolation end is connected to the isolation resistor R ios The coupling end is connected to the input end of the balanced power amplifier B1, and the through end is connected to the input end of the balanced power amplifier B2.

[0009] Furthermore, the input end of the output coupler is connected to the output end of the balanced power amplifier B1, the isolation end is connected to the output end of the balanced power amplifier B2, the coupling end is connected to the input end of the impedance transformation line TL4, and the through end is connected to the input end of the rear matching network.

[0010] Furthermore, the output end of the main power amplifier M1 is connected to the input end of the quarter-wavelength impedance transformation line TL1, the output end of the auxiliary power amplifier A1 is connected to the input end of TL3, and the output end of TL3 is connected to the input end of TL2, wherein the output end of TL3 is connected in parallel to the output end of the auxiliary power amplifier A2, the output end of TL2 is connected to the output end of TL1, and finally the output end of TL2 and the output end of TL1 are connected in parallel to the output end of the quarter-wavelength impedance transformation line TL4.

[0011] Furthermore, the output of the post-matching network is connected to a system load, which is usually 50 ohms, in order to achieve matching of the characteristic impedance Z0 of the output coupler to the system impedance of 50 ohms.

[0012] Furthermore, the main power amplifier M1, auxiliary power amplifiers A1, A2, and balanced power amplifiers B1 and B2 are all sub-power amplifiers that already include corresponding input and output matching networks.

[0013] Furthermore, the main power amplifier M1 is in class AB bias, the auxiliary power amplifiers A1 and A2 and the balanced power amplifiers B1 and B2 are all in class C bias, and are controlled by different gate voltages and turned on in sequence, and the turn-on order is A1>A2>B1=B2.

[0014] The above-mentioned design method of a structure for improving the average efficiency of the power amplifier back-off interval is specifically as follows:

[0015] Set the total output power P of the amplifier according to system requirements out The output power fallback points corresponding to the other three efficiency peaks are P_bo3=P out -g 3_dB , P_bo2=P out -g 2_dB 、P_bo1=P out -g 1_dB , all sub-amplifiers have the same drain bias voltage V DD , ideal knee voltage V K ≈0.

[0016] Definition i is the normalized input voltage corresponding to the back-off point:

[0017]

[0018] The characteristic impedance calculation formulas of the quarter-wavelength impedance transformation lines TL1, TL2, TL3 and TL4 are:

[0019]

[0020]

[0021]

[0022]

[0023] in

[0024]

[0025] The present invention proposes a circuit and a design method for improving the average efficiency of a power amplifier in a back-off interval, and the beneficial effects are: (1) The innovation of the present invention is that it can significantly improve the efficiency of the power amplifier in a larger output power back-off interval; (2) By introducing a new combiner structure, the main power amplifier enters the saturation state after the third efficiency peak point, which can reduce the nonlinear problem caused by oversaturation to a certain extent; (3) The present invention can flexibly set the corresponding output power back-off point according to system requirements, and has a high degree of system adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A schematic diagram of a circuit for improving the average efficiency of a power amplifier in a back-off interval.

[0028] Figure 2 It is the equivalent circuit structure diagram of the present invention.

[0029] Figure 3 Schematic diagram of the variation of drain fundamental current with input voltage according to an embodiment of the present invention

[0030] Figure 4 Schematic diagram of the variation of drain fundamental voltage with input voltage according to an embodiment of the present invention

[0031] Figure 5 This is a comparison diagram of the efficiency of the present invention and the prior art when the output power is backed off by 21 dB.

[0032] Figure 6 This is an efficiency curve of another embodiment of the present invention in an unequally divided output power back-off range. DETAILED DESCRIPTION

[0033] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings and embodiments. For those skilled in the art, all other embodiments obtained based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0034] Figure 1It is a circuit diagram of the present invention, which can be understood as a three-stage Doherty power amplifier as a control amplifier of LMBA to achieve a large power back-off range. Specifically, the power distributor is for the main power amplifier M1, the auxiliary power amplifiers A1, A2, and the balanced power amplifiers B1, B2 to improve the appropriate power distribution; the combiner is to improve the output power of the main power amplifier M1, the auxiliary power amplifiers A1 and A2 to achieve the correct phase shift and load modulation; the phase shifter is to complete the correct power synthesis of BA1 and BA2 through the output coupler and the output power of the three-stage Doherty power amplifier, thereby completing the correct load modulation of the balanced power amplifier; the other end of the quarter-wavelength impedance transformation line TL3 is connected to the coupling end of the output coupler, in order to achieve the impedance transformation between the three-stage Doherty power amplifier load and the output coupler characteristic impedance Z0; the post-matching network is to match the load impedance with the output coupler characteristic impedance Z0. The design will be specifically described below with an embodiment.

[0035] Figure 2 The equivalent circuit diagram of the present invention is shown. In order to ensure the correct power synthesis at the combining point, the output signals of each sub-amplifier need to be properly phase offset, such as Figure 2 shown.

[0036] The output power P of the power amplifier is known. out The back-off points corresponding to the four efficiency peaks, for example, the efficiency peaks are reached at the back-off 21dB, 14dB, 7dB and saturated output, that is, P_bo3 = P out -21dB, P_bo2 = P out -14dB, P_bo1=P out -7dB, assuming the same drain bias voltage V for all sub-amps DD and the same knee voltage V K , in ideal condition V K ≈0.

[0037] Definition i is the normalized input voltage corresponding to the back-off point:

[0038]

[0039] but Figure 2 The characteristic impedance calculation formulas of transmission lines TL1, TL2 and TL3 are:

[0040]

[0041]

[0042]

[0043]

[0044] in

[0045]

[0046] The maximum drain current ratio of the main power amplifier M1, auxiliary power amplifiers A1, A2, and balanced power amplifiers B1, B2 is:

[0047]

[0048] According to the back-off points of 7dB, 14dB, and 21dB, the maximum drain current ratio can be calculated to be 1:1.8:2.2:10. The drain fundamental current of each sub-amplifier is plotted as follows: Figure 3 As shown, the drain fundamental voltage is Figure 4 As shown. Combined Figure 3 and Figure 4 The basic working principle of the embodiment of the present invention can be divided into four stages:

[0049] Phase 1: As the input power increases, only the main power amplifier M1 is in operation. When the total output power reaches P_bo3 = P out At -21dB, the drain fundamental voltage V_M1 of the main power amplifier M1 reaches its maximum value, ushering in the first efficiency peak, and the auxiliary power amplifier A1 starts to work at the same time;

[0050] Phase 2: As the input power increases, after the auxiliary power amplifier A1 is turned on, the main power amplifier, under the load modulation, the drain current I_M1 continues to increase, while the drain fundamental voltage V_M1 remains unchanged. When the total output power reaches P_bo2 = P out After -14dB, the drain fundamental voltage V_A1 of the auxiliary power amplifier A1 reaches its maximum value, ushering in the second efficiency peak, and the auxiliary power amplifier A2 starts to work at the same time;

[0051] Phase 3: As the input power increases, under the load modulation of the auxiliary power amplifier A2, the fundamental current I_A1 of the auxiliary power amplifier A1 and the fundamental current I_M1 of the main power amplifier M1 continue to increase, while the corresponding drain fundamental voltages V_A1 and V_M1 remain unchanged. When the total output power reaches P_bo1=P out At -7dB, the drain fundamental voltage V_A2 of the auxiliary power amplifier A2 reaches its maximum value, ushering in the third efficiency peak. The drain fundamental currents of the main power amplifier M1, auxiliary power amplifiers A1 and A2 reach their maximum values ​​at the same time and remain unchanged in the subsequent process. At the same time, the balancing power amplifiers B1 and B2 start working;

[0052] Stage 4: Finally, as the input power increases, the voltage and current of the balanced amplifiers B1 and B2 reach their maximum values ​​at the same time, and all sub-amplifiers reach saturation. At this time, the total output power reaches the maximum value P out.

[0053] The comparison of the efficiency curve of the embodiment of the present invention with the prior art is as follows: Figure 5 As shown, it can be seen that the present invention can achieve four efficiency peaks within the 21 dB back-off interval, so that the average efficiency of the present invention in the high-power back-off interval is the highest.

[0054] In addition, the present invention can not only achieve an equal back-off ratio, but also an unequal output power back-off ratio. For example, when the total back-off amount is 21dB, the first back-off point is set to 6dB, the second back-off point is set to 14dB, and the third back-off point is set to 21dB. The efficiency curve is as follows: Figure 6 As shown, the design method is consistent with the above embodiment. It can be seen that the present invention has high flexibility in setting the backoff ratio.

[0055] Those skilled in the art should understand that the main power amplifier M1, auxiliary power amplifiers A1, A2, and balanced power amplifiers B1, B2 in this embodiment can be a single transistor, or can be composed of a plurality of transistors connected in parallel or stacked together. The transistor can be implemented by a variety of processes, including but not limited to one or any mixture of CMOS, LDMOS, GaN, InP, and GaAs.

[0056] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A circuit and a design method for improving the average efficiency of a power amplifier back-off interval, characterized in that: The power amplifier comprises: a power divider, a phase shifter, a main power amplifier (M1), an auxiliary power amplifier (A1, A2), a balanced power amplifier (B1, B2), two quarter-wavelength lines (ML1, ML2), a combiner, four quarter-wavelength impedance transformation lines (TL1, TL2, TL3, TL4), an isolation resistor R ios , input coupler, output coupler and post-matching network; The input end of the power divider is connected to the radio frequency signal input, the first port of the output end is connected to the input end of the quarter-wavelength line (ML1) cascaded main power amplifier (M1), the second port of the output end is connected to the input end of the auxiliary power amplifier (A1), the third port of the output end is connected to the input end of the quarter-wavelength line (ML2) cascaded auxiliary power amplifier (A2), and the fourth port of the output end is connected to the input end of the phase shifter; The input end of the input coupler is connected to the output end of the phase shifter, and the isolation end is connected to the isolation resistor (R ios ), the coupling end is connected to the input end of the balanced power amplifier (B1), and the through end is connected to the input end of the balanced power amplifier (B2); The input end of the output coupler is connected to the output end of the balanced power amplifier (B1), the isolation end is connected to the output end of the balanced power amplifier (B2), the coupling end is connected to the input end of the impedance transformation line (TL4), and the through end is connected to the input end of the rear matching network.

2. The power amplifier according to claim 1, characterized in that: The output end of the main power amplifier (M1) is connected to the input end of the impedance transformation line (TL1), the output end of the auxiliary power amplifier A1 is connected to the input end of TL3, the output end of TL3 is connected to the input end of TL2, wherein the output end of TL3 is connected in parallel to the output end of the auxiliary power amplifier A2, the output end of TL2 is connected to the output end of TL1, and finally the output end of TL2 and the output end of TL1 are connected in parallel to the output end of the impedance transformation line TL4.

3. The power amplifier according to claim 1, characterized in that: One end of the post-matching network is connected to the through end of the output coupler, and the other end is connected to the system load, which is usually 50 ohms.

4. The power amplifier according to claim 1, characterized in that: The main power amplifier (M1), the auxiliary power amplifiers (A1, A2), and the balanced power amplifiers (B1, B2) are all sub-power amplifiers that already include corresponding input and output matching networks.

5. The sub-power amplifier according to claim 4, characterized in that: The main power amplifier (M1) is in class AB bias, the auxiliary power amplifiers (A1 and A2) and the balanced power amplifiers (B1 and B2) are in class C bias, and are controlled by different gate voltages and turned on in sequence, and the turn-on sequence is A1>A2>B1=B2.

6. The power amplifier design method according to claim 1 is specifically: Set the total output power P of the amplifier according to system requirements out , and three output power back-off points, namely P_bo3=P out -g 3_dB , P_bo2=P out -g 2_dB 、P_bo1=P out -g 1_dB , all sub-amplifiers have the same drain bias voltage V DD And the knee voltage V K ; Definition i is the normalized input voltage corresponding to the back-off point: The characteristic impedance calculation formulas of the quarter-wavelength impedance transformation lines TL1, TL2, TL3 and TL4 are: in

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