A low noise amplifier and radio frequency chip

Abstract

The present invention is applicable to the field of wireless communication technology, and in particular to a low noise amplifier and a radio frequency chip. The low noise amplifier includes an input matching circuit, a bias circuit, an amplifying circuit, an output matching circuit, an attenuator, and an anti-distortion gain suppression circuit. Compared with the prior art, the present invention adds an anti-distortion gain suppression circuit at the connection between the first MOS tube and the second MOS tube of the amplifying circuit, which can prevent distortion caused by excessive waveform amplitude. The anti-distortion gain suppression circuit can effectively reduce the linearity deterioration problem of the chip amplification link caused by excessive waveform amplitude, thereby enabling the low noise amplifier to output a radio frequency signal with better linearity.

Description

Technical Field

[0001] The present invention is applicable to the field of wireless communication technology, and in particular relates to a low noise amplifier and a radio frequency chip. Background Art

[0002] As an important component of wireless communication systems, low noise amplifiers (LNAs) are mainly used in the RF front end of wireless communication receivers. As the first-stage active device of the receiver's RF front end, low noise amplifiers play a vital role in the performance of the receiving system. In order to ensure the receiver's receiving sensitivity, the low noise amplifier is usually required to have a certain gain to amplify the weak signal received by the antenna, while being able to effectively suppress the noise of the subsequent modules, and the low noise amplifier itself also needs to have very low noise. The system receives a high-power signal from the antenna. In order to ensure that the system is not distorted and does not cause damage to the subsequent active devices, the low noise amplifier is required to have variable gain and the ability to expand the dynamic range. Therefore, in addition to the gain and noise meeting the system requirements, high linearity design has also become a necessary point for low noise amplifiers.

[0003] Existing low noise amplifiers mainly use output attenuation and bias current adjustment to adjust the gain of different gears of low noise amplifiers, but this method has certain disadvantages in improving linearity. For example, the design method using output attenuation, although the gain is adjustable, cannot bring about an improvement in linearity and cannot meet the step-by-step IIP3 index of the communication system; and by adjusting the bias current, the amplifier tube will work in the subthreshold region due to the low current at low gain, which will lead to poor linearity and matching of the low noise amplifier.

[0004] Therefore, there is an urgent need for a new low-noise amplifier and radio frequency chip to solve the above technical problems. Summary of the invention

[0005] The present invention provides a low noise amplifier and a radio frequency chip, aiming to improve the linearity of the low noise amplifier at different gain levels.

[0006] In a first aspect, a low noise amplifier includes an input matching circuit, a bias circuit, an amplification circuit, an output matching circuit, and an anti-distortion gain suppression circuit;

[0007] The input end of the input matching circuit serves as the input end of the low noise amplifier and is used to receive a radio frequency signal, and the output end of the input matching circuit is connected to the first input end of the amplifier circuit;

[0008] The bias circuit is used to provide a bias voltage for the amplifier circuit;

[0009] The output end of the amplifier circuit is connected to the input end of the output matching circuit;

[0010] The output end of the output matching circuit serves as the output end of the low noise amplifier;

[0011] The anti-distortion gain suppression circuit is used to provide feedback regulation for the gain outputs of different gears achieved by the amplifier circuit, so as to improve the linearity of the gain outputs of the amplifier circuit at different gears.

[0012] Preferably, the amplifier circuit includes a first MOS tube, a second MOS tube and a first inductor; the gate of the first MOS tube serves as the first input end of the amplifier circuit, the source of the first MOS tube is grounded after being connected in series with the first inductor, the drain of the first MOS tube is connected to the source of the second MOS tube, the gate of the second MOS tube serves as the second input end of the amplifier circuit, and the drain of the second MOS tube serves as the output end of the amplifier circuit; the bias circuit provides bias voltages for the first MOS tube and the second MOS tube respectively.

[0013] Preferably, the anti-distortion gain suppression circuit includes a capacitor unit, a plurality of first switches and a plurality of first resistors; the first end of the capacitor unit is respectively connected to the drain of the first MOS tube and the source of the second MOS tube, the second end of the capacitor unit is respectively connected to the first ends of the plurality of first resistors, the second ends of the plurality of first resistors are respectively connected one-to-one with the control ends of the plurality of first switches, and the output ends of the plurality of first switches are connected to each other and grounded.

[0014] Preferably, the anti-distortion gain suppression circuit includes a capacitor unit, multiple first switches and multiple first resistors; the first end of the capacitor unit is connected to the drain of the second MOS tube, the second end of the capacitor unit is respectively connected to the first ends of multiple first resistors, the second ends of the multiple first resistors are respectively connected to the control ends of multiple first switches in a one-to-one correspondence, and the output ends of the multiple first switches are connected to each other and to the gate of the first MOS tube.

[0015] Preferably, the anti-distortion gain suppression circuit includes a capacitor unit, a plurality of first switches and a plurality of first resistors; the first end of the capacitor unit is respectively connected to the drain of the first MOS tube and the source of the second MOS tube, the second end of the capacitor unit is respectively connected to the first ends of the plurality of first resistors, the second ends of the plurality of first resistors are respectively connected to the control ends of the plurality of first switches in a one-to-one correspondence, and the output ends of the plurality of first switches are connected to the gate of the first MOS tube after being connected to each other.

[0016] Preferably, the capacitor unit includes multiple first capacitors and multiple second switches; the first ends of the multiple first capacitors are interconnected and serve as the first end of the capacitor unit, the second ends of the multiple first capacitors are respectively connected one-to-one with the control ends of the multiple second switches, and the output ends of the multiple second switches are connected to each other and serve as the second end of the capacitor unit.

[0017] Preferably, the anti-distortion gain suppression circuit further includes a second capacitor; a first end of the second capacitor is connected to the first end of the capacitor unit, and a second end of the second capacitor is respectively connected to the output ends of the plurality of first switches.

[0018] Preferably, the bias circuit includes a filter circuit for providing a bias voltage for the second MOS tube and a current mirror circuit for providing a bias voltage for the first MOS tube, the filter circuit includes a second resistor and a fourth capacitor, the first end of the second resistor serves as an input end of the filter circuit and is used to connect an external voltage source, the second end of the second resistor serves as an output end of the filter circuit and is connected to the gate of the second MOS tube, the first end of the fourth capacitor is connected to the second end of the second resistor, and the second end of the fourth capacitor is grounded.

[0019] Preferably, the current mirror circuit includes a third MOS tube and a third resistor; the source of the third MOS tube is grounded, the drain of the third MOS tube serves as the input end of the current mirror circuit and is used to connect an external current source, the gate of the third MOS tube is respectively connected to the first end of the third resistor and the drain of the third MOS tube, and the second end of the third resistor is connected to the gate of the first MOS tube as the output end of the current mirror circuit.

[0020] Preferably, the output matching circuit includes a third inductor, a first adjustable resistor, a fifth capacitor and an attenuator; the first end of the first adjustable resistor is connected to the first end of the third inductor, the second end of the first adjustable resistor is connected to the second end of the third inductor, the first end of the third inductor is used to be connected to an external power supply voltage, the second end of the third inductor is connected to the first end of the fifth capacitor, the first end of the fifth capacitor serves as the input end of the output matching circuit, the second end of the fifth capacitor is connected to the input end of the attenuator, and the output end of the attenuator serves as the output end of the output matching circuit.

[0021] In a second aspect, the present invention further provides a radio frequency chip, wherein the radio frequency chip comprises a low noise amplifier as described in any one of the above embodiments.

[0022] Compared with the prior art, the present invention adds an anti-distortion gain suppression circuit at the connection between the first MOS tube and the second MOS tube of the amplifier circuit, which can prevent distortion caused by excessive waveform amplitude. The anti-distortion gain suppression circuit can effectively reduce the linearity deterioration problem of the chip amplification link caused by excessive waveform amplitude, so that the low-noise amplifier can output a radio frequency signal with better linearity. At the same time, the present invention designs the structure of the anti-distortion gain suppression circuit, and can achieve linearity improvement under different gains by adjusting the first switch and the first resistor in the anti-distortion gain suppression circuit. By setting the resistance value of the first resistor and the resistance value of the first capacitor in the capacitor unit, higher-precision signal attenuation can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0024] Figure 1 1 is a schematic diagram of the circuit structure of a low noise amplifier provided in Embodiment 1 of the present invention;

[0025] Figure 2 is a schematic diagram of the circuit structure of a low noise amplifier provided in Embodiment 2 of the present invention;

[0026] Figure 3 Schematic diagram of the circuit structure of a low noise amplifier provided in Embodiment 3 of the present invention;

[0027] Figure 4 1 is a schematic diagram of the circuit structure of a low noise amplifier provided in Embodiment 4 of the present invention;

[0028] Figure 5 It is a schematic diagram of the circuit structure of a low noise amplifier provided in Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0030] Embodiment 1

[0031] Please refer to Figure 1 , the present invention provides a low noise amplifier 100, comprising an input matching circuit 1, a bias circuit 2, an amplifying circuit 3, an output matching circuit 4 and an anti-distortion gain suppression circuit 5;

[0032] The input end of the input matching circuit 1 is used as the input end of the low noise amplifier 100 to receive the radio frequency signal, and the output end of the input matching circuit 1 is connected to the first input end of the amplifier circuit 3;

[0033] The bias circuit 2 is used to provide a bias voltage for the amplifier circuit 3;

[0034] The output end of the amplifier circuit 3 is connected to the input end of the output matching circuit 4;

[0035] The output end of the output matching circuit 4 is connected to the output end of the low noise amplifier 100;

[0036] The anti-distortion gain suppression circuit 5 is used to provide feedback regulation for the gain outputs of different gears achieved by the amplifier circuit 3 , so as to improve the linearity of the gain outputs of the amplifier circuit 3 at different gears.

[0037] In the embodiment of the present invention, the amplifier circuit 3 includes a first MOS transistor NM1, a second MOS transistor NM2 and a first inductor L1; the gate of the first MOS transistor NM1 serves as the first input terminal of the amplifier circuit 3, the source of the first MOS transistor NM1 is connected in series with the first inductor L1 and then grounded, the drain of the first MOS transistor NM1 is connected to the source of the second MOS transistor NM2, the gate of the second MOS transistor NM2 serves as the second input terminal of the amplifier circuit 3, and the drain of the second MOS transistor NM2 serves as the output terminal of the amplifier circuit 3; the bias circuit 2 provides bias voltages for the first MOS transistor and the second MOS transistor, respectively. The first inductor L1 is a source degeneration inductor, which is used to provide input matching.

[0038] In the embodiment of the present invention, the input matching circuit 1 includes a second inductor L2 and a third capacitor C3; the first end of the second inductor L2 serves as the input end of the input matching circuit 1, the second end of the second inductor L2 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 serves as the output end of the input matching circuit 1. The third capacitor C3 is an isolating capacitor.

[0039] In an embodiment of the present invention, the bias circuit 2 includes a filter circuit 21 for providing a bias voltage for the second MOS transistor and a current mirror circuit 22 for providing a bias voltage for the first MOS transistor. The filter circuit 21 includes a second resistor R2 and a fourth capacitor C4. The first end of the second resistor R2 serves as an input end of the filter circuit 21 and is used to connect an external voltage source. The second end of the second resistor R2 serves as an output end of the filter circuit 21 and is connected to the gate of the second MOS transistor. The first end of the fourth capacitor C4 is connected to the second end of the second resistor R2, and the second end of the fourth capacitor C4 is grounded.

[0040] In the embodiment of the present invention, the current mirror circuit 22 includes a third MOS tube NM3 and a third resistor R3; the source of the third MOS tube NM3 is grounded, the drain of the third MOS tube NM3 serves as the input end of the current mirror circuit 22 and is used to connect an external current source, the gate of the third MOS tube NM3 is respectively connected to the first end of the third resistor R3 and the drain of the third MOS tube NM3, and the second end of the third resistor R3 serves as the output end of the current mirror circuit 22 and is connected to the gate of the first MOS tube. The third resistor R3 is used to isolate the RF and analog circuit modules, and its resistance is set according to actual conditions to avoid introducing excessive noise.

[0041] In the embodiment of the present invention, the output matching circuit 4 includes a third inductor L3, a first adjustable resistor Rbank, a fifth capacitor C5 and an attenuator 41; the first end of the first adjustable resistor Rbank is connected to the first end of the third inductor L3, the second end of the first adjustable resistor Rbank is connected to the second end of the third inductor L3, the first end of the third inductor L3 is used to connect to the external power supply voltage VDD, the second end of the third inductor L3 is connected to the first end of the fifth capacitor C5, the first end of the fifth capacitor C5 serves as the input end of the output matching circuit 4, the second end of the fifth capacitor C5 is connected to the input end of the attenuator 41, and the output end of the attenuator 41 serves as the output end of the output matching circuit 4. Among them, the fifth capacitor C5 is a separation capacitor, and the third inductor L3 is a source load inductor.

[0042] In the embodiment of the present invention, the anti-distortion gain suppression circuit 5 includes a capacitor unit 51, a plurality of first switches T1, and a plurality of first resistors R1; the first end of the capacitor unit 51 is respectively connected to the drain of the first MOS transistor NM1 and the source of the second MOS transistor NM2, the second end of the capacitor unit 51 is respectively connected to the first ends of the plurality of first resistors R1, the second ends of the plurality of first resistors R1 are respectively connected to the control ends of the plurality of first switches T1 in a one-to-one correspondence, and the output ends of the plurality of first switches T1 are connected to each other and grounded. The capacitor unit 51 is a first capacitor C1, the first end of the first capacitor C1 serves as the first end of the capacitor unit 51, and the second end of the first capacitor C1 serves as the second end of the capacitor unit 51.

[0043] Specifically, the first end of the first capacitor C1 is connected to the node netB in the amplifier circuit 3, and is connected to multiple first resistors R1 and multiple first switches T1 through the second end of the first capacitor C1. Since a series switch array is added to the ground at the node netB, good output signal attenuation can be achieved. By adjusting the multiple first resistors R1 to different resistance values, different switch resistances can be switched for different gear gains, thereby achieving improved linearity under different gear gains. It should be noted that the capacitance value of the first capacitor C1 cannot be too low, and the value should be in the pF level, otherwise the required frequency band signal cannot be transmitted well, which is not conducive to improving the linearity of the low-noise amplifier 100. At the same time, the resistance value and number of the first resistor R1 and the number of the first switches T1 can be set according to actual conditions. Figure 1 The three first resistors R1 and the three first switches T1 are only examples, and other numbers of first resistors R1 and first switches T1 are also feasible. The numbers of the first resistors R1 and the first switches T1 can be adjusted to increase different gear gains.

[0044] Embodiment 2

[0045] Please refer to Figure 2 , Embodiment 2 of the present invention provides a low noise amplifier 200. The circuit structure of the low noise amplifier 200 of Embodiment 2 of the present invention is basically the same as that of the low noise amplifier 100 of Embodiment 1 of the present invention, and the difference between the two is that:

[0046] The anti-distortion gain suppression circuit 5 includes a capacitor unit 51, a plurality of first switches T1, and a plurality of first resistors R1; the first end of the capacitor unit 51 is connected to the drain of the second MOS transistor NM2, the second end of the capacitor unit 51 is respectively connected to the first ends of the plurality of first resistors R1, the second ends of the plurality of first resistors R1 are respectively connected to the control ends of the plurality of first switches T1 in a one-to-one correspondence, the output ends of the plurality of first switches T1 are connected to each other and to the gate of the first MOS transistor NM1. The capacitor unit 51 is a first capacitor C1, the first end of the first capacitor C1 serves as the first end of the capacitor unit 51, and the second end of the first capacitor C1 serves as the second end of the capacitor unit 51.

[0047] Specifically, the first end of the first capacitor C1 is connected to the node netC at the output end of the amplifier circuit 3, the second end of the first capacitor C1 is connected to the common end of the plurality of first resistors R1 connected to each other, the plurality of first resistors R1 are respectively connected to the control ends of the plurality of first switches T1 in a one-to-one correspondence, and the common end of the output ends of the plurality of first switches T1 connected to each other is connected to the node netA at the input end of the amplifier circuit 3. By feeding back the output signal to the gate of the first MOS tube NM1, the net input signal amplitude at the input end can be effectively reduced, thereby improving the linearity. At the same time, by adjusting the plurality of first resistors R1 to different resistance values, different switch resistances can be switched for different gear gains, thereby achieving improved linearity under different gear gains. It should be noted that the capacitance value of the first capacitor C1 cannot be too low, and the value is in the pF level, otherwise the required frequency band signal cannot be transmitted well, which is not conducive to improving the linearity of the low noise amplifier 100. At the same time, the resistance value and number of the first resistor R1 and the number of the first switches T1 can be set according to actual conditions, Figure 2 The three first resistors R1 and the three first switches T1 are only examples, and other numbers of first resistors R1 and first switches T1 are also feasible. The numbers of the first resistors R1 and the first switches T1 can be adjusted to increase different gear gains.

[0048] Embodiment 3

[0049] Please refer to Figure 3 , Embodiment 3 of the present invention provides a low noise amplifier 300. The circuit structure of the low noise amplifier 300 of Embodiment 3 of the present invention is basically the same as that of the low noise amplifier 100 of Embodiment 1 of the present invention, and the difference between the two is that:

[0050] The anti-distortion gain suppression circuit 5 includes a capacitor unit 51, a plurality of first switches T1, and a plurality of first resistors R1; the first end of the capacitor unit 51 is respectively connected to the drain of the first MOS transistor NM1 and the source of the second MOS transistor NM2, the second end of the capacitor unit 51 is respectively connected to the first ends of the plurality of first resistors R1, the second ends of the plurality of first resistors R1 are respectively connected to the control ends of the plurality of first switches T1 in a one-to-one correspondence, and the output ends of the plurality of first switches T1 are connected to the gate of the first MOS transistor NM1 after being connected to each other. The capacitor unit 51 is a first capacitor C1, the first end of the first capacitor C1 serves as the first end of the capacitor unit 51, and the second end of the first capacitor C1 serves as the second end of the capacitor unit 51.

[0051] Specifically, the first end of the first capacitor C1 is connected to the node netB in the amplifier circuit 3, the second end of the first capacitor C1 is connected to the common end of the plurality of first resistors R1 connected to each other, the plurality of first resistors R1 are respectively connected to the control ends of the plurality of first switches T1 in a one-to-one correspondence, and the common end of the output ends of the plurality of first switches T1 connected to each other is connected to the node netA of the input end of the amplifier circuit 3. By feeding back the output signal to the gate of the first MOS tube NM1, the net input signal amplitude of the input end can be effectively reduced, thereby improving the linearity. At the same time, by adjusting the plurality of first resistors R1 to different resistance values, different switch resistances can be switched for different gear gains, thereby achieving improved linearity under different gear gains. It should be noted that the capacitance value of the first capacitor C1 cannot be too low, and the value is in the pF level, otherwise the required frequency band signal cannot be transmitted well, which is not conducive to improving the linearity of the low noise amplifier 100. At the same time, the resistance value and number of the first resistor R1 and the number of the first switches T1 can be set according to actual conditions, Figure 3 The three first resistors R1 and the three first switches T1 are only examples, and other numbers of first resistors R1 and first switches T1 are also feasible. The numbers of the first resistors R1 and the first switches T1 can be adjusted to increase different gear gains.

[0052] Embodiment 4

[0053] Please refer to Figure 4 , Embodiment 4 of the present invention provides a low noise amplifier 400. The circuit structure of the low noise amplifier 400 of Embodiment 4 of the present invention is basically the same as that of the low noise amplifier 300 of Embodiment 3 of the present invention, and the difference between the two is that:

[0054] The capacitor unit 51 includes multiple first capacitors C1 and multiple second switches T2; the first ends of the multiple first capacitors C1 are interconnected and serve as the first end of the capacitor unit 51, the second ends of the multiple first capacitors C1 are respectively connected one-to-one with the control ends of the multiple second switches T2, and the output ends of the multiple second switches T2 are connected to each other and serve as the second end of the capacitor unit.

[0055] Specifically, by adaptively adjusting the plurality of first capacitors C1 and the plurality of second switches T2, a higher precision signal attenuation can be achieved according to different gears, so as to better improve the linearity of the low noise amplifier 100. It should be noted that although Figure 4 The number of the first capacitors C1 and the number of the second switches T2 are three, but it cannot be assumed that the number of the first capacitors C1 and the second switches T2 is only three. Other numbers of the first capacitors C1 and the second switches T2 are also feasible. Different gear gains can be increased by adjusting the number of the first capacitors C1 and the second switches T2.

[0056] Embodiment 5

[0057] Please refer to Figure 5 , Embodiment 2 of the present invention provides a low noise amplifier 500. The circuit structure of the low noise amplifier 500 of Embodiment 2 of the present invention is basically the same as that of the low noise amplifier 300 of Embodiment 3 of the present invention, and the difference between the two is that:

[0058] The anti-distortion gain suppression circuit 5 further includes a second capacitor C2; a first end of the second capacitor C2 is connected to a first end of the capacitor unit 51, and a second end of the second capacitor C2 is respectively connected to output ends of a plurality of first switches T1.

[0059] Specifically, due to the addition of the second capacitor C2 , the anti-distortion gain suppression circuit 57 can provide a higher-precision signal attenuation, thereby better improving the linearity of the low-noise amplifier 500 .

[0060] Compared with the prior art, the present invention adds an anti-distortion gain suppression circuit at the connection between the first MOS tube and the second MOS tube of the amplifier circuit, which can prevent distortion caused by excessive waveform amplitude. The anti-distortion gain suppression circuit can effectively reduce the linearity deterioration problem of the chip amplification link caused by excessive waveform amplitude, so that the low-noise amplifier can output a radio frequency signal with better linearity. At the same time, the present invention designs the structure of the anti-distortion gain suppression circuit, and can achieve linearity improvement under different gains by adjusting the first switch and the first resistor in the anti-distortion gain suppression circuit. By setting the resistance value of the first resistor and the resistance value of the first capacitor in the capacitor unit, higher-precision signal attenuation can be achieved.

[0061] Embodiment 6

[0062] An embodiment of the present invention further provides a radio frequency chip, which includes the low noise amplifier as described in the above embodiment and can achieve the same technical effect. Please refer to the description in the above embodiment and will not be repeated here.

[0063] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0064] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A low noise amplifier, characterized in that: It includes an input matching circuit, a bias circuit, an amplifying circuit, an output matching circuit and an anti-distortion gain suppression circuit; The input end of the input matching circuit serves as the input end of the low noise amplifier and is used to receive a radio frequency signal, and the output end of the input matching circuit is connected to the first input end of the amplifier circuit; The bias circuit is used to provide a bias voltage for the amplifier circuit; The output end of the amplifier circuit is connected to the input end of the output matching circuit; The output end of the output matching circuit serves as the output end of the low noise amplifier; The anti-distortion gain suppression circuit is used to provide feedback adjustment for the gain outputs of different gears realized by the amplifier circuit, so as to improve the linearity of the gain outputs of the amplifier circuit at different gears; The amplifier circuit includes a first MOS tube, a second MOS tube and a first inductor; the gate of the first MOS tube serves as a first input end of the amplifier circuit, the source of the first MOS tube is connected in series with the first inductor and then grounded, the drain of the first MOS tube is connected to the source of the second MOS tube, the gate of the second MOS tube serves as a second input end of the amplifier circuit, and the drain of the second MOS tube serves as an output end of the amplifier circuit; the bias circuit provides bias voltages for the first MOS tube and the second MOS tube respectively; The anti-distortion gain suppression circuit comprises a capacitor unit, a plurality of first switches and a plurality of first resistors; the first end of the capacitor unit is respectively connected to the drain of the first MOS tube and the source of the second MOS tube, the second end of the capacitor unit is respectively connected to the first ends of the plurality of first resistors, the second ends of the plurality of first resistors are respectively connected to the control ends of the plurality of first switches in a one-to-one correspondence, and the output ends of the plurality of first switches are connected to each other and grounded; The anti-distortion gain suppression circuit includes a capacitor unit, multiple first switches and multiple first resistors; the first end of the capacitor unit is connected to the drain of the second MOS tube, the second end of the capacitor unit is respectively connected to the first ends of the multiple first resistors, the second ends of the multiple first resistors are respectively connected to the control ends of the multiple first switches in a one-to-one correspondence, and the output ends of the multiple first switches are connected to each other and to the gate of the first MOS tube.

2. The low noise amplifier according to claim 1, characterized in that The anti-distortion gain suppression circuit includes a capacitor unit, a plurality of first switches and a plurality of first resistors; the first end of the capacitor unit is respectively connected to the drain of the first MOS tube and the source of the second MOS tube, the second end of the capacitor unit is respectively connected to the first ends of the plurality of first resistors, the second ends of the plurality of first resistors are respectively connected to the control ends of the plurality of first switches in a one-to-one correspondence, and the output ends of the plurality of first switches are connected to the gate of the first MOS tube after being connected to each other.

3. The low noise amplifier according to any one of claims 1 to 2, characterized in that: The capacitor unit includes multiple first capacitors and multiple second switches; the first ends of the multiple first capacitors are connected to each other and serve as the first end of the capacitor unit, the second ends of the multiple first capacitors are respectively connected to the control ends of the multiple second switches in a one-to-one correspondence, and the output ends of the multiple second switches are connected to each other and serve as the second end of the capacitor unit.

4. The low noise amplifier according to any one of claims 1 to 2, characterized in that: The anti-distortion gain suppression circuit further includes a second capacitor; a first end of the second capacitor is connected to the first end of the capacitor unit, and a second end of the second capacitor is respectively connected to the output ends of the plurality of first switches.

5. The low noise amplifier according to claim 1, wherein: The bias circuit includes a filter circuit for providing a bias voltage for the second MOS tube and a current mirror circuit for providing a bias voltage for the first MOS tube. The filter circuit includes a second resistor and a fourth capacitor. The first end of the second resistor serves as an input end of the filter circuit and is used to connect an external voltage source. The second end of the second resistor serves as an output end of the filter circuit and is connected to the gate of the second MOS tube. The first end of the fourth capacitor is connected to the second end of the second resistor, and the second end of the fourth capacitor is grounded.

6. The low noise amplifier according to claim 5, characterized in that The current mirror circuit includes a third MOS tube and a third resistor; the source of the third MOS tube is grounded, the drain of the third MOS tube serves as the input end of the current mirror circuit and is used to connect an external current source, the gate of the third MOS tube is respectively connected to the first end of the third resistor and the drain of the third MOS tube, and the second end of the third resistor is connected to the gate of the first MOS tube as the output end of the current mirror circuit.

7. The low noise amplifier according to claim 1, wherein: The output matching circuit includes a third inductor, a first adjustable resistor, a fifth capacitor and an attenuator; the first end of the first adjustable resistor is connected to the first end of the third inductor, the second end of the first adjustable resistor is connected to the second end of the third inductor, the first end of the third inductor is used to be connected to an external power supply voltage, the second end of the third inductor is connected to the first end of the fifth capacitor, the first end of the fifth capacitor serves as the input end of the output matching circuit, the second end of the fifth capacitor is connected to the input end of the attenuator, and the output end of the attenuator serves as the output end of the output matching circuit.

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