Controllable ON / OFF follower

Abstract

A follower capable of controlling ON / OFF (following switch for short) is characterized in that two modules for controlling ON / OFF are added in a basic follower, one module is a control output tube T1amp, and the other module is a control output tube T1amp; the T2 is provided with an ON / OFF state control module 13, and the other control short circuit branch 14 is provided with an ON / OFF state short circuit control module 15. When J = 0, making K1amp; k2 is set to be OFF and KF is set to be ON; k1amp; K1amp; k2 is set to be OFF and can be regarded as K1amp; if the K2 does not exist, returning the controllable operational amplifier to a basic operational amplifier state; meanwhile, the KF is set to be ON, namely the controllable short-circuit branch 14 is set to be in a short-circuit state, and the two states are combined, so that the following switch is in an ON state; when J = 1, making K1amp; k2 is set to be ON, and KF is set to be OFF; the K1 is set to be ON, so that the base electrode of the T1 is communicated with a power supply-VCC, and the T1 is cut off; the K2 is set to be ON, so that the base electrode of the T2 is communicated with the power supply + VCC, and the T2 is cut off; meanwhile, the KF is set to be OFF, namely a controllable short-circuit branch 14 is set to be open, so that the following switch is in an OFF state.

Description

Technical field:

[0001] The invention discloses a follower device with controllable ON / OFF, referred to as a follower switch, and belongs to the field of electronic circuits. Technical background:

[0002] The voltage follower can improve the load capacity of the signal source. It is referred to as a follower. Under ideal conditions, the voltage at the output of the follower will follow and be equal to the voltage at its input. It is one of the important applications of the integrated operational amplifier (op amp for short). The basic structure of the op amp is input stage 10 + intermediate stage 11 + output stage 12, that is, Figure 1 The solid rectangular frame 1 in the figure removes the output tube control module part of the dotted frame 13.

[0003] Because in the amplification state, the op amp's in-phase input and inverting input are "virtually shorted". O With the inverting input u N Short circuit, then it is equivalent to the output terminal u O With the same phase input terminal u P Virtual short, u O and u P On this basis, let the in-phase input end serve as the input end of the follower, then the output end u O The voltage at the input terminal u P The voltage of the voltage follower is formed. The follower does not have a shutdown function. If a controllable shutdown function is added to the follower, it becomes a controllable ON / OFF follower, referred to as a follower switch.

[0004] In order to avoid confusion, this article calls the current op amp a basic op amp, and the basic op amp with the output tube control module 13 added is called a controllable op amp; the current follower is called a basic follower, and the follower with controllable ON / OFF in this article is called a follower switch. Summary of the invention:

[0005] The present invention is an improvement on the basic follower, which adds a shutdown function to the basic follower, and becomes a follower with an ON / OFF function, which is called a follower switch. That is, when it is in the ON state, the output terminal u o With input u P Virtual short, zero voltage loss; when it is in the OFF state, its output terminal u o With input u P disconnect.

[0006] To avoid confusion, some definitions, conventions, and explanations are given first.

[0007] ●A / B means A or B; A&B means A and B;

[0008] ●A pair of transistors at the output stage, NPN transistor T1 and PNP transistor T2 are collectively referred to as output transistors T1 & T2; control transistors K1 & K2 for ON / OFF control of output transistors T1 & T2 are referred to as output control transistors, and a module including output control transistors is referred to as an output transistor control module;

[0009] ●Control tube K X :K X (Subscript X is a wildcard) is a controlled switch device, including a control pin and two channel pins that constitute a controllable ON / OFF main channel. The control word J controls the ON / OFF of the main channel through the control pin. The device types of control tubes include but are not limited to triodes / field effect tubes / analog switches / transmission gates; the control pin of the triode is the base, and the channel pins are the emitter and collector; the control stage of the field effect tube is the gate, and the channel pins are the source and drain; the control stage of the analog switch / transmission gate is CONTROL, and their channel pins are the IN pin and OUT pin;

[0010] ●The working types of control tubes include output control tubes and short-circuit control tubes. Their icons are based on the contact icons of the borrowed switch with an additional control foot.

[0011] ●ON definition: For control tube K X For the output tubes T1 and T2, ON means that T1 and T2 are in the amplification state.

[0012] ●The current operational amplifier is called a basic operational amplifier, and the basic operational amplifier with the output tube control module 13 added is called a controllable operational amplifier; the current follower is called a basic follower, and the follower with controllable ON / OFF in this article is called a follower switch;

[0013] The present invention is a follower device with controllable ON / OFF Figure 1 ), referred to as follower switch, its symbol is S, S is based on the basic follower with an extended controllable ON / OFF function.

[0014] Technical feature 1: The present invention is a controllable ON / OFF follower, referred to as a follower switch, which is a basic follower with two modules for controlling ON / OFF added.

[0015] One is a control module 13 for controlling the output tubes T1 & T2 to be set to an ON / OFF state, referred to as the output tube control module 13, and the other is a short circuit control module 15 for controlling the short circuit branch 14 to be set to an ON / OFF state, referred to as the short circuit control module 15. Specifically,

[0016] One is the structure of the output tube control module 13: an output tube control module 13 is added to the structure of the basic operational amplifier in the basic follower (input stage 10 + intermediate stage 11 + output stage 12), which controls the output tubes T1 & T2 in the output stage 12 to be turned on / off, so that the basic operational amplifier is upgraded to a controllable ON / OFF operational amplifier ( Figure 1 The output tube control module 13 includes two control tubes K1 & K2 for controlling the output tubes T1 & T2 to be turned on / off, wherein K1 is used to control the ON / OFF of T1 and is called the first control tube, and K2 is used to control the ON / OFF of T2 and is called the second control tube. K1 & K2 are collectively called output control tubes, and the control pins of the two output control tubes K1 & K2 are controlled by the same control word J; the two channel pins of the first control tube K1 are respectively connected to the power supply -V CC and the base of the NPN output transistor T1 to control the ON / OFF of the output transistor T1; the two channel pins of the second control tube K2 are respectively connected to the power supply +V CC With the base of the PNP output transistor T2, it is used to control the ON / OFF of the output transistor T2;

[0017] The second is the structure of the short-circuit control module 15: the short-circuit branch 14 is used to short-circuit the output terminal u o and the inverting input terminal u N A short circuit control module 15 is connected to the short circuit branch 14 to control the ON / OFF of the short circuit branch 14; the simplest structure of the short circuit control module 15 is a short circuit control tube K F ; Short-circuit control tube K F The ON / OFF state of the output control tube K1&K2 is opposite to that of the output control tube K1&K2. That is, when K1&K2 is OFF, K F must be set to ON; otherwise, when K1&K2 are set to ON, K F Must be set to OFF; if K F If the ON / OFF state of K1 & K2 is the same, use an inverter to adjust them to be mutually inverted;

[0018] J=0 or J=1 agreement: the control word J can be high or low, so that K1 & K2 are turned on and K F The OFF level is agreed to be "J = 1", so that K1 & K2 are OFF and K F The ON level is agreed to be "J = 0", ( Figure 1 status shown in ).

[0019] Working principle of follower switch:

[0020] One is the principle of following the switch to ON: the necessary and sufficient condition for following the switch to ON is that the output control tubes K1 & K2 are OFF and the control tube K is short-circuited. F Set to ON;

[0021] When J=0, K1&K2 are turned OFF and K F K1 and K2 are set to ON; K1 and K2 are set to OFF, which can be regarded as K1 and K2 not existing, so that the controllable operational amplifier returns to the basic operational amplifier state; at the same time, K F Turning ON means setting the controllable short-circuit branch 14 to a short-circuit state. The combination of these two states causes the follower switch to return to a basic follower state, that is, the follower switch is in an ON state;

[0022] The second is the principle of following the switch to OFF: the necessary and sufficient condition for following the switch to OFF is that the output control tubes K1 & K2 are turned ON (making the output tubes T1 & T2 turned OFF) and the control tube K is short-circuited. F Set OFF;

[0023] When J=1, K1&K2 are turned ON and K F Set OFF;

[0024] Because the main channel of K1 is connected across the base of the output transistor T1 and the power supply -V CC , so K1 is turned ON so that the base of T1 is connected to the power supply -V CC Connected, T1 is cut off; similarly, because the main channel of K2 is connected across the base of the output transistor T2 and the power supply +V CC , so K2 is turned ON to make the base of T2 connected to the power supply +V CC connected, making T2 off; that is, K1 & K2 are turned ON, making T1 & T2 OFF, making the output terminal u o and controllable op amp truncation;

[0025] At the same time, K F OFF means setting the controllable short-circuit branch 14 to an open circuit, so that the output terminal u o With the inverting input u N The short-circuit connection is cut off;

[0026] Output terminal u o The controllable op amp is cut off and connected to the inverting input terminal u N Truncation, that is, the output end u o All the previous circuits are cut off, so that the follower switch is in the OFF state;

[0027] Technical feature 2: A controllable ON / OFF follower according to technical feature 1, characterized in that:

[0028] The output control tubes K1 and K2 use triodes and corresponding base resistors, short-circuiting the control tube K F Adopt bidirectional analog switch; it can meet the requirements of follower switch;

[0029] Experiments show that, under the premise that the offset voltage of the basic op amp is at the μV level, a resistor less than 10KΩ can be used as K F , its following accuracy can reach 10 6 ~10 7 , and the ON resistance value of the bidirectional analog switch is less than 100Ω; from an engineering point of view, it can be regarded as zero loss, so the follower switch can also be called a follower switch.

[0030] If K1&K2 and K F If the ON / OFF states of the two transistors are consistent, an inverter is used to make their ON / OFF states opposite.

[0031] Technical feature 3: A controllable ON / OFF follower according to technical feature 1, characterized in that:

[0032] Based on the follower switch, a bidirectional follower switch is constructed. Specifically,

[0033] Connect the follower switch S1 and the follower switch S2 in forward and reverse parallel ( Figure 2.1 ), and at the same time connect the control words of the two to form a bidirectional follower switch;

[0034] Technical feature 4: A controllable ON / OFF follower according to technical feature 1, characterized in that the sample-and-hold device is constructed based on a follower switch, specifically

[0035] The switch in the existing sample-and-hold device is replaced by a follower switch to form a follower switch type sample-and-hold device, including a follower switch type feedback type sample-and-hold device ( Figure 3.1 ) and follower switch series sample and hold ( Figure 3.2 ).

[0036] Technical feature 5: A controllable ON / OFF follower according to technical feature 1, characterized in that a plurality of follower switches are used to form a multi-way follower switch, specifically, the input pins of the plurality of follower switches are connected to form a common input pin type multi-way follower switch, and the output pins of the plurality of follower switches are connected to form a common output pin type multi-way follower switch ( Figure 4 The MS dotted box in the figure) connects the control pins of multiple follower switches to form a common control pin type multi-channel follower switch

[0037] Additional notes on the following technical features

[0038] ●Stage-ADC is referred to as StADC, SUB-ADC is referred to as SADC, and SUB-DAC is referred to as SDAC; ADC and DAC (hereinafter referred to as ADC&DAC) will generate many symbols, including (V λe , R λe , J λe ,PS λe , S λe ), the first subscript of these symbols is the stage subscript, and λ is the wildcard for the stage subscript, which is (α, β, γ, …, m), representing the first stage, the second stage, the third stage, …, and the last stage, respectively. (α, β, γ, …, m) is (1, 2, 3, …, m); the second subscript is the step subscript, and e is the wildcard for the step subscript, which is (0, 1, 2, …, Q λ -1), indicating the 0th order, 1st order, 2nd order, ..., Q-1th order of the device chain.

[0039] ● The subscript of a superscript or the subscript of a subscript (secondary subscript) cannot be written. There are two ways to express it. The first is the equal method, that is, the secondary subscript is the same size as its primary superscript or subscript. qβ In the example, the subscript β of the first-level superscript q is equal to q. Similar examples include: subscript (Q λ 、E λ ) is represented by (Qλ, Eλ); the second is the omission method, that is, when it is known that it is at the λ level, the secondary subscript λ is omitted by default, such as (d λ(qλ-1) , J λ(Qλ-1) , S λEλ , J λEλ ) is written as (d λ(q-1) , J λ(Q-1) , S λE , J λE );

[0040] ●The λth level SADC & SDAC has q λ bit, forming Q λ =2^q λ Order (0, 1, 2, ..., Q λ -1), because the subscript of the subscript or the subscript of the superscript cannot be written, so the subscript Qλ is used to represent the subscript Q λ , such as V λ(Qλ-1) Qλ in is represented by Q λ , use superscript qλ to represent superscript q λ , such as Q β =2^q β =2 qβ , when it is known that it is at the λth level, λ can be omitted and written as V λ(Q-1) , Q λ =2q , V λE The subscript E is actually E λ , because the subscript of the subscript cannot be written, we have to default to E when it is known that it is at level λ λ Indicated by E.

[0041] Let Q = 2 q =2^q,Q λ =2 qλ =2^q λ .

[0042] ●The single letter D acts as a noun prefix, and D means "digital signal", such as "digital signal input terminal" is abbreviated as "D input terminal"; similarly, the single letter A acts as a noun prefix, and A means "analog signal", such as "analog signal input terminal" is abbreviated as "A input terminal"; the default "input terminal" without a prefix is ​​"A input terminal".

[0043] ●At a certain moment, when the analog signal U λZ Among the reference potentials, there must be one that is closest to U λZ The potential is V λE , the reference potential V λE ADCB λ The bridge potential at this moment, V λE <U λZ <V λ(E+1) , the bridge potential V can be obtained by rounding λE , V λE =INT(U λZ / ΔV)*ΔV, that is, based on the quantitative unit ΔV, V λE Is the analog quantity U λZ The integer part of the voltage U λX It is the analog quantity U λZ The decimal part, U λX <ΔV, mantissa voltage U λX =Analog voltage U λZ - Bridge potential V λE ;

[0044] Technical feature 6: A controllable ON / OFF follower according to technical feature 1, characterized in that a bridge potential DAC ( Figure 5 ), specifically

[0045] An n-bit DAC is composed of m SUB-DACs and a weight summing amplifier (WA∑), and the SUB-DAC is referred to as SDAC in the following;

[0046] (α level, β level, γ level, ..., m level) m SDACs are respectively (SDAC α 、SDAC β 、SDAC γ ,…,SDAC m ), their digits are (q α ,q β ,q γ ,…,q m ), where m is the final stage, n = q α +q β +q γ +…+q m ;

[0047] Use the λth sub-level SDAC λ Wildcard all sub-levels, SDAC λ The number of digits is q λ , SDAC λ Contains a q λ Bit multiplexer follower switch MS λ (multiway switch) and a q λ Bit reference resistor chain RC λ (R-chain);

[0048] The reference potential chain RC λ The resistors are equal and connected across (-V REF ~V REF ), 2 qλ A reference resistor (R λ0 , R λ1 , R λ2 , …, R λ(Qλ-1) ) will (-V REF ~V REF ) is divided into 2 qλ To simplify the analysis, let -V REF =0, each equally divided voltage ΔV is ΔV=V REF / 2 qλ ; Form 2 qλ +1 potential point (V λ0 ~V λQλ ), of which 2 qλ Reference potential point (V λ0 ~V λ(Qλ-1) ), namely V λ0 =0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ(Qλ-1) =(Q λ -1)ΔV,(V λQλ =Q λ ΔV=V REF, does not serve as a reference potential point), called V λe The reference potential of the λth order e is:

[0049] The λth stage multi-way follower switch MS λ Including a q λ Bit Decoder YM λ and a q λ Follower switch chain SC λ =(S λ0 , S λ1 , S λ2 ,…,S λ(Qλ-1) ); Multi-channel follower switch MS λ It has three groups of ports, one of which is the control port - the control word (J λ0 , J λ1 , …, J λ(Qλ-1) ); one group is A input terminal - each follower switch (S λ0 , S λ1 ,…,S λ(Qλ-1) )'s A input terminal, one group is the A output terminal - the A output terminal of each follower switch;

[0050] The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and Q λ =2 qλ Decoded output word (J λ0 , J λ1 , …, J λ(Qλ-1) ), the decoded output word is the same as the 2 qλ The control word of the following switch (J λ0 , J λ1 , …, J λ(Qλ-1) ) are connected according to the corresponding relationship of equal subscripts;

[0051] 2 qλ Follow-up switch (S λ0 , S λ1 ,…,S λ(Qλ-1) ) is connected to the reference potential point (V λ0 、V λ1 ,…,V λ(Qλ-1) ), the A output of all follower switches is connected to the λth level common output BUS λ ( Figure 5 );

[0052] When SDAC λ The D input terminal (d λ(q-1) …d λ1 d λ0) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE (Note: Under the premise of knowing that it is at the λ level, the subscript E is used by default. λ Indicated by E), J λE Sent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the λth level;

[0053] V λE It is both an analog potential and corresponds to a digital signal (d λ(q-1) …d λ1 d λ0 ) value, is the bridge between analog signal and digital signal, so V λE Named "bridge potential"; get each level of SDAC in turn λ The bridge potential (V αE 、V βE 、V γE ,……,V mE );

[0054] For example, when the 3-bit SDAC λ The D input terminal (d λ2 d λ1 d λ0 ) receives the digital signal (011), converts it into the octal number 3, and generates a selected word J among the 8 decoded output words. λ3 , J λ3 Sent to the corresponding follower switch S λ3 Control word J λ3 , so that the follower switch S λ3 Set to ON, and the rest of the follow switches to OFF; S λ3 After turning ON, take out the corresponding reference potential point V λ3 =3ΔV; the DA conversion obtained by this pulse is (011)→3ΔV;

[0055] Each bridge potential V λE With different rights λ Therefore, the bridge potential V λE Multiply by the weight WA λ Get the weight bridge potential WV λE , that is, WVλE =WA λE *V λE To this end, it is necessary to pass the bridge potential of each level through the BUS line (BUS α 、BUS β 、BUS γ 、……、BUS m ) and then sent to the Weight-ALU (WA α , W.A. β , W.A. γ ,…,WA m ) to perform weight calculation; WA λ The corresponding weight is WA λ ; Let WA α =1, the weight of the first level (λ+1) is 2 less than that of the first level λ qλ times, that is, WA (λ+1) =WA λ / 2 qλ ; with WA α As a benchmark, we get

[0056] WA α =1, WA β =1 / 2 qα , W.A. γ =WA β / 2 qβ =1 / 2 (qα+qβ) ,…,WA m =WA (m-1) / 2 q(m-1) =1 / 2 (q α+qβ+…+q(m-1))

[0057] (Note: Here 2 (qα+qβ+…+q(m-1)) (α, β, ..., (m-1)) in the equation are subscripts of q)

[0058] The potential of each level of weight bridge passes through the summator ∑ λ After summing, the total DAC output voltage V out ,Right now,

[0059] V out =WV αE +WV βE +WV γE +…+WV λm =WA αE *V αE +V αE +WA β *V βE +WA γ *V γE +…+WA m *V λm=V αE +V βE / 2 qα +V γE / 2 qα+qβ +…+V λm / 2 qα+qβ+…+q(m-1) ;

[0060] Technical feature 7: A controllable ON / OFF follower according to technical feature 6, characterized in that an MS-type bridge potential pipeline ADC1 is formed by replacing the SDAC in the pipeline ADC with a common output multi-channel follower switch (MS), referred to as bridge potential ADC1, specifically,

[0061] The bridge potential ADC1 is the same as the traditional pipeline ADC, which is composed of multi-stage Stage-ADC λ The two are composed of one stage after another. In order to distinguish the two, the following will be the Stage-ADC of the Type 1 bridge potential ADC1 λ StADC1 for short λ , the Stage-ADC of the traditional pipeline ADC λ Referred to as StaADC λ ;StaADC λ Includes a SUB-ADC λ (SADC λ ), a SUB-DAC λ (SDAC λ ) and an interstage module ISM λ (Interstage module); while StADC1 λ Just StaADC λ SDAC λ Replace it with a multi-way follower switch; that is, the StADC1 λ ( Figure 6.1 ) includes a SADC λ , a multi-channel follower switch MS λ and an interstage module ISM λ ,

[0062] The StADC1 λ SADC λ Includes a reference resistor chain RC λ , a comparator chain CC λ , an encoder ENC λ ;

[0063] The reference potential chain RC λ The resistors are equal and connected across (-V REF ~V REF ), 2qλ A reference resistor (R λ0 , R λ1 , R λ2 , …, R λ(Qλ-1) ) will (-V REF ~V REF ) is divided into 2 qλ Divide equally, and the voltage of each equal division is ΔV = V REF / 2 qλ ; To simplify the analysis, let -V REF =0, so that the reference resistor chain RC λ Formation (2 qλ +1) potential point (V λ0 ~V λQλ ), of which 2 qλ Reference potential point (V λ0 ~V λ(Qλ-1) ), namely V λ0 =0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ(Qλ-1) =(Q λ -1)ΔV,(V λQλ =Q λ ΔV=V REF , does not serve as a reference potential point), called V λe is the reference potential of the e-th order of the λth level;

[0064] The comparator chain CC λ By (2 qλ -1) comparator (C λ0 , C λ1 , R λ2 ,…,C λ(Qλ-1) ) across (-V REF ~V REF ), C λ0 For virtual;

[0065] Resistor chain and comparator chain CC λ There are two types of connection relationships. The first is the input signal U λY After passing through the sample-and-hold device, it is connected to the non-inverting input of each comparator. The reference potential point (V λ1 ~V λ(Qλ-1) ) is connected to the corresponding comparator (C λ1 ~C λ(Qλ-1) ) is the inverting input terminal; the second is just the opposite, the input signal U λY After passing through the sample-and-hold device, it is connected to the inverting input of each comparator. The reference potential point (V λ1 ~V λ(Qλ-1) ) is connected to the corresponding comparator (C λ1~C λ(Qλ-1) )’s non-inverting input terminal; the two have the same principle, and this paper adopts the first connection relationship for analysis;

[0066] The λth stage multi-way follower switch MS λ Including a q λ Bit Decoder YM λ and a q λ Follower switch chain SC λ =(S λ0 , S λ1 ,…,S λ(Qλ-1) );

[0067] The q λ The bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and Q λ =2 qλ Decoded output word (J λ0 , J λ1 , …, J λ(Qλ-1) );

[0068] The follower switch chain is 2 qλ Follow-up switch (S λ0 , S λ1 ,…,S λ(Qλ-1) ), its A input terminal is connected to 2 qλ Reference potential point (V λ0 、V λ1 ,…,V λ(Qλ-1) ), all A output terminals are connected to the λth level common output terminal BUS λ , its control word (J λ0 , J λ1 , …, J λ(Qλ-1) ) is connected to the decoder YM λ Output word (J λ0 , J λ1 , …, J λ(Qλ-1) );

[0069] The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and 2 qλ Decoded output word (J λ0 , J λ1 , …, J λ(Qλ-1) ), the decoded output word is the same as the 2 qλ The control word of the following switch (J λ0 , J λ1 , …, J λ(Qλ-1) ) are connected accordingly;

[0070] 2 qλ The A input terminal of each follower switch is connected to the reference potential point according to the corresponding subscript, and the output terminals of all follower switches are connected to the λth level common output terminal BUS λ ;

[0071] When SDAC λ The D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE (Note: Under the premise of knowing that it is at the λ level, the subscript E is used by default. λ Indicated by E), J λE Sent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the λth level;

[0072] The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and 2 qλ Decoded output word (J λ0 , J λ1 , …, J λ(Qλ-1) ), the decoded output word is the same as the 2 qλ The control word of the following switch (J λ0 , J λ1 , …, J λ（Qλ-1) ) are connected accordingly;

[0073] 2 qλ The A input terminal of each follower switch is connected to the reference potential point according to the corresponding subscript, and the output terminals of all follower switches are connected to the λth level common output terminal BUS λ ;

[0074] The interstage module ISM λ Including summer ∑ λ , Amplifier AM λ (The two are collectively called the summing and amplifier ∑&AM λ ) and a sample holder T / H;

[0075] When SDAC λ The D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE (Note: Under the premise of knowing that it is at the λ level, the subscript E is used by default. λ Indicated by E), J λE Sent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the λth level;

[0076] (The inter-stage module includes a sample-and-hold device T / H, a summer ∑ λ , Amplifier AM λ );

[0077] The bridge potential V λE The extraction module includes a q λ bit multi-way follower switch; the q λ The bit multiplexer follower switch includes a q λ bit decoder, a follower switch chain (S λ0 , S λ1 , S λ2 ,…,S λ(Qλ-1) ), each follower switch output is connected to the common output terminal BUS λ ;

[0078] The A input terminal of each follower switch of the follower switch chain, the inverting input terminal of each comparator of the comparator chain, and each reference potential point of the reference resistor chain are connected according to the corresponding relationship of the subscripts;

[0079] Technical feature 8: A controllable ON / OFF follower according to technical feature 1, characterized in that a logic operator is used to perform logic operations on multiple logic signals, including a combinational logic operator and a sequential logic operator, to obtain a control word J for controlling the ON / OFF of the follower switch;

[0080] Technical feature 9: A controllable ON / OFF follower according to technical feature 8, characterized in that an AND gate is used to operate two control signals to obtain a dual-control follower switch PSλe Specifically

[0081] The dual-control follower switch PS λe There are two control signals (j λ(e+1) ) and (j λe ), using an AND gate, only when PS λe The control word below (j λe )=1 and the upper control word (j λ(e+1) )=0, the obtained control word J makes the state of the follower switch ON; because (j λe ) and PS λe The order is the same, so it is also named (j λe ) is the main control word, (j λ(e+1) ) is the slave control word.

[0082] Technical feature 10: A controllable ON / OFF follower according to technical feature 9, characterized in that the bridge potential ADC based on the dual-control follower switch chain (PSC) design is called a PSC-type bridge potential ADC, referred to as bridge potential ADC2; specifically,

[0083] An n-bit dual-control follower switch bridge potential ADC includes m sub-stages StADC, m sub-stages (StADC α 、StADC β 、StADC γ ,…,StADC m ) are (q α ,q β ,q γ ,…,q m ), where m is the final stage, n = q α +q β +q γ +…+q m ;

[0084] The λth sub-stage StADC is a q λ StADC λ , including a q λ Bit-Parallel ADCB λ , a bridge potential V λE An extraction module, an inter-level module,

[0085] The interstage module includes a sample-and-hold device T / H, a summer ∑ λ , Amplifier AM λ ;

[0086] The λth analog signal voltage U λy After connecting the sample and hold device T / H, it becomes a stable signal voltage U λZ , UλZ Two branches, one is sent to the summator∑ λ The minuend end is sent to the comparator chain to act as the in-phase input signal of each comparator, and is compared with the reference potential connected to the inverting input end of each comparator; (the subscript Q λ Can't write, here below, subscript Q λ Written Qλ )

[0087] The q λ Bit-Parallel ADCB λ Including a q λ The bit reference resistor chain (R λ0 , R λ1 , R λ2 , …, R λ(Qλ-1) ), a q λ Bit comparator chain (C λ0 , C λ1 , C λ2 ,…,C λ(Qλ-1) , where comparator C λ0 Can be omitted), a q λ bit encoder, the reference potential chain resistors are equal to form Q λ There are ΔV reference potential points (V λ0 、V λ1 、V λ2 ,…,V λ(Qλ-1) );

[0088] The bridge potential V λE The extraction module consists of a λ A dual-control follower switch (PS λ0 ,PS λ1 ,PS λ2 , …, PS λ(Qλ-1) ) λ bit double control follower switch chain, the bridge potential V λE The mathematical expression is: V λE =INT(U λZ / ΔV)*ΔV

[0089] The inverting input end of each comparator of the comparator chain, the input end of each dual-control follower switch of the dual-control follower switch chain, and each reference potential point of the reference resistor chain, and each end or point of the three are connected according to the corresponding relationship of the subscripts;

[0090] The dual-control follower switch PS λe Below is J λe , J on top λe , by P.S. λ0 of - Jλ0 Connect to PS λ1 of + J λ1 ,PS λ1 of - J λ1 Connect to PS λ2 of + J λ2 ,PS λ2 of - J λ2 Connect to PS λ3 of + J λ3 , ..., and so on, (PS λ0 ,PS λ1 ,PS λ2 , …, PS λ(Qλ-1) ) forms Q λ -1 connection point, each connection point is J λe Mark out to form a double-control follower switch PS λe Control word chain (J λ1 , J λ2 , …, J λ(Qλ-1) ), and PS λ0 J λ0 Fixed connection 1, PS λ(Qλ-1) J λ(Qλ-1) Fixed to 0; that is, let j λ0 ≡1, j λQ ≡0;

[0091] The control word of the comparison word output terminal of the comparator chain (J λ1 , J λ2 , …, J λ(Qλ-1) ) has two output directions, one output direction is the encoder, and the encoder is used to obtain the λth level ADCB λ Q λ bit digital signal to realize the λth level AD conversion; the other output direction is connected to the corresponding subscript as the control word of the dual-control follower switch control word ( + J λ1 , + J λ2 , …, + J λ(Qλ-1) ), each output end of the double-control follower switch is connected to the common output end BUS λ Then connected to the summer ∑ λ The minus end of

[0092] When the q λ Bit-Parallel ADCB λ Get the analog signal voltage U λZ When U λZThe value must be between two reference potentials, where the following reference potential is defined as the bridge potential V λE , bridge potential V λE is not greater than and closest to U λZ The reference potential is expressed as: V λE =INT(U λZ / ΔV)*ΔV:

[0093] Bridge potential V λE The comparator output value corresponding to the reference potential point below is equal to 1, which is greater than the bridge potential V λE The comparator output value corresponding to the reference potential point of the value is equal to 0, that is, V λE The dividing point, V λE The comparator output value is a string of 1s, V λE The comparator output above is a string of 0s; only PS λE At the critical point where a string of 1s turns into a string of 0s, the dual-control follower switch PS λe The ON condition is: J λe =1 and J λ(e+1) =0; that is, only PS λE Meet J λE =1 and J λ(E+1) =0, the ON condition of the other dual-control follower switches, either the upper and lower control words are all 1, or the upper and lower control words are all 0, which does not meet the conduction condition; PS λE Turning ON will increase the bridge potential V λE Take it out and send it to the common output terminal BUS λ , and then sent to the summer ∑ λ Subtrahend terminal, summator ∑ λ Conduct U λZ -V λE After the operation, a value less than ΔV is obtained, which is named the mantissa voltage U λX , and then through the amplifier AM λ Amplify 2^q λ times, U λX Expand to (-V REF ~V REF ) voltage range, becomes the next level StADC λ+1 The input signal U (λ+1)y ;

[0094] In this way, starting from level α, the conversion is performed one level after another, and finally an n-bit digital signal is obtained. Description of the drawings:

[0095] Objects are marked with symbols and symbol diagrams known in the industry. No specific description is required unless otherwise specified. Symbols include: resistor (R * ), potential (V* )、Signal voltage(u * )、Diode (D * ), transistor (T * ), op amp (A * )、Switch(S * ), control word (J * );in" * " is a subscript wildcard.

[0096] Following the above naming rules, the symbols added in this article are: follower switch is named (S); double control word follower switch is named (PS),

[0097] Symbols that have been explained before will not be explained again unless there is a special need;

[0098] All symbols can have subscripts and superscripts, which do not change the nature of the symbol; for example, J λe 、V λe , S λe , & S λe The symbols are still J, V, S, and subscript λ and e are wildcards, indicating λ The e-th order of level.

[0099] Figure 1 ——Follower switch principle block diagram; including: S-follower switch block diagram; 1-controllable op amp block diagram (the basic op amp is obtained by removing the dotted box 13 from the controllable op amp); 10-input stage; 11-intermediate stage; 12-output stage; 13-output tube control module (control module 13 that controls the output tube T1&T2 to set the ON / OFF state); 14-short-circuit branch (connect the inverting input terminal u N and the output end are short-circuited); 15-short-circuit control module (controls the ON / OFF state of the short-circuit branch 14); T1-NPN output tube; T2-PNP output tube; D1-bias diode of T1; D2-bias diode of T2; R1-bias resistor of T1; R2-bias resistor of T2; K1-first output control tube (controls ON / OFF of T1); K2-second output control tube (controls ON / OFF of T2); K F - short-circuit control tube (controls the ON / OFF of short-circuit branch 14); J- control word (control word that follows the ON / OFF of switch); V1- base potential of T1; V2- base potential of T2; u N - Inverting input terminal; u P -In-phase input terminal; u0-output terminal; +V CC -Positive power supply; -V CC - Negative pole of power supply;

[0100] Figure 1.1 ——Logic operation module; including: 16-logic operator; j1~j k -Logical signals

[0101] Figure 1.2 ——Follow-up switch symbol diagram; including: S-follow-up switch; u i - follower switch input terminal; u0- follower switch output terminal;

[0102] Figure 2.1 Schematic diagram of the follower switch; including: i / u o - Bidirectional follower switch input / output; u o / u i -Bidirectional follower switch output / input;.

[0103] Figure 2.2 Symbol diagram of follow-up switch: including: & S-bidirectional follower switch;

[0105] Figure 3.1 ——Feedback type sample and hold; including: S1-follower switch; A0-input op amp; A1-output op amp; C1-sample and hold capacitor; CLK-clock pulse signal; V in - Sampling input terminal; V out - Sample and hold output terminal;

[0106] Figure 3.2 ——Serial sample and hold device; including: S2-follower switch; A2-voltage follower; C2-sample and hold capacitor;

[0107] Figure 3.3 ——Sampling and holding T / H symbol diagram;

[0108] Figure 4 ——The λth level SDAC (sub-level DAC) formed by multiple follower switches; including: the dashed line box SDAC λ -λth level SDAC; dotted box MS λ -λth level multi-channel follower switch; dotted line box SC λ -λth level multi-way follower switch chain; dotted box RC λ - Lambda level reference resistor chain; YM λ -λth level decoder; (d λ2 d λ1 d λ0 )-digital input signal; (J λ7 ~J λ0 )-the control word output by the λth level decoder; (S λ7 ~S λ0 )-Follow switch, forming a follow switch chain: BUS λ- the common output terminal of the λth stage multi-way follower switch; d α2 d α1 d α0 -Input signal; (R λ7 ~R λ0 )-λth level reference resistor chain; (V λ7 ~V λ0 )-λth level reference voltage chain; V λE ~λth bridge potential;

[0109] Figure 5 - Bridge potential DAC; sign and Figure 4 The symbols are the same, and the additional symbols are: WA λ - weight operator of the λth stage; ∑-summer; V ∑ - sum voltage;

[0110] Figure 5.1 -One of the structures of the weight operator, the circuit structure is too numerous to mention; this structure uses a reverse proportional op amp is a good choice, WA λ -The sign and magnification of the weight operator; U out -Output signal; U in -Input signal; R F - Feedback resistor; R X - Inverting input resistance; WA λ =U out / U in =-R F / R X =-1 / 2 (λ-1)q , determine the resistance value according to needs;

[0111] Figure 5.2 -Symbol diagram of weight operator; symbols are the same as above;

[0112] Figure 6.1 -MS type m*3bit bridge potential ADC block diagram (λth level); including: symbols not shown before: StADC1 λ -λth level MS type m*3bit bridge potential ADC; SADC λ -λth level fully parallel SUB-ADC module; CC λ (C λ7 ~C λ1 )-λth stage comparator chain; ENC λ -λth level encoder; U λy -λth level input analog signal; U λ(y+1) - The λth level outputs analog signals; U λz -Analog signal after sampling and holding; V λE - bridge potential; U λX- The mantissa voltage after extracting the bridge potential.

[0113] Figure 6.2 -PSC type m*3bit bridge potential ADC block diagram (λth level); including: Symbols not previously shown are: StADC2 λ -λth level PSC type m*3bit bridge potential ADC; PSC λ - The λth level dual-control follower switch chain; (PS λ7 ~PS λ0 )-λth level double control follower switch.

[0114] Figure 6.3 -PSC type m*3bit bridge potential ADC dual control follower switch PS; using an AND gate, when PS λe The control word below (j λe )=1 and the upper control word (j λ(e+1) )=0, the obtained control word J makes the state of the follower switch ON; because (j λe ) and PS λe The order is the same, so it is also named (j λe ) is the main control word, (j λ(e+1) ) is the slave control word. Example

[0115] Embodiment 1: Output control tubes K1 & K2 are composed of NPN transistors and short-circuit control tube K is composed of bidirectional analog switches F Follow switch.

[0116] The first control tube K1 is used to control the ON / OFF of T1, and the second control tube K2 is used to control the ON / OFF of T2. K1 & K2 are collectively referred to as output control tubes. The bases of the two output control tubes K1 & K2 are controlled by the same control word J (the bases are connected to current limiting resistors as needed); the emitter of the first control tube K1 is connected to the power supply -V CC The collector of the second control tube K2 is connected to the base of the NPN output transistor T1 to control the ON / OFF of the output transistor T1; the collector of the second control tube K2 is connected to the power supply +V CC The emitter is connected to the base of the PNP output transistor T2 to control the ON / OFF of the output transistor T2;

[0117] The second is the structure of the short-circuit control module 15: the short-circuit branch 14 is used to short-circuit the output terminal u o and the inverting input terminal u N A short circuit control module 15 is connected to the short circuit branch 14 to control the ON / OFF of the short circuit branch 14; the short circuit control module 15 uses a bidirectional analog switch as a short circuit control tube K F ; Short-circuit control tube KF The ON / OFF state of the output control tube K1&K2 is opposite to that of the output control tube K1&K2. That is, when K1&K2 is OFF, K F must be set to ON; otherwise, when K1&K2 are set to ON, K F Must be set to OFF; if K F If the ON / OFF state of K1 & K2 is the same, use an inverter to adjust them to be mutually inverted;

[0118] J=0 or J=1 agreement: the control word J can be high or low, so that K1 & K2 are turned on and K F The OFF level is agreed to be "J = 1", so that K1 & K2 are OFF and K F The ON level is agreed to be "J = 0", ( Figure 1 status shown in ).

[0119] Working principle of follower switch:

[0120] One is the principle of following the switch to ON: the necessary and sufficient condition for following the switch to ON is that the output control tubes K1 & K2 are OFF and the control tube K is short-circuited. F Set to ON;

[0121] When J = low level, K1 & K2 are turned OFF and K F K1 and K2 are set to ON; K1 and K2 are set to OFF, which can be regarded as K1 and K2 not existing, so that the controllable operational amplifier returns to the basic operational amplifier state; at the same time, K F Turning ON means setting the controllable short-circuit branch 14 to a short-circuit state. The combination of these two states causes the follower switch to return to a basic follower state, that is, the follower switch is in an ON state;

[0122] The second is the principle of following the switch to OFF: the necessary and sufficient condition for following the switch to OFF is that the output control tubes K1 & K2 are turned ON (making the output tubes T1 & T2 turned OFF) and the control tube K is short-circuited. F Set OFF;

[0123] When J = high level, K1 & K2 are turned ON and K F Set OFF;

[0124] Because the main channel of K1 is connected across the base of the output transistor T1 and the power supply -V CC , so K1 is turned ON so that the base of T1 is connected to the power supply -V CC Connected, T1 is cut off; similarly, because the main channel of K2 is connected across the base of the output transistor T2 and the power supply +V CC , so K2 is turned ON to make the base of T2 connected to the power supply +V CCconnected, making T2 off; that is, K1 & K2 are turned ON, making T1 & T2 OFF, making the output terminal u o and controllable op amp truncation;

[0125] At the same time, K F OFF means setting the controllable short-circuit branch 14 to an open circuit, so that the output terminal u o With the inverting input u N The short-circuit connection is cut off;

[0126] Output terminal u o The controllable op amp is cut off and connected to the inverting input terminal u N Truncation, that is, the output end u o All the previous circuits are cut off, so that the follower switch is in the OFF state;

[0127] Experiments show that, under the premise that the offset voltage of the basic op amp is at the μV level, a resistor less than 10KΩ can be used as K F , its following accuracy can reach 10 6 ~10 7 , and the ON resistance value of the bidirectional analog switch is less than 100Ω; from an engineering point of view, it can be regarded as zero loss, so the follower switch can also be called a follower switch.

[0128] If K1&K2 and K F If the ON / OFF states of the two transistors are consistent, an inverter is used to make their ON / OFF states opposite.

[0129] This paper proposes several applications of follower switches: lossless sample-and-hold, multi-channel follower switches, bridge potential DAC and bridge potential ADC;

[0130] Embodiment 2: A follower switch type sample-and-hold device constructed by a follower switch,

[0131] There are many types of sample-and-hold devices, the mainstream ones are feedback sample-and-hold devices and series sample-and-hold devices;

[0132] Some switching op amps are on when J=0, and some are on when J=1. It is agreed here that no matter whether J=0 or J=1, the control word signal that makes the switching op amp in the ON state is named "ON signal", and the control word signal that makes the switching op amp in the OFF state is named "OFF signal";

[0133] Feedback Sample and Hold ( Figure 3.1 ), the switching amplifier SA1 acts as a sampling switch and input amplifier, and the non-inverting input terminal of the switching amplifier SA1 acts as the signal input terminal V inIts inverting input terminal is connected to the output terminal of the output amplifier A1 to form a large closed-loop circuit. The feedback sampling and holding capacitor C1 is connected between the inverting terminal and the output terminal of A1 to increase the charging and discharging speed. The clock pulse is connected to the control word of the switching amplifier. When the "ON signal" of the clock pulse CLK arrives, the switching amplifier SA1 is turned on, and the feedback sampling and holding capacitor C1 is connected to the input signal V in Sampling is performed. When the clock pulse CLK "OFF signal" arrives, the switching amplifier is turned off, and the feedback sampling and holding capacitor C1 holds the sampled signal, outputting the output signal V of the output amplifier A1. out Equal to the hold signal of C1;

[0134] Series Sample and Hold ( Figure 3.2 ), the follower switch S2 acts as a sampling switch, and its input signal is V in The output amplifier A2 is connected as a voltage follower, the sampling and holding capacitor C2 is connected between the output terminal of S2 and the ground, and the clock pulse is connected to the control word of S2. When the "ON signal" of the clock pulse CLK arrives, S2 is turned on, and the sampling and holding capacitor C2 is connected to the input signal V in Sampling is performed. When the clock pulse CLK "OFF signal" arrives, S2 is turned off, and the sampling and holding capacitor C2 holds the sampled signal and outputs the output signal V of the op amp A2. out Equal to the hold signal of C2;

[0135] The following are multi-channel follower switches, bridge potential DAC and bridge potential ADC; for the sake of simplicity, the following conventions are used:

[0136] (1) The multi-channel follower switch, bridge potential DAC and bridge potential ADC are collectively named "total device", and the total device is composed of multiple stages of "sub-stage devices";

[0137] (2) Imagine a total device of m levels by 3 bits, which consists of m sub-level devices. The subscripts of the sub-level devices are α, β, γ, ..., m, representing the first, second, third, ..., and last levels. In principle, each sub-level device can have different bits, but for the sake of simplicity, it is agreed that the bit of each sub-level device is equal to 3.

[0138] (3) Use λ to match all subscripts;

[0139] (4) The number system is a bracket plus a subscript. Let the binary subscript be "2" and the octal subscript be "8". The analog signal uses the octal system by default, that is, the analog signal without a subscript is assumed to be an octal number by default, such as 5 is assumed to be (5)8;

[0140] (5) Digital signals are encoded according to natural codes;

[0141] Embodiment 3: A multi-way follower switch constructed by follower switches, referred to as a multi-way switch MS (Multiway-Switch)

[0142] q bit multiplexer MS, which consists of q bit decoder YM λ and q bit rail body switch chain SC λ That is, MS = YM + SC; if q = 3, then Figure 4 Middle dotted box MS λ Circuit; the decoder selects a follower switch in the switch chain according to the control word.

[0143] Embodiment 4: A bridge potential DAC constructed on the basis of a multi-way switch; the bridge potential DAC is composed of m SDACs λ constitute;

[0144] SDAC λ Contains three modules: Decoder YM λ , S follows the switch chain SC λ (S Chain) and resistor chain RC λ (RChain); among them, the decoder YM λ , S follows the switch chain SC λ A multi-way switch MS λ ;

[0145] For simplicity, let's first describe each SDAC as 3 bits, and let: Q = 2 q =2 3 =8;

[0146] The 3-bit multiplexer MS λ Connect a 3-bit resistor chain RC λ , we can construct ( Figure 5 )SDAC λ ;

[0147] Use 8 resistors of equal resistance in series to form a resistor chain RC λ , resistor chain RC λ Connect to voltage V REF and ground potential, V REF Divided into 8 equal parts, each part voltage ΔV is ΔV = V REF / 8; form 8 reference potential points (V λ7 ~V λ0 ), that is, V0=0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ7 =7ΔV, (V λ8 =V REF , does not serve as a reference potential point), called Vλe is the reference potential of the λth level and the eth order; the multi-way switch MS λ (S λ7 ~S λ0 ) are connected to the corresponding reference potential point (V λ7 ~V λ0 ), (S λ7 ~S λ0 ) are connected to the output common terminal BUS λ , thus forming a 3-bit SDAC λ ;

[0148] m SDACs λ Can form a bridge potential DAC with m*3bit resolution ( Figure 5 ), bridge potential DAC includes SDAC α 、SDAC β 、SDAC γ ,…,SDAC m Sub-level, when the bridge potential DAC receives an m*3bit digital signal, it sends the signal to each SDAC at the same time λ , when the λth stage receives the input signal (d λ2 d λ1 d λ0 )=(E λ )8, S λE channel ON, other channels S λe OFF, S λE V λE Transmit to the public BUS λ , (SDAC α 、SDAC β 、SDAC γ ,…,SDAC m )The common terminal potentials are: (V αE 、V βE 、V γE ,……,V mE ), V λE It has dual properties. On the one hand, it is an analog potential, and on the other hand, it corresponds to a digital signal. λ2 d λ1 d λ0 =(E λ )8, that is, V λE It is the bridge between analog signal and digital signal, so it is named "bridge potential"; bridge potential V λE After being extracted, it is provided to the next link:

[0149] To build a bridge potential DAC, you need to establish the “right bridge potential V λEW"The concept of "; the weight operator WA of the λth level λ =1 / 2 (λ-1)*3 , although V αE ~V mE They are all bridge potentials, but it should be noted that the weights of the bridge potentials are different. λE Perform weight calculation, the symbol of the λth level "weight operator" is WA λ , W.A. λ It is also the symbol for its magnification, WA λ =1 / 2 (λ-1)3 , we get the I bridge potential V λEW :(V αE 、V βE / 2 3 、V γE / 2 6 ,……,V mE / 2 (m-1)3 ), the m weighted bridge potentials are summed up by the summator ∑ to obtain the total output signal V ∑ ;

[0150] Total output signal V ∑ =(V αE +V βE / 2 3 +V γE / 2 6 +…+V mE / 2(m-1)*3 ),

[0151] Thus, m 3-bit resolution SDACs are used. λ It forms a high-resolution bridge potential DAC, whose resolution bit value = 3*m;

[0152] The same principle can be used to construct an m-level bridge potential DAC with different bit levels.

[0153] Compared with the 3-bit bridge potential DAC above, its construction principle is the same, except that the 3 bits of each level are changed to q λ bit( λ is the subscript of q), let: Q λ =2^q λ , Multi-way switch MS λ and resistor chain RC λ All are q λ bit, multiplexer MS λ The A input terminal is connected to the resistor chain RC λ The reference potential in the bridge potential DAC, when receiving a digital signal of m levels with different bits, sends the signal to each SDAC at the same time. λ, when the λth stage receives the input signal (d λ(q-1) …d λ1 d λ0 )=(E) Q When (the subscripts of q and Q are λ Can't write, didn't write), S λE channel ON, other channels S λe OFF, S λE V λE Transmit to the public BUS λ , (SDAC α 、SDAC β 、SDAC γ ,…,SDAC m )The common terminal potentials are: (V αE 、V βE 、V γE ,……,V mE ), we can know that the bridge potential V λE The method is the same as before, except that the weight operator is WA λ =1 / 2^(q α +q β +…+q (λ-1) ), weight bridge potential V λEW =V λE *WA λ ,

[0154] Total output signal V ∑ =(V αE +V βE *WA β +V γE *WA γ +…+V mE *WA m ),

[0155] The resolution of the bridge potential DAC is equal to the sum of the resolutions of each SDAC;

[0156] About 3bit*m-level bridge potential DAC weight operator WA λ =1 / 2 (λ-1)*3 Analysis: V αE The weight of is 1, because the βth level has 3 bits of the αth level before it. So V βE The weight is only 1 / 2 3 , using proportional op amps to form a "weight operator" WA β , magnification WA β =1 / 2 3 , for V βE The weight calculation results in the β-th weight bridge potential being V βEW , VβEW =V βE / 2 3 ; Similarly, the γth level has 6 bits of α and β levels before it, so V γE The weight operator is WA γ =1 / 2 6 , the γth level weight bridge potential is V γEW =V γE / 2 6 ; There are already (λ-1)3 bits before the λth level, so V λE The weight operator is WA λ =1 / 2 (λ-1)3 ,

[0157] About the bridge potential DAC weight operator WA of m levels with different bits λ Analysis: V αE The weight of is 1, because there is already a q of level α before level β. α bit, so V βE The weight is only 1 / 2^q α , using proportional op amps to form a "weight operator" WA β , magnification WA β =1 / 2^q α , for V βE The weight calculation results in the β-th weight bridge potential being V βEW , V βEW =V βE *WA β ; Similarly, the γth level is already preceded by the αth level q α bit and beta level q β bit, so V γE The weight operator is WA γ =1 / 2^(q α +q β ), the γth level weight bridge potential is V γEW =V γE / 2^(q α +q β ); Similarly, the λth level WA λ =1 / 2^(q α +q β +…+q (λ-1) , weight bridge potential V λEW =V λE *WA λ .

[0158] Embodiment 9: An MS type bridge potential ADC constructed by combining a multi-way switch MS with a parallel ADC;

[0159] MS type m*q bit bridge potential ADC,

[0160] Architecture: It consists of m q bit StADC1 λ Composition, StADC1 λ =SADC λ +MS λ ;

[0161] If q=3, q bit StADC1 λ It constitutes Figure 6.1 3-bit StADC1 in λ Circuit;

[0162] Set the sign of the parallel SUB-ADC to SADC λ , SADC λ Q reference resistors with equal resistance are connected in series to form a resistor chain RC λ , V REF Divided into Q equal parts, each part voltage ΔV is ΔV = V REF / Q; forming Q reference potential points (V λ(Qλ-1) ~V λ0 ), that is, V0=0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ(Qλ-1) =(Q λ -1)ΔV,(V λQλ =V REF , does not serve as a reference potential point), multi-way switch MS λ (S λ(Qλ-1) ~S λ0 ) are connected to the reference potential point (V λ(Qλ-1) ~V λ0 ), thus forming a q bit StADC λ ;

[0163] Working principle:

[0164] Step 1: Receive data from the previous level StADC λ-1 The transmitted analog signal U λy , after passing through the sample-and-hold device T / H, it stabilizes into an analog signal U λz , enter (parallel ADC) SADC λ Perform AD conversion; U λz is a (0V~V REF ) potential, there must be a reference potential V λE (E=0~(Q λ -1)), so that V λE <U λz <V λ(E+1), based on the quantitative unit ΔV, V λE The sampling signal U λZ The integer part of V λE is the bridge potential, the mantissa voltage U λX The sampling signal U λZ The decimal part, U λX <ΔV;The last digit voltage U λX , sampling signal U λZ and bridge potential V λE The relationship is: U λX =U λZ -V λE

[0165] Step 2: SADC λ V λE Converted into digital signal D (qλ-1) ...D0, D (qλ-1) …D0 goes to two paths, one is used as AD conversion value, and the other is passed to the multi-way switch MS λ , as a switch MS λ The D input terminal d (q-1) …d0 input signal, the bridge potential V λE take out;

[0166] Step3: Change U λZ and V λE Send to the summator ∑ λ , conduct U λX =U λZ -V λE Operation, get the mantissa voltage U λX , and then through the amplifier AM λ Amplified Q times, it is still a (0V~V REF ) potential, becomes the next level StADC λ+1 The input signal U (λ+1)y ;

[0167] After such a level-by-level conversion, m q-bit StADCs constitute an m*q-bit bridge potential ADC.

[0168] Embodiment 10. A PSC-type bridge potential ADC constructed by combining an off / on chain PSC with a parallel ADC;

[0169] PSC type m*q bit bridge potential ADC, if q=3, it will form Figure 6.2 m*3bit bridge potential ADC;

[0170] Architecture: Set the sign of parallel ADC to SADC λ , SADC λQ reference resistors with equal resistance are connected in series to form a resistor chain RC λ , V REF Divided into Q equal parts, each part voltage ΔV is ΔV = V REF / Q; forming Q reference potential points (V λ(Q-1) ~V λ0 ), that is, V0=0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ(Q-1) =(Q-1)ΔV, (V λQ =V REF , does not serve as a reference potential point), the (PS λ(Q-1) ~PS λ0 ) are connected to the reference potential point (V λ(Q-1) ~V λ0 ), thus forming a 3-bit StADC λ ;PS λe The control word below (J λe ) is high ON word ( + J), upper control word (J λ(e+1) ) is low ON word ( - J), because (J λe ) and PS λe The order is the same, so it is also named (J λe ) is the main control word, (J λ(e+1) ) is the slave control word; in addition, let J λ0 ≡1, J λQ ≡0;

[0171] Working principle:

[0172] Step 1: Receive data from the previous SADC (λ-1) The transmitted analog signal U λy , after passing through the sample-and-hold device T / H, it stabilizes into an analog signal U λz , enter (parallel ADC) SADC λ Perform AD conversion; U λz is a (0V~V REF ) potential, there must be a reference potential V λE (E=0~(Q-1)), so that V λE <U λz <V λ(E+1) , based on the quantitative unit ΔV, V λE The sampling signal U λZ The integer part of V λE is the bridge potential, the mantissa voltage U λX The sampling signal U λZThe decimal part, U λX <ΔV;The last digit voltage U λX , sampling signal U λZ and bridge potential V λE The relationship is: U λX =U λZ -V λE

[0173] Step 2: SADC λ The comparator chain in the control word group (J λ(Q-1) ~J λ0 )Get V λE ; It is particularly important to note that this control word group is different from the control word group of the decoder. In the control word group of the decoder, only the selected control word is equal to 0, while Figure 6.2 Because the comparator's non-inverting input is connected to U λZ The inverting input terminal is connected to the reference potential, so the control word group output by the comparator is (J λ0 ~J λE )=1,(J λ(E+1) ~J λQ )=0; it can be seen that J λ0 ~J λQ The point where 1…1 is about to change to 0…0 is the flip point J. λE , the potential point it corresponds to is the bridge potential point V λE ; Of course, if the opposite is true, the inverting input of the comparator is connected to U λZ The in-phase input terminal is connected to the reference potential, and the control word group output by the comparator is (J λ0 ~J λE )=0,(J λ(E+1) ~J λQ )=1, in this case, it needs to be adjusted to PS λe The upper control word (J λe ) is high ON word ( + J), the lower control word (J λ(e+1) ) is low ON word ( - J); control word group (J λ(Q-1) ~J λ0 ) is divided into two paths, one to the encoder ENC to form a digital signal, and the other to the switch chain. Note that PS λe The control word below (J λe ) is high ON word ( + J), upper control word (J λ(e+1) ) is low ON word ( - J); Referring to the previous analysis, it can be seen that the low ON word must be at a low level ( - J=0) and the high ON word is at high level ( + J = 1), that is,+ J / - J=1 / 0 (1 down, 0 up), turn PS off / on λe It will be in the ON state, and this PS λe The A input terminal is connected to the bridge potential point. λe It happens to be PS λE ;PS λE Set the bridge potential V λE Take it out and send it to the next stage;

[0174] Step3: Change U λZ and V λE Send to the summator ∑ λ , conduct U λX =U λZ -V λE Operation, get the mantissa voltage U λX , and then through the amplifier AM λ Amplified Q times, it is still a (0V~V REF ) potential, becomes the next level StADC (λ+1) The input signal U (λ+1)y ;

[0175] After such a level-by-level conversion, m 3-bit StADCs constitute an m*3-bit bridge potential ADC.

Claims

1. The present invention is a controllable ON / OFF follower, referred to as a follower switch, which is a basic follower with two modules for controlling ON / OFF added. One is a control module 13 for controlling the output tubes T1 & T2 to be set to an ON / OFF state, referred to as the output tube control module 13, and the other is a short circuit control module 15 for controlling the short circuit branch 14 to be set to an ON / OFF state, referred to as the short circuit control module 15. Specifically, One is the structure of the output tube control module 13: an output tube control module 13 is added to the structure of the basic operational amplifier in the basic follower (input stage 10+intermediate stage 11+output stage 12) to control the output tubes T1&T2 in the output stage 12 to be turned on / off, so that the basic operational amplifier is upgraded to a controllable ON / OFF operational amplifier (the architecture of the solid line rectangular frame 1 in FIG. 1), which is referred to as a controllable operational amplifier; the output tube control module 13 includes two control tubes K1&K2 for controlling the output tubes T1&T2 to be turned on / off, wherein K1 is used to control the ON / OFF of T1 and is called the first control tube, and K2 is used to control the ON / OFF of T2 and is called the second control tube, and K1&K2 are collectively referred to as output control tubes, and the control pins of the two output control tubes K1&K2 are controlled by the same control word J; the two channel pins of the first control tube K1 are respectively connected to the power supply -V CC and the base of the NPN output transistor T1 to control the ON / OFF of the output transistor T1; the two channel pins of the second control tube K2 are respectively connected to the power supply +V CC With the base of the PNP output transistor T2, it is used to control the ON / OFF of the output transistor T2; The second is the structure of the short-circuit control module 15: the short-circuit branch 14 is used to short-circuit the output terminal u o and the inverting input terminal u N A short circuit control module 15 is connected to the short circuit branch 14 to control the ON / OFF of the short circuit branch 14. The simplest structure of the short circuit control module 15 is a short circuit control tube K. F ; Short-circuit control tube K F The ON / OFF state of the output control tube K1 & K2 is opposite to each other, that is, when K1 & K2 are OFF, K F must be set to ON; otherwise, when K1&K2 are set to ON, K F Must be set to OFF; if K F If the ON / OFF state of K1 & K2 is the same, use an inverter to adjust them to be mutually inverted; J=0 or J=1 agreement: the control word J can be high or low, so that K1 & K2 are turned on and K F The OFF level is agreed to be "J = 1", so that K1 & K2 are OFF and K F The ON level is agreed to be "J=0", (the state shown in Figure 1); Working principle of follower switch: One is the principle of following the switch to ON: the necessary and sufficient condition for following the switch to ON is that the output control tubes K1 & K2 are OFF and the control tube K is short-circuited. F Set to ON; When J=0, K1&K2 are turned OFF and K F K1 and K2 are set to ON; K1 and K2 are set to OFF, which can be regarded as K1 and K2 not existing, so that the controllable operational amplifier returns to the basic operational amplifier state; at the same time, K F Turning ON means setting the controllable short-circuit branch 14 to a short-circuit state. The combination of these two states causes the follower switch to return to a basic follower state, that is, the follower switch is in an ON state; The second is the principle of following the switch to OFF: the necessary and sufficient condition for following the switch to OFF is that the output control tubes K1 & K2 are turned ON (making the output tubes T1 & T2 turned OFF) and the control tube K is short-circuited. F Set OFF; When J=1, K1&K2 are turned ON and K F Set OFF; Because the main channel of K1 is connected across the base of the output transistor T1 and the power supply -V CC , so K1 is turned ON so that the base of T1 is connected to the power supply -V CC Connected, T1 is cut off; similarly, because the main channel of K2 is connected across the base of the output transistor T2 and the power supply +V CC , so K2 is turned ON to make the base of T2 connected to the power supply +V CC connected, making T2 off; that is, K1 & K2 are turned ON, making T1 & T2 OFF, making the output terminal u o and controllable op amp truncation; At the same time, K F Setting OFF means setting the controllable short-circuit branch 14 to an open circuit, so that the output terminal u o With the inverting input u N The short-circuit connection is cut off; Output terminal u o The controllable op amp is cut off and connected to the inverting input terminal u N Truncation, that is, the output end u o All the previous circuits are cut off, making the follower switch in the OFF state.

2. The ON / OFF controllable follower according to claim 1, characterized in that: The output control tubes K1 and K2 use triodes and corresponding base resistors, short-circuiting the control tube K F Use a bidirectional analog switch; if K1&K2 and K F If the ON / OFF states of the two transistors are consistent, an inverter is used to make their ON / OFF states opposite.

3. The ON / OFF controllable follower according to claim 1, characterized in that: Based on the follower switch, a bidirectional follower switch is constructed. Specifically, The follower switch S1 and the follower switch S2 are connected in parallel in forward and reverse directions, and the control words of the two are connected at the same time to form a bidirectional follower switch.

4. The ON / OFF controllable follower according to claim 1, characterized in that The sample-and-hold circuit based on the follower switch structure is as follows: The switch in the existing sample-and-hold device is replaced by a follower switch to form a follower switch type sample-and-hold device, including a follower switch type feedback type sample-and-hold device and a follower switch type series type sample-and-hold device.

5. The ON / OFF controllable follower according to claim 1, characterized in that A multi-way follower switch is constructed using multiple follower switches. Specifically, the input pins of multiple follower switches are connected to form a multi-way follower switch with a common input pin, the output pins of multiple follower switches are connected to form a multi-way follower switch MS with a common output pin, and the control pins of multiple follower switches are connected to form a multi-way follower switch with a common control pin.

6. The ON / OFF controllable follower according to claim 1, characterized in that: A bridge potential DAC based on a common output multi-channel follower switch MS structure, specifically An n-bit DAC is composed of m SUB-DACs and a weight summing amplifier (WA∑), and the SUB-DAC is referred to as SDAC in the following; (α level, β level, γ level, ..., m level) m SDACs are respectively (SDAC α 、SDAC β 、SDAC γ ,…,SDAC m ), their digits are (q α ,q β ,q γ ,…,q m ), where m is the final stage, n = q α +q β +q γ +…+q m ; Use the λth sub-level SDAC λ Wildcard all sub-levels, SDAC λ The number of digits is q λ , SDAC λ Contains a q λ Bit multiplexer follower switch MS λ (multiway switch) and a q λ Bit reference resistor chain RC λ (R-chain); The reference potential chain RC λ The resistors are equal and connected across (-V REF ~V REF ), 2 qλ A reference resistor (R λ0 , R λ1 , R λ2 , …, R λ(Qλ-1) ) will (-V REF ~V REF ) is divided into 2 qλ To simplify the analysis, let -V REF =0, each equally divided voltage ΔV is ΔV=V REF / 2 qλ ; Form 2 qλ +1 potential point (V λ0 ~V λQλ ), of which 2 qλ Reference potential point (V λ0 ~V λ(Qλ-1) ), namely V λ0 =0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ(Qλ-1) =(Q λ -1)ΔV,(V λQλ =Q λ ΔV=V REF , does not serve as a reference potential point), called V λe is the reference potential of the e-th order of the λth level; The λth stage multi-way follower switch MS λ Including a q λ Bit Decoder YM λ and a q λ Follower switch chain SC λ =(S λ0 , S λ1 , S λ2 ,…,S λ(Qλ-1) ); Multi-channel follower switch MS λ It has three groups of ports, one of which is the control port - the control word (J λ0 , J λ1 , …, J λ(Qλ-1) ); one group is A input terminal - each follower switch (S λ0 , S λ1 ,…,S λ(Qλ-1) )'s A input terminal, one group is the A output terminal - the A output terminal of each follower switch; The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and Q λ =2 qλ Decoded output word (J λ0 , J λ1 , …, J λ(Qλ-1) ), the decoded output word is the same as the 2 qλ The control word of the following switch (J λ0 , J λ1 , …, J λ(Qλ-1) ) are connected according to the corresponding relationship of equal subscripts; 2 qλ Follow-up switch (S λ0 , S λ1 ,…,S λ(Qλ-1) ) is connected to the reference potential point (V λ0 、V λ1 ,…,V λ(Qλ-1) ), the A output of all follower switches is connected to the λth level common output BUS λ (Figure 5); When SDAC λ The D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE , J λE Sent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the λth level; V λE It is both an analog potential and corresponds to a digital signal (d λ(q-1) …d λ1 d λ0 ) value, is the bridge between analog signal and digital signal, so V λE Named "bridge potential"; get each level of SDAC in turn λ The bridge potential (V αE 、V βE 、V γE ,……,V mE ); Each bridge potential V λE With different rights λ Therefore, the bridge potential V λE Multiply by the weight WA λ Get the weight bridge potential WV λE , that is, WV λE =WA λE *V λE To this end, it is necessary to pass the bridge potential of each level through the BUS line (BUS α 、BUS β 、BUS γ 、……、BUS m ) and then sent to the Weight-ALU (WA α , W.A. β , W.A. γ ,…,WA m ) to perform weight calculation; WA λ The corresponding weight is WA λ ; Let WA α =1, the weight of the first level (λ+1) is 2 less than that of the first level λ qλ times, that is, WA (λ+1) =WA λ / 2 qλ ; with WA α As a benchmark, we get W.A. α = 1, WA β = 1 / 2 qα , W.A. γ =WA β / 2 qβ = 1 / 2 (qα+qβ) , …, W.A. m =WA (m-1) / 2 q(m-1) = 1 / 2 (qα+qβ+…+q(m-1)) (Note: Here 2 (qα+qβ+…+q(m-1)) (α, β, ..., (m-1)) in the equation are subscripts of q) The potential of each level of weight bridge passes through the summator ∑ λ After summing, the total DAC output voltage V out ,Right now, V out =WV αE +WV βE +WV γE +...+WV λm =WORLD αE *V αE +V αE +WA β *V βE +WA γ *V γE +...+WORLD m *V λm =V αE +V βE / 2 q α +V γE / 2 qα+qβ +...+V λm / 2 qα+qβ+…+q(m-1) 。 7. The ON / OFF controllable follower according to claim 6, characterized in that: An MS type bridge potential pipeline ADC1 is formed by replacing the SDAC in the pipeline ADC with a common output multi-channel follower switch (MS), referred to as bridge potential ADC1. Specifically, The bridge potential ADC1 is the same as the traditional pipeline ADC, which is composed of multi-stage Stage-ADC λ The two are composed of one stage after another. In order to distinguish the two, the following will be the Stage-ADC of the Type 1 bridge potential ADC1 λ StADC1 for short λ , the Stage-ADC of the traditional pipeline ADC λ Referred to as StaADC λ ;StaADC λ Includes a SUB-ADC λ (SADC λ ), a SUB-DAC λ (SDAC λ ) and an interstage module ISM λ (Interstage module); while StADC1 λ Just StaADC λ SDAC λ Replace it with a multi-way follower switch; that is, the StADC1 λ (Figure 6.1) includes a SADC λ , a multi-channel follower switch MS λ and an interstage module ISM λ , The StADC1 λ SADC λ Includes a reference resistor chain RC λ , a comparator chain CC λ , an encoder ENC λ ; The reference potential chain RC λ The resistors are equal and connected across (-V REF ~V REF ), 2 qλ A reference resistor (R λ0 , R λ1 , R λ2 , …, R λ(Qλ-1) ) will (-V REF ~V REF ) is divided into 2 qλ Divide equally, and the voltage of each equal division is ΔV = V REF / 2 qλ ; To simplify the analysis, let -V REF =0, so that the reference resistor chain RC λ Formation (2 qλ +1) potential point (V λ0 ~V λQλ ), of which 2 qλ Reference potential point (V λ0 ~V λ(Qλ-1) ), namely V λ0 =0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ(Qλ-1) =(Q λ -1)ΔV,(V λQλ =Q λ ΔV=V REF , does not serve as a reference potential point), called V λe is the reference potential of the e-th order of the λth level; The comparator chain CC λ By (2 qλ -1) comparator (C λ0 , C λ1 , R λ2 ,…,C λ(Qλ-1) ) across (-V REF ~V REF ), C λ0 For virtual; Resistor chain and comparator chain CC λ There are two types of connection relationships. The first is the input signal U λy After passing through the sample-and-hold device, it is connected to the non-inverting input of each comparator. The reference potential point (V λ1 ~V λ(Qλ-1) ) is connected to the corresponding comparator (C λ1 ~C λ(Qλ-1) ) is the inverting input terminal; the second is just the opposite, the input signal U λy After passing through the sample-and-hold device, it is connected to the inverting input of each comparator. The reference potential point (V λ1 ~V λ(Qλ-1) ) is connected to the corresponding comparator (C λ1 ~C λ(Qλ-1) )’s non-inverting input terminal; the two have the same principle, and this paper adopts the first connection relationship for analysis; The λth stage multi-way follower switch MS λ Including a q λ Bit Decoder YM λ and a q λ Follower switch chain SC λ =(S λ0 , S λ1 ,…,S λ(Qλ 1) ); The q λ The bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and Q λ =2 qλ Decoded output word (J λ0 , J λ1 , …, J λ(Qλ-1) ); The follower switch chain is 2 qλ Follow-up switch (S λ0 , S λ1 ,…,S λ(Qλ-1) ), its A input terminal is connected to 2 qλ Reference potential point (V λ0 、V λ1 ,…,V λ(Qλ-1) ), all A output terminals are connected to the λth level common output terminal BUS λ , its control word (J λ0 , J λ1 , …, J λ(Qλ-1) ) is connected to the decoder YM λ The output word (J λ0 , J λ1 , …, J λ(Qλ-1) ); The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and 2 qλ Decoded output word (J λ0 , J λ1 , …, J λ(Qλ-1) ), the decoded output word is the same as the 2 qλ The control word of the following switch (J λ0 , J λ1 , …, J λ(Qλ-1) ) are connected accordingly; 2 qλ The A input terminal of each follower switch is connected to the reference potential point according to the corresponding subscript, and the output terminals of all follower switches are connected to the λth level common output terminal BUS λ ; When SDAC λ The D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE (Note: Under the premise of knowing that it is at the λ level, the subscript E is used by default. λ Indicated by E), J λE Sent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the λth level; The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and 2 qλ Decoded output word (J λ0 , J λ1 , …, J λ(Qλ-1) ), the decoded output word is the same as the 2 qλ The control word of the following switch (J λ0 , J λ1 , …, J λ(Qλ-1) ) are connected accordingly; 2 qλ The A input terminal of each follower switch is connected to the reference potential point according to the corresponding subscript, and the output terminals of all follower switches are connected to the λth level common output terminal BUS λ ; The interstage module ISM λ Including summer ∑ λ , Amplifier AM λ (The two are collectively called the summing and amplifier ∑&AM λ ) and a sample holder T / H; When SDAC λ The D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE (Note: Under the premise of knowing that it is at the λ level, the subscript E is used by default. λ Indicated by E), J λE Sent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the λth level; The interstage module includes a sample-and-hold device T / H, a summer ∑ λ , Amplifier AM λ ; The bridge potential V λE The extraction module includes a q λ bit multi-way follower switch; the q λ The bit multiplexer follower switch includes a q λ bit decoder, a follower switch chain (S λ0 , S λ1 , S λ2 ,…,S λ(Qλ-1) ), each follower switch output is connected to the common output terminal BUS λ ; The A input terminal of each follower switch of the follower switch chain, the inverting input terminal of each comparator of the comparator chain, and the reference potential points of the reference resistor chain are connected according to the corresponding relationship of the subscripts.

8. The ON / OFF controllable follower according to claim 1, characterized in that A logic operator is used to perform logic operations on multiple logic signals, including a combinational logic operator and a sequential logic operator, to obtain a control word J for controlling the ON / OFF of the follower switch.

9. The ON / OFF controllable follower according to claim 8, characterized in that Use an AND gate to operate the two control signals to obtain the dual-control follower switch PS λe Specifically The dual-control follower switch PS λe There are two control signals (j λ(e+1) ) and (j λe ), using an AND gate, only when PS λe The control word below (j λe )=1 and the upper control word (j λ(e+1) )=0, the obtained control word J makes the state of the follower switch ON.

10. The ON / OFF controllable follower according to claim 9, characterized in that: The bridge potential ADC based on the dual-control follower switch chain (PSC) design is called the PSC bridge potential ADC, or bridge potential ADC2 for short. An n-bit dual-control follower switch bridge potential ADC includes m sub-stages StADC, m sub-stages (StADC α 、StADC β 、StADC γ ,…,StADC m ) are (q α ,q β ,q γ ,…,q m ), where m is the final stage, n = q α +q β +q γ +…+q m ; The λth sub-stage StADC is a q λ StADC λ , including a q λ Bit-Parallel ADCB λ , a bridge potential V λE An extraction module, an inter-level module, The interstage module includes a sample-and-hold device T / H, a summer ∑ λ , Amplifier AM λ ; The λth analog signal voltage U λy After connecting the sample and hold device T / H, it becomes a stable signal voltage U λZ , U λZ Two branches, one is sent to the summator∑ λ The minuend end is sent to the comparator chain to act as the in-phase input signal of each comparator, and is compared with the reference potential connected to the inverting input end of each comparator; (the subscript Q λ Can't write, here below, subscript Q λ Written Qλ ) The q λ Bit-Parallel ADCB λ Including a q λ The bit reference resistor chain (R λ0 , R λ1 , R λ2 , …, R λ(Qλ-1) ), a q λ Bit comparator chain (C λ0 , C λ1 , C λ2 ,…,C λ(Qλ-1 ), where comparator C λ0 Can be omitted), a q λ bit encoder, the reference potential chain resistors are equal to form Q λ There are ΔV reference potential points (V λ0 、V λ1 、V λ2 ,…,V λ(Qλ-1) ); The bridge potential V λE The extraction module consists of a λ A dual-control follower switch (PS λ0 ,PS λ1 ,PS λ2 , …, PS λ(Qλ-1) ) λ bit dual-control follower switch chain, the bridge potential V λE The mathematical expression is: V λE =INT(U λZ / ΔV)*ΔV The inverting input end of each comparator of the comparator chain, the input end of each dual-control follower switch of the dual-control follower switch chain, and each reference potential point of the reference resistor chain, and each end or point of the three are connected according to the corresponding relationship of the subscripts; The dual-control follower switch PS λe Below is J λe , J on top λe , by P.S. λ0 of - J λ0 Connect to PS λ1 of + J λ1 ,PS λ1 of - J λ1 Connect to PS λ2 of + J λ2 ,PS λ2 of - J λ2 Connect to PS λ3 of + J λ3 , ..., and so on, (PS λ0 ,PS λ1 ,PS λ2 , …, PS λ(Qλ-1) ) forms Q λ -1 connection point, each connection point is J λe Mark out to form a double-control follower switch PS λe Control word chain (J λ1 , J λ2 , …, J λ(Qλ-1) ), and PS λ0 J λ0 Fixed connection 1, PS λ(Qλ-1) J λ(Qλ-1) Fixed to 0; that is, let j λ0 ≡1, j λQ ≡0; The control word of the comparison word output terminal of the comparator chain (J λ1 , J λ2 , …, J λ(Qλ-1) ) has two output directions, one output direction is the encoder, and the encoder is used to obtain the λth level ADCB λ Q λ bit digital signal to realize the λth level AD conversion; the other output direction is connected to the corresponding subscript as the control word of the dual-control follower switch control word ( + J λ1 , + J λ2 , …, + J λ(Qλ-1) ), each output end of the double-control follower switch is connected to the common output end BUS λ Then connected to the summer ∑ λ The minus end of When the q λ Bit-Parallel ADCB λ Get the analog signal voltage U λZ When U λZ The value must be between two reference potentials, where the following reference potential is defined as the bridge potential V λE , bridge potential V λE is not greater than and closest to U λZ The reference potential is expressed as: V λE =INT(U λZ / ΔV)*ΔV; Bridge potential V λE The comparator output value corresponding to the reference potential point below is equal to 1, which is greater than the bridge potential V λE The comparator output value corresponding to the reference potential point of the value is equal to 0, that is, V λE The dividing point, V λE The comparator output value is a string of 1s, V λE The output value of the comparator above is a string of 0s; only PS λE At the critical point where a string of 1s turns into a string of 0s, the dual-control follower switch PS λe The ON condition is: J λe =1 and J λ(e+1) =0; that is, only PS λE Meet J λE =1 and J λ(E+1) =0, the ON condition of the other dual-control follower switches, either the upper and lower control words are all 1, or the upper and lower control words are all 0, which does not meet the conduction condition; PS λE Turning ON will increase the bridge potential V λE Take it out and send it to the common output terminal BUS λ , and then sent to the summer ∑ λ Subtrahend terminal, summator ∑ λ Conduct U λZ -V λE After the operation, a value less than ΔV is obtained, which is named the mantissa voltage U λX , and then through the amplifier AM λ Amplify 2^q λ times, U λX Expand to (-V REF ~V REF ) voltage range, becomes the next level StADC λ+1 The input signal U (λ+1)y ; In this way, starting from level α, the conversion is performed one level after another, and finally an n-bit digital signal is obtained.

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