Double-sampling readout circuit based on composite dielectric gate double-transistor photosensitive detector

Abstract

The invention relates to a double-sampling readout circuit based on a composite dielectric gate double-transistor photosensitive detector, and belongs to the field of analog integrated circuits. The double-sampling reading circuit comprises a detection unit, a source-drain connection switch, a double-sampling module and an output signal gating module, can provide working modes of on-chip double-sampling, off-chip double-sampling and single-sampling, is suitable for single-tube and array reading, realizes quantification of threshold voltage by using charging and discharging of a sampling capacitor, and improves the sampling accuracy. And the quantization range of the ADC can be adapted by modulating the reference voltage, so that the cascade connection with the high-precision and high-speed ADC is realized. And the source end and the drain end of the detection unit which does not read out are communicated, so that leakage current is avoided, and power consumption is reduced. The readout circuit provided by the invention remarkably reduces the swing of the output voltage, improves the readout speed and accuracy, reduces the power consumption and noise, can be cascaded with a low-swing, high-precision and high-speed ADC (Analog to Digital Converter), and is used for meeting the requirements of high image quality and high frame rate of an image sensor.

Description

Technical Field

[0001] The invention relates to a double sampling readout circuit based on a composite dielectric gate double transistor photosensitive detector, belonging to the field of analog integrated circuits. Background Art

[0002] As a photoelectric signal converter, photodetectors can effectively convert light signals into electrical signals and further display images. They are widely used in daily life, security, national defense and other fields. At present, mainstream photodetectors are divided into two categories: CCD (Charge-Coupled Device) and CMOS-APS (Complementary Metal-Oxide-Semiconductor Active Pixel Sensor). CCD can convert light signals into analog current signals, and after transmission, amplification and analog-to-digital conversion, it can achieve image acquisition, storage, transmission, processing and reproduction. It has the advantages of small size, light weight, low power consumption and high sensitivity. CMOS-APS is an image sensor that integrates image acquisition and signal processing functions. Unlike CCD, CMOS-APS can amplify signals within the pixel unit, and has the advantages of low power consumption, high integration, fast reading speed and strong flexibility.

[0003] The composite dielectric gate dual-transistor photodetector combines the advantages of CCD and CMOS-APS, and is expected to become a new generation of mainstream photodetectors. The Chinese patent with publication number CN102938409A provides a fixed voltage readout method based on a composite dielectric gate dual-transistor photodetector. This method achieves readout by applying a constant voltage to the gate and drain terminals and quantifying the drain current before and after exposure, but it will produce a large fixed pattern noise; and such a readout method quantifies the number of photogenerated electrons by applying a ramp voltage and using a counter technology. This process usually requires hundreds of clock cycles, thereby limiting the frame rate and noise performance of the photodetector. In contrast, the mainstream CMOS-APS uses a source-following readout method, which has a faster speed. However, due to the fundamental structural differences between CMOS-APS and composite dielectric gate dual-transistor photodetectors, the source-following readout method of CMOS-APS cannot be directly applied to composite dielectric gate dual-transistor photodetectors. Therefore, the Chinese patent with publication number CN118574028A explores a source-following readout method suitable for a composite dielectric gate dual-transistor photodetector. The detection unit is connected to a current source, and the threshold voltage has good linearity with the source voltage. However, due to process differences, the output voltage swing is large, which makes ADC quantization difficult. In addition, on-chip double sampling can theoretically reduce the noise with correlation between the two samples (the noise of the two samples before and after will have a correlated part, so double sampling can reduce the noise, that is, the variance of the difference between the signals has a negative covariance). In order to reduce noise and solve the ADC quantization difficulty, a double sampling circuit is considered. However, the conventional double sampling circuit has the disadvantages of high power consumption and single function, and cannot realize off-chip double sampling and single sampling modes, and has poor compatibility with the composite dielectric gate dual-transistor photodetector array. Summary of the invention

[0004] Based on the above background, the present invention proposes a dual sampling readout circuit based on a composite dielectric gate dual transistor photosensitive detector. The technical solution adopted by the present invention is as follows:

[0005] A dual sampling readout circuit based on a composite dielectric gate dual transistor photosensitive detector comprises: a detection unit of the composite dielectric gate dual transistor photosensitive detector; a transmission gate S2 connecting the detection unit and the dual sampling module, which is required not to limit the current source flowing through the device; a transmission gate S1 transmitting a high voltage at the drain end to the source end; a current mirror I as a current source; a voltage buffer; and a sampling capacitor C. c ; Two transmission gates S3 and S4; Two transmission gates S5 and S6 serve as output signal selection modules.

[0006] Furthermore, the readout circuit only utilizes the principle of charge conservation and has a simple structure. When the source voltage and the reference voltage are read out for the first time, the sampling capacitor Cc Charging is performed to keep the capacitor charge unchanged. The lower plate is floated for the second reading. The upper plate is connected to the source voltage after the threshold voltage changes. Then the lower plate voltage is the sum of the reference voltage and the source voltage change. The reference voltage can be modulated to adapt to the quantization range of the ADC. Isolation measures should also be taken between the output end of the circuit and the ADC to avoid charge loss.

[0007] Furthermore, the dual sampling readout circuit of the present invention, for reading the composite dielectric gate dual transistor photosensitive detector array, connects the bit line of certain columns to the drain line when certain columns are not selected, and the source terminal potential is the same as the drain terminal, which can avoid unnecessary current flowing through the device and reduce power consumption.

[0008] Furthermore, multiple columns can be selected to reuse the same readout circuit according to the size of the detection unit and the array scale. When multiple bit lines reused by a readout circuit do not need to be read out, they are all connected to the drain line, and the enable signal of the voltage buffer of the subsequent double sampling circuit will be switched to the off state.

[0009] Furthermore, the readout time is mainly limited by the response speed of the voltage buffer. Usually, the voltage buffer is connected in an operational amplifier structure. The response time can be reduced to the ns level by slightly increasing the conversion rate SR and unit gain bandwidth GBW of the operational amplifier. Considering the ADC, the readout time will normally be within 1us.

[0010] Furthermore, the readout circuit has a significant advantage in speed. During sampling, the pixel switches to the readout mode and turns on the source follower, and the switching time is limited by the driving circuit. The buffer then drives the sampling capacitor to establish the target voltage. The on-chip double sampling result of a row can be locked in the lower plate of the capacitor of the readout circuit, and the single sampling result can be locked in the upper plate of the capacitor. Quantization only needs to be completed before the next row of detectors enters the readout state, and the readout time is only limited by the capacitor charging time. Such high-speed readout can ensure that there is a sufficiently high frame number in the composite dielectric gate dual transistor photosensitive detector with large-scale pixels. The reduction of the shortest readout time can optimize the exposure time limitation problem. Since the rolling shutter mode is usually used for exposure readout reset, there is a shortest exposure time. If a source follower readout circuit is used, the shortest exposure time can be shortened, making the composite dielectric gate dual transistor photosensitive detector suitable for low-light scenes and improving the dynamic range of the detector.

[0011] Furthermore, the noise of the readout circuit will be lower. First, the voltage difference read out in the double sampling mode reflects the change in the charge in the pixel truthfully, and will not be disturbed by the inconsistency of the pixel threshold. Moreover, the interval between the two samples is very short, which eliminates the influence of low-frequency noise and has a natural high-pass filtering function. Secondly, the noise sources of the entire readout path are sorted out, from front to back: the error introduced by the source follower, the error introduced by the buffer, the charge injection of the switch tube, and the clock feedthrough. Among them, the gain of the source follower structure has been tested and proved to have good linearity. As long as the current source is stable enough, it is considered that the noise introduced by the source follower can be ignored. The other three noise sources can also be reduced by careful design of the circuit and layout. The noise introduced by the switch is reduced by the sampling capacitor. The larger the sampling capacitor, the longer the voltage is held and the lighter the process mismatch. If there is a correlation between the noise of the two sampling signals, this part of the noise can be reduced by double sampling.

[0012] Furthermore, the readout circuit supports a single sampling mode, can directly quantize the source voltage, and further analyze the readout noise after removing the quantization noise, as well as the relationship between the actual working linearity and related parameters and the source voltage.

[0013] The readout circuit of the present invention is particularly suitable for use in applications of high-speed computing and large-scale pixel image processing, and can be cascaded with a high-precision and high-speed ADC to meet the requirements of high image quality and high frame rate of image sensors.

[0014] The beneficial effects provided by the present invention are:

[0015] The readout circuit proposed by the present invention realizes quantization of threshold voltage by utilizing the charging and discharging of sampling capacitors, has a simple structure, and can adapt to the quantization range of ADC by modulating the reference voltage to realize cascading with high-precision and high-speed ADC; the source end and the drain end of the detection unit that is not selected for reading are connected to avoid generating unnecessary current and thus reduce power consumption; because the readout circuit realizes reading by utilizing the charging and discharging of the sampling capacitors, the reading time is only limited by the charging time of the capacitors, and a sufficiently high frame number can be maintained while reading at a high speed; in addition, a source follower readout mode is adopted to shorten the shortest exposure time and improve the dynamic range of the detector; the double-sampling readout circuit will not be disturbed by the inconsistency of pixel threshold value and the time interval between two samplings is very short, thereby avoiding the influence of low-frequency noise, and other noises can be reduced by circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a circuit diagram of a double sampling readout circuit based on a composite dielectric gate dual transistor photosensitive detector of the present invention;

[0018] Figure 2 It is a schematic diagram of a double sampling readout circuit based on composite dielectric gate dual transistor photosensitive detector array reading of the present invention;

[0019] Figure 3 It is a timing diagram of the on-chip double sampling operation of the double sampling readout circuit based on the composite dielectric gate double transistor photosensitive detector of the present invention;

[0020] Figure 4 The single sampling operation timing diagram of the dual sampling readout circuit based on the composite dielectric gate dual transistor photosensitive detector of the present invention. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0022] Embodiment 1:

[0023] The present embodiment provides a dual sampling readout circuit based on a composite dielectric gate dual transistor photosensitive detector, which is used to perform dual sampling readout on a detection unit composed of a single composite dielectric gate dual transistor photosensitive detector or a composite dielectric gate dual transistor photosensitive detector array; the dual sampling readout circuit includes a source-drain connection switch S1, a dual sampling module and an output signal selection module; wherein the dual sampling module is connected to the detection unit through a transmission gate S2; the source-drain connection switch S1 is connected between the source end and the drain end of the composite dielectric gate dual transistor photosensitive detector, the dual sampling module includes a current source, a voltage buffer, and a sampling capacitor C c and two transmission gates S3 and S4; the output signal selection module includes two transmission gates S5 and S6.

[0024] like Figure 1 As shown, for a single composite dielectric gate dual transistor photosensitive detector, the source-drain connection switch S1 uses a PMOS tube S1 that transmits positive high voltage; in the dual sampling module, the current source uses a current mirror I, a voltage buffer, a transmission gate S3, and a sampling capacitor C cThe transmission gate S4 is connected in sequence, the other end of the transmission gate S4 is connected to the reference voltage VREE, one end of the current mirror I is connected to the input end of the voltage buffer, and the other end is grounded. A transmission gate S5 in the output signal selection module is connected to the output end of the voltage buffer, and another transmission gate S6 is connected to the sampling capacitor C c One end connected to the transmission gate S4.

[0025] By adjusting the width and length of the PMOS tubes and NMOS tubes in S3, S4 and S6, the effects of charge injection, clock feedthrough, etc. can be effectively reduced.

[0026] Figure 2 The present invention is a schematic diagram of a dual sampling readout circuit based on a composite dielectric gate dual transistor photosensitive detector array. The control gates of the composite dielectric gate dual transistor photosensitive detectors in the same row of the array are interconnected to form a word line WL, the sources of the detection units in the same column are interconnected to form a bit line BL, and the drains of all the detection units are interconnected to form a total drain line DL. A multi-column shared readout circuit is adopted, and the multiplexing relationship between the bit line BL and the readout circuit is determined according to the size of the detection unit. The multiple bit lines BL are connected to the source end of the address selection tube, the drain end of the address selection tube is connected to the input end of the current source and voltage buffer of the dual adoption circuit, and the gate of the address selection tube is connected to the address selection signal of BL.

[0027] Embodiment 2:

[0028] This embodiment provides a dual sampling readout method based on a composite dielectric gate dual transistor photosensitive detector. Based on the circuit implementation provided in the first embodiment, the specific working mode of the efficient readout circuit based on the composite dielectric gate dual transistor photosensitive detector is introduced below:

[0029] In the above structure: the substrate of the detection unit is usually connected to a negative voltage. In the exposure state, the control gate (WL voltage) can be connected to 0V or a positive high voltage, so that the C region of the pixel generates an electric field in the direction of the gate substrate, thereby collecting photoelectrons. The potential of the C region changes, which leads to a change in the threshold voltage of the device; when reading, the control gate is connected to a positive voltage to turn on the device, that is, greater than the threshold voltage when the full well is reached. The drain end (DL voltage) needs to be connected to a positive voltage, which is greater than the overdrive voltage of the device to put the device in the saturation region. After the device collects photoelectrons, it starts the first reading and then resets, and then performs the second reading. When reading, a source follower structure is used, with the pixel tube as the input tube of the source follower. When reading, the pixel is in the saturation region. Under the condition of fixed current and gate voltage, the source terminal voltage is: The source voltage is only linearly related to the threshold voltage, and other parameters are only related to the pixel itself.

[0030] If the bit line is not selected, S1 is closed, the address selection tube is disconnected, and the bit line potential is the same as the total leakage line to prevent the influence of the leakage current of the bit line. When all the bit lines connected to the double sampling circuit are not selected, S2 is disconnected and the voltage buffer is turned off to reduce unnecessary power consumption.

[0031] If the bit line is selected, the address selector is closed, S1 is disconnected, and the voltage buffer is turned on. There are several reading modes:

[0032] 1. On-chip double sampling mode: S6 is closed, S5 is open, the circuit works as follows Figure 3 When reading for the first time, S3 and S4 are closed, the upper plate voltage of the sampling capacitor is the pixel source voltage transmitted by the voltage buffer, and the lower plate voltage is connected to the reference voltage VREF. The source voltage at this time is recorded as V s1 , then the charge stored in the capacitor is Cc(V s1 -VREF); Since the pixel is in the off state during reset, the source voltage is at the lowest potential of the current mirror. In order to maintain the charge of the sampling capacitor as much as possible, S3 needs to be disconnected after charging is completed and before reset. After reset, the threshold voltage changes. Before the second reading, S4 is disconnected, and the lower board is suspended. After the second reading, the source voltage increases, and S3 is closed. Since the charge of the sampling capacitor remains unchanged, the voltage of the upper board is V s2 , the voltage of the lower board is equal to the voltage of the OUT terminal, which is VREF+V s2 -V s1 , and then transmit the OUT terminal voltage to the next level ADC for quantization.

[0033] 2. Single sampling mode: S5 is closed, S6 is disconnected, and the source voltage is directly transmitted to the ADC through the voltage buffer for quantization: S5 is closed, S6 is disconnected, and the single sampling signal output path is opened. In order not to affect the phase margin of the voltage buffer, etc., its load capacitance is still the sampling capacitor Cc, then S3 and S4 are closed, and the source voltage signal can be quickly transmitted from the voltage buffer to the ADC for quantization from the single sampling signal output path. Even if it is limited by the ADC quantization range, the double sampling mode used for large arrays to output images, the single sampling mode usually serves part of the array or a single detection unit, and the ADC quantization starting point can be adjusted to achieve the purpose) The off-chip double sampling and single sampling functions can be realized through algorithms. The working timing for realizing the single sampling function is as follows Figure 4 shown.

[0034] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0035] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A dual sampling readout circuit based on a composite dielectric gate dual transistor photosensitive detector, characterized in that: The circuit is used for performing double sampling readout on a detection unit composed of a single composite dielectric gate dual transistor photosensitive detector or a composite dielectric gate dual transistor photosensitive detector array, and the circuit comprises a source-drain connection switch S1, a double sampling module and an output signal gating module; the double sampling module is connected to the detection unit through a transmission gate S2; The source-drain connection switch S1 is connected between the source and drain ends of the composite dielectric gate dual transistor photosensitive detector. The dual sampling module includes a current source, a voltage buffer, and a sampling capacitor C c and two transmission gates S3 and S4; the output signal selection module includes two transmission gates S5 and S6.

2. The circuit according to claim 1, characterized in that In the dual sampling module, the voltage buffer, the transmission gate S3, the sampling capacitor C c and a transmission gate S4 are connected in sequence, the other end of the transmission gate S4 is connected to a reference voltage VREE, one end of the current source is connected to the input end of the voltage buffer, and the other end is grounded.

3. The circuit according to claim 2, characterized in that A transmission gate S5 in the output signal selection module is connected to the output end of the voltage buffer, and another transmission gate S6 is connected to the sampling capacitor C c One end connected to the transmission gate S4.

4. The circuit according to claim 3, characterized in that The dual sampling module uses a source follower method for readout, the current source is connected to the source end of the composite dielectric gate dual transistor photosensitive detector, the gate voltage and the drain voltage are fixed so that the detector is in the saturation region when reading, the source voltage and the threshold voltage show a linear relationship, and the threshold voltage is quantified by reading the source voltage, thereby obtaining the number of absorbed photons.

5. The circuit according to claim 4, characterized in that The source-drain connection switch S1 controls the connectivity between the source and drain ends of the photosensitive detector. For the detection unit that is not read, the source-drain connection switch is closed to make the potential of the source and drain ends the same, avoiding unnecessary current and switching the enable signal of the voltage buffer to the off state.

6. The circuit according to claim 5, characterized in that The reference voltage is determined according to the source terminal voltage of the detection unit in the read state and the ADC quantization range.

7. The circuit according to claim 6, characterized in that The circuit provides an on-chip double sampling working mode, using a capacitor to couple the difference of the sampling signals read twice to one end of the capacitor, and performs voltage raising to obtain a double sampling result; Sampling in the read state after exposure, the upper plate of the capacitor is the sampling signal, and the lower plate is connected to the reference voltage; The detection unit gate is connected to the reset voltage before reading. The lower board must be floated before reading. The voltage read the second time is the difference between the two sampling signals plus a reference voltage, obtaining the on-chip double sampling result.

8. The circuit according to claim 7, characterized in that The circuit provides an off-chip double sampling and single sampling working mode, directly outputs the output terminal voltage of the voltage buffer, the upper capacitor board is always connected to the output terminal of the voltage buffer, and the lower capacitor board is fixed to the reference voltage; the detection unit in the off-chip double sampling mode still undergoes the process of reset-exposure-readout-reset-readout, and the sampling results of the two reads are quantized by the analog-to-digital conversion circuit that converts the analog signal into a digital signal, and processed off-chip; The detection unit in single sampling mode goes through the states of reset-exposure-reading, quantifying the result of a single reading.

9. The circuit according to claim 8, characterized in that The source-drain connection switch S1 adopts a PMOS tube that transmits positive high voltage. When the circuit is applied to a single composite dielectric gate dual transistor photodetector for double sampling reading, the gate of the composite dielectric gate dual transistor photodetector is connected to a control signal, the source end of the source-drain connection switch S1 is connected to the drain end of the composite dielectric gate dual transistor, and the drain end of S1 is connected to the source end of the composite dielectric gate dual transistor.

10. The circuit according to claim 9, characterized in that When the circuit is applied to a composite dielectric gate dual transistor photosensitive detector array for double sampling reading, the control gates of the composite dielectric gate dual transistor photosensitive detectors in the same row of the array are interconnected to form a word line; the source electrodes of the detection units in the same column are interconnected to form a bit line; the drain electrodes of all the detection units are interconnected to form a total drain line, and the source end and the drain end of the source-drain connection switch S1 are respectively connected to the bit line and the drain line of the photosensitive detector array; The column readout method is adopted, and the multiplexing relationship between the bit line and the readout circuit is determined according to the size of the detection unit. Multiple bit lines are connected to the source end of the address selection tube, the drain end of the address selection tube is connected to the current source of the dual-adoption circuit and the input end of the voltage buffer, and the gate of the address selection tube is connected to the address selection signal of the bit line; For the readout of the array, the on-chip double sampling result of a row can be latched in the lower plate of the capacitor of the readout circuit, and the single sampling result can be latched in the upper plate of the capacitor; the quantization only needs to be completed before the detector of the next row enters the readout state, and the readout time is only limited by the charging time of the capacitor. Before the next row is read out, the capacitor does not need to be reset and recharged and discharged.

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