Digital-to-analog converter, analog-to-digital converter, chip and electronic device
By combining the low MOS pipe array and high C-2C capacitor arrays in DAC, the problem of large resistance array, high power consumption and capacitance loss, and achieve higher linearity, accuracy, and digital flexibility.
Patent Information
- Application Number
- CN202411419359.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-01-28
AI Technical Summary
Under the requirements of ultra-low power consumption, the existing hybrid capacitor-DAC has a large area and high power consumption, and the binary weighted capacitor array is prone to mismatch, affecting linear and precision performance, limiting the number of bits of the DAC.
The low-level MOS tube array and the high-level C-2C capacitor array are combined to form a new type of hybrid structure DAC to replace the resistance array to reduce the static current and area. Essence
Effectively reduce power consumption and area, improve the linear and accuracy of DAC, reduce capacitance loss, relieve the number of digits, and improve the overall performance.
Smart Images
Figure CN119382709A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a chip and an electronic device. Background Art
[0002] At present, the RF transceiver chip is responsible for the high-speed conversion between digital signals and analog signals of the fifth-generation mobile communication technology (5G) base station, and is called the "pearl" of the 5G base station. Among them, ADC and DAC are important parts of the RF transceiver chip.
[0003] In the related art, under a given unit capacitance, the total capacitance of the pure capacitor DAC is too large, resulting in a large chip area and high power consumption. Considering the above-mentioned disadvantages of the pure capacitor DAC, the current pure capacitor DAC is gradually replaced by the hybrid capacitor DAC. There are two common structures of the hybrid capacitor DAC, namely the hybrid capacitor-resistor DAC and the hybrid capacitor-metal-oxide-semiconductor (MOS) DAC.
[0004] However, under the requirement of ultra-low power consumption, the resistor array of the hybrid capacitor-resistor DAC may consume a large area, and the high-bit binary weighted capacitor array in the hybrid capacitor-MOS DAC has a large difference in the capacitance value of each capacitor when the number of input signal bits increases. Due to unavoidable process factors, the binary weighted capacitor array is prone to mismatch, and the linearity and accuracy performance of the DAC cannot be guaranteed. In addition, capacitor mismatch will limit the number of bits of the hybrid capacitor-MOS DAC when it is used. Summary of the invention
[0005] In order to solve the technical problems existing in the related art, the embodiments of the present application provide a digital-to-analog converter, an analog-to-digital converter, a chip and an electronic device.
[0006] To achieve the above purpose, the technical solution of the embodiment of the present application is implemented as follows:
[0007] In a first aspect, an embodiment of the present application provides a DAC, wherein the DAC comprises:
[0008] The first sub-DAC module includes a capacitor array of one or more bits, the capacitor array is a C-2C capacitor array, and the C-2C capacitor array includes a plurality of first capacitors and one or more bridge capacitors; the capacitance value of each first capacitor is C q The capacitance value of each bridge capacitor is 2C. q , the C q is the unit capacitance;
[0009] A second sub-DAC module, the second sub-DAC module includes a MOS transistor array of one or more bits and a second capacitor; the MOS transistor array is controlled by the second capacitor, and the bit of the MOS transistor array is lower than the bit of the C-2C capacitor array;
[0010] A connection switch is used to control the connection between the MOS tube array and the C-2C capacitor array by switching the connection switch.
[0011] In a second aspect, an embodiment of the present application further provides an analog-to-digital converter, which includes the digital-to-analog converter described in the embodiment of the present application.
[0012] In a third aspect, an embodiment of the present application further provides a chip, wherein the chip includes the digital-to-analog converter described in the embodiment of the present application, or includes the analog-to-digital converter described in the embodiment of the present application.
[0013] In a fourth aspect, an embodiment of the present application further provides an electronic device, which includes a device body and the chip described in the embodiment of the present application disposed in the device body.
[0014] The DAC, analog-to-digital converter, chip and electronic device provided in the embodiments of the present application include: a first sub-DAC module, the first sub-DAC module includes a capacitor array of one or more bits, the capacitor array is a C-2C capacitor array, the C-2C capacitor array includes a plurality of first capacitors and one or more bridge capacitors; the capacitance value of each first capacitor is C q The capacitance value of each bridge capacitor is 2C. q , the C qA unit capacitor; a second sub-DAC module, the second sub-DAC module includes a MOS tube array of one or more bits and a second capacitor; the MOS tube array is controlled by the second capacitor, and the bit of the MOS tube array is lower than the bit of the C-2C capacitor array; a connecting switch is used to control the connection between the MOS tube array and the C-2C capacitor array by switching the connecting switch. The scheme of the embodiment of the present application is adopted, and a new hybrid structure DAC is formed by combining a low-bit MOS tube array and a high-bit C-2C capacitor array, wherein the resistor array in the hybrid capacitor-resistor DAC is replaced by a MOS tube array. The use of a MOS tube array can reduce static current to reduce power consumption, and compared with the resistor array, the area consumed by the MOS tube array is also reduced, which can solve the problem of large resistor array area and high power consumption in the hybrid capacitor-resistor DAC; because the capacitor array of the new hybrid structure DAC adopts a C-2C capacitor array, and the capacitance value of each first capacitor in the C-2C capacitor array is C q , the capacitance value of each bridge capacitor is 2C q , avoiding the situation where the capacitance values of each capacitor differ greatly, improving the linearity and precision performance of the DAC, and reducing capacitor mismatch and improving the yield, thereby effectively solving the problem that capacitor mismatch will limit the number of bits of the hybrid capacitor-MOS DAC of the related technology when used. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 The structure of the DAC in the embodiment of the present application is shown as follows: Figure 1 ;
[0016] Figure 2 The structure of the DAC in the embodiment of the present application is shown as follows: Figure 2 ;
[0017] Figure 3 The structure of the DAC in the embodiment of the present application is shown as follows: Figure 3 ;
[0018] Figure 4 The structure of the DAC in the embodiment of the present application is shown as follows: Figure 4 ;
[0019] Figure 5 This is a structural schematic diagram of a 6-bit capacitor DAC array in a 9-bit novel hybrid capacitor-MOS type DAC according to an embodiment of the present application;
[0020] Figure 6 The structure of the ADC in the embodiment of the present application is shown as follows: Figure 1 ;
[0021] Figure 7 The structure of the ADC in the embodiment of the present application is shown as follows: Figure 2 . DETAILED DESCRIPTION
[0022] The present application will be further described in detail below with reference to the accompanying drawings and embodiments.
[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0024] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are described first. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.
[0025] DAC is a device that converts digital signals into analog signals and is widely used in RF transceiver chips.
[0026] ADC is a device that converts analog signals into digital signals and is widely used in RF transceiver chips.
[0027] Capacitive DAC is a parallel input charge proportional scaling DAC. Pure capacitive DAC (also called pure capacitive DAC) has the characteristics of high speed, high precision, high resolution and good linearity, which makes it advantageous in certain applications.
[0028] At present, the RF transceiver chip is responsible for the high-speed conversion between digital signals and analog signals of 5G base stations, and is called the "pearl" of 5G base stations. Among them, ADC and DAC are important parts of the RF transceiver chip.
[0029] In order to realize monotonic DAC, different types of pure capacitor DAC can be used. At present, there are two common structures of pure capacitor DAC. The first is binary weighted capacitor network DAC, which has a relatively simple structure and uses a small number of capacitors. However, when the number of input signal bits gradually increases, the capacitance value difference between the most significant bit (MSB) and the least significant bit (LSB) capacitor in the binary weighted capacitor network DAC is very large, resulting in mismatch between the MSB and LSB capacitors, and the linearity and precision performance of the entire binary weighted capacitor network DAC cannot be guaranteed. The second is the most widely used C-2C capacitor network DAC, which is a good improvement on the disadvantage of the large capacitance value difference of each capacitor in the binary weighted capacitor network DAC, and can achieve good capacitor matching regardless of the number of input signal bits. Since the number of capacitors increases linearly with the number of bits, the capacitor array area of the C-2C capacitor network DAC is smaller than that of the traditional binary weighted capacitor network DAC capacitor array, thereby achieving the purpose of high speed and low power consumption. However, under a given unit capacitance, the capacitance value of the total capacitor of the pure capacitor DAC will be too large, resulting in a large chip area and high power consumption.
[0030] Considering the above-mentioned disadvantages of pure capacitor DAC, the current pure capacitor DAC is gradually replaced by hybrid capacitor DAC. Among them, there are two common structures of hybrid capacitor DAC, namely hybrid capacitor-resistor DAC and hybrid capacitor-MOS DAC.
[0031] Specifically, a hybrid capacitor-resistor DAC is a common and effective method for achieving higher resolution by reducing the capacitance value and power consumption of the total capacitance in the DAC. However, under the requirement of ultra-low power consumption, the resistor array of the hybrid capacitor-resistor DAC may consume a large area. Generally, the low bits in the common hybrid capacitor-MOS DAC are MOS arrays, and the high bits are binary weighted capacitor arrays. Under the same conditions, when driving the same capacitor, the MOS array in the hybrid capacitor-MOS DAC has the advantage of lower static current than the resistor array in the hybrid capacitor-resistor DAC. In addition, in the sub-μA range, the MOS array is usually smaller in area than the resistor array. However, for the high-bit binary weighted capacitor array, when the number of input signal bits increases, the capacitance value difference of each capacitor is large. Due to inevitable process factors, the binary weighted capacitor array is not matched, and the linearity and precision performance of the DAC cannot be guaranteed. In addition, the capacitor mismatch will limit the number of bits of the hybrid capacitor-MOS DAC when it is used. Therefore, in order to improve the limitation of the number of bits of binary weighted capacitor arrays due to capacitor mismatch as the number of bits of the input signal increases, and to improve the problems of large area, high power consumption and low precision of common hybrid capacitor-MOS DACs, new methods or structures need to be explored to meet these challenges.
[0032] Based on this, an embodiment of the present application proposes a DAC. In various embodiments of the present application, a new hybrid structure DAC is formed by combining a low-order MOS tube array and a high-order C-2C capacitor array, wherein the resistor array in the hybrid capacitor-resistor DAC is replaced by a MOS tube array. The use of the MOS tube array can reduce the static current to reduce power consumption, and compared with the resistor array, the area consumed by the MOS tube array is also reduced, which can solve the problem of large resistor array area and high power consumption in the hybrid capacitor-resistor DAC. Since the capacitor array of the new hybrid structure DAC adopts a C-2C capacitor array, and the capacitance value of each first capacitor in the C-2C capacitor array is C q , the capacitance value of each bridge capacitor is 2C q , avoiding the situation where the capacitance values of each capacitor differ greatly, improving the linearity and precision performance of the DAC, and reducing capacitor mismatch and improving the yield, thereby effectively solving the problem that capacitor mismatch will limit the number of bits of the hybrid capacitor-MOS DAC of the related technology when used.
[0033] The embodiment of the present application provides a DAC, Figure 1 The structure of the DAC in the embodiment of the present application is shown as follows: Figure 1 ,like Figure 1 As shown, the DAC includes:
[0034] The first sub-DAC module 11 includes a capacitor array of one or more bits, the capacitor array is a C-2C capacitor array 14, and the C-2C capacitor array 14 includes a plurality of first capacitors 15 and one or more bridge capacitors 16; the capacitance value of each first capacitor 15 is C q The capacitance value of each bridge capacitor 16 is 2C. q , the C q is the unit capacitance;
[0035] A second sub-DAC module 12, the second sub-DAC module 12 includes a MOS transistor array 17 of one or more bits and a second capacitor 18; the MOS transistor array 17 is controlled by the second capacitor 18, and the bit of the MOS transistor array 17 is lower than the bit of the C-2C capacitor array 14;
[0036] The connection switch 13 is used to control the connection between the MOS tube array 17 and the C-2C capacitor array 14 by switching the connection switch 13 .
[0037] In the embodiment of the present application, the first sub-DAC module 11 is a high-order sub-DAC module, and specifically, may include a capacitor array of one or more bits, and the capacitor array is a C-2C capacitor array 14, that is, the high-order sub-DAC module is actually a C-2C capacitor DAC array module.
[0038] Here, the C-2C capacitor array 14 includes a plurality of first capacitors 15 and one or more bridging capacitors 16, wherein the number of the first capacitors 15 is 1 more than the number of the bridging capacitors 16. Exemplarily, assuming that the C-2C capacitor array 14 includes k first capacitors 15, the number of bridging capacitors 16 in the C-2C capacitor array 14 is k-1, wherein k is a positive integer greater than 1. The first capacitor can be understood as a capacitor located at a high position, i.e., a high-position capacitor.
[0039] It should be noted that the capacitance value of each of the first capacitors 15 is C q The capacitance value of each bridge capacitor 16 is 2C. q , the C q is the unit capacitance, that is, C q is the unit capacitance given in the first sub-DAC module. In this way, by setting the capacitance value of each first capacitor in the C-2C capacitor array in the novel hybrid structure DAC to be C q The capacitance value of each bridge capacitor 16 is 2C. q, avoiding the situation where the capacitance values of each capacitor differ greatly, improving the linearity and precision performance of the DAC, and reducing capacitor mismatch and improving the yield, thereby effectively solving the problem that capacitor mismatch will limit the number of bits of the hybrid capacitor-MOS DAC of the related technology when used.
[0040] In the embodiment of the present application, the second sub-DAC module 12 is a low-position sub-DAC module, specifically, it can include one or more bit MOS tube arrays 17 and a second capacitor 18, that is, the low-position sub-DAC module is actually a MOSDAC array module. The second capacitor can be understood as a capacitor located at a low position, that is, a low-position capacitor.
[0041] Here, by setting the low bits in the new hybrid structure DAC to be MOS tube arrays, the use of MOS tube arrays can reduce static current to reduce power consumption, and compared with the resistor array in the traditional hybrid capacitor-resistor DAC, the area consumed by the MOS tube array is also reduced, which can solve the problem of large resistor array area and high power consumption in the hybrid capacitor-resistor DAC. In addition, the MOS tube array only needs to be controlled by a second capacitor 18, and the control structure is relatively simple, which reduces the control cost of the MOS tube array.
[0042] Here, the number of MOS tubes corresponding to the second capacitor 18 is 2 m Wherein, m is a positive integer greater than or equal to 1.
[0043] In the embodiment of the present application, the capacitance value of the second capacitor 18 is C p , the C p is the unit capacitance, and the C p With the C q are equal in size, that is, C p is the unit capacitance given in the second sub-DAC module; that is, C p With C q Although the meanings are slightly different, the numerical values of the two are equal.
[0044] In the embodiment of the present application, one end of the connection switch 13 is connected to the common mode voltage, and the other end of the connection switch 13 is connected to one end of the second capacitor 18 .
[0045] In one embodiment, the first sub-DAC module 11 further includes a plurality of first-type switches, wherein the first-type switches represent control switches associated with the C-2C capacitor array 14;
[0046] Among them, the number of the first type switches matches the number of the first capacitors 15 in the C-2C capacitor array 14, and one end of each of the first type switches is connected to one end of the corresponding first capacitor 15, and the other end of each of the first type switches is respectively connected to the common mode voltage, the reference voltage, and the ground.
[0047] In one embodiment, one end of each of the first capacitors 15 is connected to one end of the corresponding first-type switch, and the other end of each of the first capacitors 15 is connected to one end of the corresponding bridge capacitor 16 .
[0048] In one embodiment, the first sub-DAC module 11 further includes a capacitor switch, and the C-2C capacitor array 14 further includes a redundant capacitor;
[0049] One end of the redundant capacitor is connected to one end of the capacitor switch, and the other end of the redundant capacitor is connected to one end of the corresponding bridge capacitor 16 and one end of the corresponding first capacitor 15 respectively.
[0050] In one embodiment, the second sub-DAC module 12 further includes a plurality of second-type switches, wherein the second-type switches represent control switches associated with the MOS transistor array 17;
[0051] One end of the second capacitor 18 is connected to one end of the connection switch 13 and one end of each of the second-type switches, and the other end of the second capacitor 18 is connected to the original output voltage.
[0052] Here, the MOS transistor array 17 includes a plurality of MOS transistors, each of which includes a gate, a drain and a source, and the second sub-DAC module further includes a bootstrap switch;
[0053] The gate and drain of the MOS tube of the lowest bit are connected, and one end of the connected end is connected to one end of the corresponding second type switch; the source of the MOS tube of the lowest bit is respectively connected to one end of the bootstrap switch and one end of the corresponding second type switch;
[0054] The gate and drain of the MOS tube of the highest bit are connected, and one end of the connected ends is connected to the reference voltage; the source of the MOS tube of the highest bit is connected to one end of the corresponding second type switch;
[0055] The gate and drain of the other MOS tubes are connected, and one end of the connected end is connected to one end of the corresponding second type switch; the source of the other MOS tube is connected to one end of another corresponding second type switch; the other MOS tube represents the MOS tube other than the MOS tube with the lowest bit and the MOS tube with the highest bit among the multiple MOS tubes.
[0056] Here, one end of the bootstrap switch is connected to the source of the MOS tube of the lowest bit, and the other end of the bootstrap switch is connected to the ground.
[0057] The DAC proposed in the embodiment of the present application is a novel hybrid capacitor-MOS type DAC. The overall structure of the novel hybrid capacitor-MOS type DAC is described below.
[0058] Figure 2 The structure of the DAC in the embodiment of the present application is shown as follows: Figure 2 ,like Figure 2 As shown, the DAC includes: a kbit capacitor DAC array (corresponding to the aforementioned capacitor array) and an mbit MOS DAC array (corresponding to the aforementioned MOS tube array), wherein k is a positive integer greater than 1, m is a positive integer greater than or equal to 1, and n=k+m, where n is the number of bits of the entire new hybrid capacitor-MOS type DAC.
[0059] Here, the capacitor DAC array is a C-2C capacitor array. Specifically, the capacitor DAC array includes k first capacitors C L1 , C L2 , C L3 ,......,C Lk , 1 redundant capacitor C d , k-1 bridge capacitors C S1 , C S2 , C S3 ,......,C S(k-1) ; Wherein, each first capacitor C L1 , C L2 , C L3 ,......,C Lk The capacitance value is C q , each bridge capacitor C S1 , C S2 , C S3 ,......,C S(k-1) The capacitance value is 2C q , redundant capacitor C d The capacitance value is 0.5C q , where C q is the unit capacitance.
[0060] Here, the mbit MOS DAC array consists of 2 m MOS tubes M1, M2, ..., Each MOS tube includes a gate, a drain and a source. m The MOS tube is controlled by a second capacitor C1, wherein the capacitance value of the second capacitor C1 is C p , C pis the unit capacitance, and C p =C q .
[0061] Here, 2 m MOS tubes M1, M2, ..., Respectively by 2 m Low-order MOS array sub-DAC reset switches (corresponding to the second type of switches mentioned above) S1, S2, ..., Control, wherein each MOS tube M1, M2, ..., The gate and drain are connected.
[0062] exist Figure 2 Based on the overall structural block diagram of the novel hybrid capacitor-MOS type DAC shown, the embodiment of the present application also provides a detailed structural block diagram of the novel hybrid capacitor-MOS type DAC.
[0063] For example, Figure 3 The structure of the DAC in the embodiment of the present application is shown as follows: Figure 3 ,like Figure 3 As shown, the DAC includes: a kbit high-bit capacitance sub-DAC (corresponding to the aforementioned first sub-DAC module) and an mbit low-bit MOS sub-DAC (corresponding to the aforementioned second sub-DAC module), wherein the kbit high-bit capacitance sub-DAC includes a kbit capacitance DAC array (corresponding to the aforementioned capacitance array), and the mbit low-bit MOS sub-DAC includes an mbit MOS DAC array (corresponding to the aforementioned MOS tube array), wherein k is a positive integer greater than 1, and m is a positive integer greater than or equal to 1.
[0064] Here, the kbit high-bit capacitor sub-DAC is a high-bit sub-DAC module, and the kbit capacitor DAC array is a C-2C capacitor DAC array.
[0065] Furthermore, the high-position sub-DAC module includes: k first capacitors C L1 , C L2 , C L3 ,......,C Lk , 1 redundant capacitor C d , k-1 bridge capacitors C S1 , C S2 , C S3 ,......,C S(k-1) , k first-class switches S L1 , S L2 , S L3 ,......,S Lk , capacitor switch S d2 , where each first capacitor C L1 , CL2 , C L3 ,......,C Lk The capacitance value is C q , each bridge capacitor C S1 , C S2 , C S3 ,......,C S(k-1) The capacitance value is 2C q , redundant capacitor C d The capacitance value is 0.5C q , where C q is the unit capacitance.
[0066] In the embodiment of the present application, the first capacitor C L1 One end of the switch S L1 One end of the first capacitor C L1 The other end is connected to the bridge capacitor C S1 , Redundant capacitor C d One end of the connection;
[0067] The first capacitor C L2 One end of the switch S L2 One end of the first capacitor C L2 The other end is connected to the bridge capacitor C S1 , C S2 One end of the connection;
[0068] The first capacitor C L3 One end of the switch S L3 One end of the first capacitor C L3 The other end is connected to the bridge capacitor C S2 , C S3 One end of the connection; ............
[0070] The first capacitor C Lk One end of the switch S Lk One end of the first capacitor C Lk The other end of the bridge capacitor C S(k-1) one end of the .
[0071] Redundant capacitor C d One end of the capacitor switch S d2 One end of the redundant capacitor C d The other end is connected to the bridge capacitor C S1 , the first capacitor C L1 one end of the .
[0072] Bridge capacitor C S1 One end of each capacitor C L1 , Redundant capacitor Cd One end of the bridge capacitor C S1 The other end of the first capacitor C L2 One end of the connection;
[0073] Bridge capacitor C S2 One end of the first capacitor C L2 One end of the bridge capacitor C S2 The other end of the first capacitor C L3 One end of the connection; ............
[0075] Bridge capacitor C S(k-1) One end of the first capacitor C Lk One end of the bridge capacitor C S(k-1) The other end of the first capacitor C L(k-1) one end of the .
[0076] Switch S L1 One end of the first capacitor C L1 One end of the switch S L1 The other end is connected to the common mode voltage (V CM )、reference voltage (V R ), ground terminal (GND) connection;
[0077] Switch S L2 One end of the first capacitor C L2 One end of the switch S L2 The other end is connected to V CM 、V R , GND connection;
[0078] Switch S L3 One end of the first capacitor C L3 One end of the switch S L3 The other end is connected to V CM 、V R , GND connection; ............
[0080] Switch S Lk One end of the first capacitor C Lk One end of the switch S Lk The other end is connected to V CM 、V R , GND connection.
[0081] Here, the mbit low-bit MOS sub-DAC is a low-bit sub-DAC module, that is, a MOS DAC array module.
[0082] Furthermore, the low-level sub-DAC module includes: a second capacitor C1, MOS tubes M1, M2, ..., 2 m Low-order MOS array sub-DAC reset switches (corresponding to the second type of switches mentioned above) S1, S2, ..., Connection switch S d1 , bootstrap switch S q .
[0083] One end of the second capacitor C1 is connected to the switch S d1 And reset switches S1, S2, ..., The other end of the second capacitor C1 is connected to the original output voltage (V out )connect.
[0084] The gate and drain of the MOS tube M1 are connected, and one end of the connected end is connected to one end of the reset switch S2. The source of the MOS tube M1 is connected to the reset switch S1 and the bootstrap switch S2 respectively. q One end of the connection;
[0085] The gate and drain of the MOS tube M2 are connected, and one end of the connected end is connected to one end of the reset switch S3, and the source of the MOS tube M2 is connected to one end of the reset switch S2; ............
[0087] MOS tube The gate and drain of the One end of the MOS tube is connected Source and reset switches One end of the connection;
[0088] MOS tube The gate and drain of the R Connection, MOS tube Source and reset switches one end of the .
[0089] One end of the reset switch S1 is connected to the source of the MOS tube M1 and the bootstrap switch S q One end of the reset switch S1 is connected to one end of the second capacitor C1; the other end of the reset switch S1 is connected to one end of the second capacitor C1;
[0090] One end of the reset switch S2 is connected to the source of the MOS tube M2 and one end of the gate and drain of the MOS tube M1, respectively, and the other end of the reset switch S2 is connected to one end of the second capacitor C1; ............
[0092] Reset switch One end of each MOS tube The source and MOS tube The gate and drain terminals are connected to reset the switch The other end is connected to one end of the second capacitor C1;
[0093] Reset switch One end of each MOS tube The source and MOS tube The gate and drain terminals are connected to reset the switch The other end of is connected to one end of the second capacitor C1.
[0094] Connection switch S d1 One end of the CM Connect, connect switch S d1 The other end of is connected to one end of the second capacitor C1.
[0095] Bootstrap switch S q One end of the bootstrap switch S is connected to the source of the MOS tube M1. q The other end is connected to GND.
[0096] exist Figure 3 Based on the structure of the DAC shown, for example, assuming that k is 6 and m is 3, the number of bits of the novel hybrid capacitor-MOS DAC is n=k+m=6+3=9. Figure 4 The structure of the DAC in the embodiment of the present application is shown as follows: Figure 4 ,like Figure 4 As shown, the DAC is a 9-bit new hybrid capacitor-MOS type DAC, which includes: a 6-bit high-bit capacitor sub-DAC (corresponding to the aforementioned first sub-DAC module) and a 3-bit low-bit MOS sub-DAC (corresponding to the aforementioned second sub-DAC module), wherein the 6-bit high-bit capacitor sub-DAC includes a 6-bit capacitor DAC array (corresponding to the aforementioned capacitor array), and the 3-bit low-bit MOS sub-DAC includes a 3-bit MOS DAC array (corresponding to the aforementioned MOS tube array). For the components of the 6-bit high-bit capacitor sub-DAC and the 3-bit low-bit MOS sub-DAC, as well as the connection relationship between the components, please refer to Figure 3 The structure of the DAC shown in the figure can be understood and will not be repeated here.
[0097] In the embodiment of the present application, the weight values of the node voltages corresponding to the first capacitors in the C-2C capacitor array are not equal;
[0098] Among them, the weight value of the node voltage corresponding to each first capacitor is determined based on the ratio of the incremental output voltage to the incremental voltage of the corresponding first capacitor; the incremental output voltage represents the difference between the output voltage generated after the charge redistribution of the DAC and the original output voltage.
[0099] exist Figure 4 The structure of the DAC shown is based on Figure 5 Schematic diagram of the structure of a 6-bit capacitor DAC array (i.e., a C-2C capacitor array) in a 9-bit novel hybrid capacitor-MOS type DAC according to an embodiment of the present application. Figure 5 As shown, the 6-bit C-2C capacitor array includes 6 first capacitors C L1 , C L2 , C L3 , C L4 , C L5 , C L6 , 1 redundant capacitor C d , 5 bridge capacitors C S1 , C S2 , C S3 , C S4 , C S5 ; Wherein, each first capacitor C L1 , C L2 , C L3 , C L4 , C L5 , C L6 The capacitance value is C q , each bridge capacitor C S1 , C S2 , C S3 , C S4 , C S5 The capacitance value is 2C q , redundant capacitor C d The capacitance value is 0.5C q , where C q is the unit capacitance.
[0100] Combine the following Figure 5 The structure of the 6-bit C-2C capacitor array shown in FIG. 1 illustrates the weight value of the node voltage corresponding to each first capacitor in the C-2C capacitor array.
[0101] Next, we will verify the weight distribution of the node voltage corresponding to the first capacitor of the C-2C capacitor array structure under ideal conditions. Considering the charge conservation of sampling and quantization, before the first bit quantization, the initial output voltage of the six nodes of the upper plate is V 01 ~V 06 According to the law of conservation of current and voltage, the following formula can be obtained:
[0102] ①(In 01 -V 02 )*2*C q +V 01 *2*C q =V cm *2*C q
[0103] ②(In 02 -V 03 )*2*C q +(V 02 -V 01 )*2*C q +V 02 *C q =V cm *C q
[0104] ③(In 03 -V 04 )*2*C q +(V 03 -V 02 )*2*C q +V 03 *C q =V cm *C q
[0105] ④(In 04 -V 05 )*2*C q +(V 04 -V 03 )*2*C q +V 04 *C q =V cm *C q
[0106] ⑤(In 05 -V 06 )*2*C q +(V 05 -V 04 )*2*C q +V 05 *C q =V cm *C q
[0107] ⑥(In 06 -V 05 )*2*C q +V 06 *C q =(V cm -V in )*Cq
[0108] Solving the above formulas in sequence yields:
[0109] ①
[0110] ②
[0111] ③
[0112] ④
[0113] ⑤
[0114] ⑥
[0115] After calculating the initial state of the C-2C capacitor array, it is necessary to further calculate the weight of the node voltage corresponding to each first capacitor, and introduce an incremental voltage △V to this capacitor through the lower plate switch of the capacitor. Then, the output voltage V of the DAC after charge redistribution is out An incremental output voltage △V will also be generated accordingly out , △V out The ratio of ΔV is the weight value of the node voltage corresponding to this capacitor. Taking the weight of the highest bit MSB as an example, the upper plate voltage after the increment is calculated:
[0116] ①(V1-V2)*2*C q +V1*C q +(V1-△V)*C q =(V 01 -V 02 )*2*C q +V 01 *2*C q
[0117] ②(V2-V3)*2*C q +(V2-V1)*2*C q +V2*C q =(V 02 -V 03 )*2*C q +(V 02 -V 01 )*2*C q +V 02 *C q
[0118] ③(V3-V4)*2*C q +(V3-V2)*2*C q +V3*Cq =(V 03 -V 04 )*2*C q +(V 03 -V 02 )*2*C q +V 03 *C q
[0119] ④(V4-V5)*2*C q +(V4-V3)*2*C q +V4*C q =(V 04 -V 05 )*2*C q +(V 04 -V 03 )*2*C q +V 04 *C q
[0120] ⑤(V5-V6)*2*C q +(V5-V4)*2*C q +V5*C q =(V5-V 06 )*2*C q +(V 05 -V 04 )*2*C q +V 05 *C q
[0121] ⑥V out *C q +(V out -V5)*2*C q =(V 06 -V 05 )*2*C q +V 06 *C q
[0122] By calculation, we can get the weight of the node voltage corresponding to the lowest capacitance in the upper 6 bits as △V out The differential value of △V, that is:
[0123]
[0124] The weights of the node voltages corresponding to the capacitances from low to high in the C-2C capacitor array are:
[0125]
[0126] The embodiment of the present application forms a new hybrid structure DAC by combining a low m-bit MOS tube DAC array and a high k-bit C-2C capacitor DAC array; the new hybrid structure DAC replaces the resistor array in the hybrid capacitor-resistor DAC of the related art with a MOS tube array. The use of the MOS tube array can reduce the static current to reduce power consumption, and compared with the resistor array, the area consumed by the MOS tube array is also reduced, which can solve the problems of large resistor array area and high power consumption in the hybrid capacitor-resistor DAC; and the capacitor array of the hybrid capacitor-MOS DAC of the related art is a binary weighted capacitor array. When the number of bits of the DAC input signal increases, the capacitance difference of each capacitor becomes larger, and a capacitor mismatch phenomenon occurs. To address this problem, the capacitor array of the new hybrid structure DAC of the embodiment of the present application adopts a C-2C capacitor array, and the capacitance value of each first capacitor in the C-2C capacitor array is C q , the capacitance value of each bridge capacitor is 2C q , effectively solving the problem of capacitor mismatch, thereby improving the accuracy of DAC. Since the problem of capacitor mismatch will limit the number of bits of DAC during use, the bit limit of the new hybrid structure DAC in the embodiment of the present application becomes smaller.
[0127] In summary, the embodiments of the present application not only effectively solve the problems of large resistor array area and high power consumption in the hybrid capacitor-resistor DAC in the related art, but also effectively solve the problems of low precision and limited number of capacitor DAC bits in the hybrid capacitor-MOS DAC in the related art.
[0128] In an exemplary embodiment, the embodiment of the present application further provides an analog-to-digital converter (ADC), and the analog-to-digital converter includes the digital-to-analog converter (DAC) described in the embodiment of the present application. That is to say, the new hybrid structure DAC proposed in the embodiment of the present application can be applied to the ADC. For example, the ADC can be a successive approximation analog-to-digital converter (SAR ADC, Successive Approximation Register Analog to Digital Converter). Of course, the ADC can also be other types of ADC structures, which are not limited in the embodiment of the present application.
[0129] The structure of the ADC is described below by taking the application of the novel hybrid structure DAC proposed in the embodiment of the present application in the SAR ADC as an example.
[0130] Figure 6 The structure of the ADC in the embodiment of the present application is shown as follows: Figure 1 ,like Figure 6As shown, the ADC is a single-ended input SAR ADC. The single-ended input SAR ADC here can be understood as having only one DAC in the input comparator, that is, the single-ended input SAR ADC is an ADC with a single-ended input DAC, wherein the DAC of the input comparator is a new hybrid structure DAC proposed in the embodiment of the present application. Figure 6 For the new hybrid structure DAC in Figure 3 The structure of the DAC shown in the figure can be understood and will not be repeated here.
[0131] In the embodiment of the present application, the single-ended input SAR ADC includes: two sample-and-hold circuits S / H1 and S / H2, two start switches S qd1 and S qd2 , a new hybrid capacitor-MOS type DAC, a comparator (COMP), a logic controller (such as a logic module SAR register) and a synchronous timing generator. The synchronous timing generator is used to provide a clock signal (CLK) to the comparator; the comparator has two input terminals, namely a positive input terminal and a negative input terminal.
[0132] Here, one end of the sample-and-hold circuit S / H1 is connected to V in+ (positive phase voltage input terminal), the other end of the sampling and holding circuit S / H1 is connected to the start switch S qd1 Connect one end of the sample-and-hold circuit S / H2 to V in- (inverting voltage input terminal), the other end of the sampling and holding circuit S / H2 is connected to the start switch S qd2 Connection: The output of the new hybrid capacitor-MOS DAC is connected to the positive input of COMP, and the negative input of COMP is connected to the common mode voltage V CM2 ; Under the control of the clock signal, COMP is used to convert the output voltage V of the new hybrid capacitor-MOS DAC DAC With the common mode voltage V CM2 The SAR register is connected to the output terminal of COMP, and the SAR register is used to control the output voltage V of the new hybrid capacitor-MOS type DAC according to the comparison result. DAC With common mode voltage V CM2 approach each other successively until the set conditions are met, that is, the comparison result V generated by COMP COMP It is used to control the SAR register through the control of each switch in the new hybrid capacitor-MOS type DAC so that the output voltage V DAC Successive approximation common mode voltage V CM2, until n quantizations are completed to obtain n-bit digital output code values, where n is the number of bits of the entire new hybrid capacitor-MOS type DAC, and n=k+m, k is the number of bits of the capacitor DAC array, and m is the number of bits of the MOS DAC array. The MOS DAC array includes 2 m MOS tubes, k is a positive integer greater than 1, and m is a positive integer greater than or equal to 1.
[0133] Figure 7 The structure of the ADC in the embodiment of the present application is shown as follows: Figure 2 ,like Figure 7 As shown, the ADC is a fully differential input SAR ADC. The fully differential input SAR ADC here can be understood as having two DACs in the input comparator, that is, the fully differential input SAR ADC is an ADC with a dual-ended input DAC, wherein the DAC of the input comparator is a new hybrid structure DAC proposed in the embodiment of the present application. Figure 7 For the new hybrid structure DAC in Figure 3 The structure of the DAC shown in the figure can be understood and will not be repeated here.
[0134] In the embodiment of the present application, the fully differential input SAR ADC includes: two sample-and-hold circuits S / H1 and S / H2, two start switches S qd1 and S qd2 , two new hybrid capacitor-MOS type DACs, COMP, a logic controller (such as a logic module SAR register) and a synchronous timing generator. The synchronous timing generator is used to provide CLK to the comparator; the comparator has two input terminals, namely a positive input terminal and a negative input terminal.
[0135] Here, one end of the sample-and-hold circuit S / H1 is connected to V in+ (positive phase voltage input terminal), the other end of the sampling and holding circuit S / H1 is connected to the start switch S qd1 Connect one end of the sample-and-hold circuit S / H2 to V in- (inverting voltage input terminal), the other end of the sampling and holding circuit S / H2 is connected to the start switch S qd2 Connection. In sampling mode, the sample-and-hold amplifier (SHA) samples the signal; it keeps the signal constant during the hold mode. The timing is adjusted so that the ADC encoder at the subsequent stage converts the analog signal to a digital signal during the hold time. Since the signal is almost unchanged in the hold mode, the ADC can process fast-changing high-frequency signals. The upper frequency limit is not determined by the ADC encoder, but by the aperture jitter, bandwidth, and distortion performance of the SHA.
[0136] Here, the outputs of the two new hybrid capacitor-MOS DACs are connected to the positive and negative inputs of COMP respectively; under the control of the clock signal, COMP is used to convert the voltage V DAC+ and the voltage at the inverting input V DAC- Compare and get the comparison result; the SAR register is connected to the output of COMP, and the SAR register is used to control the voltage V of the non-inverting input terminal according to the comparison result. DAC+ The voltage at the inverting input V DAC- approach each other successively until the set conditions are met, that is, the comparison result V generated by COMP COMP The SAR register controls the switches in the two novel hybrid capacitor-MOS type DACs during the quantization process, so that the output voltages of the two novel hybrid capacitor-MOS type DACs are close to each other successively, until n quantizations are completed to obtain an n-bit digital output code value, wherein n is the number of bits of the entire novel hybrid capacitor-MOS type DAC, and n=k+m, k is the number of bits of the capacitor DAC array, m is the number of bits of the MOS DAC array, and the MOS DAC array includes 2 m MOS tubes, k is a positive integer greater than 1, and m is a positive integer greater than or equal to 1.
[0137] The novel hybrid structure DAC proposed in the embodiment of the present application, which is formed by combining a low-m-bit MOS tube DAC array and a high-k-bit C-2C capacitor DAC array, can be applied to ADC (such as SAR ADC). When used in the ADC, the adaptation of the capacitor array will be reduced, so the linearity of the ADC is significantly improved, thereby increasing the conversion accuracy between digital signals and analog signals; since the power consumption of the capacitor array is reduced, the power consumption of the overall ADC will also be reduced, and the area will be reduced.
[0138] The embodiment of the present application proposes a novel hybrid capacitor-MOS DAC, in which the low bits are MOS tube arrays and the high bits are C-2C capacitor arrays; since the capacitor array of the novel hybrid capacitor-MOS DAC adopts a C-2C capacitor array, the situation that the capacitance values of each capacitor differ greatly when the number of bits of the input signal increases is avoided, the accuracy and linearity are improved, and the capacitor mismatch can be reduced, the yield is improved, and the limitation of the number of bits of the binary weighted capacitor array is solved; the novel hybrid capacitor-MOS DAC adopts a MOS tube array for low bit control, and the use of the MOS tube array can reduce the static current to reduce power consumption, and compared with the resistor array, the area consumed by the MOS tube array is also reduced; the novel hybrid capacitor-MOS DAC can be used in an ADC (such as a SAR ADC), and when used in the ADC, the adaptation of the capacitor array will be reduced, so the linearity of the ADC is significantly improved, thereby increasing the conversion accuracy between digital signals and analog signals; since the power consumption of the capacitor array is reduced, the power consumption of the overall ADC will also be reduced, and the area will be reduced; the novel hybrid capacitor-MOS DAC and the use of the novel hybrid capacitor-MOS The ADC of DAC can be used in transceiver chips such as RF transceiver chips, which will increase the conversion accuracy of high-speed conversion between 5G base station digital signals and analog signals, reduce power consumption, and reduce area.
[0139] In an exemplary embodiment, the embodiment of the present application further provides a chip, wherein the chip includes the digital-to-analog converter described in the embodiment of the present application, or includes the analog-to-digital converter described in the embodiment of the present application.
[0140] In an exemplary embodiment, the embodiment of the present application further provides an electronic device, which includes a device body and the chip described in the embodiment of the present application disposed in the device body.
[0141] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0142] In addition, the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.
[0143] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A digital-to-analog converter DAC, characterized in that: The DAC comprises: The first sub-DAC module includes a capacitor array of one or more bits, the capacitor array is a C-2C capacitor array, and the C-2C capacitor array includes a plurality of first capacitors and one or more bridge capacitors; the capacitance value of each first capacitor is C q The capacitance value of each bridge capacitor is 2C. q , the C q is the unit capacitance; A second sub-DAC module, the second sub-DAC module includes a metal-oxide-semiconductor MOS transistor array of one or more bits and a second capacitor; the MOS transistor array is controlled by the second capacitor, and the bit of the MOS transistor array is lower than the bit of the C-2C capacitor array; A connection switch is used to control the connection between the MOS tube array and the C-2C capacitor array by switching the connection switch.
2. The DAC according to claim 1, characterized in that The first sub-DAC module further includes a plurality of first-type switches, the first-type switches representing control switches associated with the C-2C capacitor array; Among them, the number of the first type switches matches the number of first capacitors in the C-2C capacitor array, and one end of each of the first type switches is connected to one end of the corresponding first capacitor, and the other end of each of the first type switches is respectively connected to the common mode voltage, the reference voltage, and the ground.
3. The DAC according to claim 2, characterized in that The number of the first capacitors is one more than the number of the bridging capacitors; One end of each of the first capacitors is connected to one end of the corresponding first-type switch, and the other end of each of the first capacitors is connected to one end of the corresponding bridge capacitor.
4. The DAC according to claim 1, wherein: The first sub-DAC module further includes a capacitor switch, and the C-2C capacitor array further includes a redundant capacitor; One end of the redundant capacitor is connected to one end of the capacitor switch, and the other end of the redundant capacitor is respectively connected to one end of the corresponding bridge capacitor and one end of the corresponding first capacitor.
5. The DAC according to claim 1, wherein: The second sub-DAC module further includes a plurality of second-type switches, wherein the second-type switches represent control switches associated with the MOS tube array; One end of the second capacitor is connected to one end of the connection switch and one end of each of the second-type switches, and the other end of the second capacitor is connected to the original output voltage.
6. The DAC according to claim 5, characterized in that The MOS transistor array includes a plurality of MOS transistors, each of the MOS transistors includes a gate, a drain and a source, and the second sub-DAC module also includes a bootstrap switch; The gate and drain of the MOS tube of the lowest bit are connected, and one end of the connected end is connected to one end of the corresponding second type switch; the source of the MOS tube of the lowest bit is respectively connected to one end of the bootstrap switch and one end of the corresponding second type switch; The gate and drain of the MOS tube of the highest bit are connected, and one end of the connected ends is connected to the reference voltage; the source of the MOS tube of the highest bit is connected to one end of the corresponding second type switch; The gate and drain of the other MOS tubes are connected, and one end of the connected end is connected to one end of the corresponding second type switch; the source of the other MOS tube is connected to one end of another corresponding second type switch; the other MOS tube represents the MOS tube other than the MOS tube with the lowest bit and the MOS tube with the highest bit among the multiple MOS tubes.
7. The DAC according to claim 6, characterized in that One end of the bootstrap switch is connected to the source of the MOS tube of the lowest bit, and the other end of the bootstrap switch is connected to the ground.
8. The DAC according to claim 1, wherein: One end of the connection switch is connected to the common mode voltage, and the other end of the connection switch is connected to one end of the second capacitor.
9. The DAC according to claim 1, wherein: The capacitance value of the second capacitor is C p , the C p is the unit capacitance, and the C p With the C q are equal in size.
10. The DAC according to claim 1, wherein: The number of MOS tubes corresponding to the second capacitor is 2 m Wherein, m is a positive integer greater than or equal to 1.
11. The DAC according to claim 1, wherein: The weight values of the node voltages corresponding to the first capacitors in the C-2C capacitor array are not equal; Among them, the weight value of the node voltage corresponding to each first capacitor is determined based on the ratio of the incremental output voltage to the incremental voltage of the corresponding first capacitor; the incremental output voltage represents the difference between the output voltage generated after the charge redistribution of the DAC and the original output voltage.
12. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises the digital-to-analog converter according to any one of claims 1 to 11.
13. A chip, characterized in that: The chip includes the digital-to-analog converter according to any one of claims 1 to 11, or includes the analog-to-digital converter according to claim 12.
14. An electronic device, characterized in that: The electronic device includes a device body, and the chip according to claim 13 disposed in the device body.