Bit interleaving method and device, bit interleaver and storage medium

Abstract

The embodiment of the invention provides a bit interleaving method and device, a bit interleaver and a storage medium, and relates to the technical field of data processing, and the method comprises the steps: determining a parallel bit width and a modulation order; writing to-be-processed data into a cache space in a memory; starting from the initial address of the cache space, reading a bit group with the length equal to the parallel bit width from the cache space for multiple rounds, and performing each next reading on the address obtained by adding the preset address offset to the current read address until the last line in the cache space is read to complete one round of reading, the preset address offset is the length of a row of data in the cache space, and the data row number in the cache space is a modulation order; the next round of reading is carried out on the initial address of the data which are not read in the first row of the cache space until all the data are read; and performing intra-byte interleaving processing on the read bit group to obtain a bit interleaving result. By applying the scheme provided by the embodiment of the invention, the waste of cache space can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a bit interleaving method, device, bit interleaver and storage medium. Background Art

[0002] Compared with Turbo code, LDPC (Low Density Parity Check code) can achieve lower decoding delay and higher throughput, and can be applied to the channel coding process of 5G (5th Generation Mobile Communication Technology) NR (New Radio) shared channels.

[0003] During data transmission, some subcarriers or OFDM (Orthogonal Frequency Division Multiplexing) symbols may experience deep fading in some cases, resulting in more serious codeword burst errors during LDPC channel coding. Bit interleaving, as a key part of the LDPC channel coding process, can diffuse the burst errors that occur in the channel into the entire codeword, so that the receiving end decoder will treat the diffused burst errors (bit errors) as random errors, effectively eliminating burst errors and effectively combating deep fading.

[0004] In the related art, in order to improve data processing efficiency, bit interleaving is usually performed in parallel. Specifically, the data to be processed needs to be stored in the storage space of different memories respectively, and the data is read from different memories respectively to perform bit interleaving. However, since multiple memories need to be used to store multiple copies of the same data to be processed, a large amount of memory cache space is wasted. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a bit interleaving method, device, bit interleaver and storage medium to reduce the waste of cache space. The specific technical solution is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a bit interleaving method, which is applied to a bit interleaver. The method includes:

[0007] Determine the parallel bit width and the modulation order of the base station where the bit interleaver is located, and obtain data to be processed;

[0008] Writing a target bit group in the data to be processed to a write address in a cache space in a memory, wherein an initial target bit group is a frontmost bit group of the data to be processed, and a length of each target bit group is the parallel bit width;

[0009] Taking the next bit group adjacent to the current target bit group as a new target bit group, and accumulating the parallel bit width on the basis of the current write address to obtain a new write address;

[0010] Returning to the step of writing the target bit group in the data to be processed into the write address in the cache space in a memory until all the data to be processed are written into the cache space;

[0011] Reading a bit group having a length equal to the parallel bit width from a read address in the cache space;

[0012] Accumulating a preset address offset on the basis of the current read address to obtain a new read address, wherein the initial read address is the starting address of the cache space, the preset address offset is equal to the length of a row of data in the cache space, and the number of data rows in the cache space is equal to the modulation order;

[0013] Returning to the step of reading a bit group having a length of the parallel bit width from the read address in the cache space, until the read bit group is located in the last row in the cache space;

[0014] The read address is adjusted to the starting address of the unread data in the first row of the cache space, and the step of reading a bit group having a length of the parallel bit width from the read address in the cache space is returned to perform the next round of bit group reading until all the data in the cache space is read out;

[0015] The read bit group is subjected to intra-byte interleaving processing to obtain a bit interleaving result.

[0016] In one embodiment of the present invention, the step of performing intra-byte interleaving processing on the read bit group to obtain a bit interleaving result includes:

[0017] For the bit groups read in the target round, in the order in which the bit groups are read, data of the target position is obtained from each bit group in sequence, 1 is added to the current target position to obtain a new target position, and the step of obtaining data of the target position from each bit group in sequence in the order in which the bit groups are read is returned to be executed until all bits in the bit groups of the target round are obtained, wherein the initial value of the target position is the first position;

[0018] Add 1 to the current target round to obtain a new target round, adjust the target position to the initial value, return to execute the step of obtaining data of the target position from each bit group in the order in which each bit group is read, until all bits in the bit groups read in each round are obtained;

[0019] Arrange the bits in the order of acquisition to obtain the bit interleaving result.

[0020] In one embodiment of the present invention, the parallel bit width and the modulation order are set based on primitives, the parallel bit width is defined in a macro definition and can be modified, and when the parallel bit width is modified to a target bit width, the parallel bit width determined by the bit interleaver is the target bit width; the length of each target bit group is the target bit width;

[0021] The step of accumulating the parallel bit width based on the current write address includes:

[0022] Accumulate the target bit width based on the current write address;

[0023] The step of reading a bit group having a length equal to the parallel bit width from a read address in the cache space comprises:

[0024] A bit group having a length equal to the target bit width is read from a read address in the cache space.

[0025] In one embodiment of the present invention, the length of the data to be processed is calculated in the following manner:

[0026] Calculate the number of resource units RE scheduled by the base station each time based on the number of physical downlink shared channel PDSCH channel symbols of the base station, the number of physical resource blocks PRB in each symbol, and the number of streams of stream mapping;

[0027] The length of the data to be processed is calculated based on the number of REs, the modulation order and the number of REs that need to be scheduled in each code block CB.

[0028] In one embodiment of the present invention, the length of the data to be processed is: calculated by a programmable logic array FPGA where the bit interleaver is located, or calculated by other equipment outside the base station;

[0029] The preset FPGA calculation parameters are used to control whether the FPGA calculates the length of the data to be processed.

[0030] In a second aspect, an embodiment of the present invention provides a bit interleaver, including a memory, a transceiver, and a processor:

[0031] A memory for storing a computer program; a transceiver for transmitting and receiving data under the control of the processor; and a processor for reading the computer program in the memory and performing the following operations:

[0032] Determine the parallel bit width and the modulation order of the base station where the bit interleaver is located, and obtain data to be processed;

[0033] Writing a target bit group in the data to be processed to a write address in a cache space in a memory, wherein an initial target bit group is a frontmost bit group of the data to be processed, and a length of each target bit group is the parallel bit width;

[0034] Taking the next bit group adjacent to the current target bit group as a new target bit group, and accumulating the parallel bit width on the basis of the current write address to obtain a new write address;

[0035] Returning to the step of writing the target bit group in the data to be processed into the write address in the cache space in a memory until all the data to be processed are written into the cache space;

[0036] Reading a bit group having a length equal to the parallel bit width from a read address in the cache space;

[0037] Accumulating a preset address offset on the basis of the current read address to obtain a new read address, wherein the initial read address is the starting address of the cache space, the preset address offset is equal to the length of a row of data in the cache space, and the number of data rows in the cache space is equal to the modulation order;

[0038] Returning to the step of reading a bit group having a length of the parallel bit width from the read address in the cache space, until the read bit group is located in the last row in the cache space;

[0039] The read address is adjusted to the starting address of the unread data in the first row of the cache space, and the step of reading a bit group having a length of the parallel bit width from the read address in the cache space is returned to perform the next round of bit group reading until all the data in the cache space is read out;

[0040] The read bit group is subjected to intra-byte interleaving processing to obtain a bit interleaving result.

[0041] In one embodiment of the present invention, performing intra-byte interleaving processing on the read bit group to obtain a bit interleaving result specifically includes:

[0042] For the bit groups read in the target round, in the order in which the bit groups are read, data of the target position is obtained from each bit group in sequence, 1 is added to the current target position to obtain a new target position, and the step of obtaining data of the target position from each bit group in sequence in the order in which the bit groups are read is returned to be executed until all bits in the bit groups of the target round are obtained, wherein the initial value of the target position is the first position;

[0043] Add 1 to the current target round to obtain a new target round, adjust the target position to the initial value, return to execute the step of obtaining data of the target position from each bit group in the order in which each bit group is read, until all bits in the bit groups read in each round are obtained;

[0044] Arrange the bits in the order of acquisition to obtain the bit interleaving result.

[0045] In one embodiment of the present invention, the parallel bit width and the modulation order are set based on primitives, the parallel bit width is defined in a macro definition and can be modified, and when the parallel bit width is modified to a target bit width, the parallel bit width determined by the bit interleaver is the target bit width; the length of each target bit group is the target bit width;

[0046] The step of accumulating the parallel bit width based on the current write address specifically includes:

[0047] Accumulate the target bit width based on the current write address;

[0048] The step of reading a bit group having a length of the parallel bit width from a read address in the cache space specifically includes:

[0049] A bit group having a length equal to the target bit width is read from a read address in the cache space.

[0050] In one embodiment of the present invention, the length of the data to be processed is calculated in the following manner:

[0051] Calculate the number of resource units RE scheduled by the base station each time based on the number of physical downlink shared channel PDSCH channel symbols of the base station, the number of physical resource blocks PRB in each symbol, and the number of streams of stream mapping;

[0052] The length of the data to be processed is calculated based on the number of REs, the modulation order and the number of REs that need to be scheduled in each code block CB.

[0053] In one embodiment of the present invention, the length of the data to be processed is: calculated by a programmable logic array FPGA where the bit interleaver is located, or calculated by other equipment outside the base station;

[0054] The preset FPGA calculation parameters are used to control whether the FPGA calculates the length of the data to be processed.

[0055] In a third aspect, an embodiment of the present invention provides a bit interleaving device, which is applied to a bit interleaver, and the device includes:

[0056] A parameter determination module, used to determine the parallel bit width and the modulation order of the base station where the bit interleaver is located, and obtain data to be processed;

[0057] A data writing module is used to write a target bit group in the data to be processed to a write address in a cache space in a memory, wherein the initial target bit group is the frontmost bit group of the data to be processed, and the length of each target bit group is the parallel bit width;

[0058] Taking the next bit group adjacent to the current target bit group as a new target bit group, and accumulating the parallel bit width on the basis of the current write address to obtain a new write address;

[0059] Returning to the step of writing the target bit group in the data to be processed into the write address in the cache space in a memory until all the data to be processed are written into the cache space;

[0060] A data reading module, used for reading a bit group having a length equal to the parallel bit width from a reading address in the cache space;

[0061] Accumulating a preset address offset on the basis of the current read address to obtain a new read address, wherein the initial read address is the starting address of the cache space, the preset address offset is equal to the length of a row of data in the cache space, and the number of data rows in the cache space is equal to the modulation order;

[0062] Returning to the step of reading a bit group having a length of the parallel bit width from the read address in the cache space, until the read bit group is located in the last row in the cache space;

[0063] The read address is adjusted to the starting address of the unread data in the first row of the cache space, and the step of reading a bit group having a length of the parallel bit width from the read address in the cache space is returned to perform the next round of bit group reading until all the data in the cache space is read out;

[0064] The result generating module is used to perform intra-byte interleaving processing on the read bit group to obtain a bit interleaving result.

[0065] In one embodiment of the present invention, the result generation module is specifically used to:

[0066] For the bit groups read in the target round, in the order in which the bit groups are read, data of the target position is obtained from each bit group in sequence, 1 is added to the current target position to obtain a new target position, and the step of obtaining data of the target position from each bit group in sequence in the order in which the bit groups are read is returned to be executed until all bits in the bit groups of the target round are obtained, wherein the initial value of the target position is the first position;

[0067] Add 1 to the current target round to obtain a new target round, adjust the target position to the initial value, return to execute the step of obtaining data of the target position from each bit group in the order in which each bit group is read, until all bits in the bit groups read in each round are obtained;

[0068] Arrange the bits in the order of acquisition to obtain the bit interleaving result.

[0069] In one embodiment of the present invention, the parallel bit width and the modulation order are set based on primitives, the parallel bit width is defined in a macro definition and can be modified, and when the parallel bit width is modified to a target bit width, the parallel bit width determined by the bit interleaver is the target bit width; the length of each target bit group is the target bit width;

[0070] The data writing module is used to accumulate the parallel bit width based on the current writing address, specifically to:

[0071] Accumulate the target bit width based on the current write address;

[0072] The data reading module is used to read a bit group with a length of the parallel bit width from a reading address in the cache space, specifically to:

[0073] A bit group having a length equal to the target bit width is read from a read address in the cache space.

[0074] In one embodiment of the present invention, the device further comprises:

[0075] The data length calculation module is used to calculate the length of the data to be processed in the following way:

[0076] Calculate the number of resource units RE scheduled by the base station each time based on the number of physical downlink shared channel PDSCH channel symbols of the base station, the number of physical resource blocks PRB in each symbol, and the number of streams of stream mapping;

[0077] The length of the data to be processed is calculated based on the number of REs, the modulation order and the number of REs that need to be scheduled in each code block CB.

[0078] In one embodiment of the present invention, the length of the data to be processed is: calculated by a programmable logic array FPGA where the bit interleaver is located, or calculated by other equipment outside the base station;

[0079] The preset FPGA calculation parameters are used to control whether the FPGA calculates the length of the data to be processed.

[0080] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps of any one of the first aspects described above are implemented.

[0081] In a fifth aspect, an embodiment of the present invention further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the above-mentioned methods of the first aspect.

[0082] Beneficial effects of the embodiments of the present invention:

[0083] The bit interleaving method provided in an embodiment of the present invention is applied to a bit interleaver. When reading data, the next reading is performed at an interval of a preset address offset, that is, the next data reading is performed at an interval of the length of a row of data in the cache space, so that the data read next time is located in a position of different rows in the same column, thereby realizing longitudinal column-by-column reading and realizing a parallel bit interleaving process. In addition, since the bit interleaver only writes the data to be processed into the cache space in a memory, the waste of cache space is reduced.

[0084] Of course, it is not necessary to achieve all of the advantages described above at the same time to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0086] Figure 1A schematic diagram of a flow chart of a bit interleaving method provided in an embodiment of the present invention;

[0087] Figure 2 A schematic diagram of a data writing process provided by an embodiment of the present invention;

[0088] Figure 3 A schematic diagram of directions for writing and reading data provided by an embodiment of the present invention;

[0089] Figure 4 A schematic diagram of an address stream, an inter-byte interleaved data stream, and an intra-byte interleaved data stream provided by an embodiment of the present invention;

[0090] Figure 5 A schematic diagram of a parallel bit interleaving process provided by an embodiment of the present invention;

[0091] Figure 6 A schematic diagram of generating an inter-node interleaving result and an intra-byte interleaving result provided by an embodiment of the present invention;

[0092] Figure 7 A schematic diagram of a serial bit interleaving process provided by an embodiment of the present invention;

[0093] Figure 8 A schematic diagram of a process for performing intra-byte interleaving provided by an embodiment of the present invention;

[0094] Fig. 9 A schematic diagram of a flow chart for calculating the length of data to be processed provided by an embodiment of the present invention;

[0095] Fig.10 A schematic diagram of a first bit interleaving process provided by an embodiment of the present invention;

[0096] Fig.11 A schematic diagram of a second process of performing bit interleaving provided by an embodiment of the present invention;

[0097] Fig.12 A schematic diagram of the structure of a bit interleaver provided by an embodiment of the present invention;

[0098] Fig.13 A schematic structural diagram of a bit interleaving device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0099] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field based on the present invention belong to the scope of protection of the present invention.

[0100] In order to reduce the waste of cache space, a bit interleaving method, device, bit interleaver and storage medium are specifically described below.

[0101] The embodiment of the present invention provides a bit interleaving method, which is applied to a bit interleaver, see Figure 1 , Figure 1 A flowchart of a bit interleaving method provided in an embodiment of the present invention is provided. The method includes the following steps S101-S1010.

[0102] S101, determine the parallel bit width and the modulation order of the base station where the bit interleaver is located, and obtain data to be processed.

[0103] The above parallel bit width is set to a fixed value, and the value can also be adjusted according to needs. The parallel bit width is the number of bits processed in each FPGA (Field Programmable Gate Array) clock cycle. The larger the parallel bit width, the more bits can be processed in each clock cycle.

[0104] The number of bits of a group of data to be processed (the length of the data to be processed) is the depth of bit interleaving of the group of data. The embodiment of the present invention adopts the bit interleaving method, so it can effectively resist burst errors, and as the depth of interleaving increases, the ability to resist burst errors will be enhanced accordingly.

[0105] The depth of bit interleaving, i.e., the interleaving depth, is related to the modulation method adopted by the base station. The higher the modulation level of the modulation method adopted by the base station, the greater the interleaving depth. For the specific calculation process of the length of the data to be processed, please refer to the subsequent Fig. 9 The relevant descriptions in the embodiments are not repeated here.

[0106] The above modulation order and the number of subsequent interleaving rows are related to the modulation level. The higher the modulation level, the greater the modulation order, which means that the number of effective bits scheduled in each RE (Resource Element) is greater. The greater the modulation order, the greater the number of subsequent interleaving rows.

[0107] Specifically, the number of interleaving rows to be performed subsequently can be determined according to the relationship between the modulation level, the modulation order, and the number of interleaving rows in the related art. For the convenience of subsequent description, in the embodiment of the present invention, an interleaving method in which the modulation order is equal to the number of interleaving rows is used for subsequent description. Of course, other interleaving methods can also be used according to requirements.

[0108] See Table 1, which is a table of the correspondence between a modulation level, a modulation order, and an interleaving row number provided in an embodiment of the present invention. The modulation levels included in the table are: π / 2-BPSK (Binary Phase Shift Keying), BPSK, QPSK (Quadrature Phase Shift Keying), 16QAM (QuadratureAmplitude Modulation), 64QAM, and 256QAM.

[0109] Table 1

[0110] Modulation level Modulation order Interleaving rows π / 2-BPSK, BPSK 1 1 QPSK 2 2 16QAM 4 4 64QAM 6 6 256QAM 8 8

[0111] In the table, the modulation level increases from top to bottom. Specifically, the level of 256QAM is higher than that of 64QAM, the level of 64QAM is higher than that of 16QAM, the level of 16QAM is higher than that of QPSK, and the level of QPSK is higher than that of π / 2-BPSK and BPSK. The table adopts an interleaving method in which the modulation order is equal to the number of interleaving rows. The modulation order can be determined according to the modulation level based on the corresponding relationship in the table, thereby determining the number of rows for subsequent interleaving.

[0112] In an example, when the base station is a 5G (5th Generation Mobile Communication Technology) NR (New Radio) base station, bit interleaving can be performed in an interleaving manner in which the number of interleaving rows is equal to the modulation order.

[0113] In an example (1), it is determined that the parallel bit width is 4 bits, the modulation order of the base station where the bit interleaver is located is 4, and the data to be processed M is obtained. M includes the 0th data to the 63rd data, and the length of M is 64 bits.

[0114] S102, writing a target bit group in the data to be processed into a write address in a cache space in a memory.

[0115] The initial target bit group is the frontmost bit group of the data to be processed, and the length of each target bit group is the parallel bit width.

[0116] The above memory can be selected according to requirements and is not limited here. In one example, the memory is RAM.

[0117] The above-mentioned write address can be generated by accumulation of the accumulator, and the initial write address is the starting address of the cache space. Specifically, since the length of each target bit group is the parallel bit width, the number of write addresses to be generated can be determined based on the parallel bit width, where the number of write addresses = the length of the data to be processed / the parallel bit width, which represents the number of data with a data length of the parallel bit width in a CB (Code Block). The number of target bit groups is the same as the number of write addresses.

[0118] Specifically, during the data writing process, the number of data rows in the cache space is equal to the modulation order.

[0119] Corresponding to the above example (1), the parallel bit width is 4 bits, the length of M is 64 bits, and 16 write addresses need to be generated. Since the parallel bit width is 4 bits, the difference between two adjacent write addresses is 4 bits. Assuming that the memory is a hexadecimal memory, the generated write addresses can specifically include: 0x00, 0x04, 0x08...0x38, 0x3C, corresponding to the first write address (addr_0), the second write address (addr_1), the third write address (addr_2)...the fifteenth write address (addr_14), and the sixteenth write address (addr_15).

[0120] Corresponding to the above example (1), the parallel bit width is 4 bits, then the target bit group is the 0th data to the 3rd data in M. Specifically, when writing for the first time, the 0th data to the 3rd data in M ​​are written as the target bit group to the cache space addr_0, that is, written to the address 0x00.

[0121] After executing the above step S102, step S103 is executed to determine whether there is any unwritten data in the data to be processed.

[0122] If there is unwritten data, step S104 is executed; if there is no unwritten data, step S105 is executed.

[0123] S104, taking the next bit group adjacent to the current target bit group as a new target bit group, and accumulating the parallel bit width on the basis of the current write address to obtain a new write address.

[0124] Corresponding to the above example (1), the 4th to 7th data adjacent to the target bit group are used as the new target bit group. Specifically, during the next write, the new target bit group consisting of the 4th to 7th data in M ​​is written to the cache space addr_1, that is, written to address 0x04.

[0125] After executing step S104, return to execute the above step S102 until all the data to be processed are written into the cache space.

[0126] Corresponding to the above example (1), since the modulation order is equal to the number of data rows in the cache space, which is equal to 4, the data to be processed is evenly divided into four rows of data. The length of each row of data in the cache space is 16 bits, and since the bit width is 4, each row contains 4 write addresses.

[0127] See also Figure 2 , Figure 2 A schematic diagram of a data writing process provided by an embodiment of the present invention, the decimal number in the box indicates the position of the number in the data to be processed, and the hexadecimal number indicates the initial address to which the corresponding data is written. Specifically, after the above two writes, continue the third write, write the new target bit group consisting of the 8th to 11th data in M ​​to the cache space addr_2, that is, write to the address 0x08... write the new target bit group consisting of the 56th to 59th data in M ​​to the cache space addr_14, that is, write to the address 0x38, write the new target bit group consisting of the 60th to 63rd data in M ​​to the cache space addr_15, that is, write to the address 0x3C, thereby completing the writing of 16 target bit groups, so that all the data to be processed are written to the cache space.

[0128] S105, reading a bit group having a length equal to the parallel bit width from a read address in the cache space.

[0129] Since data needs to be read column by column, all the data to be processed needs to be cached in the cache space before reading to avoid data loss.

[0130] The initial read address is the starting address of the cache space.

[0131] Corresponding to the above example (1) and see Figure 2 , read a bit group with a length of the parallel bit width from the starting address 0x00 in the cache space, that is, read the 0th data to the 3rd data at 0x00 in the cache space.

[0132] After executing the above step S105, step S106 is executed to determine whether the read bit group is located in the last row in the cache space.

[0133] If the read bit group is located in the last row in the cache space, it means that at least one round of the bit group has been read. In this case, step S107 is executed to determine whether there is unread data in the cache space. Reading one round of data means reading a column of data with a length of the parallel bit width, that is, reading data with a length of the parallel bit width of the number of interleaved rows. Specifically, the number of rounds is equal to the number of columns in the cache space, and the number of columns in the cache space = the length of the data to be processed / the parallel bit width / the number of data rows in the cache space. Corresponding to the above example (1), the number of rounds is 4.

[0134] For step S107 , if there is unwritten data, it means that all columns of data have not been read, and it is necessary to continue reading the next column of data. Based on this, step S109 is executed.

[0135] If there is no unwritten data, it means that the data of all columns have been read, and step S1010 is executed.

[0136] For step S106 , if the read bit group is not located in the last row in the cache space, it means that the data of a column has not been read completely and the next row of the column needs to be read. Based on this, step S108 is executed.

[0137] S108, accumulating a preset address offset on the basis of the current read address to obtain a new read address.

[0138] The preset address offset is equal to the length of a row of data in the cache space.

[0139] Corresponding to the above example (1) and see Figure 2 , when the current read address is 0x00, 0x10 is accumulated on the basis of address 0x00 to obtain a new read address 0x10.

[0140] After executing step S108, return to execute step S105.

[0141] Corresponding to the above example (1) and see Figure 2 , read the 16th to 19th data at address 0x10.

[0142] S109, adjusting the read address to the starting address of the unread data in the first row of the cache space.

[0143] Corresponding to the above example (1) and see Figure 2In the case where the read bit group is located in the first column and fourth row of data in the cache space, that is, when the 48th data to the 51st data at the read address 0x30, the read address is adjusted to the starting address of the unread data in the first row of the cache space. At this time, the unread data in the first row are: the 4th data to the 15th data, and the corresponding starting address at this time is the address corresponding to the 4th data, that is, 0x04.

[0144] After executing step S109, the process returns to step S105. Figure 2 , read the 4th to 7th data at address 0x04, and start the next round of bit group reading.

[0145] That is, the process of reading data in the cache space is performed in the following reading order. Figure 2 , the order of addresses read is: 0x00, 0x10, 0x20, 0x30, 0x04, 0x14, 0x24, 0x34, 0x08, 0x18, 0x28, 0x38, 0x0C, 0x1C, 0x2C, 0x3C.

[0146] In an example (2), the data length is E bits, the modulation level is Q, and the parallel bit width is WIDTH bits. Then the cache space can be configured to contain Q rows, and the data length of each row is E / Q bits. Since the bit width is WIDTH, a total of E / WIDTH write addresses need to be generated. On average, one row of the cache space contains E / Q / WIDTH write addresses. In the process of writing and reading data, you can refer to Figure 3 Data is written and read in the direction shown, Figure 3 A schematic diagram of the direction of writing data and reading data provided by an embodiment of the present invention, in which the dotted arrow represents the direction of writing data, and the solid arrow represents the direction of reading data, wherein addr_0 represents the first write address, addr_1 represents the second write address...addr_E / WIDTH-1 represents the E / WIDTHth write address.

[0147] S1010, performing intra-byte interleaving processing on the read bit group to obtain a bit interleaving result.

[0148] After writing the data to be processed into the cache space, the process of reading the data includes an inter-byte interleaving process and an intra-byte interleaving process. The above steps S105-S109 correspond to the inter-byte interleaving process, and all the data in the cache space are read in units of bit groups with a length of parallel bit width. Since each clock cycle carries a continuous data stream of parallel bit width bits after the inter-byte interleaving operation, bit-level interleaving is not achieved. In order to achieve bit-level interleaving, further processing is required inside the byte to generate a bit interleaving result that meets the standard. The above step S1010 corresponds to the intra-byte interleaving process, and different bit groups are interleaved in units of one data, and each data in each bit group is read.

[0149] Corresponding to example (2) above, see Figure 4 , Figure 4 The following is a schematic diagram of an address stream, a data stream after byte interleaving, and a data stream after byte interleaving provided by an embodiment of the present invention. In the process of reading data, the address stream and the data stream after byte interleaving are as follows. The description of the data stream after byte interleaving in the figure will be described later. Figure 8 The address streams are as follows: addr_0, addr_E / Q / WIDTH...addr_(Q-1)*E / Q / WIDTH, addr_1, addr_E / Q / WIDTH+1...addr_(Q-1)*E / Q / WIDTH-1, addr_E / WIDTH-1; the data streams after byte interleaving are as follows: 0~WIDTH, E / Q~E / Q+WIDTH-1...(Q-1)*E / Q~(Q-1)*E / Q+WIDTH-1, WIDTH~2*WIDTH-1, E / Q+WIDTH~E / Q+2*WIDTH-1...(Q-2)*E / Q+(Q-1)*WIDTH~(Q-1)*E / Q-1, E-WIDTH~E-1.

[0150] The intra-byte interleaving process is interleaved based on a column of data, so the data at the same position of each column of data is read in the order of column first and row later. A column of data contains bit groups of the number of interleaved rows, and each bit group contains data of the length of the parallel bit width.

[0151] For details on intra-byte interleaving, see the following Figure 8 The embodiment shown.

[0152] In the related art, the parallel bit interleaving process is described here by taking the to-be-processed data M, the number of interleaving rows being 4, and the parallel bit width being 4 bits as an example. Figure 5 , Figure 5 A schematic diagram of a parallel bit interleaving process provided by an embodiment of the present invention. The above process includes the following steps A1-A3.

[0153] A1, accumulates and generates a write address, and writes the to-be-processed data M into the cache space based on the write address. Since the number of interleaved rows is 4, it is necessary to use the cache space of the 4 memories according to Figure 2 Specifically, write the same data M to be processed into cache spaces 1-4 respectively according to Figure 2 The data M to be processed is written in this way.

[0154] A2, generates an interleaved read address, and reads data in the cache space based on the read address to generate an interleaved result between bytes.

[0155] In order to read a column of data in one clock cycle, it is necessary to simultaneously fetch 4 bit groups with a length equal to the parallel bit width from four cache spaces in one clock cycle, so each cache space corresponds to a different address in each clock cycle.

[0156] Specifically, in the first clock cycle, cache space 1 corresponds to the read address 0x00, cache space 2 corresponds to the read address 0x10, cache space 3 corresponds to the read address 0x20, and cache space 4 corresponds to the read address 0x30, thereby realizing the reading of the first column of data. Based on the above set read address, in the first clock cycle, the 0th to 3rd data of the 1st column and the 1st row at the read address 0x00 are read in cache space 1, the 16th to 19th data of the 1st column and the 2nd row at the read address 0x10 are read in cache space 2, the 32nd to 35th data of the 1st column and the 3rd row at the read address 0x20 are read in cache space 3, and the 48th to 51st data of the 1st column and the 4th row at the read address 0x30 are read in cache space 4, completing the reading of the first column of data, and then based on the new read address, the reading of the second column of data is read in the next clock cycle, until the reading of all columns is completed, generating the byte interleaving result, recorded as o_data_1.

[0157] A3, perform intra-byte interleaving on the inter-byte interleaving result to generate an intra-byte interleaving result, which is recorded as o_data_2.

[0158] See also Figure 6 , Figure 6 A schematic diagram of generating an inter-node interleaving result and an intra-byte interleaving result provided by an embodiment of the present invention. The numbers in the boxes in the figure indicate which data in the data to be processed is written in the box. Among them, 0 to 3 in the first box indicates that the first box has the 0th to 3rd data in the data to be processed written.

[0159] In the first clock cycle of the data reading process, the 0th to 3rd data of the 1st column and the 1st row are read out from cache space 1, the 16th to 19th data of the 1st column and the 2nd row are read out from cache space 2, the 32nd to 35th data of the 1st column and the 3rd row are read out from cache space 3, and the 48th to 51st data of the 1st column and the 4th row are read out from cache space 4, completing the reading of the first column of data. In the fourth clock cycle, the 12th to 15th data of the 4th column and the 1st row are read out from cache space 1, and the 48th to 51st data of the 1st column and the 4th row are read out from cache space 2. The 28th to 31st data of the 2nd row, the 44th to 47th data of the 4th column and the 3rd row are read out in cache space 3, and the 60th to 63rd data of the 4th column and the 4th row are read out in cache space 4, completing the reading of four columns of data. The generated byte interleaving results are: the 0th data to the 3rd data, the 16th data to the 19th data, the 32nd data to the 35th data... the 12th data to the 15th data, the 28th data to the 31st data, the 44th data to the 47th data, the 60th data to the 63rd data.

[0160] Figure 6 The description of the intra-byte interleaving results will be described later. Figure 8 The embodiment shown is described.

[0161] From the above, it can be seen that in the related technology, the data to be processed needs to be stored in multiple different cache spaces. Not only multiple cache spaces are required, but each cache space needs to completely store the data to be processed. However, when reading, only part of the data in each cache space is read, resulting in a large amount of cache space being wasted.

[0162] However, in an embodiment of the present invention, when reading data, the next reading is performed with a preset address offset as an interval, that is, the next data reading is performed with the length of a row of data in the cache space as an interval, so that the data read next time is located in a different row of the same column, thereby realizing vertical column-by-column reading and a parallel bit interleaving process. In addition, since the bit interleaver only writes the data to be processed into the cache space in a memory, the waste of cache space is reduced.

[0163] In addition, in the related art, there is also a method of performing bit interleaving in a serial manner. The serial bit interleaving realizes the interleaving function by controlling the read and write addresses. Specifically, the write address is generated by using an accumulator, and the read address is generated according to the modulation order and the length of the data to be processed. Figure 7 , Figure 7A schematic diagram of a serial bit interleaving process provided by an embodiment of the present invention, wherein the serial bit interleaving process is described by taking the to-be-processed data M and the number of interleaving rows being 4 as an example. The numbers in the figure indicate the position of the numbers in the to-be-processed data.

[0164] When writing data, M is written into a cache space with 4 rows and a row length of 16 bits in order from front to back, and only 1 bit of data is written each time. Specifically, the writing direction is the direction of rows first and columns later, that is, the 0th data, the 1st data, the 2nd data... the 62nd data, the 63rd data are written in the order of rows first and columns later. When reading data, the reading direction is the direction of columns first and rows later, that is, the data are read in the order of columns first and rows later, and the data after reading are: the 0th data, the 16th data, the 32nd data, the 48th data, the 1st data, the 17th data... the 31st data, the 47th data, the 63rd data.

[0165] However, the serial method is only applicable to the case where the interleaving depth is small. If the interleaving depth increases, the time consumed by serial processing will increase significantly.

[0166] In the embodiment of the present invention, the writing and inter-byte interleaving processes are all implemented based on a bit group. Instead of processing based on data with a width of 1 bit, processing is performed based on a bit group with a length equal to the parallel bit width, which greatly shortens the processing time. When performing intra-byte interleaving, one clock cycle will read the modulation order data, which also greatly shortens the reading time.

[0167] Furthermore, since the processing time is greatly shortened and the waste of cache space is reduced, the bit interleaving method provided in the embodiment of the present invention can be applied to 5G NR services to meet the low latency requirements of 5G. In addition, since the related technology requires the inclusion of multiple cache spaces, the probability of local wiring conflicts is increased, which may cause the equipment to fail to operate. However, in the embodiment of the present invention, only one cache space is required, which greatly reduces the probability of local wiring conflicts. The stability of equipment operation is improved.

[0168] In one embodiment of the present invention, see Figure 8 , Figure 8 A schematic diagram of a process for performing intra-byte interleaving provided by an embodiment of the present invention, Figure 1 Step S1010 may specifically include the following steps S801-S806.

[0169] S801, for the bit groups read in the target round, sequentially obtain data of the target position from each bit group according to the order in which each bit group is read.

[0170] Among them, the initial value of the target position is the first position, and the initial target round is the 1st round.

[0171] Corresponding to the above example (1) and see Figure 2 , the first round corresponds to the first column. Specifically, in the first clock cycle, for the bit group read in the first column, the first-order data is read from each bit group in order from the first row to the last row. The read data include: the 0th data, the 16th data, the 32nd data, and the 48th data.

[0172] S802, determine whether the target bit order is smaller than the parallel bit width.

[0173] If it is not less than the parallel bit width, it means that all the data in the bit group has been read out, and then step S803 is executed.

[0174] If it is less than the parallel bit width, it means that the data in the bit group has not been fully read out, and then step S804 is executed.

[0175] S803, determining whether the number of data currently read is less than the length of the data to be processed.

[0176] If it is less than the length of the data to be processed, it means that all rounds of reading have not been completed, and step S805 is executed.

[0177] If it is not less than the length of the data to be processed, it means that all rounds of reading have been completed, and step S806 is executed.

[0178] S804, adding 1 to the current target ranking to obtain a new target ranking.

[0179] Corresponding to the above example (1) and see Figure 2 , when the current target ranking is the first ranking, add 1 to the first ranking to get the second ranking as the new target ranking.

[0180] After executing the above step S804, return to execute step S801 until all bits in the bit group of the target round are obtained.

[0181] Corresponding to the above example (1) and see Figure 2 , in the second clock cycle, for the bit group read in the first column, the second-order data is read from each bit group in order from the first row to the last row, and the read data includes: the first data, the seventeenth data, the thirty-third data, and the forty-ninth data.

[0182] S805, adding 1 to the current target round to obtain a new target round, and adjusting the target ranking to the initial value.

[0183] Corresponding to the above example (1) and see Figure 2 , when the current target round is the first round, add 1 to the first round to get the second round, and adjust the target ranking to the initial value of the first ranking.

[0184] After executing the above step S805, return to execute step S801 until all bits in the bit groups read in each round are obtained.

[0185] Corresponding to the above example (1) and see Figure 2 , for the bit group read in the second column, the first-order data is read from each bit group in order from the first row to the last row. The read data include: the 4th data, the 20th data, the 36th data, and the 52nd data.

[0186] S806, arrange the bits in the order of acquisition to obtain a bit interleaving result.

[0187] Corresponding to the above Figure 6 In the embodiment shown, the generated intra-byte interleaving results are: 0th data, 16th data, 32nd data, 48th data, 1st data, 17th data, 33rd data, 49th data... 14th data, 30th data, 46th data, 62nd data, 15th data, 31st data, 47th data, 63rd data.

[0188] Corresponding to the above example (2), the data stream after intra-byte interleaving is as follows: 0, E / Q, 2E / Q...(Q-1)*E / Q; 1, E / Q+1, 2E / Q+1...(Q-1)*E / Q+1...E / Q-2, 2E / Q-2...E-2; E / Q-1, 2E / Q-1...E-1.

[0189] In the embodiment of the present invention, intra-byte interleaving is performed so that the data in the output bit interleaving result is completely disrupted based on the data to be processed, and there is no data arranged in the order of the original data to be processed, thereby ensuring the accuracy of the bit interleaving result.

[0190] In one embodiment of the present invention, the parallel bit width and the modulation order are set based on the primitive, the parallel bit width is defined in the macro definition and can be modified, and when the parallel bit width is modified to the target bit width, the parallel bit width determined by the bit interleaver is the target bit width, and the length of each target bit group is the target bit width.

[0191] The parallel bit width in the macro definition can be modified according to actual needs. The parallel bit width can be modified to 16 bits, 32 bits, 64 bits, 128 bits, etc. according to scenario requirements.

[0192] In an example, when the length of the data to be processed is 6912 bits, the parallel bit widths are 16 bits, 32 bits, 64 bits, and 128 bits respectively. It is found that when the bit interleaving process is performed based on the parallel bit width of 16 bits, the total processing time is 7217478ps, where ps is the time unit picosecond; when the bit interleaving process is performed based on the parallel bit width of 32 bits, the total processing time is 3611186ps; when the bit interleaving process is performed based on the parallel bit width of 64 bits, the total processing time is 2066424ps; when the bit interleaving process is performed based on the parallel bit width of 128 bits, the total processing time is 1542932ps. It can be seen that as the parallel bit width increases, the processing time will be shortened. In the test, it was found that the resource occupancy did not change significantly with the change of the parallel bit width. Therefore, in actual situations, in order to reduce the time for bit interleaving, the parallel bit width can be adjusted to a larger value to shorten the processing time.

[0193] In addition, the number of data rows in the cache space and the data length of a row may also be defined in the macro definition and modified according to actual needs, so that data can be written and read subsequently based on the modified cache space.

[0194] In an example, the original length of the data to be processed is 64 bits, the parallel bit width is 4 bits, the modulation order is 4, the number of data rows in the cache space is defined as 4, and the data length of a row is defined as 16. However, the actual situation has changed. The modulation level of the base station has increased, which has increased the modulation order, so the number of interleaving rows is adjusted to 8, and in order to shorten the processing time, the parallel bit width is adjusted to 8 bits. In this case, the number of data rows in the cache space is modified to be defined as 8, and the data length of a row is defined as 8.

[0195] Specifically, the above primitives may be XPM (Xilinx Parameterized Macros) primitives. Among them, there are three types of XPM types, namely, cross-clock domain processing type, FIFO (First In First Out) type and MEMORY type. In one example, MEMORY type is selected as the data parameterization type. When using MEMORY XPM, the configuration of key parameters can refer to Table 2, which is a MEMORY XPM key parameter configuration table provided in an embodiment of the present invention. Each parameter in the table can be configured based on the configuration reference values ​​in the table. For the specific configuration process, refer to the relevant technology, which will not be repeated here.

[0196] Table 2

[0197]

[0198]

[0199] Specifically, when the parallel bit width is accumulated on the basis of the current write address in the above step S104, the target bit width may be accumulated on the basis of the current write address.

[0200] In the above step S105, when a bit group having a length of the parallel bit width is read from the read address in the cache space, a bit group having a length of the target bit width may be specifically read from the read address in the cache space.

[0201] In the embodiment of the present invention, since the parallel bit width and the modulation order are set based on the primitive, the parallel bit width and the modulation order are relatively easy to modify according to actual needs, so that subsequent steps are performed based on the modified parallel bit width and modulation order, thereby realizing the adaptation of the bit interleaving process to the parallel bit width and modulation order, and improving the processing flexibility.

[0202] Moreover, in the related art, when performing parallel bit interleaving, it is generally implemented by instantiating the IP core, so after the configuration of the IP core is determined, the parallel bit width and interleaving depth will be fixed. After the parallel bit width is fixed, the processing speed will also be fixed and cannot change with the change of the amount of data to be processed. In the embodiment of the present invention, the parallel bit width and modulation order can be modified according to actual needs, and can be adjusted to a suitable range according to the change of the amount of data to be processed or the modulation level of the base station to improve the processing speed.

[0203] In addition, since the parallel bit width and modulation order are set based on primitives, the rate of code porting between different chip platforms is improved compared to the IP core setting-based method in related technologies.

[0204] In one embodiment of the present invention, see Fig. 9 , Fig. 9 A schematic diagram of a flow chart for calculating the length of data to be processed provided in an embodiment of the present invention may specifically include the following steps S901-S902.

[0205] S901, based on the number of PDSCH (Physical Downlink Control Channel) channel symbols of the base station, the number of PRBs (Physical Random Access Channel) in each symbol, and the number of streams of stream mapping, calculate the number of REs scheduled each time by the base station.

[0206] According to TS 38.214 of the 5G NR protocol, the length of the data after bit interleaving is related to the PDSCH parameters in the scheduling information. In order to make the length of the data after bit interleaving comply with the protocol, when obtaining the data to be processed after bit selection, the length of the data to be obtained should be the length of the data calculated later. For the sake of convenience, the calculated length of the data after bit interleaving is defined as W bits, that is, when obtaining the data to be processed after bit selection, data with a length of W bits needs to be obtained, and W is the total number of bits of the data to be processed.

[0207] The PDSCH parameters in the above scheduling information may include: PDSCH channel symbol number PDSCH symb , where the subscript symb indicates the symbol; the number of PRBs PRB, the number of symbols symb, the number of PRBs in each symbol The number of streams in the stream map layer.

[0208] The number of REs scheduled by the base station each time NUM The calculation formula is as follows:

[0209]

[0210] S902, calculating the length of the data to be processed based on the number of REs, the modulation order, and the number of REs to be scheduled in each CB.

[0211] The calculation formula for the length W of the data to be processed is as follows:

[0212]

[0213] Where Q represents the modulation order, CB NUM Indicates the number of CBs, It represents the number of REs that need to be scheduled in each CB, W represents the number of valid bits that meet the needs of this scheduling, and it is used as the length of the data to be processed obtained after the bit selection.

[0214] In addition, the parallel bit width can be configured based on the length of the data to be processed. The longer the length, the larger the parallel bit width setting.

[0215] In an embodiment of the present invention, by calculating the number of PDSCH channel symbols, the number of PRBs PRB, the number of symbols symb, the number of streams of stream mapping, the modulation order, and the number of CBs, the length of the data to be processed that meets the scheduling requirements is obtained. Since the bit interleaving process does not change the data length, the bit interleaving result finally output is also the length of the data to be processed, so that the bit interleaving result of the length specified by the protocol requirements can be generated subsequently.

[0216] In one embodiment of the present invention, the length of the data to be processed is calculated by an FPGA where the bit interleaver is located, or calculated by other equipment outside the base station.

[0217] In addition, it can also be calculated by removing the FPGA from other parts of the base station.

[0218] In the case where the length of the data to be processed is calculated externally by the FPGA, the FPGA may directly obtain the length of the data to be processed from the outside.

[0219] The preset FPGA calculation parameters are used to control whether the FPGA calculates the length of the data to be processed. The preset FPGA calculation parameters are defined in the macro definition. According to the actual situation, the preset FPGA calculation parameters are modified to control whether the FPGA calculates the length of the data to be processed.

[0220] In the embodiment of the present invention, whether to calculate the length of the data to be processed by the FPGA is controlled by a preset FPGA calculation parameter, and the calculation can be performed inside the FPGA or outside the FPGA. In the case that the device outside the base station has calculated the length of the data to be processed, the length of the data to be processed can be directly obtained from the device outside the base station. In the case that the device outside the base station has not calculated the length of the data to be processed, the length of the data to be processed can be calculated by the FPGA.

[0221] For an example, see Fig.10 , Fig.10 The first process diagram of bit interleaving provided in the embodiment of the present invention is as follows. After the bit interleaving is started, the following steps B1-B9 are required to end the bit interleaving process.

[0222] B1, determine the parallel bit width and obtain the modulation order according to the preset requirements.

[0223] The preset requirements may be the amount of data to be processed, resource occupancy, etc. If the amount of data to be processed is large, a larger parallel bit width may be set; if the resource occupancy rate is high, a smaller parallel bit width may be set.

[0224] B2, based on the determined parallel bit width and the acquired modulation order, change the parallel bit width and the modulation order in the macro definition.

[0225] B3, based on preset FPGA calculation parameters, determine whether to calculate the length of the data to be processed through FPGA.

[0226] If yes, execute step B4 to calculate the length of the data to be processed according to the scheduling information.

[0227] If not, execute step B5 to obtain the length of the data to be processed from outside the FPGA.

[0228] Specifically, it is determined whether the preset FPGA calculation parameter represents the length of the data to be processed calculated by the FPGA.

[0229] When the preset FPGA calculation parameters indicate that the length of the data to be processed is calculated by the FPGA, the length of the data to be processed is calculated by the FPGA; when the preset FPGA calculation parameters indicate that the length of the data to be processed is not calculated by the FPGA, the length of the data to be processed is obtained from outside the FPGA.

[0230] B6, obtaining the data to be processed based on the length of the data to be processed.

[0231] B7, write the acquired data to be processed into a cache space.

[0232] Specifically, write addresses are generated by accumulation, and data having a length of not more than 1 bit width is written at each write address.

[0233] B8, performs byte interleaving based on the data written in the cache space to generate a byte interleaving result.

[0234] B9, based on the inter-byte interleaving result, performs intra-byte interleaving to generate an intra-byte interleaving result.

[0235] The intra-byte interleaving result is the bit interleaving result. For the specific inter-byte interleaving and intra-byte interleaving processes, please refer to the above-mentioned related content, which will not be repeated here.

[0236] For an example, see Fig.11 , Fig.11 A second process flow diagram for performing bit interleaving provided in an embodiment of the present invention is shown in the figure. Based on the setting of the parallel bit width in the macro definition file, the bit interleaving process represented by the following steps C1-C5 is controlled.

[0237] C1, determine the target bit width and target modulation order according to the settings of parallel bit width and modulation order in the file in the macro definition.

[0238] C2, based on the target data length of the data to be processed calculated from the FPGA or directly obtained from the outside of the FPGA, accumulates and generates a write address, and generates an interleaved read address. The write address can be recorded as waddr, and the read address can be recorded as raddr.

[0239] The generated write address and read address can be adaptively adjusted according to the determined target parallel bit width.

[0240] C3, writes the data to be processed with a length equal to the target data length to a cache space set based on the XPM primitive.

[0241] C4, performs byte-to-byte interleaving based on the interleaved read address and the data written in the cache space to generate an inter-byte interleaving result.

[0242] C5, based on the inter-byte interleaving result, performs intra-byte interleaving to generate a bit interleaving result.

[0243] The intra-byte interleaving process can also be adaptively adjusted according to the determined target parallel bit width.

[0244] The embodiment of the present invention also provides a bit interleaver, see Fig.12 , Fig.12 A schematic diagram of the structure of a bit interleaver provided in an embodiment of the present invention, wherein the bit interleaver includes a memory 1201, a transceiver 1202, and a processor 1203:

[0245] The memory 1201 is used to store computer programs; the transceiver 1202 is used to send and receive data under the control of the processor 1203; the processor 1203 is used to read the computer program in the memory 1201 and perform the following operations:

[0246] Determine the parallel bit width and the modulation order of the base station where the bit interleaver is located, and obtain the data to be processed;

[0247] Writing a target bit group in the data to be processed to a write address in a cache space in a memory, wherein the initial target bit group is the frontmost bit group of the data to be processed, and the length of each target bit group is the parallel bit width;

[0248] The next bit group adjacent to the current target bit group is used as a new target bit group, and the parallel bit width is accumulated on the basis of the current write address to obtain a new write address;

[0249] Returning to the step of writing the target bit group in the data to be processed to the write address in the cache space in a memory, until all the data to be processed are written into the cache space;

[0250] Read a bit group having a length equal to the parallel bit width from a read address in the cache space;

[0251] Accumulating a preset address offset on the basis of the current read address to obtain a new read address, wherein the initial read address is the starting address of the cache space, the preset address offset is equal to the length of a row of data in the cache space, and the number of data rows in the cache space is equal to the modulation order;

[0252] Return to executing the step of reading a bit group having a length equal to the parallel bit width from the read address in the cache space until the read bit group is located at the last row in the cache space;

[0253] The read address is adjusted to the starting address of the unread data in the first row of the cache space, and the step of reading a bit group having a length equal to the parallel bit width from the read address in the cache space is returned to perform the next round of bit group reading until all the data in the cache space is read out;

[0254] The read bit group is subjected to intra-byte interleaving processing to obtain a bit interleaving result.

[0255] Among them, Fig.12 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 1203 and various circuits of memory represented by memory 1201 are linked together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 1202 may be a plurality of components, namely, a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium, which transmission medium may include a wireless channel, a wired channel, an optical cable, and other transmission media. The processor 1203 is responsible for managing the bus architecture and general processing, and the memory 1201 may store data used by the processor 1203 when performing operations.

[0256] The processor 1203 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). The processor may also adopt a multi-core architecture.

[0257] In the process of performing bit interleaving using the bit interleaver provided by the embodiment of the present invention, when reading data, the next reading is performed with a preset address offset as an interval, that is, the next data reading is performed with the length of a row of data in the cache space as an interval, so that the data read next time is located in a position of different rows in the same column, thereby realizing vertical column-by-column reading and a parallel bit interleaving process. In addition, since the bit interleaver only writes the data to be processed into the cache space in a memory, the waste of cache space is reduced.

[0258] In one embodiment of the present invention, intra-byte interleaving processing is performed on the read bit group to obtain a bit interleaving result, which specifically includes:

[0259] For the bit groups read in the target round, the data of the target position is obtained from each bit group in sequence according to the order in which each bit group is read, 1 is added to the current target position to obtain a new target position, and the step of obtaining the data of the target position from each bit group in sequence according to the order in which each bit group is read is returned to be executed until all the bits in the bit group of the target round are obtained, wherein the initial value of the target position is the first position;

[0260] Add 1 to the current target round to obtain a new target round, adjust the target position to the initial value, return to execute the step of obtaining the data of the target position from each bit group in the order in which each bit group is read, until all bits in the bit groups read in each round are obtained;

[0261] Arrange the bits in the order of acquisition to obtain the bit interleaving result.

[0262] In the embodiment of the present invention, intra-byte interleaving is performed so that the data in the output bit interleaving result is completely disrupted based on the data to be processed, and there is no data arranged in the order of the original data to be processed, thereby ensuring the accuracy of the bit interleaving result.

[0263] In one embodiment of the present invention, the parallel bit width and the modulation order are set based on the primitive, the parallel bit width is defined in the macro definition and can be modified, and when the parallel bit width is modified to the target bit width, the parallel bit width determined by the bit interleaver is the target bit width; the length of each target bit group is the target bit width;

[0264] Accumulating the parallel bit width based on the current write address specifically includes: accumulating the target bit width based on the current write address; reading a bit group with a length of the parallel bit width from the read address in the cache space specifically includes: reading a bit group with a length of the target bit width from the read address in the cache space.

[0265] In the embodiment of the present invention, since the parallel bit width and the modulation order are set based on the primitive, the parallel bit width and the modulation order are relatively easy to modify according to actual needs, so that subsequent steps are performed based on the modified parallel bit width and modulation order, thereby realizing the adaptation of the bit interleaving process to the parallel bit width and modulation order, and improving the processing flexibility.

[0266] In one embodiment of the present invention, the length of the data to be processed is calculated in the following manner: based on the number of channel symbols of the physical downlink shared channel PDSCH of the base station, the number of PRBs in each symbol, and the number of streams mapped by the stream, the number of REs scheduled each time by the base station is calculated; based on the number of REs, the modulation order, and the number of REs that need to be scheduled in each CB, the length of the data to be processed is calculated.

[0267] In an embodiment of the present invention, by calculating the number of PDSCH channel symbols, the number of PRBs PRB, the number of symbols symb, the number of streams of stream mapping, the modulation order, and the number of CBs, the length of the data to be processed that meets the scheduling requirements is obtained. Since the bit interleaving process does not change the data length, the bit interleaving result finally output is also the length of the data to be processed, so that the bit interleaving result of the length specified by the protocol requirements can be generated subsequently.

[0268] In one embodiment of the present invention, the length of the data to be processed is calculated by a programmable logic array FPGA where the bit interleaver is located, or calculated by other equipment outside the base station; the preset FPGA calculation parameters are used to control whether the FPGA calculates the length of the data to be processed.

[0269] In the embodiment of the present invention, whether to calculate the length of the data to be processed by the FPGA is controlled by a preset FPGA calculation parameter, and the calculation can be performed inside the FPGA or outside the FPGA. In the case that the device outside the base station has calculated the length of the data to be processed, the length of the data to be processed can be directly obtained from the device outside the base station. In the case that the device outside the base station has not calculated the length of the data to be processed, the length of the data to be processed can be calculated by the FPGA.

[0270] The embodiment of the present invention further provides a bit interleaving device, which is applied to a bit interleaver, see Fig.13 , Fig.13 A schematic diagram of the structure of a bit interleaving device provided in an embodiment of the present invention, the device comprising:

[0271] The parameter determination module 1301 is used to determine the parallel bit width and the modulation order of the base station where the bit interleaver is located, and obtain the data to be processed;

[0272] The data writing module 1302 is used to write a target bit group in the data to be processed to a write address in a cache space in a memory, the initial target bit group is the frontmost bit group of the data to be processed, and the length of each target bit group is the parallel bit width;

[0273] The next bit group adjacent to the current target bit group is used as a new target bit group, and the parallel bit width is accumulated on the basis of the current write address to obtain a new write address;

[0274] Returning to the step of writing the target bit group in the data to be processed to the write address in the cache space in a memory, until all the data to be processed are written into the cache space;

[0275] The data reading module 1303 is used to read a bit group having a length equal to the parallel bit width from a reading address in the cache space;

[0276] Accumulating a preset address offset on the basis of the current read address to obtain a new read address, wherein the initial read address is the starting address of the cache space, the preset address offset is equal to the length of a row of data in the cache space, and the number of data rows in the cache space is equal to the modulation order;

[0277] Return to executing the step of reading a bit group having a length equal to the parallel bit width from the read address in the cache space until the read bit group is located at the last row in the cache space;

[0278] The read address is adjusted to the starting address of the unread data in the first row of the cache space, and the step of reading a bit group having a length equal to the parallel bit width from the read address in the cache space is returned to perform the next round of bit group reading until all the data in the cache space is read out;

[0279] The result generating module 1304 is used to perform intra-byte interleaving processing on the read bit group to obtain a bit interleaving result.

[0280] In an embodiment of the present invention, when reading data, the next reading is performed with a preset address offset as an interval, that is, the next data reading is performed with the length of a row of data in the cache space as an interval, so that the data read next time is located in a different row of the same column, thereby realizing vertical column-by-column reading and a parallel bit interleaving process, and because the bit interleaver only writes the data to be processed into the cache space in a memory, the waste of cache space is reduced.

[0281] In one embodiment of the present invention, the result generation module 1304 is specifically used to:

[0282] For the bit groups read in the target round, the data of the target position is obtained from each bit group in sequence according to the order in which each bit group is read, 1 is added to the current target position to obtain a new target position, and the step of obtaining the data of the target position from each bit group in sequence according to the order in which each bit group is read is returned to be executed until all the bits in the bit group of the target round are obtained, wherein the initial value of the target position is the first position;

[0283] Add 1 to the current target round to obtain a new target round, adjust the target position to the initial value, return to execute the step of obtaining the data of the target position from each bit group in the order in which each bit group is read, until all bits in the bit groups read in each round are obtained;

[0284] Arrange the bits in the order of acquisition to obtain the bit interleaving result.

[0285] In the embodiment of the present invention, intra-byte interleaving is performed so that the data in the output bit interleaving result is completely disrupted based on the data to be processed, and there is no data arranged in the order of the original data to be processed, thereby ensuring the accuracy of the bit interleaving result.

[0286] In one embodiment of the present invention, the parallel bit width and the modulation order are set based on the primitive, the parallel bit width is defined in the macro definition and can be modified, and when the parallel bit width is modified to the target bit width, the parallel bit width determined by the bit interleaver is the target bit width; the length of each target bit group is the target bit width;

[0287] The data writing module is used to accumulate the parallel bit width based on the current writing address, specifically to: accumulate the target bit width based on the current writing address;

[0288] The data reading module is used to read a bit group with a length of parallel bit width from a reading address in the cache space, specifically to read a bit group with a length of target bit width from a reading address in the cache space.

[0289] In the embodiment of the present invention, since the parallel bit width and the modulation order are set based on the primitive, the parallel bit width and the modulation order are relatively easy to modify according to actual needs, so that subsequent steps are performed based on the modified parallel bit width and modulation order, thereby realizing the adaptation of the bit interleaving process to the parallel bit width and modulation order, and improving the processing flexibility.

[0290] In one embodiment of the present invention, the device also includes: a data length calculation module, which is used to calculate the length of the data to be processed in the following manner: based on the number of channel symbols of the physical downlink shared channel PDSCH of the base station, the number of PRBs in each symbol, and the number of streams mapped by the stream, the number of REs scheduled each time by the base station is calculated; based on the number of REs, the modulation order, and the number of REs that need to be scheduled in each CB, the length of the data to be processed is calculated.

[0291] In an embodiment of the present invention, by calculating the number of PDSCH channel symbols, the number of PRBs PRB, the number of symbols symb, the number of streams of stream mapping, the modulation order, and the number of CBs, the length of the data to be processed that meets the scheduling requirements is obtained. Since the bit interleaving process does not change the data length, the bit interleaving result finally output is also the length of the data to be processed, so that the bit interleaving result of the length specified by the protocol requirements can be generated subsequently.

[0292] In one embodiment of the present invention, the length of the data to be processed is calculated by a programmable logic array FPGA where the bit interleaver is located, or calculated by other equipment outside the base station; the preset FPGA calculation parameters are used to control whether the FPGA calculates the length of the data to be processed.

[0293] In the embodiment of the present invention, whether to calculate the length of the data to be processed by the FPGA is controlled by a preset FPGA calculation parameter, and the calculation can be performed inside the FPGA or outside the FPGA. In the case that the device outside the base station has calculated the length of the data to be processed, the length of the data to be processed can be directly obtained from the device outside the base station. In the case that the device outside the base station has not calculated the length of the data to be processed, the length of the data to be processed can be calculated by the FPGA.

[0294] In another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned bit interleaving methods are implemented.

[0295] In the process of bit interleaving using the computer program stored in the computer-readable storage medium provided by the embodiment of the present invention, when reading data, the next reading is performed with a preset address offset as an interval, that is, the next data reading is performed with the length of a row of data in the cache space as an interval, so that the data read next time is located in a different row of the same column, thereby realizing vertical column-by-column reading and a parallel bit interleaving process. In addition, since the bit interleaver only writes the data to be processed into the cache space in a memory, the waste of cache space is reduced.

[0296] In another embodiment of the present invention, a computer program product including instructions is provided, which, when executed on a computer, enables the computer to execute any one of the bit interleaving methods in the above embodiments.

[0297] In the process of performing bit interleaving using the computer program product provided by the embodiment of the present invention, when reading data, the next reading is performed with a preset address offset as an interval, that is, the next data reading is performed with the length of a row of data in the cache space as an interval, so that the data read next time is located in a different row of the same column, thereby realizing vertical column-by-column reading and a parallel bit interleaving process, and because the bit interleaver only writes the data to be processed into the cache space in a memory, the waste of cache space is reduced.

[0298] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0299] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0300] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the bit interleaver, device, computer-readable storage medium, and computer program product embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0301] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A bit interleaving method, characterized in that: Applied to a bit interleaver, the method comprises: Determine the parallel bit width and the modulation order of the base station where the bit interleaver is located, and obtain data to be processed; Writing a target bit group in the data to be processed to a write address in a cache space in a memory, wherein an initial target bit group is a frontmost bit group of the data to be processed, and a length of each target bit group is the parallel bit width; Taking the next bit group adjacent to the current target bit group as a new target bit group, and accumulating the parallel bit width on the basis of the current write address to obtain a new write address; Returning to the step of writing the target bit group in the data to be processed into the write address in the cache space in a memory until all the data to be processed are written into the cache space; Reading a bit group having a length equal to the parallel bit width from a read address in the cache space; Accumulating a preset address offset on the basis of the current read address to obtain a new read address, wherein the initial read address is the starting address of the cache space, the preset address offset is equal to the length of a row of data in the cache space, and the number of data rows in the cache space is equal to the modulation order; Returning to the step of reading a bit group having a length of the parallel bit width from the read address in the cache space, until the read bit group is located in the last row in the cache space; The read address is adjusted to the starting address of the unread data in the first row of the cache space, and the step of reading a bit group having a length of the parallel bit width from the read address in the cache space is returned to perform the next round of bit group reading until all the data in the cache space is read out; The read bit group is subjected to intra-byte interleaving processing to obtain a bit interleaving result.

2. The method according to claim 1, characterized in that The step of performing intra-byte interleaving processing on the read bit group to obtain a bit interleaving result includes: For the bit groups read in the target round, in the order in which the bit groups are read, data of the target position is obtained from each bit group in sequence, 1 is added to the current target position to obtain a new target position, and the step of obtaining data of the target position from each bit group in sequence in the order in which the bit groups are read is returned to be executed until all bits in the bit groups of the target round are obtained, wherein the initial value of the target position is the first position; Add 1 to the current target round to obtain a new target round, adjust the target position to the initial value, return to execute the step of obtaining data of the target position from each bit group in the order in which each bit group is read, until all bits in the bit groups read in each round are obtained; Arrange the bits in the order of acquisition to obtain the bit interleaving result.

3. The method according to claim 1, characterized in that The parallel bit width and the modulation order are set based on primitives, the parallel bit width is defined in a macro definition and can be modified, and when the parallel bit width is modified to a target bit width, the parallel bit width determined by the bit interleaver is the target bit width; The length of each target bit group is the target bit width; The step of accumulating the parallel bit width based on the current write address includes: Accumulate the target bit width based on the current write address; The step of reading a bit group having a length equal to the parallel bit width from a read address in the cache space comprises: A bit group having a length equal to the target bit width is read from a read address in the cache space.

4. The method according to any one of claims 1 to 3, characterized in that The length of the data to be processed is calculated in the following way: Calculate the number of resource units RE scheduled by the base station each time based on the number of physical downlink shared channel PDSCH channel symbols of the base station, the number of physical resource blocks PRB in each symbol, and the number of streams of stream mapping; The length of the data to be processed is calculated based on the number of REs, the modulation order and the number of REs that need to be scheduled in each code block CB.

5. The method according to claim 4, characterized in that The length of the data to be processed is calculated by a programmable logic array FPGA where the bit interleaver is located, or calculated by other equipment outside the base station; The preset FPGA calculation parameters are used to control whether the FPGA calculates the length of the data to be processed.

6. A bit interleaver, characterized in that: Including memory, transceiver, processor: A memory for storing a computer program; a transceiver for transmitting and receiving data under the control of the processor; and a processor for reading the computer program in the memory and performing the following operations: Determine the parallel bit width and the modulation order of the base station where the bit interleaver is located, and obtain data to be processed; Writing a target bit group in the data to be processed to a write address in a cache space in a memory, wherein an initial target bit group is a frontmost bit group of the data to be processed, and a length of each target bit group is the parallel bit width; Taking the next bit group adjacent to the current target bit group as a new target bit group, and accumulating the parallel bit width on the basis of the current write address to obtain a new write address; Returning to the step of writing the target bit group in the data to be processed into the write address in the cache space in a memory until all the data to be processed are written into the cache space; Reading a bit group having a length equal to the parallel bit width from a read address in the cache space; Accumulating a preset address offset on the basis of the current read address to obtain a new read address, wherein the initial read address is the starting address of the cache space, the preset address offset is equal to the length of a row of data in the cache space, and the number of data rows in the cache space is equal to the modulation order; Returning to the step of reading a bit group having a length of the parallel bit width from the read address in the cache space, until the read bit group is located in the last row in the cache space; The read address is adjusted to the starting address of the unread data in the first row of the cache space, and the step of reading a bit group having a length of the parallel bit width from the read address in the cache space is returned to perform the next round of bit group reading until all the data in the cache space is read out; The read bit group is subjected to intra-byte interleaving processing to obtain a bit interleaving result.

7. The bit interleaver according to claim 6, characterized in that: The intra-byte interleaving process is performed on the read bit group to obtain a bit interleaving result, specifically including: For the bit groups read in the target round, in the order in which the bit groups are read, data of the target position is obtained from each bit group in sequence, 1 is added to the current target position to obtain a new target position, and the step of obtaining data of the target position from each bit group in sequence in the order in which the bit groups are read is returned to be executed until all bits in the bit groups of the target round are obtained, wherein the initial value of the target position is the first position; Add 1 to the current target round to obtain a new target round, adjust the target position to the initial value, return to execute the step of obtaining data of the target position from each bit group in the order in which each bit group is read, until all bits in the bit groups read in each round are obtained; Arrange the bits in the order of acquisition to obtain the bit interleaving result.

8. The bit interleaver according to claim 6, characterized in that: The parallel bit width and the modulation order are set based on primitives, the parallel bit width is defined in a macro definition and can be modified, and when the parallel bit width is modified to a target bit width, the parallel bit width determined by the bit interleaver is the target bit width; The length of each target bit group is the target bit width; The step of accumulating the parallel bit width based on the current write address specifically includes: Accumulate the target bit width based on the current write address; The step of reading a bit group having a length of the parallel bit width from a read address in the cache space specifically includes: A bit group having a length equal to the target bit width is read from a read address in the cache space.

9. A bit interleaving device, characterized in that: Applied to a bit interleaver, the device comprises: A parameter determination module, used to determine the parallel bit width and the modulation order of the base station where the bit interleaver is located, and obtain data to be processed; A data writing module is used to write a target bit group in the data to be processed to a write address in a cache space in a memory, wherein the initial target bit group is the frontmost bit group of the data to be processed, and the length of each target bit group is the parallel bit width; Taking the next bit group adjacent to the current target bit group as a new target bit group, and accumulating the parallel bit width on the basis of the current write address to obtain a new write address; Returning to the step of writing the target bit group in the data to be processed into the write address in the cache space in a memory until all the data to be processed are written into the cache space; A data reading module, used for reading a bit group having a length equal to the parallel bit width from a reading address in the cache space; Accumulating a preset address offset on the basis of the current read address to obtain a new read address, wherein the initial read address is the starting address of the cache space, the preset address offset is equal to the length of a row of data in the cache space, and the number of data rows in the cache space is equal to the modulation order; Returning to the step of reading a bit group having a length of the parallel bit width from the read address in the cache space, until the read bit group is located in the last row in the cache space; The read address is adjusted to the starting address of the unread data in the first row of the cache space, and the step of reading a bit group having a length of the parallel bit width from the read address in the cache space is returned to perform the next round of bit group reading until all the data in the cache space is read out; The result generating module is used to perform intra-byte interleaving processing on the read bit group to obtain a bit interleaving result.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of claims 1 to 5 are implemented.

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