Digital front-end processing system suitable for ORAN equipment

Abstract

The invention discloses a digital front-end processing system suitable for ORAN equipment. The digital front-end processing system comprises an ORAN forward transmission interface, a downlink, an uplink, a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module and a TA timing management module. The downlink comprises a Beamforming Managent module, an OFDM (Orthogonal Frequency Division Multiplexing) module, a Channel Filter module, a DUC-DDC Mixer module, a CFR (Computational Fluid Ratio) algorithm module, a DPD (Digital Pre-Distortion) algorithm module and a PAP (Picture Access Point) module; and the uplink comprises a Beamforming module, a frequency compensation module, a temperature compensation module, a PIM Cancellation module and a PRACH (Physical Random Access Channel) processing module. According to the radio frequency equipment meeting the standard, a unified system test and management scheme can be realized, and radio frequency equipment and digital equipment of different manufacturers can be butted.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communication equipment, and in particular to a digital front-end processing system suitable for ORAN equipment. Background Art

[0002] Traditional wireless access network equipment uses CPRI and eCPRI interfaces, and the interface protocols are relatively closed. The interface protocols of different manufacturers are different, and the data front-end uplink and downlink processing of each manufacturer has different layered processing, resulting in more interfaces for each module and data links that are not uniform. As a result, the RF equipment and digital equipment of different manufacturers are incompatible, and the equipment docking and debugging are cumbersome and complicated, lacking a unified system testing and equipment management solution. The open radio access network, referred to as ORAN, uses an independent building block design to allow interoperability between cellular network equipment developed by different vendors. With the development of technology and the improvement of data processing capabilities, ORU, as a component of ORAN, will have a wider range of applications.

[0003] To address this problem, a FPGA-based digital front-end processing system suitable for ORAN ORU equipment was developed. Summary of the invention

[0004] The object of the present invention is to provide a digital front-end processing system suitable for ORAN equipment to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions: a digital front-end processing system suitable for ORAN equipment, including an ORAN fronthaul interface, a downlink, an uplink, a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module and a TA timing management module;

[0006] The downlink includes a Beamforming Management module, an OFDM module, a Channel Filter module, a DUC-DDC Mixer module, a CFR algorithm module, a DPD algorithm module, and a PAP module; the uplink includes a Beamforming module, a frequency compensation module, a temperature compensation module, a PIM Cancellation module, and a PRACH channel processing module;

[0007] The PIM Cancellation module includes a passive intermodulation cancellation system. The entire system runs on the XCZU67 RF-SoC hardware platform and includes a PS processing unit, a PL logic unit, and a radio frequency link. PIM usually occurs in the radio frequency link. It includes PIMI and PIMD software algorithm control and PIMC custom logic modules. The PIMD and PIMI modules are implemented by software control in dual-frequency devices. The PIMC module needs to be processed in real time by FPGA custom logic. The input and configuration are determined by the PIMD and PIMI modules. The Data Capture required by PIMD and PIMI is also completed by FPGA, and the PS processing unit needs to be configured for this purpose.

[0008] Preferably, the ORAN fronthaul interface includes:

[0009] 10 / 25G line rate Fronthaul Interface;

[0010] C-Plane, U-Plane, S-Plane, M-Plane link data processing;

[0011] Beamforming Management;

[0012] AXI-Lite configuration interface;

[0013] Fronthaul Interface Package filter module processing;

[0014] ORAN router module;

[0015] Support 1588v2 protocol;

[0016] Supports module simulation and system simulation.

[0017] Preferably, the Beamforming Management module is used to perform weight processing on all IQ data according to the time information provided by the timing module.

[0018] Preferably, the OFDM module is used to perform mutual conversion between the frequency domain and the time domain, supports up to 8 antennas, and up to 8 CCs are dynamically aggregated on a specific antenna; the OFDM module performs partial mapping of subcarriers, FFT / IFFT conversion, scaling and cyclic prefix insertion / deletion, and supports the following functions:

[0019] The maximum sampling rate is 491.52MSPS;

[0020] Supports up to 8 CCs, supporting LTE and 5G-NR;

[0021] Supports 15kHz, 30kHz and 60kHz subcarrier spacing (SCS) (FR1); supports 512, 1K, 2K and 4K FFT sizes;

[0022] Supports up to 8 downlinks or uplinks;

[0023] Each I or Q sample uses a 16-bit data interface;

[0024] Enable CC programming through the processor interface;

[0025] Provides CC buffer overflow indication via status register;

[0026] Delay matching passes through the TUSER information accompanying the data in the IP core.

[0027] Preferably, the functions supported by the Channel Filter module are as follows:

[0028] Each instance supports up to 16 CCs;

[0029] Supports 8 programmable coefficient sets;

[0030] 16-bit coefficients, up to 256 Tap Engines or 128 Tap Engines; 16-bit or 18-bit I+Q input and output, AXI4-Stream interface;

[0031] Flexible time-division multiplexing of multiple component carriers and antennas;

[0032] Support time division duplex switching of uplink and downlink channels;

[0033] Delay-compensated sideband channels for sampling accurate frames;

[0034] Trigger coefficient switching, buffer refresh, uplink / downlink switching;

[0035] Support power-off and dynamic power saving modes;

[0036] A memory mapped AXI4-Lite control and status interface is provided with a software API. Preferably, the functions supported by the DUC-DDCMixer module are as follows:

[0037] Supports up to 16 component carriers and up to 8 antennas;

[0038] Interpolation and decimation factors up to 16 times;

[0039] Cordic-based dual-mode NCO for frequency error-free operation; 16-bit or 18-bit I+Q input and output, AXI4-Stream interface;

[0040] Flexible time-division multiplexing of multiple component carriers and antennas;

[0041] Delay-compensated sideband channels for sampling accurate frames;

[0042] Trigger parameter change operations and buffer flushes;

[0043] Support power-off and dynamic power saving modes;

[0044] Provides an AXI4-Lite memory-mapped control and status interface with a software API;

[0045] Supports uplink and downlink channel switching.

[0046] Preferably, the CFR algorithm module is used to subtract a spectrum-shaped pulse matching the input signal spectrum from the signal peak value exceeding the threshold, thereby reducing the signal peak-to-average ratio;

[0047] The CFR algorithm module functional modules include a peak detection module, a peak scaling module, a distributor, and a peak clipping pulse generator. The peak detection module first calculates the amplitude and phase of the input signal, and then indicates the amplitude and phase that exceed the threshold;

[0048] The peak value and phase detected by the peak scaling module are used as the input of this module. The module determines the complex scaling, and its scaling amplitude is equal to the difference between the signal peak value and the threshold value. The phase is the phase information of the peak signal;

[0049] The distributor includes a peak distributor and a CPG distributor, wherein the peak distributor calculates an indication signal after peak scaling according to the provided peak delay and the set maximum allowable delay, and the indication signal corresponds to the scaling factor;

[0050] The clipping pulse of the clipping pulse generator is designed to have the same frequency band as the input signal. The coefficient of the clipping pulse can be obtained through the filter design method. First, a prototype filter that matches the single-carrier spectrum should be designed. If the input signal is a single carrier, the coefficient of the prototype filter is the coefficient required for the clipping pulse. For multi-carrier configuration, frequency shifting should be performed on the basis of the prototype filter. The replica of the prototype filter after shifting is required to be placed at the center frequency of each carrier. Then these replicas of the prototype filter are added together to obtain a composite multi-band filter. The coefficient of the composite multi-band filter is the coefficient required for peak clipping.

[0051] Preferably, the DPD algorithm module is implemented on Matlab, and the entire DPD simulation architecture is mainly composed of three modules, including a source data reading module, a PD model calculation module, and a PA output calculation module;

[0052] The source data reading model is used to read forward and feedback data. It obtains data from the mat file collected by Xilinx software. There are 8192 32-bit read data in the mat file, of which the first 4096 data are used as tx_data forward data, and the following 4096 data are used as rx_data receiving data. The 32-bit rx_data is converted into 16-bit two-way signed I and Q signals, and the two-way signals are interpolated into one way with 8192 points.

[0053] The data rx_data after the PA is processed by a filter, and the output is the feedback data fb_data of the PA. The feedback data is the data amplified by the power amplifier PA. The amplification factor of the feedback data, i.e., the gain, needs to be eliminated. The method of gain elimination is to divide the power of the transmitted signal by the power of the feedback signal to obtain its amplification factor, and then divide the feedback signal by the amplification factor, so that the feedback data without amplification can be obtained;

[0054] The PD model calculation module is used to realize the pre-distortion function. PD usually adopts a memory polynomial structure. Here you can write code to select different PD model types. The PD model calculation module also needs to read the source data first. The process is the same as the PA reading data source. After that, the dpd_process function is used to calculate the parameters of the PD module.

[0055] In dpd_process, the input signal and feedback signal are first synchronized and power aligned, then the corresponding PD model is selected according to the power amplifier model, and finally the parameters of the PD polynomial are calculated according to the forward and feedback data and stored in the corresponding data file for subsequent processing. After the PD parameters are calculated, the parameters are saved, and then the calculation of the PD polynomial needs to be implemented. The memory polynomial structure is usually used to describe the PD model, and the PD coefficient is obtained by reading the parameter data file. If there is no data file, the default output is equal to the input, that is, there is no PD function.

[0056] Preferably, the PAP module adopts Verilog coding language, and its functions are divided into three large modules: PAP_CTRL module, SRL_DET module, and Data_Ramping module, to realize common protection of PA.

[0057] Preferably, the functions supported by the PRACH channel processing module are as follows:

[0058] Supports up to three independent frequency bands;

[0059] Supports up to 8 antennas with 16 component carriers per antenna on each frequency band;

[0060] Up to 245.76MSPS component carrier sampling rate;

[0061] 16-bit or 18-bit IQ data input, 16-bit IQ data output;

[0062] AXI4-Stream data interface with flexible time-division multiplexing;

[0063] Each antenna processes up to 16 PRACH channels across all component carriers;

[0064] Supports all LTE and 5G NR PRACH formats;

[0065] Memory-mapped AXI interface for control, status, and static PRACH scheduling;

[0066] Optional ax4-stream control interface for dynamic scheduling;

[0067] Power-down and dynamic power-saving modes.

[0068] Compared with the prior art, the present invention has the following beneficial effects:

[0069] The system modular design framework facilitates the migration of different hardware solutions, accelerates the R&D cycle, covers the entire product R&D and testing cycle, supports seamless docking of equipment from different ORAN vendors, ORAN Interface / BeamformingManagement / PIMC Cancellation / PAP, OFDM / DFE Channel Filter / DFE DUC / DDC Mixer / CFR / DPD / PRACH / AGC, Power Meter / TA Timing / Temperature Frequency Compensation / Calibration Interface / DFE unified peripheral management, and signal simulation analysis for in-depth data simulation and analysis at multiple module points on the link. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 It is a schematic diagram of the structure of the present invention;

[0071] Figure 2 This is a schematic diagram of the ORAN fronthaul interface of the present invention;

[0072] Figure 3 It is a schematic diagram of the Beamforming Management module of the present invention;

[0073] Figure 4This is a schematic diagram of an OFDM module of the present invention;

[0074] Figure 5 This is a schematic diagram of the Channel Filter module of the present invention;

[0075] Figure 6 This is a schematic diagram of the DUC-DDC Mixer module of the present invention;

[0076] Figure 7 This is a schematic diagram of the CFR algorithm module of the present invention;

[0077] Figure 8 This is a schematic diagram of the DPD algorithm module of the present invention;

[0078] Fig. 9 This is a schematic diagram of a PAP module of the present invention;

[0079] Fig.10 This is a schematic diagram of the PIM Cancellation module of the present invention;

[0080] Fig.11 It is a schematic diagram of a PRACH channel processing module of the present invention. DETAILED DESCRIPTION

[0081] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0082] See also Figure 1-11 , the present invention provides a technical solution: a digital front-end processing system suitable for ORAN equipment, including an ORAN fronthaul interface, a downlink, an uplink, a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module and a TA timing management module;

[0083] The downlink includes a Beamforming Management module, an OFDM module, a Channel Filter module, a DUC-DDC Mixer module, a CFR algorithm module, a DPD algorithm module, and a PAP module; the uplink includes a Beamforming module, a frequency compensation module, a temperature compensation module, a PIM Cancellation module, and a PRACH channel processing module;

[0084] The PIM Cancellation module includes a passive intermodulation cancellation system. The entire system runs on the XCZU67 RF-SoC hardware platform 5, which includes a PS processing unit 4, a PL logic unit 6 and a RF link 8. PIM usually occurs in the RF link 8, which includes PIMI3 and PIMD2 software algorithm control and PIMC9 custom logic modules. The PIMD2 and PIMI3 modules are implemented by software control in dual-frequency devices. The PIMC9 module needs to be processed in real time by FPGA custom logic. The input and configuration are determined by the PIMD2 and PIMI3 modules. The Data Capture 7 required by PIMD2 and PIMI3 is also completed by the FPGA, and the PS processing unit 4 needs to be configured for this.

[0085] In the present invention, the ORAN fronthaul interface includes:

[0086] 10 / 25G line rate Fronthaul Interface;

[0087] C-Plane, U-Plane, S-Plane, M-Plane link data processing;

[0088] Beamforming Management;

[0089] AXI-Lite configuration interface;

[0090] Fronthaul Interface Package filter module processing;

[0091] ORAN router module;

[0092] Support 1588v2 protocol;

[0093] Supports module simulation and system simulation.

[0094] In the present invention, the Beamforming Management module is used to perform weight processing on all IQ data according to the time information provided by the timing module.

[0095] ORAN C-Plane section extension 1 applies to sending beamforming weights from O-DU to O-RU. When section extension 1 appears in the section description, the O-RU shall associate the beamforming weight set delivered in the section extension 1 with the beamforming weight set delivered in the section description. In subsequent C-Plane messages, the same beamId can be called without sending the beamforming weights again. The meaning of each field is as follows:

[0096]

[0097]

[0098] ORAN C-Plane section extension 2 is applicable to sending beamforming attributes from ODU to ORU;

[0099]

[0100] In the present invention, the OFDM module is used to perform mutual conversion between the frequency domain and the time domain, supports up to 8 antennas, and up to 8 CCs are dynamically aggregated on a specific antenna; the OFDM module performs partial mapping of subcarriers, FFT / IFFT conversion, scaling, and cyclic prefix insertion / deletion, and supports the following functions:

[0101] The maximum sampling rate is 491.52MSPS;

[0102] Supports up to 8 CCs, supporting LTE and 5G-NR;

[0103] Supports 15kHz, 30kHz and 60kHz subcarrier spacing (SCS) (FR1);

[0104] Supports 512, 1K, 2K and 4K FFT sizes;

[0105] Supports up to 8 downlinks or uplinks;

[0106] Each I or Q sample uses a 16-bit data interface;

[0107] Enable CC programming through the processor interface;

[0108] Provides CC buffer overflow indication via status register;

[0109] Delay matching passes through the TUSER information accompanying the data in the IP core.

[0110] In the present invention, the functions supported by the Channel Filter module are as follows:

[0111] Each instance supports up to 16 CCs;

[0112] Supports 8 programmable coefficient sets;

[0113] 16-bit coefficients, up to 256 Tap Engines or 128 Tap Engines;

[0114] 16-bit or 18-bit I+Q input and output, AXI4-Stream interface;

[0115] Flexible time-division multiplexing of multiple component carriers and antennas;

[0116] Support time division duplex switching of uplink and downlink channels;

[0117] Delay-compensated sideband channels for sampling accurate frames;

[0118] Trigger coefficient switching, buffer refresh, uplink / downlink switching;

[0119] Support power-off and dynamic power saving modes;

[0120] A memory mapped AXI4-Lite control and status interface is provided with a software API.

[0121] In the present invention, the functions supported by the DUC-DDC Mixer module are as follows:

[0122] Supports up to 16 component carriers and up to 8 antennas;

[0123] Interpolation and decimation factors up to 16 times;

[0124] Cordic-based dual-mode NCO for frequency error-free operation;

[0125] 16-bit or 18-bit I+Q input and output, AXI4-Stream interface;

[0126] Flexible time-division multiplexing of multiple component carriers and antennas;

[0127] Delay-compensated sideband channels for sampling accurate frames;

[0128] Trigger parameter change operations and buffer flushes;

[0129] Support power-off and dynamic power saving modes;

[0130] Provides an AXI4-Lite memory-mapped control and status interface with a software API;

[0131] Supports uplink and downlink channel switching.

[0132] In the present invention, the CFR algorithm module is used to subtract the spectrum-shaped pulse matching the input signal spectrum from the signal peak value exceeding the threshold, so as to reduce the signal peak-to-average ratio;

[0133] The CFR algorithm module functional modules include peak detection module, peak scaling module, distributor, and peak clipping pulse generator. The peak detection module first calculates the amplitude and phase of the input signal, and then indicates the amplitude and phase that exceed the threshold;

[0134] The peak value and phase detected by the peak scaling module are used as the input of this module. The module determines the complex scaling, and its scaling amplitude is equal to the difference between the signal peak value and the threshold value. The phase is the phase information of the peak signal;

[0135] The distributor includes a peak distributor and a CPG distributor, wherein the peak distributor calculates an indication signal after peak scaling according to the provided peak delay and the set maximum allowable delay, and the indication signal corresponds to the scaling factor;

[0136] The clipping pulse of the clipping pulse generator is designed to have the same frequency band as the input signal. The coefficient of the clipping pulse can be obtained through the filter design method. First, a prototype filter that matches the single-carrier spectrum should be designed. If the input signal is a single carrier, the coefficient of the prototype filter is the coefficient required for the clipping pulse. For multi-carrier configuration, frequency shifting should be performed on the basis of the prototype filter. The replica of the prototype filter after shifting is required to be placed at the center frequency of each carrier. Then these replicas of the prototype filter are added together to obtain a composite multi-band filter. The coefficient of the composite multi-band filter is the coefficient required for peak clipping.

[0137] In the present invention, the DPD algorithm module is implemented on Matlab, and the entire DPD simulation architecture is mainly composed of three modules, including a source data reading module, a PD model calculation module, and a PA output calculation module;

[0138] The source data reading model is used to read forward and feedback data. It obtains data from the mat file collected by Xilinx software. There are 8192 32-bit read data in the mat file, of which the first 4096 data are used as tx_data forward data, and the following 4096 data are used as rx_data receiving data. The 32-bit rx_data is converted into 16-bit two-way signed I and Q signals, and the two-way signals are interpolated into one way with 8192 points.

[0139] The data rx_data after the PA is processed by a filter, and the output is the feedback data fb_data of the PA. The feedback data is the data amplified by the power amplifier PA. The amplification factor of the feedback data, i.e., the gain, needs to be eliminated. The method of gain elimination is to divide the power of the transmitted signal by the power of the feedback signal to obtain its amplification factor, and then divide the feedback signal by the amplification factor, so that the feedback data without amplification can be obtained;

[0140] The PD model calculation module is used to realize the pre-distortion function. PD usually adopts a memory polynomial structure. Here you can write code to select different PD model types. The PD model calculation module also needs to read the source data first. The process is the same as the PA reading data source. After that, the dpd_process function is used to calculate the parameters of the PD module.

[0141] In dpd_process, the input signal and feedback signal are first synchronized and power aligned, then the corresponding PD model is selected according to the power amplifier model, and finally the parameters of the PD polynomial are calculated according to the forward and feedback data and stored in the corresponding data file for subsequent processing. After the PD parameters are calculated, the parameters are saved, and then the calculation of the PD polynomial needs to be implemented. The memory polynomial structure is usually used to describe the PD model, and the PD coefficient is obtained by reading the parameter data file. If there is no data file, the default output is equal to the input, that is, there is no PD function.

[0142] In the present invention, the PAP module adopts the Verilog coding language, and the function realization is divided into three large modules: PAP_CTRL module, SRL_DET module, and Data_Ramping module; and the PA is jointly protected.

[0143] In the present invention, the functions supported by the PRACH channel processing module are as follows:

[0144] Supports up to three independent frequency bands;

[0145] Supports up to 8 antennas with 16 component carriers per antenna on each frequency band;

[0146] Up to 245.76MSPS component carrier sampling rate;

[0147] 16-bit or 18-bit IQ data input, 16-bit IQ data output;

[0148] AXI4-Stream data interface with flexible time-division multiplexing;

[0149] Each antenna processes up to 16 PRACH channels across all component carriers;

[0150] Supports all LTE and 5G NR PRACH formats;

[0151] Memory-mapped AXI interface for control, status, and static PRACH scheduling;

[0152] Optional ax4-stream control interface for dynamic scheduling;

[0153] Power-down and dynamic power-saving modes.

[0154] The system of the present invention includes modules such as processing of C / U / S / M data of the ORAN fronthaul interface, downlink Beamforming Management, OFDM, Channel Filter, DUC Mixer, CFR, DPD, PAP, uplink Beamforming, frequency compensation, temperature compensation, PIM Cancellation, PRACH channel processing, calibration interface configuration, power measurement, etc. The radio frequency equipment that meets the standard can realize a unified system test and management solution, and realize the connection between radio frequency equipment and digital equipment from different manufacturers.

[0155] The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in the field. Although the embodiments of the present invention have been shown and described, it is understood by ordinary technicians in the field that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A digital front-end processing system suitable for ORAN equipment, characterized in that: Including ORAN fronthaul interface, downlink, uplink, calibration interface configuration module, power measurement interface configuration module, DEF unified peripheral management module and TATiming management module; The downlink includes a Beamforming Management module, an OFDM module, a Channel Filter module, a DUC-DDC Mixer module, a CFR algorithm module, a DPD algorithm module, and a PAP module; the uplink includes a Beamforming module, a frequency compensation module, a temperature compensation module, a PIM Cancellation module, and a PRACH channel processing module; The PIM Cancellation module includes a passive intermodulation cancellation system. The entire system runs on an XCZU67 RF-SoC hardware platform (5), including a PS processing unit (4), a PL logic unit (6) and a radio frequency link (8), wherein PIM usually occurs in the radio frequency link (8), and includes PIMI (3) and PIMD (2) software algorithm control and PIMC (9) custom logic modules, wherein the PIMD (2) and PIMI (3) modules are implemented by software control in a dual-frequency device, the PIMC (9) module needs to be processed in real time by FPGA custom logic, and the input and configuration are determined by the PIMD (2) and PIMI (3) modules. The DataCapture data capture (7) required by PIMD (2) and PIMI (3) is also completed by the FPGA, and the PS processing unit (4) needs to be configured for this purpose.

2. A digital front-end processing system suitable for ORAN equipment according to claim 1, characterized in that: The ORAN fronthaul interface includes: 10 / 25G line rate Fronthaul Interface; C-Plane, U-Plane, S-Plane, M-Plane link data processing; Beamforming Management; AXI-Lite configuration interface; Fronthaul Interface Package filter module processing; ORAN router module; Support 1588v2 protocol; Supports module simulation and system simulation.

3. The digital front-end processing system for ORAN equipment according to claim 1, characterized in that: The Beamforming Management module is used to perform weight processing on all IQ data according to the time information provided by the timing module.

4. The digital front-end processing system for ORAN equipment according to claim 1, characterized in that: The OFDM module is used to perform mutual conversion between the frequency domain and the time domain, supports up to 8 antennas, and up to 8 CCs are dynamically aggregated on a specific antenna; the OFDM module performs partial mapping of subcarriers, FFT / IFFT conversion, scaling, and cyclic prefix insertion / deletion, and supports the following functions: The maximum sampling rate is 491.52MSPS; Supports up to 8 CCs, supporting LTE and 5G-NR; Supports 15kHz, 30kHz and 60kHz subcarrier spacing (SCS) (FR1); Supports 512, 1K, 2K and 4K FFT sizes; Supports up to 8 downlinks or uplinks; Each I or Q sample uses a 16-bit data interface; Enable CC programming through the processor interface; Provides CC buffer overflow indication via status register; Delay matching passes through the TUSER information accompanying the data in the IP core.

5. The digital front-end processing system applicable to ORAN equipment according to claim 1, characterized in that: The functions supported by the Channel Filter module are as follows: Each instance supports up to 16 CCs; Supports 8 programmable coefficient sets; 16-bit coefficients, up to 256 Tap Engines or 128 Tap Engines; 16-bit or 18-bit I+Q input and output, AXI4-Stream interface; Flexible time-division multiplexing of multiple component carriers and antennas; Support time division duplex switching of uplink and downlink channels; Delay-compensated sideband channels for sampling accurate frames; Trigger coefficient switching, buffer refresh, uplink / downlink switching; Support power-off and dynamic power saving modes; A memory mapped AXI4-Lite control and status interface is provided with a software API.

6. A digital front-end processing system suitable for ORAN equipment according to claim 1, characterized in that: The functions supported by the DUC-DDC Mixer module are as follows: Supports up to 16 component carriers and up to 8 antennas; Interpolation and decimation factors up to 16 times; Cordic-based dual-mode NCO for frequency error-free operation; 16-bit or 18-bit I+Q input and output, AXI4-Stream interface; Flexible time-division multiplexing of multiple component carriers and antennas; Delay-compensated sideband channels for sampling accurate frames; Trigger parameter change operations and buffer flushes; Support power-off and dynamic power saving modes; Provides an AXI4-Lite memory-mapped control and status interface with a software API; Supports uplink and downlink channel switching.

7. The digital front-end processing system applicable to ORAN equipment according to claim 1, characterized in that: The CFR algorithm module is used to subtract the spectrum-shaped pulse matching the input signal spectrum from the signal peak value exceeding the threshold, so as to reduce the signal peak-to-average ratio; The CFR algorithm module functional modules include a peak detection module, a peak scaling module, a distributor, and a peak clipping pulse generator. The peak detection module first calculates the amplitude and phase of the input signal, and then indicates the amplitude and phase that exceed the threshold; The peak value and phase detected by the peak scaling module are used as the input of this module. The module determines the complex scaling, and its scaling amplitude is equal to the difference between the signal peak value and the threshold value. The phase is the phase information of the peak signal; The distributor includes a peak distributor and a CPG distributor, wherein the peak distributor calculates an indication signal after peak scaling according to the provided peak delay and the set maximum allowable delay, and the indication signal corresponds to the scaling factor; The clipping pulse of the clipping pulse generator is designed to have the same frequency band as the input signal. The coefficient of the clipping pulse can be obtained through the filter design method. First, a prototype filter that matches the single-carrier spectrum should be designed. If the input signal is a single carrier, the coefficient of the prototype filter is the coefficient required for the clipping pulse. For multi-carrier configuration, frequency shifting should be performed on the basis of the prototype filter. The replica of the prototype filter after shifting is required to be placed at the center frequency of each carrier. Then these replicas of the prototype filter are added together to obtain a composite multi-band filter. The coefficient of the composite multi-band filter is the coefficient required for peak clipping.

8. The digital front-end processing system applicable to ORAN equipment according to claim 1, characterized in that: The DPD algorithm module is implemented on Matlab. The entire DPD simulation architecture is mainly composed of three modules, including source data reading module, PD model calculation module, and PA output calculation module; The source data reading model is used to read forward and feedback data. It obtains data from the mat file collected by Xilinx software. There are 8192 32-bit read data in the mat file, of which the first 4096 data are used as tx_data forward data, and the following 4096 data are used as rx_data receiving data. The 32-bit rx_data is converted into 16-bit two-way signed I and Q signals, and the two-way signals are interpolated into one way with 8192 points. The data rx_data after the PA is processed by a filter, and the output is the feedback data fb_data of the PA. The feedback data is the data amplified by the power amplifier PA. The amplification factor of the feedback data, i.e., the gain, needs to be eliminated. The method of gain elimination is to divide the power of the transmitted signal by the power of the feedback signal to obtain its amplification factor, and then divide the feedback signal by the amplification factor, so that the feedback data without amplification can be obtained; The PD model calculation module is used to realize the pre-distortion function. PD usually adopts a memory polynomial structure. Here you can write code to select different PD model types. The PD model calculation module also needs to read the source data first. The process is the same as the PA reading data source. After that, the dpd_process function is used to calculate the parameters of the PD module. In dpd_process, the input signal and feedback signal are first synchronized and power aligned, then the corresponding PD model is selected according to the power amplifier model, and finally the parameters of the PD polynomial are calculated according to the forward and feedback data and stored in the corresponding data file for subsequent processing. After the PD parameters are calculated, the parameters are saved, and then the calculation of the PD polynomial needs to be implemented. The memory polynomial structure is usually used to describe the PD model, and the PD coefficient is obtained by reading the parameter data file. If there is no data file, the default output is equal to the input, that is, there is no PD function.

9. The digital front-end processing system applicable to ORAN equipment according to claim 1, characterized in that: The PAP module adopts Verilog coding language, and its functions are divided into three large modules: PAP_CTRL module, SRL_DET module, and Data_Ramping module; to realize the common protection of PA.

10. A digital front-end processing system suitable for ORAN equipment according to claim 1, characterized in that: The functions supported by the PRACH channel processing module are as follows: Supports up to three independent frequency bands; Supports up to 8 antennas with 16 component carriers per antenna on each frequency band; Up to 245.76MSPS component carrier sampling rate; 16-bit or 18-bit IQ data input, 16-bit IQ data output; AXI4-Stream data interface with flexible time-division multiplexing; Each antenna processes up to 16 PRACH channels across all component carriers; Supports all LTE and 5G NRPRACH formats; Memory-mapped AXI interface for control, status, and static PRACH scheduling; Optional ax4-stream control interface for dynamic scheduling; Power-down and dynamic power-saving modes.

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