Pixel array data processing circuit meeting requirements of Cameralink interface

Abstract

The invention discloses a pixel array data processing circuit meeting requirements of a Cameralink interface. The circuit comprises a pixel input controller, a serial shift register array, a tap, a configurable sliding tap address pointer generator, an alternative selector MUX, a tap range controller and a trigger. The serial shift register array comprises (n-1) levels of caches, each level of cache comprises two shift registers, and a tap is generated every two shift registers. The configurable sliding tap address pointer generator comprises an adder, a column pixel number counter, a comparator 1, a comparator 2, an AND gate and a pixel array row counter. The tap range controller comprises an adder, a column pixel number counter, a comparator 3 and a comparator 4. According to the circuit provided by the invention, an idle interval can be inserted between rows of a continuous pixel array output by an infrared detector, so that the format of output pixel data meets the interface requirement of a Cameralink acquisition card, and the problem that the format of output data of some infrared detectors is incompatible with the Cameralink acquisition card is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of infrared imaging image processing, and in particular relates to a pixel array data processing circuit that meets the requirements of a Cameralink interface. Background Art

[0002] At present, monitoring equipment has been widely used in both military and civilian fields. Especially with the implementation of "Safe City", the market has stimulated potential demand for infrared imaging detectors and infrared image processing chips.

[0003] The infrared imaging system includes an infrared imaging detector and an infrared image processing circuit system. Due to differences in application scenarios, the pixel sizes of infrared imaging detectors are also varied, resulting in differences in the infrared pixel data formats output by detectors with different pixel arrays. Normally, the infrared pixel data output by the detector is within a frame of image data, and there is an idle interval between rows of pixel data (at this time, the pixel synchronization signal is low, and the frame synchronization signal is always high), that is, a frame of pixel data is not output continuously. However, the pixel data output by some detectors with small pixel arrays is continuous, that is, there is no idle interval between rows of infrared pixel data within a frame (at this time, the pixel synchronization signal and the frame synchronization signal are always high). In the infrared image processing circuit system, after the infrared pixel data input by the detector is processed by the image, if it is selected to be output through the Cameralink interface, then the continuous frame of pixel data has no idle interval between rows, which will cause the Cameralink acquisition card to be unable to normally receive the serial data output by the Cameralink interface in the image processing circuit. Summary of the invention

[0004] In order to solve the problem that some detectors continuously output a frame of pixel data without idle intervals between rows, resulting in the Cameralink acquisition card being unable to receive data normally, the present invention proposes a pixel array data processing circuit that meets the requirements of the Cameralink interface.

[0005] The present invention proposes a pixel array data processing circuit that meets the requirements of the Cameralink interface. The circuit includes: a pixel input controller, a serial shift register array, a tap, a configurable sliding tap address pointer generator, a two-to-one selector MUX, a tap range controller and a trigger, wherein:

[0006] The pixel input controller controls and selects the pixel data output by the external detector and outputs it to the serial shift register array;

[0007] The serial shift register array includes cascaded n-1 levels of cache, each cache is composed of two cascaded shift registers, the input end of each cache and the output end of the last level of cache are used as a tap, forming n taps;

[0008] The configurable sliding tap address pointer generator is used to scan the row address of the entire pixel array and select the tap output of the corresponding serial shift register array;

[0009] The tap range controller is used to control the tap output of the selected serial shift register array or to insert an idle interval accordingly;

[0010] The 2-to-1 selector MUX selects and outputs according to the output of the tap range controller;

[0011] The trigger samples the output Y of the 2-to-1 selector MUX as its input under the driving of the clock CLK edge, and latches the output as the final output of the pixel array data processing circuit.

[0012] Furthermore, all shift registers share a clock CLK, and the first register receives the output from the pixel input controller. In the cascade structure of the registers, the positive phase output end of the previous register serves as the input end of the next register.

[0013] Furthermore, the configurable sliding tap address pointer generator comprises an adder, a column pixel number counter, a first comparator 1, a second comparator 2, an AND gate and a pixel array row counter, wherein:

[0014] The number of interval clocks of effective pixel data between rows in each frame of pixel data and the number of columns of the external detector pixel array are added by an adder;

[0015] The column pixel number counter is used to count the number of column pixels under a clock edge, and the output value of the column pixel number counter is compared with the output value of the adder through the first comparator 1 to see whether they are equal;

[0016] The outputs of the first comparator 1 and the second comparator 2 are processed through an AND gate and used as the inputs of a pixel array row calculator;

[0017] The second comparator is used to compare whether the value of the pixel array row counter is less than the preset number of pixel array rows.

[0018] Furthermore, the first comparator 1 compares the output values ​​of the column pixel number counter and the adder. When the two are equal, the output value Y1 of the first comparator 1 is a high level, otherwise the output value Y1 is a low level.

[0019] Further, when the output value Y1 of the first comparator 1 is a high level, if the output value of the pixel array row counter is less than the preset number of pixel array rows, the output value Y2 of the second comparator 2 is a high level, otherwise its output value Y2 is a low level; when the output value Y2 of the second comparator 2 is a low level, the row address scan of the entire pixel array is completed, and the output value of the pixel array row counter is represented as the address pointer of the serial shift register array tap, which is used to select the tap output of the corresponding serial shift register array.

[0020] Furthermore, the tap range controller includes an adder, a column pixel number counter, a third comparator 3 and a fourth comparator 4, wherein:

[0021] The number of interval clocks of effective pixel data between rows in each frame of pixel data and the number of columns of the external detector pixel array are added by an adder;

[0022] The column pixel number counter starts counting after the frame synchronization signal, the row synchronization signal and the clock signal are valid, and the output value of the column pixel number counter is compared with the output value of the adder through the third comparator 3, and the output value of the third comparator 3 is used as the reset signal of the column pixel number counter;

[0023] The fourth comparator 4 is used to compare the output value of the column pixel number counter with the preset column pixel number. When the output value of the column pixel number counter is less than the preset column pixel number, the output value of the fourth comparator 4 is a high level, and the tap output of the corresponding serial shift register array is selected as its output; otherwise, the output value of the fourth comparator 4 is a low level, and "0" is selected as the output, i.e., the corresponding idle interval is inserted.

[0024] Furthermore, the third comparator 3 is used to compare the output values ​​of the column pixel number counter and the adder. When the two are equal, the output value Y3 of the third comparator 3 is a high level, otherwise the output value Y3 is a low level. The high level output by the third comparator 3 is input into the column pixel number counter as a reset signal, and the column pixel number counter is reset to count and restarts counting the next row of column pixels.

[0025] The beneficial effects of the present invention are: inserting idle intervals between rows of continuous pixel arrays so that the output pixel data format meets the interface requirements of the Cameralink acquisition card, solving the problem that the output data format of some infrared detectors is incompatible with the Cameralink acquisition card. The circuit interface is simple, the shift register array length n is configurable, and the logic resources are small. It can be integrated into any image processing circuit system in the form of register transfer level (RTL). BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the circuit structure of an embodiment of the present invention;

[0027] Figure 2 Schematic diagram of the circuit structure of a serial shift register array in an embodiment of the present invention;

[0028] Figure 3 It is a structural schematic diagram of a configurable sliding tap address pointer generator in an embodiment of the present invention;

[0029] Figure 4 Schematic diagram of the structure of the tap range controller in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] The infrared imaging system includes an infrared imaging detector and an infrared image processing circuit system. The infrared pixel data formats output by different pixel array detectors are different. Usually, the infrared pixel data output by the detector is within a frame of image data, and there is an idle interval between the pixel data of rows. However, the pixel data of a frame output by some detectors with small pixel arrays is continuous, that is, there is no idle interval between the infrared pixel data of rows in a frame. In the infrared image processing circuit system, after the infrared pixel data input by the detector is processed by the image, if it is selected to be output through the Cameralink interface, the infrared pixel data output by the detector is required to be within a frame of image data, and there is an idle interval between the pixel data of rows. Therefore, for some detectors whose output is continuous pixel data, it is necessary to perform data processing on their output pixel data.

[0032] Figure 1 Schematic diagram of the circuit structure of an embodiment of the present invention.

[0033] The embodiment of the present invention proposes a pixel array data processing circuit that meets the requirements of the Cameralink interface. Figure 1 As shown, the circuit includes: a pixel input controller, a serial shift register array, a tap, a configurable sliding tap address pointer generator, a two-to-one selector MUX, a tap range controller and a trigger, wherein:

[0034] The pixel input controller controls and selects the pixel data of the image input by the external detector and outputs it to the serial shift register array;

[0035] The serial shift register array includes cascaded n-1 levels of cache, each cache is composed of two cascaded shift registers, the input end of each cache and the output end of the last level of cache are used as a tap, forming n taps;

[0036] The configurable sliding tap address pointer generator is used to scan the row address of the entire pixel array and select the tap output of the corresponding serial shift register array;

[0037] The tap range controller is used to control the tap output of the selected serial shift register array or to insert an idle interval accordingly;

[0038] The 2-to-1 selector MUX selects and outputs according to the output of the tap range controller;

[0039] The trigger samples the output Y of the 2-to-1 selector MUX as its input under the driving of the clock CLK edge, and latches the output as the final output of the pixel array data processing circuit.

[0040] The pixel data of the external detector input image is an m×n pixel array, that is, there are n rows of pixels, and each row of pixels has m columns. Let the value of the idle interval inserted between the rows of the pixel array be set to 2. Since the pixel data of one frame of the detector is continuously input, that is, when the idle interval is inserted between the rows of the pixel array, the pixel data of the detector is still input normally, at this time, a register is needed to cache the received pixel data, and the number of inserted idle intervals and the number of registers for caching pixels must be consistent.

[0041] Figure 1In the example, the first row of pixels is directly output after receiving. After the first row of pixel data is output, an idle interval of two clock CLKs needs to be inserted, that is, the output data and the line synchronization signal output are set to 0. At this time, the second row of pixels is normally and continuously input, so two registers are used to cache the input pixel data. At the same time, in order to ensure that the order of the pixel data remains unchanged, the cached pixel data is shifted in sequence while caching the pixel data. After the first row of idle interval insertion is completed, the output tap needs to be switched to the tap output of the first-level cache end to obtain the second row of pixel data, and the output of the third row of pixel data needs to be switched to the output tap of the second-level cache end, and so on. The output of the last row of pixel data needs to be switched to the output tap of the n-1th level cache. The switching of the output tap is controlled by the pixel array row counter. The count value 0 corresponds to the first row tap, the count value 1 corresponds to the second row tap, and so on. The count value n-1 corresponds to the nth row tap. The insertion of idle intervals is dynamically controlled by the column pixel number counter. When the column pixel number counter value is less than the preset value of a row of column pixels, the received pixel data is selected for output. When the column pixel number counter value reaches the preset value of a row of column pixels, "0" is selected as the output of the processing circuit, that is, an idle interval is inserted.

[0042] The pixel input controller controls and selects the pixel data output by the external detector. When the input frame synchronization and line synchronization signals are valid, the pixel input controller receives the pixel data and outputs it to the serial shift register array of the next level. When the input frame synchronization and line synchronization signals are invalid, the pixel input controller outputs 0.

[0043] In some preferred embodiments, all shift registers share a clock CLK, the first register receives the output from the pixel input controller, and in the cascade structure of the registers, the positive phase output end of the previous register serves as the input end of the next register. Driven by the clock CLK edge, the received pixel data is sequentially stored in the next shift register as the input pixel data.

[0044] Figure 2 Schematic diagram of the circuit structure of the serial shift register array in an embodiment of the present invention.

[0045] Figure 2In the embodiment of the present invention, the serial shift register array includes 2n shift registers, the input end of the first shift register receives the output of the pixel input controller, the output end Q of the previous shift register of the serial shift register array is connected to the input end D of the next shift register, every two shift registers form a first-level cache, and the 2n shift registers share a clock CLK. In the embodiment of the present invention, the input pixel data is received by the first shift register under the drive of the clock CLK, and the pixel data received by the previous clock CLK is shifted to the next-level shift register under the drive of the clock CLK, and so on, the received first pixel data will be serially shifted to the last shift register. The shift array continues to be driven by the clock CLK, and if the first pixel data is not selected by the tap address pointer after being shifted out of the last shift register, then the pixel data will be discarded. The serial shift register array includes n tap outputs, and the tap output starts from the input end of the first shift register, and a tap is generated every 2 shift registers. The tap is the output of the corresponding cache level.

[0046] Figure 3 It is a schematic diagram of the structure of a configurable sliding tap address pointer generator in an embodiment of the present invention.

[0047] In some preferred embodiments, reference Figure 3 As shown, the configurable sliding tap address pointer generator includes an adder, a column pixel number counter, a comparator 1, a comparator 2, an AND gate and a pixel array row counter, wherein:

[0048] The number of interval clocks of effective pixel data between rows in each frame of pixel data and the number of columns of the external detector pixel array are added by an adder;

[0049] The column pixel number counter is used to count the number of column pixels under a clock edge, and the output value of the column pixel number counter is compared with the output value of the adder through the first comparator 1 to see whether they are equal;

[0050] The outputs of the first comparator 1 and the second comparator 2 are processed through an AND gate and used as the inputs of a pixel array row calculator;

[0051] The second comparator is used to compare whether the value of the pixel array row counter is less than the preset number of pixel array rows.

[0052] In some preferred embodiments, reference Figure 3 As shown, the first comparator 1 compares the output values ​​of the column pixel number counter and the adder. When the two are equal, the output value Y1 of the first comparator 1 is a high level, otherwise the output value Y1 is a low level.

[0053] In some preferred embodiments, reference Figure 3 As shown, when the output value Y1 of the first comparator 1 is high, if the output value of the pixel array row counter is less than the preset number of pixel array rows, the output value Y2 of the second comparator 2 is high, otherwise its output value Y2 is low; when the output value Y2 of the second comparator 2 is low, the row address scan of the entire pixel array is completed, and the output value of the pixel array row counter is represented as the address pointer of the serial shift register array tap, which is used to select the tap output of the corresponding serial shift register array.

[0054] Figure 3 In the figure, the idle interval is the number of clocks between valid pixel data rows in a frame of pixel data. In this idle interval, the pixel synchronization signal is at a low level, while the frame synchronization signal is always at a high level. The number of columns of the external detector pixel array is used as the preset column pixel number. The preset column pixel number and the idle interval are added by an adder to obtain the highest threshold value of the column pixel number, which represents the number of clocks for a row of the pixel array. When the frame synchronization and row synchronization signals are valid, the column pixel number counter counts once at each clock CLK edge to count the number of column pixels within a row of pixel time. Comparator 1 is used to compare the value of the column pixel number counter and the threshold value output by the adder. When the two are equal, the output value Y1 of comparator 1 is high, otherwise Y1 is low. The equality of the two means that a row of pixel time has been reached. At this time, if the value of the pixel array row counter is less than the preset number of pixel array rows, the output value Y2 of comparator 2 is high, indicating that the counting time has not reached the last row of the pixel array. If the value of the pixel array row counter is equal to the preset number of pixel array rows, the output value Y2 is low, indicating that the counting time has reached the last row of the pixel array, and the row address scanning of the entire pixel array is completed. When the number of column pixels counted by the column pixel number counter in a row of pixel time reaches a row of pixel time, and the number of rows counted by the pixel array row counter has not reached the last row of the pixel array, the pixel array row counter counts 1 under the clock CLK edge drive, and the output value of the pixel array row counter and the cache tap sequence in the serial shift register array are in a one-to-one correspondence, that is, the count value 0 corresponds to the first row tap of the serial shift register array, the count value 1 corresponds to the second row tap, and so on, the count value n-1 corresponds to the nth row tap. The count value of the pixel array row counter is represented as an address pointer of the serial shift register array tap, which is used to select the corresponding tap output of the serial shift register array.

[0055] Figure 4 Schematic diagram of the structure of the tap range controller in an embodiment of the present invention.

[0056] In some preferred embodiments, reference Figure 4As shown, the tap range controller includes an adder, a column pixel number counter, a comparator 3 and a comparator 4, wherein:

[0057] The number of interval clocks of effective pixel data between rows in each frame of pixel data and the number of columns of the external detector pixel array are added by an adder;

[0058] The column pixel number counter starts counting after the frame synchronization signal, the row synchronization signal and the clock signal are valid, and the output value of the column pixel number counter is compared with the output value of the adder through the third comparator 3, and the output value of the third comparator 3 is used as the reset signal of the column pixel number counter;

[0059] The fourth comparator 4 is used to compare the output value of the column pixel number counter with the preset column pixel number. When the output value of the column pixel number counter is less than the preset column pixel number, the output value of the fourth comparator 4 is a high level, and the tap output of the corresponding serial shift register array is selected as its output; otherwise, the output value of the fourth comparator 4 is a low level, and "0" is selected as the output, i.e., the corresponding idle interval is inserted.

[0060] In some preferred embodiments, reference Figure 4 As shown, the third comparator 3 compares the output values ​​of the column pixel number counter and the adder. When the two are equal, the output value Y3 of the third comparator 3 is a high level, otherwise the output value Y3 is a low level; the high level output by the third comparator 3 is input into the column pixel number counter as a reset signal, and the column pixel number counter resets the count and restarts the next row of column pixel counts.

[0061] Figure 4In the embodiment, the tap range controller includes an adder, a column pixel number counter, a comparator 3 and a comparator 4. The idle interval is the number of clocks between valid pixel data in each frame of pixel data. The number of columns of the external detector pixel array is used as the preset column pixel number. The preset column pixel number and the idle interval are added by the adder to obtain the highest threshold value of the column pixel number, which represents the number of counts required for a row of the pixel array. The column pixel number counter starts counting after the frame synchronization and row synchronization signals become effective. The comparator 3 is used to compare the value of the column pixel number counter and the threshold value output by the adder. When the two are equal, the output value Y3 of the comparator 3 is a high level, otherwise Y3 is a low level. The equality of the two means that the number of counts required for a row of the pixel array has been reached. After the high level of Y3 is input into the column pixel number counter as a clearing signal, the column pixel number counter value is cleared, thereby starting the next row of column pixel counting. At the same time, comparator 4 is used to compare the value of the column pixel number counter with the preset column pixel number. When the column pixel number counter value is less than the preset column pixel number, the output value of comparator 4 is a high level, and the tap output of the serial shift register array is selected as the output of the processing circuit; otherwise, the output value of comparator 4 is a low level, and "0" is selected as the output, that is, an idle interval is inserted.

[0062] In some preferred embodiments, reference Figure 1 As shown, when the tap range controller output is a high level, the 2-to-1 selector MUX selects the output of the configurable sliding tap address pointer generator as its output; when the tap range controller output is a low level, the 2-to-1 selector MUX selects "0" as its output.

[0063] In some preferred embodiments, reference Figure 1 As shown, the trigger samples the output of the 2-to-1 selector MUX as its input under the driving of the clock CLK edge, and latches the output as the final output of the pixel array data processing circuit.

[0064] The length n of the serial shift register array, the number of preset column pixels, the number of preset pixel array rows, and the idle interval can all be set to dynamic configuration, thereby meeting the application requirements of different detector pixel arrays.

[0065] The invention discloses a pixel data processing circuit for inserting idle intervals between rows of a pixel array and meeting the requirements of a Cameralink interface. The circuit adopts Verilog HDL design and can be integrated into any infrared image imaging system.

[0066] The present invention is characterized in that idle intervals are inserted between rows of continuous pixel arrays output by infrared detectors, so that the output pixel data format meets the interface requirements of Cameralink acquisition cards, and solves the problem that the output data format of some infrared detectors is incompatible with Cameralink acquisition cards. The chip provided by the embodiment of the present invention has the following advantages: the circuit interface is simple, the shift register array length n is configurable, and the logic resources are small, and it can be integrated into any image processing circuit system in the form of RTL.

[0067] A person skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, which can include: ROM, RAM, disk or CD, etc.

[0068] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A pixel array data processing circuit that meets the requirements of the Cameralink interface, characterized in that: The circuit includes a pixel input controller, a serial shift register array, a tap, a configurable sliding tap address pointer generator, a two-to-one selector MUX, a tap range controller and a trigger, wherein: The pixel input controller controls and selects the pixel data output by the external detector and outputs it to the serial shift register array; The serial shift register array includes cascaded n-1 levels of cache, each cache is composed of two cascaded shift registers, the input end of each cache and the output end of the last level of cache are used as a tap, forming n taps; The configurable sliding tap address pointer generator is used to scan the row address of the entire pixel array and select the tap output of the corresponding serial shift register array; The tap range controller is used to control the tap output of the selected serial shift register array or to insert an idle interval accordingly; The 2-to-1 selector MUX selects and outputs according to the output of the tap range controller; The trigger samples the output Y of the 2-to-1 selector MUX as its input under the driving of the clock CLK edge, and latches the output as the final output of the pixel array data processing circuit.

2. A pixel array data processing circuit that meets the Cameralink interface requirements according to claim 1, characterized in that: All shift registers share a clock CLK. The first register receives the output from the pixel input controller. In the cascade structure of the registers, the positive phase output of the previous register serves as the input of the next register.

3. A pixel array data processing circuit that meets the Cameralink interface requirements according to claim 1, characterized in that: The configurable sliding tap address pointer generator comprises an adder, a column pixel number counter, a first comparator (1), a second comparator (2), an AND gate and a pixel array row counter, wherein: The number of interval clocks of effective pixel data between rows in each frame of pixel data and the number of columns of the external detector pixel array are added by an adder; The column pixel number counter is used to count the number of column pixels under a clock edge, and the output value of the column pixel number counter is compared with the output value of the adder through a first comparator (1) to see whether they are equal; The outputs of the first comparator (1) and the second comparator (2) are processed through an AND gate and used as inputs of a pixel array row calculator; The second comparator is used to compare whether the value of the pixel array row counter is less than the preset number of pixel array rows.

4. A pixel array data processing circuit that meets the Cameralink interface requirements according to claim 3, characterized in that: The first comparator (1) compares the output values ​​of the column pixel number counter and the adder. When the two are equal, the output value (Y1) of the first comparator (1) is a high level, otherwise the output value (Y1) is a low level.

5. A pixel array data processing circuit that meets the Cameralink interface requirements according to claim 4, characterized in that: When the output value (Y1) of the first comparator (1) is at a high level, if the output value of the pixel array row counter is less than the preset number of pixel array rows, the output value (Y2) of the second comparator (2) is at a high level, otherwise its output value (Y2) is at a low level; when the output value (Y2) of the second comparator (2) is at a low level, the row address scan of the entire pixel array is completed, and the output value of the pixel array row counter is represented as an address pointer of a serial shift register array tap, which is used to select the tap output of the corresponding serial shift register array.

6. A pixel array data processing circuit that meets the Cameralink interface requirements according to claim 1, characterized in that: The tap range controller comprises an adder, a column pixel number counter, a third comparator (3) and a fourth comparator (4), wherein: The number of interval clocks of effective pixel data between rows in each frame of pixel data and the number of columns of the external detector pixel array are added by an adder; The column pixel number counter starts counting after the frame synchronization signal, the row synchronization signal and the clock signal are valid, and compares the output value of the column pixel number counter with the output value of the adder through a third comparator (3), and uses the output value of the third comparator (3) as a reset signal of the column pixel number counter; The fourth comparator (4) is used to compare the output value of the column pixel number counter with the preset column pixel number. When the output value of the column pixel number counter is less than the preset column pixel number, the output value of the fourth comparator (4) is a high level, and the tap output of the corresponding serial shift register array is selected as its output. Otherwise, the output value of the fourth comparator (4) is a low level, and "0" is selected as the output, i.e., the corresponding idle interval is inserted.

7. A pixel array data processing circuit that meets the Cameralink interface requirements according to claim 6, characterized in that: The third comparator (3) compares the output value of the column pixel number counter and the output value of the adder. When the two are equal, the output value (Y3) of the third comparator (3) is a high level, otherwise the output value (Y3) is a low level. The high level output by the third comparator (3) is input as a clearing signal into the column pixel number counter, and the column pixel number counter is cleared to count and restarts counting the next row of column pixels.

8. The pixel array data processing circuit that meets the Cameralink interface requirements according to claim 1, characterized in that: When the tap range controller output is high, the 2-to-1 selector MUX selects the output of the configurable sliding tap address pointer generator as its output; when the tap range controller output is low, the 2-to-1 selector MUX selects "0" as its output.

9. A pixel array data processing circuit that meets the Cameralink interface requirements according to claim 1 or 8, characterized in that: The trigger samples the output of the 2-to-1 selector MUX as its input under the driving of the clock CLK edge, and latches the output as the final output of the pixel array data processing circuit.

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