Debugging system and method for built-in logic analyzer and ultra-wideband communication

Abstract

The invention discloses a built-in logic analyzer which can be arranged in equipment to be debugged and comprises a logic analysis sub-module, a control sub-module and a storage sub-module. Wherein the logic analysis sub-module is used for synchronously receiving a signal received by a receiving module of a to-be-debugged device and a signal to be transmitted by a transmitting module, storing the signal within a specified duration before and / or after a preset condition is met to the storage sub-module when the preset condition is met, and generating an interruption event. And the control sub-module is in communication connection with the logic analysis sub-module, the receiving module and the transmitting module and is used for judging whether a preset condition is met or not. The built-in logic analyzer is applied to the UWB system so as to capture abnormal behaviors in the system while monitoring the transmitting and receiving processes of signals in real time, thereby helping developers to quickly position and solve problems.

Description

Technical Field

[0001] The invention relates to the field of ultra-wideband technology, and in particular to a debugging system and method for a built-in logic analyzer and ultra-wideband communication. Background Art

[0002] Ultra-wideband (UWB) is a short-range wireless communication technology with the characteristics of high data rate, low power consumption and high positioning accuracy. With the rapid development of wireless communication technology, UWB technology has been widely used in the fields of Internet of Things, smart home, industrial automation and medical treatment.

[0003] The high frequency characteristics of UWB signals make them susceptible to interference and attenuation, especially in complex wireless environments, where the signal reception quality and communication reliability are difficult to guarantee. In addition, UWB systems need to deal with channel characteristics such as multipath effects, which places higher demands on signal processing algorithms. Therefore, when designing and debugging UWB systems, it is often necessary to capture and analyze signals in detail to optimize system performance.

[0004] Since there are many high-speed signals in UWB, the traditional debugging process is difficult to apply to UWB. Figure 1 As shown in the figure, traditional debugging methods usually rely on external logic analyzers or oscilloscopes. However, it is difficult to achieve real-time automatic monitoring of the debugging process of external devices within the system, resulting in low debugging efficiency. In addition, external debugging equipment used for high-speed signals is usually complex to operate and expensive, making it difficult to be widely used in large-scale projects. Summary of the invention

[0005] In view of some or all of the problems in the prior art, the first aspect of the present invention provides a built-in logic analyzer, which is arranged inside a device to be debugged and includes:

[0006] A logic analysis submodule, which synchronously receives the signal received by the receiving module of the device to be debugged and the signal to be transmitted by the transmitting module, and when a preset condition is met, stores the signal within a specified time before and / or after the preset condition is met in the storage submodule, and generates an interrupt event;

[0007] a control submodule, which is communicatively connected to the logic analysis submodule, the receiving module and the transmitting module, and is used to determine whether a preset condition is met; and

[0008] The storage submodule is communicatively connected to the logic analysis submodule and is used to store signals within a specified time period before and / or after a preset condition is met.

[0009] Furthermore, the preset conditions include: an internal state machine jumps, and / or a specified signal is received.

[0010] Furthermore, the built-in logic analyzer has a local timestamp.

[0011] Based on the built-in logic analyzer as described above, a second aspect of the present invention provides a debugging system for ultra-wideband communication, which includes a receiving module, a transmitting module, and the built-in logic analyzer as described above.

[0012] Furthermore, the debugging system also includes a debugging module, which is communicatively connected to the receiving module, the built-in logic analyzer and the transmitting module, and is used for analyzing and debugging the signal.

[0013] Based on the above-mentioned debugging system, the third aspect of the present invention provides a debugging method for ultra-wideband communication, comprising:

[0014] synchronously receiving signals through the built-in logic analyzer as described above, and storing the specified signals; and

[0015] Perform signal analysis based on the stored signals and debug the signals according to the analysis results.

[0016] Further, storing the designated signal includes:

[0017] When the control submodule of the built-in logic analyzer detects a jump of the internal state machine and / or receives a specified signal, the logic analysis submodule automatically stores the received signal within a specified time period before and / or after that moment in the storage submodule.

[0018] Furthermore, the designated signal includes: a designated waveform signal received by the built-in logic analyzer, and / or a designated waveform signal sent by the transmitting module, and / or a designated waveform signal received by the receiving module.

[0019] Further, the signal analysis includes:

[0020] Analyze the signals before and after the internal state machine jumps to determine whether the state machine jump time point is accurate; and / or

[0021] Analyze the signals before and after the designated signal to determine whether the time positioning of the designated signal is accurate.

[0022] Furthermore, debugging the signal includes:

[0023] Locate abnormal problems based on signal analysis results; and

[0024] Debug the signal based on the problem location.

[0025] The present invention provides a built-in logic analyzer, which can be applied to an ultra-wideband communication system to assist in signal debugging. The built-in logic analyzer can capture and analyze the timing and state information of the signal in real time, and provide more accurate debugging feedback. In particular, in a UWB system, the built-in logic analyzer can capture abnormal behaviors in the system while monitoring the transmission and reception process of the signal in real time, thereby helping developers to quickly locate and solve problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0027] Figure 1 A schematic diagram showing the structure of an existing ultra-wideband communication debugging system;

[0028] Figure 2 A schematic diagram showing the structure of a debugging system for ultra-wideband communication according to an embodiment of the present invention; and

[0029] Figure 3 A schematic flow chart of a method for debugging ultra-wideband communication according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0030] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0031] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0032] The UWB system has the characteristics of high bandwidth and extremely short pulses. According to the 802.15.4z protocol, the highest PRF of UWB is usually 499.2MHz, and the minimum sampling frequency is as high as 1GHz. Traditional logic analyzers that support these characteristics are usually expensive and complicated to operate, which is bound to pose a great challenge to the debugging process using traditional logic analyzers. At the same time, current UWB applications are more sensitive to the real-time nature of signals, and the synchronization and precise triggering of signals are very critical. The traditional debugging process lacks the linkage between signal events and high-speed signals within the system, and has difficulties in processing high-precision synchronization and triggering. In response to this problem, the present invention proposes a debugging system for UWB systems. Compared with traditional debugging modules, its main difference is that it is combined with a built-in logic analyzer. The built-in logic analyzer can capture and analyze the timing and status information of the signal in real time, providing more accurate debugging feedback. By integrating the logic analysis function within the UWB debugging system, the transmission and reception of the signal can be monitored in real time, while realizing rapid monitoring and analysis of high-speed content such as ADC / DAC signals and channel pulse response data, capturing abnormal behavior in the system, thereby helping developers to quickly locate and solve problems.

[0033] The technical solution of the present invention is further described below in conjunction with the accompanying drawings of the embodiments.

[0034] Figure 2 FIG. 2 is a schematic diagram showing the structure of a debugging system for ultra-wideband communication according to an embodiment of the present invention. Figure 2 As shown, a debugging system for ultra-wideband communication includes a receiving module 201, a built-in logic analyzer 202, a transmitting module 203, and a debugging module 204.

[0035] As shown in the figure, the debugging system performs relevant signal analysis and processing based on digital signals. Based on this, it needs to be connected to the ultra-wideband communication system through an analog-to-digital converter 001 and a digital-to-analog converter 002. The input end of the analog-to-digital converter 001 is connected to the output end of the analog front end of the UWB, and is used to convert the analog signal output by the analog front end into a digital signal. The digital signal converted by the analog-to-digital converter 001 is synchronously sent to the receiving module 201 and the built-in logic analyzer 202.

[0036] The input end of the digital-to-analog converter 002 is connected to the output end of the transmitting module 203, and is used to convert the digital signal output by the transmitting module into an analog signal, and send it to the analog front end, and then send it out via the antenna. At the same time, the digital signal output by the transmitting module 203 is also synchronously sent to the built-in logic analyzer 202.

[0037] The receiving module 201 , the transmitting module 203 and the built-in logic analyzer 202 work in parallel, and key signals of the receiving module 201 and the transmitting module 203 need to be connected to the built-in logic analyzer 202 .

[0038] When entering the debugging process, the built-in logic analyzer 202 will continue to receive signals but not save them. According to the pre-configured conditions, the received signals of the logic analyzer and the key signals in the transmitter / receiver process will be continuously observed. Once the signal meets the trigger condition, the logic analyzer will store the signal in the cache and generate an interrupt event to the host computer.

[0039] The built-in logic analyzer 202 can automatically collect and save the required signals for signal analysis. All the data recorded by the built-in logic analyzer are related to time, so they can be used to analyze the timing and status information of the signal. Specifically, in the UWB process, there are many processes such as decoding data packets and combining data packets that run at a higher rate. The traditional UWB debugging system cannot transmit the situation of these signals in real time when processing data packets, but through the built-in logic analyzer with reasonable condition settings, the actual situation of the data signal before and after the conditions are met can be better seen. Therefore, the internal logic analyzer can be configured in advance, such as configuring the trigger conditions, whether to issue an interrupt, and which signals to save after the interrupt is triggered. The trigger condition refers to the signal conditions that need to be met for the built-in logic analyzer to automatically collect data and save. Generally, some collected signals are selected in the setting stage, and then the level conditions and / or logical operation conditions that they need to meet are set. Once the collected signals meet the set conditions, the built-in logic analyzer can save all the collected signals for a period of time before and / or after the conditions are met for signal analysis. In one embodiment of the present invention, the trigger condition is set according to the characteristics of the UWB packet. Specifically, for example, in the frame synchronization part, after receiving the preamble, there will be a jump of the internal state machine to receiving the SFD, and the data of the preamble and the SFD will be significantly different. At this time, the built-in logic analyzer uses the internal state machine jump as a trigger condition, and stores the signals before and after the internal state machine jump for analysis to determine whether the time point of the state machine jump is accurate. For another example, in the UWB packet, there is a special signal RMARKER after the frame synchronization is completed. Then, the signal is captured as a trigger condition, and the actual situation of receiving the data packet is analyzed to observe whether the system accurately locates the RMARKER time. In other embodiments of the present invention, similar methods can also be used to locate and analyze the remaining special nodes of the frame synchronization link, as well as various time nodes in data signals such as scrambled timestamp sequences and data packets.

[0040] As shown in the figure, in one embodiment of the present invention, the built-in logic analyzer 202 includes a logic analysis submodule 221, a control submodule 222 and a storage submodule 223. The logic analysis submodule 221 synchronously receives the signal received by the receiving module of the device to be debugged and the signal to be transmitted by the transmitting module, and when the preset condition is met, the signal within a specified time before and / or after the preset condition is met is stored in the storage submodule 223, and an interrupt event is generated. The control submodule 222 is communicatively connected with the logic analysis submodule 221, the receiving module 201 and the transmitting module 203 to determine whether the preset condition is met. In one embodiment of the present invention, in order to improve real-time performance, the storage submodule 223 is a high-speed storage submodule. After the trigger condition is met, the designated signal is cached and stored in the storage submodule 223.

[0041] In addition, in order for the host computer to more accurately locate the information stored in the storage submodule 221, in one embodiment of the present invention, the built-in logic analyzer has a local timestamp.

[0042] The debugging module 204 is communicatively connected to the receiving module 201, the built-in logic analyzer 202 and the transmitting module 203, and is used to analyze and debug the signal. In one embodiment of the present invention, the function of the debugging module 204 is implemented by a microcontroller unit (MCU), for example, and the control unit can also configure the built-in logic analyzer 202 and control the startup of the receiving module and the transmitting module.

[0043] Figure 3 FIG. 2 is a flow chart showing a method for debugging ultra-wideband communication according to an embodiment of the present invention. Figure 3 As shown, a debugging method for ultra-wideband communication includes:

[0044] First, in step 301, the debugging system is configured. The debugging system is configured, including determining whether to enter the debugging process, the conditions for triggering the built-in logic analyzer, whether to issue an interrupt, which parts of the signal are cached in the cache after the trigger, etc.;

[0045] Next, in step 302, data collection is performed. The receiving module, the transmitting module and the built-in logic analyzer are started, wherein the receiving module, the transmitting module and the built-in logic analyzer work in parallel, and the built-in logic analyzer continuously receives signals but does not save them. The signals include signals sent to the receiving module and signals to be sent by the transmitting module, etc.;

[0046] Next, in step 303, it is detected whether the trigger condition is met. The built-in logic analyzer monitors the received signal and the key signal in the transmitter / receiver process in real time according to the pre-configured conditions, and determines whether the trigger condition is met. If so, it proceeds to step 304 to store the signal;

[0047] In step 304, the signal is stored and an interrupt is generated. When the trigger condition is met, the received signal within the specified time length before and / or after the trigger condition is met is stored in the storage submodule, and an interrupt event is generated. In one embodiment of the present invention, the trigger signal includes a jump of an internal state machine, and / or receiving a specified signal, wherein the specified signal can be, for example, a specified waveform signal received by a built-in logic analyzer, and / or a specified waveform signal sent by a transmitting module, and / or a specified waveform signal received by the receiving module, such as RMARKER after frame synchronization reception;

[0048] Next, in step 305, signal analysis is performed. The stored signal is analyzed, for example, the signal before and after the internal state machine jump is analyzed to determine whether the state machine jump time point is accurate, and for example, the signal before and after the designated signal is analyzed to determine whether the designated signal time positioning is accurate, etc.; and

[0049] Finally, in step 306, signal debugging is performed according to the signal analysis result, for example, the abnormal problem is located according to the signal analysis result, and the signal is debugged according to the problem location.

[0050] It should be understood that after an interrupt event occurs, if the sending and / or receiving process has not yet ended, the aforementioned steps may be continuously repeated until all data are sent and received.

[0051] Since the signals of the UWB transceiver process are connected to the conditional trigger module of the logic analyzer inside the system, compared with the traditional debugging process, the signals collected by the built-in logic analyzer are not only more accurate in time, but the internal processing also avoids the influence of external electromagnetic signals. Based on this, the actual situation of each module in the entire UWB business process can be fed back more accurately.

[0052] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A built-in logic analyzer, characterized in that: It can be set inside the device to be debugged and includes: a logic analysis submodule, which is configured to synchronously receive the signal received by the receiving module of the device to be debugged and the signal to be transmitted by the transmitting module, and when a preset condition is met, store the signal within a specified time before and / or after the preset condition is met in the storage submodule, and generate an interrupt event; a control submodule, which is communicatively connected to the logic analysis submodule, the receiving module and the transmitting module, and is configured to determine whether a preset condition is met; and The storage submodule is communicatively connected to the logic analysis submodule and is configured to store signals within a specified time period before and / or after a preset condition is met.

2. The built-in logic analyzer according to claim 1, wherein: The preset conditions include: an internal state machine jump occurs, and / or a specified signal is received.

3. The built-in logic analyzer according to claim 1, wherein: The built-in logic analyzer has local time stamping.

4. A debugging system for ultra-wideband communication, characterized in that: It comprises a receiving module, a transmitting module, and a built-in logic analyzer as claimed in any one of claims 1 to 3.

5. The debugging system according to claim 4, characterized in that: Also includes: A debugging module is communicatively connected to the receiving module, the built-in logic analyzer and the transmitting module, and the debugging module is configured to analyze and debug the signal.

6. A debugging method for ultra-wideband communication, characterized in that: Includes steps: Synchronously receiving signals through the built-in logic analyzer as described in any one of claims 1 to 3, and storing designated signals; and Perform signal analysis based on the stored signals and debug the signals according to the analysis results.

7. The debugging method according to claim 6, characterized in that: Storing the specified signal includes the steps of: When the control submodule of the built-in logic analyzer detects a jump of the internal state machine and / or receives a specified signal, the logic analysis submodule automatically stores the jump of the internal state machine and / or the received signal within a specified time period before and / or after receiving the specified signal to the storage submodule.

8. The debugging method according to claim 7, characterized in that: The designated signal includes: A specified waveform signal received by the built-in logic analyzer; and / or A specified waveform signal sent by the transmitting module; and / or The receiving module receives the specified waveform signal.

9. The debugging method according to claim 7, characterized in that: Signal analysis includes the following steps: Analyze the signals before and after the internal state machine jumps to determine whether the state machine jump time point is accurate; and / or Analyze the signals before and after the designated signal to determine whether the time positioning of the designated signal is accurate.

10. The debugging method according to claim 6, characterized in that: Debugging the signal includes: Locate abnormal problems based on signal analysis results; and Debug the signal based on the problem location.

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