Semiconductor structure, forming method thereof and memory

Abstract

The embodiment of the invention discloses a semiconductor structure, a forming method thereof and a memory, and the forming method of the semiconductor structure comprises the steps: providing an initial stacking structure which comprises first sacrificial layers and second sacrificial layers which are alternately stacked; forming a plurality of first grooves penetrating through the initial stacking structure; etching along the lateral direction of the first groove so as to remove the first part of each layer of the first sacrificial layer and form a plurality of first filling areas; forming a dielectric layer in each first filling area; removing the second sacrificial layer to form a plurality of second filling areas, and forming a bit line layer in each second filling area; and removing the reserved second part of each first sacrificial layer to form a plurality of cavities.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same, and a memory. Background Art

[0002] The integration of a two-dimensional semiconductor memory device is mainly determined by the area occupied by the memory cell, and therefore its integration is largely affected by the level of fine pattern formation technology. In order to overcome the limitation of the fine pattern technology level on the integration of semiconductor memory devices, a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells has been proposed recently.

[0003] However, conventional three-dimensional semiconductor memory devices and methods for forming the same still have certain defects. How to further improve the performance of three-dimensional semiconductor memory devices has become a problem that needs to be solved urgently.

[0004] Public Content

[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, and a memory.

[0006] According to a first aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:

[0007] Providing an initial stacking structure, the initial stacking structure comprising first sacrificial layers and second sacrificial layers stacked alternately;

[0008] forming a plurality of first grooves penetrating the initial stacking structure;

[0009] Laterally etching along the first trench to remove a first portion of each first sacrificial layer to form a plurality of first filling regions;

[0010] forming a dielectric layer in each of the first filling regions;

[0011] removing the second sacrificial layer to form a plurality of second filling regions, and forming a bit line layer in each of the second filling regions;

[0012] The remaining second portion of each first sacrificial layer is removed to form a plurality of cavities.

[0013] In the above scheme, multiple first grooves are arranged along the first direction, the distance between the side wall of the first groove parallel to the first direction and the edge of the initial stacking structure along the second direction is H1, the distance between two adjacent first grooves along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacking structure.

[0014] In the above solution, the second sacrificial layer is removed to form a plurality of second filling regions, and a bit line layer is formed in each of the second filling regions, including:

[0015] Laterally etching along the first trench to remove a third portion of each second sacrificial layer to form a plurality of third filling regions;

[0016] A conductive material is filled in each of the third filling regions; the conductive material is filled between the fourth portions of each of the retained second sacrificial layers;

[0017] removing the fourth portion to form a plurality of fourth filling areas;

[0018] The conductive material is filled in each of the fourth filling regions; and the conductive material in the third filling region and the fourth filling region constitutes the bit line layer.

[0019] In the above solution, after the dielectric layer is formed in each of the first filling regions, the dielectric layer is filled between the second portions of each of the retained first sacrificial layers;

[0020] The removing of the fourth part and the removing of the second part comprises:

[0021] After each of the third filling regions is filled with a conductive material, a second trench penetrating the initial stacked structure is formed; the second trench exposes a sidewall of the fourth portion and a sidewall of the second portion;

[0022] performing lateral etching along the second groove to remove the fourth portion;

[0023] Performing lateral etching along the second trench to remove the second portion.

[0024] In the above scheme, the method further comprises:

[0025] Before performing lateral etching along the first trench to remove the first portion of each first sacrificial layer, filling at least a portion of the first trench with a third sacrificial layer;

[0026] After a dielectric layer is formed in each of the first filling regions, the third sacrificial layer is removed to form a fourth trench, wherein the fourth trench exposes a sidewall of the second portion.

[0027] In the above solution, the second sacrificial layer is removed to form a plurality of second filling regions, and a bit line layer is formed in each of the second filling regions, including:

[0028] Filling a fourth sacrificial layer in the first trench, and laterally etching along the fourth trench to remove a fifth portion of each second sacrificial layer to form a plurality of fifth filling regions;

[0029] Filling each of the fifth filling regions with a conductive material;

[0030] removing the fourth sacrificial layer, and removing the sixth portion of each retained second sacrificial layer along the first trench to form a plurality of sixth filling regions;

[0031] The conductive material is filled in each of the sixth filling regions; and the conductive materials in the fifth filling region and the sixth filling region constitute the bit line layer.

[0032] In the above solution, the plurality of first grooves are arranged along a first direction, and the method further comprises:

[0033] After a dielectric layer is formed in each of the first filling regions, a third groove is formed between two adjacent first grooves, the third groove penetrates the initial stacking structure and exposes the side wall of the second portion; the distance between the third groove and the adjacent first groove along the first direction is H3, the distance between the side wall of the third groove or the first groove parallel to the first direction and the edge of the initial stacking structure along the second direction is H1, and the ratio of H3 to H1 is greater than 2; the first direction is perpendicular to the second direction and is perpendicular to the stacking direction of the initial stacking structure.

[0034] In the above solution, the second sacrificial layer is removed to form a plurality of second filling regions, and a bit line layer is formed in each of the second filling regions, including:

[0035] Laterally etching along the third trench to remove a seventh portion of each second sacrificial layer to form a plurality of seventh filling regions;

[0036] Filling each of the seventh filling regions with a conductive material;

[0037] Laterally etching along the first trench to remove the eighth portion of the retained second sacrificial layer to form a plurality of eighth filling regions;

[0038] The conductive material is filled in each of the eighth filling regions; the conductive materials in the seventh filling region and the eighth filling region constitute the bit line layer;

[0039] The removing of the second portion of each of the first sacrificial layers that is retained includes: performing lateral etching along the third trench to remove the second portion of each of the first sacrificial layers that is retained.

[0040] According to a second aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0041] A stacked structure including alternately stacked bit line layers and dielectric layers;

[0042] Wherein, the stacking structure includes a plurality of first grooves penetrating the stacking structure;

[0043] The bit line layer comprises a plurality of first bit line portions located at both sides of the first trench along a first direction and a second bit line portion located at one side of the plurality of first bit line portions along a second direction, wherein the second bit line portion extends along the first direction;

[0044] There is a cavity in the dielectric layer between adjacent first trenches.

[0045] In the above scheme, multiple first grooves are arranged along the first direction, the width of the second bit line portion along the second direction is H1, the width of the first bit line portion along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the stacking structure.

[0046] In the above scheme, the ratio of H2 to H1 ranges from 3 to 6.

[0047] In the above solution, the cavity is located between the first bit line portions adjacent to each other along the stacking direction, and a dielectric layer is provided between the cavity and two first trenches adjacent to each other along the first direction.

[0048] In the above scheme, the ratio range of H2 to H1 is greater than 6, and the stacking structure also includes a third groove running through the stacking structure, and the third groove is located between two adjacent first grooves. The distance between the third groove and the adjacent first groove along the first direction is H3, and the ratio range of H3 to H1 is 3-6.

[0049] In the above scheme, the cavity is located between the first bit line parts adjacent to each other along the stacking direction and between the second bit line parts adjacent to each other along the stacking direction, and the cavity is located on both sides of the third groove along the first direction and on one side along the second direction, a dielectric layer is provided between the first groove and the cavity, and the third groove is connected to the cavity.

[0050] According to a third aspect of the present disclosure, a memory is provided, comprising a semiconductor structure as described in any of the above solutions.

[0051] In the embodiment of the present disclosure, a first groove penetrating the initial stacking structure is formed in the initial stacking structure, a first portion of the first sacrificial layer is removed by lateral etching along the first groove, a dielectric layer is filled in the area where the first portion of the first sacrificial layer is removed, and after the second sacrificial layer is removed and a bit line layer is formed, the second portion of the first sacrificial layer is removed, thereby forming a cavity between two bit line layers adjacent to each other along the stacking direction of the initial stacking structure. This can reduce the coupling effect between the two bit line layers adjacent to each other along the stacking direction of the initial stacking structure, and can reduce the parasitic capacitance between the two bit line layers adjacent to each other along the stacking direction of the initial stacking structure, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0053] Figures 2 to 33 A schematic diagram of a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure;

[0054] Fig.34 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure Figure 1 ;

[0055] Fig.35 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0056] In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0057] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0058] It will be understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0059] Additionally, for ease of description, spatially relative terms such as "on," "over," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0060] In the disclosed embodiments, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, silicon carbide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0061] In the disclosed embodiments, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is smaller than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductors and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0062] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0063] The semiconductor structure involved in the embodiments of the present disclosure is to be used in subsequent processes to form at least a portion of the final device structure. Here, the final device may include a memory, which includes but is not limited to a dynamic random access memory (DRAM). The following description will only be made using a dynamic random access memory as an example.

[0064] In the currently proposed architecture of three-dimensional dynamic random access memory, horizontal bit lines and vertical word lines are easier to integrate, so they have become the mainstream development direction. Due to the continuous improvement of memory density requirements, the distance between bit lines in the architecture of horizontal bit lines of three-dimensional dynamic random access memory is getting smaller and smaller, which causes coupling effect between adjacent bit lines and easily forms parasitic capacitance. In addition, in order to ensure that the bit lines have a smaller resistance, materials with smaller resistance, such as metal materials, are generally selected as the materials of the bit lines, but this further aggravates the coupling effect between bit lines and the problem of parasitic capacitance, seriously affecting the reliability of the memory. How to improve the coupling effect between adjacent bit lines and reduce the parasitic capacitance between adjacent bit lines has become an urgent problem to be solved.

[0065] Based on the above problems, the present disclosure provides a method for forming a semiconductor structure. Figure 1 The following is a flow chart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure. Figure 1 As shown, the method for forming a semiconductor structure provided by the embodiment of the present disclosure includes the following steps:

[0066] S1100: providing an initial stacking structure, the initial stacking structure comprising first sacrificial layers and second sacrificial layers alternately stacked;

[0067] S1200: forming a plurality of first grooves penetrating the initial stacking structure;

[0068] S1300: performing lateral etching along the first trench to remove a first portion of each first sacrificial layer to form a plurality of first filling regions;

[0069] S1400: forming a dielectric layer in each first filling region;

[0070] S1500: removing the second sacrificial layer, forming a plurality of second filling regions, and forming a bit line layer in each of the second filling regions;

[0071] S1600: removing the second portion of each retained first sacrificial layer to form a plurality of cavities.

[0072] It should be understood that Figure 1 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 1 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0073] Figures 2 to 33 The structure diagram of the semiconductor structure forming process provided by the embodiment of the present disclosure is as follows. Figure 1 , Figures 2 to 33 The method for forming the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0074] Reference Figure 2 , perform step S1100 to provide an initial stacking structure 101, where the initial stacking structure 101 includes first sacrificial layers 102 and second sacrificial layers 103 that are alternately stacked.

[0075] It should be noted that Figure 2 The numbers of the first sacrificial layers 102 and the second sacrificial layers 103 shown in the figure are only examples, and the present disclosure does not limit the specific numbers of the first sacrificial layers 102 and the second sacrificial layers 103 in the initial stacking structure 101 .

[0076] In some specific examples, the first sacrificial layer 102 and the second sacrificial layer 103 can be formed by a deposition process or an epitaxy (EPI) process. Figure 2 A first sacrificial layer 102 is formed on the first sacrificial layer 102 (not shown), and then a second sacrificial layer 103 is formed on the first sacrificial layer 102. The process is repeated to form an initial stacking structure 101 in which the first sacrificial layer 102 and the second sacrificial layer 103 are alternately stacked.

[0077] It should be noted that the selection of materials for the first sacrificial layer 102 and the second sacrificial layer 103 needs to consider reducing the impact on the second sacrificial layer 103 when the first sacrificial layer 102 is laterally removed, and reducing the impact on the first sacrificial layer 102 when the second sacrificial layer 103 is laterally removed. In some specific examples, the material of the first sacrificial layer 102 can be silicon germanium; the material of the second sacrificial layer 103 can be silicon.

[0078] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0079] In some specific examples, such as Figure 2 As shown, the method further includes: forming a mask layer 133 on the initial stacked structure 101, the mask layer 133 may be a composite layer or a single layer, and illustratively, the mask layer 133 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon nitride oxide layer.

[0080] Reference Figure 3, executing step S1200 to form a plurality of first trenches 104 penetrating the initial stacking structure 101 .

[0081] In some specific examples, the method of forming the first trench 104 includes but is not limited to dry etching. Here, the dry etching process can be an etching process with good directionality such as plasma etching, sputtering etching, ion beam etching, reactive ion etching, etc.

[0082] In the present disclosure, Figure 3 As shown, multiple first grooves 104 are arranged along the first direction, the distance between the side wall of the first groove 104 parallel to the first direction and the edge of the initial stacking structure 101 along the second direction is H1, the distance between two adjacent first grooves 104 along the first direction is H2, and the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacking structure 101.

[0083] In the embodiment of the present disclosure, the first direction is the X direction, the second direction is the Y direction, and the stacking direction of the initial stacking structure 101 is the Z direction.

[0084] Here, for the corresponding relationship between H2 and H1, the embodiment of the present disclosure provides multiple situations, and the corresponding methods of forming the bit line layer, the dielectric layer, and the cavity are also different. The embodiment of the present disclosure provides three solutions. The following will first take the case where the ratio of H2 to H1 is greater than 2 and less than 6 as an example to specifically explain the solution 1.

[0085] Reference Figure 4 , performing step S1300 , etching laterally along the first trench 104 to remove the first portion of each first sacrificial layer 102 , and forming a plurality of first filling regions 106 .

[0086] In some specific examples, a method of removing the first portion of each first sacrificial layer 102 includes, but is not limited to, a wet etching process.

[0087] like Figure 4 As shown, the remaining first sacrificial layer 102 is the second portion 109 of the first sacrificial layer 102 . The remaining second portion 109 of each first sacrificial layer 102 is located between adjacent first trenches 104 .

[0088] It can be understood that when the first sacrificial layer 102 is laterally etched along the first groove 104, the first sacrificial layer 102 between two adjacent first grooves 104 is etched from both sides along the first direction at the same time, so both sides of the second portion 109 along the first direction are the first filling regions 106. In the embodiment of the present disclosure, the ratio of H2 to H1 is greater than 2 and less than 6, so that when the first sacrificial layer 102 is laterally etched along the first groove 104, the first sacrificial layer 102 on both sides of the first groove 104 along the second direction can be completely removed, and the first sacrificial layer 102 between two adjacent first grooves 104 along the first direction can retain the second portion 109, where the retained second portion 109 of the first sacrificial layer 102 is located between the two adjacent first grooves 104 along the first direction, and the retained second portion 109 of the first sacrificial layer 102 can play a supporting role.

[0089] Reference Figure 5 to Figure 6 , executing step S1400 , forming a dielectric layer 107 in each first filling region 106 .

[0090] In some specific examples, the material of the dielectric layer 107 may be a low dielectric constant material, and the low dielectric constant material includes but is not limited to one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride.

[0091] It is understandable that the dielectric layer 107 in the embodiment of the present disclosure uses a low dielectric constant material to reduce the coupling effect and parasitic capacitance between two bit line layers that are subsequently formed and are adjacent to each other along the stacking direction of the initial stacking structure 101 .

[0092] It should be noted that the selection of the material for the dielectric layer 107 here needs to take into account the reduction of the impact on the dielectric layer 107 when removing the remaining first sacrificial layer 102 , the remaining second sacrificial layer 103 and part of the conductive material layer in the subsequent process.

[0093] In some specific examples, a dielectric material layer 129 can be first deposited on the sidewalls and top of the first filling region 106 and the initial stacking structure 101, and then an etching process is used to remove the dielectric material layer 129 on the sidewalls and top of the initial stacking structure 101, retaining the dielectric material layer 129 in the first filling region 106 to form a dielectric layer 107.

[0094] Reference Figures 7 to 13 , executing step S1500 , removing the second sacrificial layer 103 , forming a plurality of second filling regions, and forming a bit line layer 108 in each of the second filling regions.

[0095] In some embodiments, Figures 7 to 13As shown, the second sacrificial layer 103 is removed to form a plurality of second filling regions, and a bit line layer 108 is formed in each second filling region, including: lateral etching along the first groove 104 to remove the third portion of each second sacrificial layer 103 to form a plurality of third filling regions 112; a conductive material layer 113 is filled in each third filling region 112; the conductive material layer 113 is filled between the retained fourth portions 114 of each second sacrificial layer 103; the fourth portions 114 are removed to form a plurality of fourth filling regions 115; a conductive material layer 113 is filled in each fourth filling region 115; the conductive material layer 113 in the third filling region 112 and the fourth filling region 115 constitute the bit line layer 108.

[0096] It can be understood that the second sacrificial layer 103 in the embodiment of the present disclosure is removed in two steps, firstly, the third part of each second sacrificial layer is removed to form a third filling area 112, and the third filling area 112 is filled with a conductive material layer 113; then, the fourth part 114 of the second sacrificial layer 103 is removed to form a fourth filling area 115, and the fourth filling area 115 is filled with a conductive material layer 113. When the third part is removed, the fourth part 114 can play a supporting role, and when the fourth part 114 is removed, the conductive material layer 113 filled in the third filling area 112 can play a supporting role.

[0097] In some specific examples, the material of the conductive material layer 113 includes but is not limited to metal tungsten. The method of forming the conductive material layer includes but is not limited to a deposition process.

[0098] It can be understood that the use of tungsten as the material of the bit line layer 108 in the embodiment of the present disclosure can reduce the bit line resistance and improve the performance of the memory.

[0099] In some specific examples, such as Figure 8 as well as Fig. 9 As shown, after forming multiple third filling areas 112, a conductive material layer 113 can be first deposited on the third filling areas 112 and the side walls and the top of the initial stacking structure 101, and then an etching process is used to remove the conductive material layer 113 on the side walls and the top of the initial stacking structure 101 along the stacking direction of the initial stacking structure 101, retaining the conductive material layer 113 located in the third filling area 112.

[0100] It should be noted that in order to more clearly show the initial stacking structure 101 between adjacent first trenches 104, Figures 2 to 9 For partial views only, e.g. Fig. 9 for Fig.10 A stereogram of the upper half cut along the AA' direction.

[0101] In some embodiments, Figures 9 to 12As shown, after the dielectric layer 107 is formed in each first filling area 106, the dielectric layer 107 is filled between the second parts 109 of each retained first sacrificial layer 102; the fourth part 114 is removed, and the second part 109 is removed, including: after the conductive material layer 113 is filled in each third filling area 112, a second groove 116 is formed that penetrates the initial stacking structure 101; the second groove 116 exposes the sidewalls of the fourth part 114 and the sidewalls of the second part 109; the second groove 116 is laterally etched to remove the fourth part 114; the second groove 116 is laterally etched to remove the second part 109.

[0102] In some specific examples, such as Fig.11 As shown, the second trench 116 extends along the first direction and communicates with the first trench 104 .

[0103] In some specific examples, a method of removing the fourth portion 114 includes, but is not limited to, a wet etching process.

[0104] It can be understood that, since both sidewalls of the second portion 109 of the first sacrificial layer 102 along the first direction are covered by the dielectric layer 107, and both sidewalls of the fourth portion 114 of the second sacrificial layer 103 along the first direction are covered by the conductive material layer 113, the first trench 104 does not expose the second portion 109 of the first sacrificial layer 102, and the first trench 104 does not expose the fourth portion 114 of the second sacrificial layer 103, so the second portion 109 and the fourth portion 114 cannot be removed through the first trench 104. In the embodiment of the present disclosure, the second trench 116 is formed to penetrate the initial stacking structure 101, and the second trench 116 exposes the sidewalls of the fourth portion 114 and the sidewalls of the second portion 109, so that the second portion 109 and the fourth portion 114 can be removed from the second trench 116.

[0105] Reference Fig.14 , executing step S1600 , removing the second portion 109 of each retained first sacrificial layer 102 to form a plurality of cavities 110 .

[0106] In some specific examples, the method of removing the second portion 109 includes, but is not limited to, wet etching.

[0107] In some specific examples, the method further includes: after forming the cavity 110 , removing the mask layer 133 .

[0108] It can be understood that in the embodiment of the present disclosure, a plurality of cavities 110 are formed between two bit line layers 108 adjacent along the stacking direction of the initial stacking structure 101, so that the coupling effect of the two bit line layers adjacent along the stacking direction of the initial stacking structure 101 can be reduced, and the parasitic capacitance of the two bit line layers adjacent along the stacking direction of the initial stacking structure 101 can be reduced, thereby improving the performance of the memory.

[0109] When the ratio of H2 to H1 is greater than 2 and less than 6, the embodiment of the present disclosure also provides the following method to form the bit line layer 108, the dielectric layer 107 and the cavity 110. Figures 15 to 24 The second option is described in detail.

[0110] In some embodiments, Figures 15 to 18 As shown, the method also includes: before laterally etching along the first groove 104 to remove the first portion of each first sacrificial layer 102, filling a third sacrificial layer 117 in at least a portion of the first groove 104; after forming a dielectric layer 107 in each first filling area 106, removing the third sacrificial layer 117 to form a fourth groove 118, and the fourth groove 118 exposes the side wall of the second portion 109.

[0111] It should be noted that Fig.15 The figure only exemplarily shows the case where the third sacrificial layer 117 is filled in one first trench 104 . The third sacrificial layer 117 may also be filled in a plurality of first trenches 104 that are continuous along the first direction.

[0112] It can be understood that in the above embodiment, the third sacrificial layer 117 is first filled in part of the first groove 104, and the first groove 104 not filled with the third sacrificial layer 117 is used to remove part of the first sacrificial layer 102, and then the second part 109 of the first sacrificial layer 102 is removed using the fourth groove after removing the third sacrificial layer.

[0113] In some embodiments, Figures 19 to 23 As shown, the second sacrificial layer 103 is removed to form a plurality of second filling regions, and a bit line layer 108 is formed in each of the second filling regions, including: filling a fourth sacrificial layer 119 in the first trench 104, and laterally etching along the fourth trench 118 to remove the fifth portion of each second sacrificial layer 103 to form a plurality of fifth filling regions 123; filling a conductive material layer 113 in each of the fifth filling regions 123; removing the fourth sacrificial layer 119, and removing the retained sixth portion 120 of each second sacrificial layer 103 along the first trench 104 to form a plurality of sixth filling regions 121; filling a conductive material layer 113 in each of the sixth filling regions 121; the conductive material layer 113 in the fifth filling region 123 and the conductive material layer 113 in the sixth filling region 121 constitute the bit line layer 108.

[0114] like Fig.24 As shown, the method further includes: removing the second portion 109 of each of the first sacrificial layers 102 to form a plurality of cavities 110 . The cavities here are connected to the fourth trench 118 .

[0115] In some specific examples, the method further includes: after forming the cavity 110 , removing the mask layer 133 .

[0116] The ratio of H2 to H1 can also be greater than 6. Figures 25 to 33 When the ratio of H2 to H1 is greater than 6, the process of forming the bit line layer 108 , the dielectric layer 107 and the cavity 110 in the third solution is described in detail.

[0117] In some embodiments, Figure 25 to Figure 28 As shown, multiple first grooves 104 are arranged along the first direction, and the method also includes: after the dielectric layer 107 is formed in each first filling area 106, a third groove 124 is formed between two adjacent first grooves 104, and the third groove 124 penetrates the initial stacking structure 101 and exposes the side wall of the second part 109; the distance between the third groove 124 and the adjacent first groove 104 along the first direction is H3, and the distance between the side wall of the third groove 124 or the first groove 104 parallel to the first direction and the edge of the initial stacking structure 101 along the second direction is H1, and the ratio of H3 to H1 is greater than 2; the first direction is perpendicular to the second direction and is perpendicular to the stacking direction of the initial stacking structure 101.

[0118] Here, after the third trench 124 is formed, the ratio of H3 to H1 is greater than 2 and less than 6.

[0119] It can be understood that, compared with Scheme 1, in Scheme 3, when the ratio of H2 to H1 is greater than 6, after the first portion of the first sacrificial layer 102 is removed using the first groove 104, a larger amount of the first sacrificial layer 102 is retained between two adjacent first grooves 104, and after the dielectric layer 107 is formed in the first filling area 106, a third groove 124 is formed between the two adjacent first grooves 104, and the third groove 124 exposes the side wall of the second portion 109, so that the second portion 109 can be removed along the third groove 124 in the subsequent process.

[0120] In some embodiments, Figure 29 to Figure 32As shown, the second sacrificial layer 103 is removed to form a plurality of second filling regions, and a bit line layer 108 is formed in each of the second filling regions, including: etching laterally along the third trench 124 to remove the seventh portion of each second sacrificial layer 103 to form a plurality of seventh filling regions 126; filling each of the seventh filling regions 126 with a conductive material layer 113; etching laterally along the first trench 104 to remove the eighth portion 127 of the retained second sacrificial layer 103 to form a plurality of eighth filling regions 128; filling each of the eighth filling regions 128 with a conductive material layer 113; the conductive material layers 113 in the seventh filling regions 126 and the eighth filling regions 128 constitute the bit line layer 108;

[0121] In some specific examples, when the third trench 124 is laterally etched to remove the seventh portion of each second sacrificial layer 103, a fifth sacrificial layer may be formed in the first trench 124, so that when the third trench 124 is laterally etched, the first sacrificial layer 102 cannot be laterally etched along the first trench 104. After each seventh filling region 126 is filled with the conductive material layer 113, the fifth sacrificial layer in the first trench 124 is removed.

[0122] In some embodiments, Fig.33 As shown, removing the retained second portion 109 of each first sacrificial layer 102 includes: etching laterally along the third trench 124 to remove the retained second portion 109 of each first sacrificial layer 102 .

[0123] The present disclosure provides a method for forming a semiconductor structure, comprising: providing an initial stacking structure 101, the initial stacking structure 101 comprising alternately stacked first sacrificial layers 102 and second sacrificial layers 103; forming a plurality of first grooves 104 penetrating the initial stacking structure 101; laterally etching along the first grooves 104 to remove a first portion of each first sacrificial layer 102 to form a plurality of first filling regions 106; forming a dielectric layer 107 in each first filling region 106; removing the second sacrificial layer 103 to form a plurality of second filling regions, forming a bit line layer 108 in each second filling region; and removing the retained second portion 109 of each first sacrificial layer 102 to form a plurality of cavities 110. In the embodiment of the present disclosure, a first groove 104 is formed in the initial stacking structure 101 and penetrates the initial stacking structure 101. The first portion of the first sacrificial layer 102 is removed by lateral etching along the first groove 104, and the dielectric layer 107 is filled in the area where the first portion of the first sacrificial layer 102 is removed. After the second sacrificial layer 103 is removed and the bit line layer 108 is formed, the second portion 109 of the first sacrificial layer 102 is removed, thereby forming a cavity 110 between two bit line layers 108 adjacent to each other along the stacking direction of the initial stacking structure 101. In this way, the coupling effect between the two bit line layers 108 adjacent to each other along the stacking direction of the initial stacking structure 101 can be reduced, and the parasitic capacitance between the two bit line layers 108 adjacent to each other along the stacking direction of the initial stacking structure 101 can be reduced, thereby improving the performance of the semiconductor structure.

[0124] Based on the same technical concept as the aforementioned method for forming a semiconductor structure, an embodiment of the present disclosure provides a semiconductor structure. Fig.34 The semiconductor structure shown corresponds to the first solution in the method for forming the semiconductor structure described above. Fig.35 The semiconductor structure shown corresponds to the second and third solutions in the above-mentioned method for forming the semiconductor structure.

[0125] like Fig.34 as well as Fig.35 As shown, the semiconductor structure includes: a stacked structure 130, including alternately stacked bit line layers 108 and dielectric layers 107; wherein the stacked structure 130 includes a plurality of first grooves 104 penetrating the stacked structure 130; the bit line layer 108 has a plurality of first bit line portions 131 located on both sides of the first grooves 104 along a first direction and a second bit line portion 132 located on one side of the plurality of first bit line portions 131 along a second direction, and the second bit line portion 132 extends along the first direction; and a cavity 110 is provided in the dielectric layer 107 between adjacent first grooves 104.

[0126] It can be understood that in the embodiment of the present disclosure, there is a cavity 110 between two bit line layers 108 adjacent along the stacking direction of the stacking structure 130, so that the coupling effect between the two bit line layers 108 adjacent along the stacking direction of the stacking structure 130 can be reduced, and the parasitic capacitance generated between the two bit line layers 108 adjacent along the stacking direction of the stacking structure 130 can be reduced, thereby effectively improving the performance of the memory.

[0127] In some specific examples, the material of the bit line layer 108 includes, but is not limited to, metal tungsten.

[0128] It can be understood that the use of tungsten as the material of the bit line layer 108 in the embodiment of the present disclosure can reduce the bit line resistance and improve the performance of the memory.

[0129] In some specific examples, the material of the dielectric layer 107 may be a low dielectric constant material, and the low dielectric constant material includes but is not limited to one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride. It is understood that the use of a low dielectric constant material for the dielectric layer 107 in the embodiment of the present disclosure can further reduce the coupling effect and parasitic capacitance between two adjacent bit line layers 108 along the stacking direction of the stack structure 130.

[0130] In some embodiments, Fig.34 As shown, multiple first grooves 104 are arranged along the first direction, the width of the second bit line portion 132 along the second direction is H1, the width of the first bit line portion 131 along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the stacking structure 130.

[0131] In some embodiments, the ratio of H2 to H1 ranges from 3-6.

[0132] In some embodiments, Fig.34 As shown, the cavity 110 is located between the first bit line portions 131 adjacent to each other along the stacking direction, and a dielectric layer 107 is provided between the cavity 110 and two first trenches 104 adjacent to each other along the first direction.

[0133] In some embodiments, Fig.35 As shown, the ratio of H2 to H1 ranges from 6, and the stacking structure 130 also includes a third groove 124 that penetrates the stacking structure 130. The third groove 124 is located between two adjacent first grooves 104. The distance between the third groove 124 and the adjacent first groove 104 along the first direction is H3, and the ratio of H3 to H1 ranges from 3 to 6.

[0134] In some embodiments, the cavity 110 is located between the first bit line portions 131 adjacent to each other along the stacking direction and between the second bit line portions 132 adjacent to each other along the stacking direction, and the cavity 110 is located on both sides of the third groove 124 along the first direction and on one side along the second direction, a dielectric layer 107 is provided between the first groove 104 and the cavity 110, and the third groove 124 is connected to the cavity 110.

[0135] Based on the above semiconductor structure, an embodiment of the present disclosure further provides a memory, comprising the semiconductor structure of any one of the above embodiments.

[0136] In some specific examples, the memory includes but is not limited to dynamic random access memory, static random access memory (SRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM) and flash memory.

[0137] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0138] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0139] The specific implementation methods of the present disclosure are disclosed, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing an initial stacking structure, the initial stacking structure comprising first sacrificial layers and second sacrificial layers stacked alternately; forming a plurality of first grooves penetrating the initial stacking structure; Laterally etching along the first trench to remove a first portion of each first sacrificial layer to form a plurality of first filling regions; forming a dielectric layer in each of the first filling regions; removing the second sacrificial layer to form a plurality of second filling regions, and forming a bit line layer in each of the second filling regions; The remaining second portion of each first sacrificial layer is removed to form a plurality of cavities.

2. The forming method according to claim 1, characterized in that: Multiple first grooves are arranged along a first direction, the distance between the side wall of the first groove parallel to the first direction and the edge of the initial stacking structure along the second direction is H1, the distance between two adjacent first grooves along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacking structure.

3. The forming method according to claim 1, characterized in that: The removing the second sacrificial layer to form a plurality of second filling regions, wherein a bit line layer is formed in each of the second filling regions, comprises: Laterally etching along the first trench to remove a third portion of each second sacrificial layer to form a plurality of third filling regions; A conductive material is filled in each of the third filling regions; the conductive material is filled between the fourth portions of each of the retained second sacrificial layers; removing the fourth portion to form a plurality of fourth filling areas; The conductive material is filled in each of the fourth filling regions; and the conductive material in the third filling region and the fourth filling region constitutes the bit line layer.

4. The forming method according to claim 3, characterized in that: After forming a dielectric layer in each of the first filling regions, the dielectric layer is filled between the second portions of each of the retained first sacrificial layers; The removing of the fourth part and the removing of the second part comprises: After each of the third filling regions is filled with a conductive material, a second trench penetrating the initial stacked structure is formed; the second trench exposes a sidewall of the fourth portion and a sidewall of the second portion; performing lateral etching along the second groove to remove the fourth portion; Performing lateral etching along the second trench to remove the second portion.

5. The forming method according to claim 1, characterized in that: The method further comprises: Before performing lateral etching along the first trench to remove the first portion of each first sacrificial layer, filling at least a portion of the first trench with a third sacrificial layer; After a dielectric layer is formed in each of the first filling regions, the third sacrificial layer is removed to form a fourth trench, wherein the fourth trench exposes a sidewall of the second portion.

6. The forming method according to claim 5, characterized in that: The removing the second sacrificial layer to form a plurality of second filling regions, wherein a bit line layer is formed in each of the second filling regions, comprises: Filling a fourth sacrificial layer in the first trench, and laterally etching along the fourth trench to remove a fifth portion of each second sacrificial layer to form a plurality of fifth filling regions; Filling each of the fifth filling regions with a conductive material; removing the fourth sacrificial layer, and removing the sixth portion of each retained second sacrificial layer along the first trench to form a plurality of sixth filling regions; The conductive material is filled in each of the sixth filling regions; and the conductive materials in the fifth filling region and the sixth filling region constitute the bit line layer.

7. The forming method according to claim 1, characterized in that: The plurality of first grooves are arranged along a first direction, and the method further comprises: After a dielectric layer is formed in each of the first filling regions, a third groove is formed between two adjacent first grooves, the third groove penetrates the initial stacking structure and exposes the side wall of the second portion; the distance between the third groove and the adjacent first groove along the first direction is H3, the distance between the side wall of the third groove or the first groove parallel to the first direction and the edge of the initial stacking structure along the second direction is H1, and the ratio of H3 to H1 is greater than 2; the first direction is perpendicular to the second direction and is perpendicular to the stacking direction of the initial stacking structure.

8. The forming method according to claim 7, characterized in that: The removing the second sacrificial layer to form a plurality of second filling regions, wherein a bit line layer is formed in each of the second filling regions, comprises: Laterally etching along the third trench to remove a seventh portion of each second sacrificial layer to form a plurality of seventh filling regions; Filling each of the seventh filling regions with a conductive material; Laterally etching along the first trench to remove the eighth portion of the retained second sacrificial layer to form a plurality of eighth filling regions; The conductive material is filled in each of the eighth filling regions; the conductive materials in the seventh filling region and the eighth filling region constitute the bit line layer; The removing of the second portion of each of the first sacrificial layers that is retained includes: performing lateral etching along the third trench to remove the second portion of each of the first sacrificial layers that is retained.

9. A semiconductor structure, characterized in that: include: A stacked structure including alternately stacked bit line layers and dielectric layers; Wherein, the stacking structure includes a plurality of first grooves penetrating the stacking structure; The bit line layer comprises a plurality of first bit line portions located at both sides of the first trench along a first direction and a second bit line portion located at one side of the plurality of first bit line portions along a second direction, wherein the second bit line portion extends along the first direction; There is a cavity in the dielectric layer between adjacent first trenches.

10. The semiconductor structure according to claim 9, characterized in that: Multiple first grooves are arranged along a first direction, the width of the second bit line portion along the second direction is H1, the width of the first bit line portion along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the stacking structure.

11. The semiconductor structure according to claim 10, characterized in that: The ratio of H2 to H1 ranges from 3-6.

12. The semiconductor structure according to claim 11, characterized in that: The cavity is located between the first bit line portions adjacent to each other along the stacking direction, and a dielectric layer is provided between the cavity and two first trenches adjacent to each other along the first direction.

13. The semiconductor structure according to claim 10, characterized in that: The ratio of H2 to H1 ranges from 6 to 6. The stacking structure also includes a third groove running through the stacking structure. The third groove is located between two adjacent first grooves. The distance between the third groove and the adjacent first groove along the first direction is H3. The ratio of H3 to H1 ranges from 3 to 6.

14. The semiconductor structure according to claim 13, characterized in that: The cavity is located between the first bit line portions adjacent to each other along the stacking direction and between the second bit line portions adjacent to each other along the stacking direction, and the cavity is located on both sides of the third groove along the first direction and on one side along the second direction, a dielectric layer is provided between the first groove and the cavity, and the third groove is connected to the cavity.

15. A memory, characterized in that: Comprising the semiconductor structure as claimed in any one of claims 9 to 14.

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